mv643xx_eth.c 65 KB

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  1. /*
  2. * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
  3. * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
  4. *
  5. * Based on the 64360 driver from:
  6. * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
  7. * Rabeeh Khoury <rabeeh@marvell.com>
  8. *
  9. * Copyright (C) 2003 PMC-Sierra, Inc.,
  10. * written by Manish Lachwani
  11. *
  12. * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
  13. *
  14. * Copyright (C) 2004-2006 MontaVista Software, Inc.
  15. * Dale Farnsworth <dale@farnsworth.org>
  16. *
  17. * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
  18. * <sjhill@realitydiluted.com>
  19. *
  20. * Copyright (C) 2007-2008 Marvell Semiconductor
  21. * Lennert Buytenhek <buytenh@marvell.com>
  22. *
  23. * This program is free software; you can redistribute it and/or
  24. * modify it under the terms of the GNU General Public License
  25. * as published by the Free Software Foundation; either version 2
  26. * of the License, or (at your option) any later version.
  27. *
  28. * This program is distributed in the hope that it will be useful,
  29. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31. * GNU General Public License for more details.
  32. *
  33. * You should have received a copy of the GNU General Public License
  34. * along with this program; if not, write to the Free Software
  35. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  36. */
  37. #include <linux/init.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/in.h>
  40. #include <linux/tcp.h>
  41. #include <linux/udp.h>
  42. #include <linux/etherdevice.h>
  43. #include <linux/delay.h>
  44. #include <linux/ethtool.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/module.h>
  47. #include <linux/kernel.h>
  48. #include <linux/spinlock.h>
  49. #include <linux/workqueue.h>
  50. #include <linux/mii.h>
  51. #include <linux/mv643xx_eth.h>
  52. #include <asm/io.h>
  53. #include <asm/types.h>
  54. #include <asm/system.h>
  55. static char mv643xx_eth_driver_name[] = "mv643xx_eth";
  56. static char mv643xx_eth_driver_version[] = "1.2";
  57. #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
  58. #define MV643XX_ETH_NAPI
  59. #define MV643XX_ETH_TX_FAST_REFILL
  60. #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
  61. #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
  62. #else
  63. #define MAX_DESCS_PER_SKB 1
  64. #endif
  65. /*
  66. * Registers shared between all ports.
  67. */
  68. #define PHY_ADDR 0x0000
  69. #define SMI_REG 0x0004
  70. #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
  71. #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
  72. #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
  73. #define WINDOW_BAR_ENABLE 0x0290
  74. #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
  75. /*
  76. * Per-port registers.
  77. */
  78. #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
  79. #define UNICAST_PROMISCUOUS_MODE 0x00000001
  80. #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
  81. #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
  82. #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
  83. #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
  84. #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
  85. #define PORT_STATUS(p) (0x0444 + ((p) << 10))
  86. #define TX_FIFO_EMPTY 0x00000400
  87. #define TX_IN_PROGRESS 0x00000080
  88. #define PORT_SPEED_MASK 0x00000030
  89. #define PORT_SPEED_1000 0x00000010
  90. #define PORT_SPEED_100 0x00000020
  91. #define PORT_SPEED_10 0x00000000
  92. #define FLOW_CONTROL_ENABLED 0x00000008
  93. #define FULL_DUPLEX 0x00000004
  94. #define LINK_UP 0x00000002
  95. #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
  96. #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
  97. #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
  98. #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
  99. #define TX_BW_BURST(p) (0x045c + ((p) << 10))
  100. #define INT_CAUSE(p) (0x0460 + ((p) << 10))
  101. #define INT_TX_END_0 0x00080000
  102. #define INT_TX_END 0x07f80000
  103. #define INT_RX 0x0007fbfc
  104. #define INT_EXT 0x00000002
  105. #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
  106. #define INT_EXT_LINK 0x00100000
  107. #define INT_EXT_PHY 0x00010000
  108. #define INT_EXT_TX_ERROR_0 0x00000100
  109. #define INT_EXT_TX_0 0x00000001
  110. #define INT_EXT_TX 0x0000ffff
  111. #define INT_MASK(p) (0x0468 + ((p) << 10))
  112. #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
  113. #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
  114. #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
  115. #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
  116. #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
  117. #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
  118. #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
  119. #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
  120. #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
  121. #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
  122. #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
  123. #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
  124. #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
  125. #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
  126. #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
  127. #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
  128. /*
  129. * SDMA configuration register.
  130. */
  131. #define RX_BURST_SIZE_16_64BIT (4 << 1)
  132. #define BLM_RX_NO_SWAP (1 << 4)
  133. #define BLM_TX_NO_SWAP (1 << 5)
  134. #define TX_BURST_SIZE_16_64BIT (4 << 22)
  135. #if defined(__BIG_ENDIAN)
  136. #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
  137. RX_BURST_SIZE_16_64BIT | \
  138. TX_BURST_SIZE_16_64BIT
  139. #elif defined(__LITTLE_ENDIAN)
  140. #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
  141. RX_BURST_SIZE_16_64BIT | \
  142. BLM_RX_NO_SWAP | \
  143. BLM_TX_NO_SWAP | \
  144. TX_BURST_SIZE_16_64BIT
  145. #else
  146. #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
  147. #endif
  148. /*
  149. * Port serial control register.
  150. */
  151. #define SET_MII_SPEED_TO_100 (1 << 24)
  152. #define SET_GMII_SPEED_TO_1000 (1 << 23)
  153. #define SET_FULL_DUPLEX_MODE (1 << 21)
  154. #define MAX_RX_PACKET_9700BYTE (5 << 17)
  155. #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
  156. #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
  157. #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
  158. #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
  159. #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
  160. #define FORCE_LINK_PASS (1 << 1)
  161. #define SERIAL_PORT_ENABLE (1 << 0)
  162. #define DEFAULT_RX_QUEUE_SIZE 400
  163. #define DEFAULT_TX_QUEUE_SIZE 800
  164. /*
  165. * RX/TX descriptors.
  166. */
  167. #if defined(__BIG_ENDIAN)
  168. struct rx_desc {
  169. u16 byte_cnt; /* Descriptor buffer byte count */
  170. u16 buf_size; /* Buffer size */
  171. u32 cmd_sts; /* Descriptor command status */
  172. u32 next_desc_ptr; /* Next descriptor pointer */
  173. u32 buf_ptr; /* Descriptor buffer pointer */
  174. };
  175. struct tx_desc {
  176. u16 byte_cnt; /* buffer byte count */
  177. u16 l4i_chk; /* CPU provided TCP checksum */
  178. u32 cmd_sts; /* Command/status field */
  179. u32 next_desc_ptr; /* Pointer to next descriptor */
  180. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  181. };
  182. #elif defined(__LITTLE_ENDIAN)
  183. struct rx_desc {
  184. u32 cmd_sts; /* Descriptor command status */
  185. u16 buf_size; /* Buffer size */
  186. u16 byte_cnt; /* Descriptor buffer byte count */
  187. u32 buf_ptr; /* Descriptor buffer pointer */
  188. u32 next_desc_ptr; /* Next descriptor pointer */
  189. };
  190. struct tx_desc {
  191. u32 cmd_sts; /* Command/status field */
  192. u16 l4i_chk; /* CPU provided TCP checksum */
  193. u16 byte_cnt; /* buffer byte count */
  194. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  195. u32 next_desc_ptr; /* Pointer to next descriptor */
  196. };
  197. #else
  198. #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
  199. #endif
  200. /* RX & TX descriptor command */
  201. #define BUFFER_OWNED_BY_DMA 0x80000000
  202. /* RX & TX descriptor status */
  203. #define ERROR_SUMMARY 0x00000001
  204. /* RX descriptor status */
  205. #define LAYER_4_CHECKSUM_OK 0x40000000
  206. #define RX_ENABLE_INTERRUPT 0x20000000
  207. #define RX_FIRST_DESC 0x08000000
  208. #define RX_LAST_DESC 0x04000000
  209. /* TX descriptor command */
  210. #define TX_ENABLE_INTERRUPT 0x00800000
  211. #define GEN_CRC 0x00400000
  212. #define TX_FIRST_DESC 0x00200000
  213. #define TX_LAST_DESC 0x00100000
  214. #define ZERO_PADDING 0x00080000
  215. #define GEN_IP_V4_CHECKSUM 0x00040000
  216. #define GEN_TCP_UDP_CHECKSUM 0x00020000
  217. #define UDP_FRAME 0x00010000
  218. #define MAC_HDR_EXTRA_4_BYTES 0x00008000
  219. #define MAC_HDR_EXTRA_8_BYTES 0x00000200
  220. #define TX_IHL_SHIFT 11
  221. /* global *******************************************************************/
  222. struct mv643xx_eth_shared_private {
  223. /*
  224. * Ethernet controller base address.
  225. */
  226. void __iomem *base;
  227. /*
  228. * Protects access to SMI_REG, which is shared between ports.
  229. */
  230. spinlock_t phy_lock;
  231. /*
  232. * Per-port MBUS window access register value.
  233. */
  234. u32 win_protect;
  235. /*
  236. * Hardware-specific parameters.
  237. */
  238. unsigned int t_clk;
  239. int extended_rx_coal_limit;
  240. int tx_bw_control_moved;
  241. };
  242. /* per-port *****************************************************************/
  243. struct mib_counters {
  244. u64 good_octets_received;
  245. u32 bad_octets_received;
  246. u32 internal_mac_transmit_err;
  247. u32 good_frames_received;
  248. u32 bad_frames_received;
  249. u32 broadcast_frames_received;
  250. u32 multicast_frames_received;
  251. u32 frames_64_octets;
  252. u32 frames_65_to_127_octets;
  253. u32 frames_128_to_255_octets;
  254. u32 frames_256_to_511_octets;
  255. u32 frames_512_to_1023_octets;
  256. u32 frames_1024_to_max_octets;
  257. u64 good_octets_sent;
  258. u32 good_frames_sent;
  259. u32 excessive_collision;
  260. u32 multicast_frames_sent;
  261. u32 broadcast_frames_sent;
  262. u32 unrec_mac_control_received;
  263. u32 fc_sent;
  264. u32 good_fc_received;
  265. u32 bad_fc_received;
  266. u32 undersize_received;
  267. u32 fragments_received;
  268. u32 oversize_received;
  269. u32 jabber_received;
  270. u32 mac_receive_error;
  271. u32 bad_crc_event;
  272. u32 collision;
  273. u32 late_collision;
  274. };
  275. struct rx_queue {
  276. int index;
  277. int rx_ring_size;
  278. int rx_desc_count;
  279. int rx_curr_desc;
  280. int rx_used_desc;
  281. struct rx_desc *rx_desc_area;
  282. dma_addr_t rx_desc_dma;
  283. int rx_desc_area_size;
  284. struct sk_buff **rx_skb;
  285. struct timer_list rx_oom;
  286. };
  287. struct tx_queue {
  288. int index;
  289. int tx_ring_size;
  290. int tx_desc_count;
  291. int tx_curr_desc;
  292. int tx_used_desc;
  293. struct tx_desc *tx_desc_area;
  294. dma_addr_t tx_desc_dma;
  295. int tx_desc_area_size;
  296. struct sk_buff **tx_skb;
  297. };
  298. struct mv643xx_eth_private {
  299. struct mv643xx_eth_shared_private *shared;
  300. int port_num;
  301. struct net_device *dev;
  302. struct mv643xx_eth_shared_private *shared_smi;
  303. int phy_addr;
  304. spinlock_t lock;
  305. struct mib_counters mib_counters;
  306. struct work_struct tx_timeout_task;
  307. struct mii_if_info mii;
  308. /*
  309. * RX state.
  310. */
  311. int default_rx_ring_size;
  312. unsigned long rx_desc_sram_addr;
  313. int rx_desc_sram_size;
  314. u8 rxq_mask;
  315. int rxq_primary;
  316. struct napi_struct napi;
  317. struct rx_queue rxq[8];
  318. /*
  319. * TX state.
  320. */
  321. int default_tx_ring_size;
  322. unsigned long tx_desc_sram_addr;
  323. int tx_desc_sram_size;
  324. u8 txq_mask;
  325. int txq_primary;
  326. struct tx_queue txq[8];
  327. #ifdef MV643XX_ETH_TX_FAST_REFILL
  328. int tx_clean_threshold;
  329. #endif
  330. };
  331. /* port register accessors **************************************************/
  332. static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
  333. {
  334. return readl(mp->shared->base + offset);
  335. }
  336. static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
  337. {
  338. writel(data, mp->shared->base + offset);
  339. }
  340. /* rxq/txq helper functions *************************************************/
  341. static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
  342. {
  343. return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
  344. }
  345. static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
  346. {
  347. return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
  348. }
  349. static void rxq_enable(struct rx_queue *rxq)
  350. {
  351. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  352. wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
  353. }
  354. static void rxq_disable(struct rx_queue *rxq)
  355. {
  356. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  357. u8 mask = 1 << rxq->index;
  358. wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
  359. while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
  360. udelay(10);
  361. }
  362. static void txq_reset_hw_ptr(struct tx_queue *txq)
  363. {
  364. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  365. int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
  366. u32 addr;
  367. addr = (u32)txq->tx_desc_dma;
  368. addr += txq->tx_curr_desc * sizeof(struct tx_desc);
  369. wrl(mp, off, addr);
  370. }
  371. static void txq_enable(struct tx_queue *txq)
  372. {
  373. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  374. wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
  375. }
  376. static void txq_disable(struct tx_queue *txq)
  377. {
  378. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  379. u8 mask = 1 << txq->index;
  380. wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
  381. while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
  382. udelay(10);
  383. }
  384. static void __txq_maybe_wake(struct tx_queue *txq)
  385. {
  386. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  387. /*
  388. * netif_{stop,wake}_queue() flow control only applies to
  389. * the primary queue.
  390. */
  391. BUG_ON(txq->index != mp->txq_primary);
  392. if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
  393. netif_wake_queue(mp->dev);
  394. }
  395. /* rx ***********************************************************************/
  396. static void txq_reclaim(struct tx_queue *txq, int force);
  397. static void rxq_refill(struct rx_queue *rxq)
  398. {
  399. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  400. unsigned long flags;
  401. spin_lock_irqsave(&mp->lock, flags);
  402. while (rxq->rx_desc_count < rxq->rx_ring_size) {
  403. int skb_size;
  404. struct sk_buff *skb;
  405. int unaligned;
  406. int rx;
  407. /*
  408. * Reserve 2+14 bytes for an ethernet header (the
  409. * hardware automatically prepends 2 bytes of dummy
  410. * data to each received packet), 4 bytes for a VLAN
  411. * header, and 4 bytes for the trailing FCS -- 24
  412. * bytes total.
  413. */
  414. skb_size = mp->dev->mtu + 24;
  415. skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
  416. if (skb == NULL)
  417. break;
  418. unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
  419. if (unaligned)
  420. skb_reserve(skb, dma_get_cache_alignment() - unaligned);
  421. rxq->rx_desc_count++;
  422. rx = rxq->rx_used_desc;
  423. rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
  424. rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
  425. skb_size, DMA_FROM_DEVICE);
  426. rxq->rx_desc_area[rx].buf_size = skb_size;
  427. rxq->rx_skb[rx] = skb;
  428. wmb();
  429. rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
  430. RX_ENABLE_INTERRUPT;
  431. wmb();
  432. /*
  433. * The hardware automatically prepends 2 bytes of
  434. * dummy data to each received packet, so that the
  435. * IP header ends up 16-byte aligned.
  436. */
  437. skb_reserve(skb, 2);
  438. }
  439. if (rxq->rx_desc_count != rxq->rx_ring_size) {
  440. rxq->rx_oom.expires = jiffies + (HZ / 10);
  441. add_timer(&rxq->rx_oom);
  442. }
  443. spin_unlock_irqrestore(&mp->lock, flags);
  444. }
  445. static inline void rxq_refill_timer_wrapper(unsigned long data)
  446. {
  447. rxq_refill((struct rx_queue *)data);
  448. }
  449. static int rxq_process(struct rx_queue *rxq, int budget)
  450. {
  451. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  452. struct net_device_stats *stats = &mp->dev->stats;
  453. int rx;
  454. rx = 0;
  455. while (rx < budget) {
  456. struct rx_desc *rx_desc;
  457. unsigned int cmd_sts;
  458. struct sk_buff *skb;
  459. unsigned long flags;
  460. spin_lock_irqsave(&mp->lock, flags);
  461. rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
  462. cmd_sts = rx_desc->cmd_sts;
  463. if (cmd_sts & BUFFER_OWNED_BY_DMA) {
  464. spin_unlock_irqrestore(&mp->lock, flags);
  465. break;
  466. }
  467. rmb();
  468. skb = rxq->rx_skb[rxq->rx_curr_desc];
  469. rxq->rx_skb[rxq->rx_curr_desc] = NULL;
  470. rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
  471. spin_unlock_irqrestore(&mp->lock, flags);
  472. dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
  473. mp->dev->mtu + 24, DMA_FROM_DEVICE);
  474. rxq->rx_desc_count--;
  475. rx++;
  476. /*
  477. * Update statistics.
  478. *
  479. * Note that the descriptor byte count includes 2 dummy
  480. * bytes automatically inserted by the hardware at the
  481. * start of the packet (which we don't count), and a 4
  482. * byte CRC at the end of the packet (which we do count).
  483. */
  484. stats->rx_packets++;
  485. stats->rx_bytes += rx_desc->byte_cnt - 2;
  486. /*
  487. * In case we received a packet without first / last bits
  488. * on, or the error summary bit is set, the packet needs
  489. * to be dropped.
  490. */
  491. if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
  492. (RX_FIRST_DESC | RX_LAST_DESC))
  493. || (cmd_sts & ERROR_SUMMARY)) {
  494. stats->rx_dropped++;
  495. if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
  496. (RX_FIRST_DESC | RX_LAST_DESC)) {
  497. if (net_ratelimit())
  498. dev_printk(KERN_ERR, &mp->dev->dev,
  499. "received packet spanning "
  500. "multiple descriptors\n");
  501. }
  502. if (cmd_sts & ERROR_SUMMARY)
  503. stats->rx_errors++;
  504. dev_kfree_skb_irq(skb);
  505. } else {
  506. /*
  507. * The -4 is for the CRC in the trailer of the
  508. * received packet
  509. */
  510. skb_put(skb, rx_desc->byte_cnt - 2 - 4);
  511. if (cmd_sts & LAYER_4_CHECKSUM_OK) {
  512. skb->ip_summed = CHECKSUM_UNNECESSARY;
  513. skb->csum = htons(
  514. (cmd_sts & 0x0007fff8) >> 3);
  515. }
  516. skb->protocol = eth_type_trans(skb, mp->dev);
  517. #ifdef MV643XX_ETH_NAPI
  518. netif_receive_skb(skb);
  519. #else
  520. netif_rx(skb);
  521. #endif
  522. }
  523. mp->dev->last_rx = jiffies;
  524. }
  525. rxq_refill(rxq);
  526. return rx;
  527. }
  528. #ifdef MV643XX_ETH_NAPI
  529. static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
  530. {
  531. struct mv643xx_eth_private *mp;
  532. int rx;
  533. int i;
  534. mp = container_of(napi, struct mv643xx_eth_private, napi);
  535. #ifdef MV643XX_ETH_TX_FAST_REFILL
  536. if (++mp->tx_clean_threshold > 5) {
  537. mp->tx_clean_threshold = 0;
  538. for (i = 0; i < 8; i++)
  539. if (mp->txq_mask & (1 << i))
  540. txq_reclaim(mp->txq + i, 0);
  541. if (netif_carrier_ok(mp->dev)) {
  542. spin_lock(&mp->lock);
  543. __txq_maybe_wake(mp->txq + mp->txq_primary);
  544. spin_unlock(&mp->lock);
  545. }
  546. }
  547. #endif
  548. rx = 0;
  549. for (i = 7; rx < budget && i >= 0; i--)
  550. if (mp->rxq_mask & (1 << i))
  551. rx += rxq_process(mp->rxq + i, budget - rx);
  552. if (rx < budget) {
  553. netif_rx_complete(mp->dev, napi);
  554. wrl(mp, INT_CAUSE(mp->port_num), 0);
  555. wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
  556. wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
  557. }
  558. return rx;
  559. }
  560. #endif
  561. /* tx ***********************************************************************/
  562. static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
  563. {
  564. int frag;
  565. for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
  566. skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
  567. if (fragp->size <= 8 && fragp->page_offset & 7)
  568. return 1;
  569. }
  570. return 0;
  571. }
  572. static int txq_alloc_desc_index(struct tx_queue *txq)
  573. {
  574. int tx_desc_curr;
  575. BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
  576. tx_desc_curr = txq->tx_curr_desc;
  577. txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
  578. BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
  579. return tx_desc_curr;
  580. }
  581. static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
  582. {
  583. int nr_frags = skb_shinfo(skb)->nr_frags;
  584. int frag;
  585. for (frag = 0; frag < nr_frags; frag++) {
  586. skb_frag_t *this_frag;
  587. int tx_index;
  588. struct tx_desc *desc;
  589. this_frag = &skb_shinfo(skb)->frags[frag];
  590. tx_index = txq_alloc_desc_index(txq);
  591. desc = &txq->tx_desc_area[tx_index];
  592. /*
  593. * The last fragment will generate an interrupt
  594. * which will free the skb on TX completion.
  595. */
  596. if (frag == nr_frags - 1) {
  597. desc->cmd_sts = BUFFER_OWNED_BY_DMA |
  598. ZERO_PADDING | TX_LAST_DESC |
  599. TX_ENABLE_INTERRUPT;
  600. txq->tx_skb[tx_index] = skb;
  601. } else {
  602. desc->cmd_sts = BUFFER_OWNED_BY_DMA;
  603. txq->tx_skb[tx_index] = NULL;
  604. }
  605. desc->l4i_chk = 0;
  606. desc->byte_cnt = this_frag->size;
  607. desc->buf_ptr = dma_map_page(NULL, this_frag->page,
  608. this_frag->page_offset,
  609. this_frag->size,
  610. DMA_TO_DEVICE);
  611. }
  612. }
  613. static inline __be16 sum16_as_be(__sum16 sum)
  614. {
  615. return (__force __be16)sum;
  616. }
  617. static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
  618. {
  619. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  620. int nr_frags = skb_shinfo(skb)->nr_frags;
  621. int tx_index;
  622. struct tx_desc *desc;
  623. u32 cmd_sts;
  624. int length;
  625. cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
  626. tx_index = txq_alloc_desc_index(txq);
  627. desc = &txq->tx_desc_area[tx_index];
  628. if (nr_frags) {
  629. txq_submit_frag_skb(txq, skb);
  630. length = skb_headlen(skb);
  631. txq->tx_skb[tx_index] = NULL;
  632. } else {
  633. cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
  634. length = skb->len;
  635. txq->tx_skb[tx_index] = skb;
  636. }
  637. desc->byte_cnt = length;
  638. desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
  639. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  640. int mac_hdr_len;
  641. BUG_ON(skb->protocol != htons(ETH_P_IP) &&
  642. skb->protocol != htons(ETH_P_8021Q));
  643. cmd_sts |= GEN_TCP_UDP_CHECKSUM |
  644. GEN_IP_V4_CHECKSUM |
  645. ip_hdr(skb)->ihl << TX_IHL_SHIFT;
  646. mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
  647. switch (mac_hdr_len - ETH_HLEN) {
  648. case 0:
  649. break;
  650. case 4:
  651. cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
  652. break;
  653. case 8:
  654. cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
  655. break;
  656. case 12:
  657. cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
  658. cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
  659. break;
  660. default:
  661. if (net_ratelimit())
  662. dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
  663. "mac header length is %d?!\n", mac_hdr_len);
  664. break;
  665. }
  666. switch (ip_hdr(skb)->protocol) {
  667. case IPPROTO_UDP:
  668. cmd_sts |= UDP_FRAME;
  669. desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
  670. break;
  671. case IPPROTO_TCP:
  672. desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
  673. break;
  674. default:
  675. BUG();
  676. }
  677. } else {
  678. /* Errata BTS #50, IHL must be 5 if no HW checksum */
  679. cmd_sts |= 5 << TX_IHL_SHIFT;
  680. desc->l4i_chk = 0;
  681. }
  682. /* ensure all other descriptors are written before first cmd_sts */
  683. wmb();
  684. desc->cmd_sts = cmd_sts;
  685. /* clear TX_END interrupt status */
  686. wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
  687. rdl(mp, INT_CAUSE(mp->port_num));
  688. /* ensure all descriptors are written before poking hardware */
  689. wmb();
  690. txq_enable(txq);
  691. txq->tx_desc_count += nr_frags + 1;
  692. }
  693. static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
  694. {
  695. struct mv643xx_eth_private *mp = netdev_priv(dev);
  696. struct net_device_stats *stats = &dev->stats;
  697. struct tx_queue *txq;
  698. unsigned long flags;
  699. if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
  700. stats->tx_dropped++;
  701. dev_printk(KERN_DEBUG, &dev->dev,
  702. "failed to linearize skb with tiny "
  703. "unaligned fragment\n");
  704. return NETDEV_TX_BUSY;
  705. }
  706. spin_lock_irqsave(&mp->lock, flags);
  707. txq = mp->txq + mp->txq_primary;
  708. if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
  709. spin_unlock_irqrestore(&mp->lock, flags);
  710. if (txq->index == mp->txq_primary && net_ratelimit())
  711. dev_printk(KERN_ERR, &dev->dev,
  712. "primary tx queue full?!\n");
  713. kfree_skb(skb);
  714. return NETDEV_TX_OK;
  715. }
  716. txq_submit_skb(txq, skb);
  717. stats->tx_bytes += skb->len;
  718. stats->tx_packets++;
  719. dev->trans_start = jiffies;
  720. if (txq->index == mp->txq_primary) {
  721. int entries_left;
  722. entries_left = txq->tx_ring_size - txq->tx_desc_count;
  723. if (entries_left < MAX_DESCS_PER_SKB)
  724. netif_stop_queue(dev);
  725. }
  726. spin_unlock_irqrestore(&mp->lock, flags);
  727. return NETDEV_TX_OK;
  728. }
  729. /* tx rate control **********************************************************/
  730. /*
  731. * Set total maximum TX rate (shared by all TX queues for this port)
  732. * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
  733. */
  734. static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
  735. {
  736. int token_rate;
  737. int mtu;
  738. int bucket_size;
  739. token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
  740. if (token_rate > 1023)
  741. token_rate = 1023;
  742. mtu = (mp->dev->mtu + 255) >> 8;
  743. if (mtu > 63)
  744. mtu = 63;
  745. bucket_size = (burst + 255) >> 8;
  746. if (bucket_size > 65535)
  747. bucket_size = 65535;
  748. if (mp->shared->tx_bw_control_moved) {
  749. wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
  750. wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
  751. wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
  752. } else {
  753. wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
  754. wrl(mp, TX_BW_MTU(mp->port_num), mtu);
  755. wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
  756. }
  757. }
  758. static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
  759. {
  760. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  761. int token_rate;
  762. int bucket_size;
  763. token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
  764. if (token_rate > 1023)
  765. token_rate = 1023;
  766. bucket_size = (burst + 255) >> 8;
  767. if (bucket_size > 65535)
  768. bucket_size = 65535;
  769. wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
  770. wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
  771. (bucket_size << 10) | token_rate);
  772. }
  773. static void txq_set_fixed_prio_mode(struct tx_queue *txq)
  774. {
  775. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  776. int off;
  777. u32 val;
  778. /*
  779. * Turn on fixed priority mode.
  780. */
  781. if (mp->shared->tx_bw_control_moved)
  782. off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
  783. else
  784. off = TXQ_FIX_PRIO_CONF(mp->port_num);
  785. val = rdl(mp, off);
  786. val |= 1 << txq->index;
  787. wrl(mp, off, val);
  788. }
  789. static void txq_set_wrr(struct tx_queue *txq, int weight)
  790. {
  791. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  792. int off;
  793. u32 val;
  794. /*
  795. * Turn off fixed priority mode.
  796. */
  797. if (mp->shared->tx_bw_control_moved)
  798. off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
  799. else
  800. off = TXQ_FIX_PRIO_CONF(mp->port_num);
  801. val = rdl(mp, off);
  802. val &= ~(1 << txq->index);
  803. wrl(mp, off, val);
  804. /*
  805. * Configure WRR weight for this queue.
  806. */
  807. off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
  808. val = rdl(mp, off);
  809. val = (val & ~0xff) | (weight & 0xff);
  810. wrl(mp, off, val);
  811. }
  812. /* mii management interface *************************************************/
  813. #define SMI_BUSY 0x10000000
  814. #define SMI_READ_VALID 0x08000000
  815. #define SMI_OPCODE_READ 0x04000000
  816. #define SMI_OPCODE_WRITE 0x00000000
  817. static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
  818. unsigned int reg, unsigned int *value)
  819. {
  820. void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
  821. unsigned long flags;
  822. int i;
  823. /* the SMI register is a shared resource */
  824. spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
  825. /* wait for the SMI register to become available */
  826. for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
  827. if (i == 1000) {
  828. printk("%s: PHY busy timeout\n", mp->dev->name);
  829. goto out;
  830. }
  831. udelay(10);
  832. }
  833. writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
  834. /* now wait for the data to be valid */
  835. for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
  836. if (i == 1000) {
  837. printk("%s: PHY read timeout\n", mp->dev->name);
  838. goto out;
  839. }
  840. udelay(10);
  841. }
  842. *value = readl(smi_reg) & 0xffff;
  843. out:
  844. spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
  845. }
  846. static void smi_reg_write(struct mv643xx_eth_private *mp,
  847. unsigned int addr,
  848. unsigned int reg, unsigned int value)
  849. {
  850. void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
  851. unsigned long flags;
  852. int i;
  853. /* the SMI register is a shared resource */
  854. spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
  855. /* wait for the SMI register to become available */
  856. for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
  857. if (i == 1000) {
  858. printk("%s: PHY busy timeout\n", mp->dev->name);
  859. goto out;
  860. }
  861. udelay(10);
  862. }
  863. writel(SMI_OPCODE_WRITE | (reg << 21) |
  864. (addr << 16) | (value & 0xffff), smi_reg);
  865. out:
  866. spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
  867. }
  868. /* mib counters *************************************************************/
  869. static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
  870. {
  871. return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
  872. }
  873. static void mib_counters_clear(struct mv643xx_eth_private *mp)
  874. {
  875. int i;
  876. for (i = 0; i < 0x80; i += 4)
  877. mib_read(mp, i);
  878. }
  879. static void mib_counters_update(struct mv643xx_eth_private *mp)
  880. {
  881. struct mib_counters *p = &mp->mib_counters;
  882. p->good_octets_received += mib_read(mp, 0x00);
  883. p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
  884. p->bad_octets_received += mib_read(mp, 0x08);
  885. p->internal_mac_transmit_err += mib_read(mp, 0x0c);
  886. p->good_frames_received += mib_read(mp, 0x10);
  887. p->bad_frames_received += mib_read(mp, 0x14);
  888. p->broadcast_frames_received += mib_read(mp, 0x18);
  889. p->multicast_frames_received += mib_read(mp, 0x1c);
  890. p->frames_64_octets += mib_read(mp, 0x20);
  891. p->frames_65_to_127_octets += mib_read(mp, 0x24);
  892. p->frames_128_to_255_octets += mib_read(mp, 0x28);
  893. p->frames_256_to_511_octets += mib_read(mp, 0x2c);
  894. p->frames_512_to_1023_octets += mib_read(mp, 0x30);
  895. p->frames_1024_to_max_octets += mib_read(mp, 0x34);
  896. p->good_octets_sent += mib_read(mp, 0x38);
  897. p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
  898. p->good_frames_sent += mib_read(mp, 0x40);
  899. p->excessive_collision += mib_read(mp, 0x44);
  900. p->multicast_frames_sent += mib_read(mp, 0x48);
  901. p->broadcast_frames_sent += mib_read(mp, 0x4c);
  902. p->unrec_mac_control_received += mib_read(mp, 0x50);
  903. p->fc_sent += mib_read(mp, 0x54);
  904. p->good_fc_received += mib_read(mp, 0x58);
  905. p->bad_fc_received += mib_read(mp, 0x5c);
  906. p->undersize_received += mib_read(mp, 0x60);
  907. p->fragments_received += mib_read(mp, 0x64);
  908. p->oversize_received += mib_read(mp, 0x68);
  909. p->jabber_received += mib_read(mp, 0x6c);
  910. p->mac_receive_error += mib_read(mp, 0x70);
  911. p->bad_crc_event += mib_read(mp, 0x74);
  912. p->collision += mib_read(mp, 0x78);
  913. p->late_collision += mib_read(mp, 0x7c);
  914. }
  915. /* ethtool ******************************************************************/
  916. struct mv643xx_eth_stats {
  917. char stat_string[ETH_GSTRING_LEN];
  918. int sizeof_stat;
  919. int netdev_off;
  920. int mp_off;
  921. };
  922. #define SSTAT(m) \
  923. { #m, FIELD_SIZEOF(struct net_device_stats, m), \
  924. offsetof(struct net_device, stats.m), -1 }
  925. #define MIBSTAT(m) \
  926. { #m, FIELD_SIZEOF(struct mib_counters, m), \
  927. -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
  928. static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
  929. SSTAT(rx_packets),
  930. SSTAT(tx_packets),
  931. SSTAT(rx_bytes),
  932. SSTAT(tx_bytes),
  933. SSTAT(rx_errors),
  934. SSTAT(tx_errors),
  935. SSTAT(rx_dropped),
  936. SSTAT(tx_dropped),
  937. MIBSTAT(good_octets_received),
  938. MIBSTAT(bad_octets_received),
  939. MIBSTAT(internal_mac_transmit_err),
  940. MIBSTAT(good_frames_received),
  941. MIBSTAT(bad_frames_received),
  942. MIBSTAT(broadcast_frames_received),
  943. MIBSTAT(multicast_frames_received),
  944. MIBSTAT(frames_64_octets),
  945. MIBSTAT(frames_65_to_127_octets),
  946. MIBSTAT(frames_128_to_255_octets),
  947. MIBSTAT(frames_256_to_511_octets),
  948. MIBSTAT(frames_512_to_1023_octets),
  949. MIBSTAT(frames_1024_to_max_octets),
  950. MIBSTAT(good_octets_sent),
  951. MIBSTAT(good_frames_sent),
  952. MIBSTAT(excessive_collision),
  953. MIBSTAT(multicast_frames_sent),
  954. MIBSTAT(broadcast_frames_sent),
  955. MIBSTAT(unrec_mac_control_received),
  956. MIBSTAT(fc_sent),
  957. MIBSTAT(good_fc_received),
  958. MIBSTAT(bad_fc_received),
  959. MIBSTAT(undersize_received),
  960. MIBSTAT(fragments_received),
  961. MIBSTAT(oversize_received),
  962. MIBSTAT(jabber_received),
  963. MIBSTAT(mac_receive_error),
  964. MIBSTAT(bad_crc_event),
  965. MIBSTAT(collision),
  966. MIBSTAT(late_collision),
  967. };
  968. static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  969. {
  970. struct mv643xx_eth_private *mp = netdev_priv(dev);
  971. int err;
  972. spin_lock_irq(&mp->lock);
  973. err = mii_ethtool_gset(&mp->mii, cmd);
  974. spin_unlock_irq(&mp->lock);
  975. /*
  976. * The MAC does not support 1000baseT_Half.
  977. */
  978. cmd->supported &= ~SUPPORTED_1000baseT_Half;
  979. cmd->advertising &= ~ADVERTISED_1000baseT_Half;
  980. return err;
  981. }
  982. static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
  983. {
  984. struct mv643xx_eth_private *mp = netdev_priv(dev);
  985. u32 port_status;
  986. port_status = rdl(mp, PORT_STATUS(mp->port_num));
  987. cmd->supported = SUPPORTED_MII;
  988. cmd->advertising = ADVERTISED_MII;
  989. switch (port_status & PORT_SPEED_MASK) {
  990. case PORT_SPEED_10:
  991. cmd->speed = SPEED_10;
  992. break;
  993. case PORT_SPEED_100:
  994. cmd->speed = SPEED_100;
  995. break;
  996. case PORT_SPEED_1000:
  997. cmd->speed = SPEED_1000;
  998. break;
  999. default:
  1000. cmd->speed = -1;
  1001. break;
  1002. }
  1003. cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
  1004. cmd->port = PORT_MII;
  1005. cmd->phy_address = 0;
  1006. cmd->transceiver = XCVR_INTERNAL;
  1007. cmd->autoneg = AUTONEG_DISABLE;
  1008. cmd->maxtxpkt = 1;
  1009. cmd->maxrxpkt = 1;
  1010. return 0;
  1011. }
  1012. static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1013. {
  1014. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1015. int err;
  1016. /*
  1017. * The MAC does not support 1000baseT_Half.
  1018. */
  1019. cmd->advertising &= ~ADVERTISED_1000baseT_Half;
  1020. spin_lock_irq(&mp->lock);
  1021. err = mii_ethtool_sset(&mp->mii, cmd);
  1022. spin_unlock_irq(&mp->lock);
  1023. return err;
  1024. }
  1025. static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
  1026. {
  1027. return -EINVAL;
  1028. }
  1029. static void mv643xx_eth_get_drvinfo(struct net_device *dev,
  1030. struct ethtool_drvinfo *drvinfo)
  1031. {
  1032. strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
  1033. strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
  1034. strncpy(drvinfo->fw_version, "N/A", 32);
  1035. strncpy(drvinfo->bus_info, "platform", 32);
  1036. drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
  1037. }
  1038. static int mv643xx_eth_nway_reset(struct net_device *dev)
  1039. {
  1040. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1041. return mii_nway_restart(&mp->mii);
  1042. }
  1043. static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
  1044. {
  1045. return -EINVAL;
  1046. }
  1047. static u32 mv643xx_eth_get_link(struct net_device *dev)
  1048. {
  1049. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1050. return mii_link_ok(&mp->mii);
  1051. }
  1052. static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
  1053. {
  1054. return 1;
  1055. }
  1056. static void mv643xx_eth_get_strings(struct net_device *dev,
  1057. uint32_t stringset, uint8_t *data)
  1058. {
  1059. int i;
  1060. if (stringset == ETH_SS_STATS) {
  1061. for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
  1062. memcpy(data + i * ETH_GSTRING_LEN,
  1063. mv643xx_eth_stats[i].stat_string,
  1064. ETH_GSTRING_LEN);
  1065. }
  1066. }
  1067. }
  1068. static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
  1069. struct ethtool_stats *stats,
  1070. uint64_t *data)
  1071. {
  1072. struct mv643xx_eth_private *mp = dev->priv;
  1073. int i;
  1074. mib_counters_update(mp);
  1075. for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
  1076. const struct mv643xx_eth_stats *stat;
  1077. void *p;
  1078. stat = mv643xx_eth_stats + i;
  1079. if (stat->netdev_off >= 0)
  1080. p = ((void *)mp->dev) + stat->netdev_off;
  1081. else
  1082. p = ((void *)mp) + stat->mp_off;
  1083. data[i] = (stat->sizeof_stat == 8) ?
  1084. *(uint64_t *)p : *(uint32_t *)p;
  1085. }
  1086. }
  1087. static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
  1088. {
  1089. if (sset == ETH_SS_STATS)
  1090. return ARRAY_SIZE(mv643xx_eth_stats);
  1091. return -EOPNOTSUPP;
  1092. }
  1093. static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
  1094. .get_settings = mv643xx_eth_get_settings,
  1095. .set_settings = mv643xx_eth_set_settings,
  1096. .get_drvinfo = mv643xx_eth_get_drvinfo,
  1097. .nway_reset = mv643xx_eth_nway_reset,
  1098. .get_link = mv643xx_eth_get_link,
  1099. .set_sg = ethtool_op_set_sg,
  1100. .get_strings = mv643xx_eth_get_strings,
  1101. .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
  1102. .get_sset_count = mv643xx_eth_get_sset_count,
  1103. };
  1104. static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
  1105. .get_settings = mv643xx_eth_get_settings_phyless,
  1106. .set_settings = mv643xx_eth_set_settings_phyless,
  1107. .get_drvinfo = mv643xx_eth_get_drvinfo,
  1108. .nway_reset = mv643xx_eth_nway_reset_phyless,
  1109. .get_link = mv643xx_eth_get_link_phyless,
  1110. .set_sg = ethtool_op_set_sg,
  1111. .get_strings = mv643xx_eth_get_strings,
  1112. .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
  1113. .get_sset_count = mv643xx_eth_get_sset_count,
  1114. };
  1115. /* address handling *********************************************************/
  1116. static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
  1117. {
  1118. unsigned int mac_h;
  1119. unsigned int mac_l;
  1120. mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
  1121. mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
  1122. addr[0] = (mac_h >> 24) & 0xff;
  1123. addr[1] = (mac_h >> 16) & 0xff;
  1124. addr[2] = (mac_h >> 8) & 0xff;
  1125. addr[3] = mac_h & 0xff;
  1126. addr[4] = (mac_l >> 8) & 0xff;
  1127. addr[5] = mac_l & 0xff;
  1128. }
  1129. static void init_mac_tables(struct mv643xx_eth_private *mp)
  1130. {
  1131. int i;
  1132. for (i = 0; i < 0x100; i += 4) {
  1133. wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
  1134. wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
  1135. }
  1136. for (i = 0; i < 0x10; i += 4)
  1137. wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
  1138. }
  1139. static void set_filter_table_entry(struct mv643xx_eth_private *mp,
  1140. int table, unsigned char entry)
  1141. {
  1142. unsigned int table_reg;
  1143. /* Set "accepts frame bit" at specified table entry */
  1144. table_reg = rdl(mp, table + (entry & 0xfc));
  1145. table_reg |= 0x01 << (8 * (entry & 3));
  1146. wrl(mp, table + (entry & 0xfc), table_reg);
  1147. }
  1148. static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
  1149. {
  1150. unsigned int mac_h;
  1151. unsigned int mac_l;
  1152. int table;
  1153. mac_l = (addr[4] << 8) | addr[5];
  1154. mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
  1155. wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
  1156. wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
  1157. table = UNICAST_TABLE(mp->port_num);
  1158. set_filter_table_entry(mp, table, addr[5] & 0x0f);
  1159. }
  1160. static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
  1161. {
  1162. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1163. /* +2 is for the offset of the HW addr type */
  1164. memcpy(dev->dev_addr, addr + 2, 6);
  1165. init_mac_tables(mp);
  1166. uc_addr_set(mp, dev->dev_addr);
  1167. return 0;
  1168. }
  1169. static int addr_crc(unsigned char *addr)
  1170. {
  1171. int crc = 0;
  1172. int i;
  1173. for (i = 0; i < 6; i++) {
  1174. int j;
  1175. crc = (crc ^ addr[i]) << 8;
  1176. for (j = 7; j >= 0; j--) {
  1177. if (crc & (0x100 << j))
  1178. crc ^= 0x107 << j;
  1179. }
  1180. }
  1181. return crc;
  1182. }
  1183. static void mv643xx_eth_set_rx_mode(struct net_device *dev)
  1184. {
  1185. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1186. u32 port_config;
  1187. struct dev_addr_list *addr;
  1188. int i;
  1189. port_config = rdl(mp, PORT_CONFIG(mp->port_num));
  1190. if (dev->flags & IFF_PROMISC)
  1191. port_config |= UNICAST_PROMISCUOUS_MODE;
  1192. else
  1193. port_config &= ~UNICAST_PROMISCUOUS_MODE;
  1194. wrl(mp, PORT_CONFIG(mp->port_num), port_config);
  1195. if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
  1196. int port_num = mp->port_num;
  1197. u32 accept = 0x01010101;
  1198. for (i = 0; i < 0x100; i += 4) {
  1199. wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
  1200. wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
  1201. }
  1202. return;
  1203. }
  1204. for (i = 0; i < 0x100; i += 4) {
  1205. wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
  1206. wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
  1207. }
  1208. for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
  1209. u8 *a = addr->da_addr;
  1210. int table;
  1211. if (addr->da_addrlen != 6)
  1212. continue;
  1213. if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
  1214. table = SPECIAL_MCAST_TABLE(mp->port_num);
  1215. set_filter_table_entry(mp, table, a[5]);
  1216. } else {
  1217. int crc = addr_crc(a);
  1218. table = OTHER_MCAST_TABLE(mp->port_num);
  1219. set_filter_table_entry(mp, table, crc);
  1220. }
  1221. }
  1222. }
  1223. /* rx/tx queue initialisation ***********************************************/
  1224. static int rxq_init(struct mv643xx_eth_private *mp, int index)
  1225. {
  1226. struct rx_queue *rxq = mp->rxq + index;
  1227. struct rx_desc *rx_desc;
  1228. int size;
  1229. int i;
  1230. rxq->index = index;
  1231. rxq->rx_ring_size = mp->default_rx_ring_size;
  1232. rxq->rx_desc_count = 0;
  1233. rxq->rx_curr_desc = 0;
  1234. rxq->rx_used_desc = 0;
  1235. size = rxq->rx_ring_size * sizeof(struct rx_desc);
  1236. if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
  1237. rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
  1238. mp->rx_desc_sram_size);
  1239. rxq->rx_desc_dma = mp->rx_desc_sram_addr;
  1240. } else {
  1241. rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
  1242. &rxq->rx_desc_dma,
  1243. GFP_KERNEL);
  1244. }
  1245. if (rxq->rx_desc_area == NULL) {
  1246. dev_printk(KERN_ERR, &mp->dev->dev,
  1247. "can't allocate rx ring (%d bytes)\n", size);
  1248. goto out;
  1249. }
  1250. memset(rxq->rx_desc_area, 0, size);
  1251. rxq->rx_desc_area_size = size;
  1252. rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
  1253. GFP_KERNEL);
  1254. if (rxq->rx_skb == NULL) {
  1255. dev_printk(KERN_ERR, &mp->dev->dev,
  1256. "can't allocate rx skb ring\n");
  1257. goto out_free;
  1258. }
  1259. rx_desc = (struct rx_desc *)rxq->rx_desc_area;
  1260. for (i = 0; i < rxq->rx_ring_size; i++) {
  1261. int nexti = (i + 1) % rxq->rx_ring_size;
  1262. rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
  1263. nexti * sizeof(struct rx_desc);
  1264. }
  1265. init_timer(&rxq->rx_oom);
  1266. rxq->rx_oom.data = (unsigned long)rxq;
  1267. rxq->rx_oom.function = rxq_refill_timer_wrapper;
  1268. return 0;
  1269. out_free:
  1270. if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
  1271. iounmap(rxq->rx_desc_area);
  1272. else
  1273. dma_free_coherent(NULL, size,
  1274. rxq->rx_desc_area,
  1275. rxq->rx_desc_dma);
  1276. out:
  1277. return -ENOMEM;
  1278. }
  1279. static void rxq_deinit(struct rx_queue *rxq)
  1280. {
  1281. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  1282. int i;
  1283. rxq_disable(rxq);
  1284. del_timer_sync(&rxq->rx_oom);
  1285. for (i = 0; i < rxq->rx_ring_size; i++) {
  1286. if (rxq->rx_skb[i]) {
  1287. dev_kfree_skb(rxq->rx_skb[i]);
  1288. rxq->rx_desc_count--;
  1289. }
  1290. }
  1291. if (rxq->rx_desc_count) {
  1292. dev_printk(KERN_ERR, &mp->dev->dev,
  1293. "error freeing rx ring -- %d skbs stuck\n",
  1294. rxq->rx_desc_count);
  1295. }
  1296. if (rxq->index == mp->rxq_primary &&
  1297. rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
  1298. iounmap(rxq->rx_desc_area);
  1299. else
  1300. dma_free_coherent(NULL, rxq->rx_desc_area_size,
  1301. rxq->rx_desc_area, rxq->rx_desc_dma);
  1302. kfree(rxq->rx_skb);
  1303. }
  1304. static int txq_init(struct mv643xx_eth_private *mp, int index)
  1305. {
  1306. struct tx_queue *txq = mp->txq + index;
  1307. struct tx_desc *tx_desc;
  1308. int size;
  1309. int i;
  1310. txq->index = index;
  1311. txq->tx_ring_size = mp->default_tx_ring_size;
  1312. txq->tx_desc_count = 0;
  1313. txq->tx_curr_desc = 0;
  1314. txq->tx_used_desc = 0;
  1315. size = txq->tx_ring_size * sizeof(struct tx_desc);
  1316. if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
  1317. txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
  1318. mp->tx_desc_sram_size);
  1319. txq->tx_desc_dma = mp->tx_desc_sram_addr;
  1320. } else {
  1321. txq->tx_desc_area = dma_alloc_coherent(NULL, size,
  1322. &txq->tx_desc_dma,
  1323. GFP_KERNEL);
  1324. }
  1325. if (txq->tx_desc_area == NULL) {
  1326. dev_printk(KERN_ERR, &mp->dev->dev,
  1327. "can't allocate tx ring (%d bytes)\n", size);
  1328. goto out;
  1329. }
  1330. memset(txq->tx_desc_area, 0, size);
  1331. txq->tx_desc_area_size = size;
  1332. txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
  1333. GFP_KERNEL);
  1334. if (txq->tx_skb == NULL) {
  1335. dev_printk(KERN_ERR, &mp->dev->dev,
  1336. "can't allocate tx skb ring\n");
  1337. goto out_free;
  1338. }
  1339. tx_desc = (struct tx_desc *)txq->tx_desc_area;
  1340. for (i = 0; i < txq->tx_ring_size; i++) {
  1341. struct tx_desc *txd = tx_desc + i;
  1342. int nexti = (i + 1) % txq->tx_ring_size;
  1343. txd->cmd_sts = 0;
  1344. txd->next_desc_ptr = txq->tx_desc_dma +
  1345. nexti * sizeof(struct tx_desc);
  1346. }
  1347. return 0;
  1348. out_free:
  1349. if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
  1350. iounmap(txq->tx_desc_area);
  1351. else
  1352. dma_free_coherent(NULL, size,
  1353. txq->tx_desc_area,
  1354. txq->tx_desc_dma);
  1355. out:
  1356. return -ENOMEM;
  1357. }
  1358. static void txq_reclaim(struct tx_queue *txq, int force)
  1359. {
  1360. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  1361. unsigned long flags;
  1362. spin_lock_irqsave(&mp->lock, flags);
  1363. while (txq->tx_desc_count > 0) {
  1364. int tx_index;
  1365. struct tx_desc *desc;
  1366. u32 cmd_sts;
  1367. struct sk_buff *skb;
  1368. dma_addr_t addr;
  1369. int count;
  1370. tx_index = txq->tx_used_desc;
  1371. desc = &txq->tx_desc_area[tx_index];
  1372. cmd_sts = desc->cmd_sts;
  1373. if (cmd_sts & BUFFER_OWNED_BY_DMA) {
  1374. if (!force)
  1375. break;
  1376. desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
  1377. }
  1378. txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
  1379. txq->tx_desc_count--;
  1380. addr = desc->buf_ptr;
  1381. count = desc->byte_cnt;
  1382. skb = txq->tx_skb[tx_index];
  1383. txq->tx_skb[tx_index] = NULL;
  1384. if (cmd_sts & ERROR_SUMMARY) {
  1385. dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
  1386. mp->dev->stats.tx_errors++;
  1387. }
  1388. /*
  1389. * Drop mp->lock while we free the skb.
  1390. */
  1391. spin_unlock_irqrestore(&mp->lock, flags);
  1392. if (cmd_sts & TX_FIRST_DESC)
  1393. dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
  1394. else
  1395. dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
  1396. if (skb)
  1397. dev_kfree_skb_irq(skb);
  1398. spin_lock_irqsave(&mp->lock, flags);
  1399. }
  1400. spin_unlock_irqrestore(&mp->lock, flags);
  1401. }
  1402. static void txq_deinit(struct tx_queue *txq)
  1403. {
  1404. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  1405. txq_disable(txq);
  1406. txq_reclaim(txq, 1);
  1407. BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
  1408. if (txq->index == mp->txq_primary &&
  1409. txq->tx_desc_area_size <= mp->tx_desc_sram_size)
  1410. iounmap(txq->tx_desc_area);
  1411. else
  1412. dma_free_coherent(NULL, txq->tx_desc_area_size,
  1413. txq->tx_desc_area, txq->tx_desc_dma);
  1414. kfree(txq->tx_skb);
  1415. }
  1416. /* netdev ops and related ***************************************************/
  1417. static void handle_link_event(struct mv643xx_eth_private *mp)
  1418. {
  1419. struct net_device *dev = mp->dev;
  1420. u32 port_status;
  1421. int speed;
  1422. int duplex;
  1423. int fc;
  1424. port_status = rdl(mp, PORT_STATUS(mp->port_num));
  1425. if (!(port_status & LINK_UP)) {
  1426. if (netif_carrier_ok(dev)) {
  1427. int i;
  1428. printk(KERN_INFO "%s: link down\n", dev->name);
  1429. netif_carrier_off(dev);
  1430. netif_stop_queue(dev);
  1431. for (i = 0; i < 8; i++) {
  1432. struct tx_queue *txq = mp->txq + i;
  1433. if (mp->txq_mask & (1 << i)) {
  1434. txq_reclaim(txq, 1);
  1435. txq_reset_hw_ptr(txq);
  1436. }
  1437. }
  1438. }
  1439. return;
  1440. }
  1441. switch (port_status & PORT_SPEED_MASK) {
  1442. case PORT_SPEED_10:
  1443. speed = 10;
  1444. break;
  1445. case PORT_SPEED_100:
  1446. speed = 100;
  1447. break;
  1448. case PORT_SPEED_1000:
  1449. speed = 1000;
  1450. break;
  1451. default:
  1452. speed = -1;
  1453. break;
  1454. }
  1455. duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
  1456. fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
  1457. printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
  1458. "flow control %sabled\n", dev->name,
  1459. speed, duplex ? "full" : "half",
  1460. fc ? "en" : "dis");
  1461. if (!netif_carrier_ok(dev)) {
  1462. netif_carrier_on(dev);
  1463. netif_wake_queue(dev);
  1464. }
  1465. }
  1466. static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
  1467. {
  1468. struct net_device *dev = (struct net_device *)dev_id;
  1469. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1470. u32 int_cause;
  1471. u32 int_cause_ext;
  1472. int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
  1473. (INT_TX_END | INT_RX | INT_EXT);
  1474. if (int_cause == 0)
  1475. return IRQ_NONE;
  1476. int_cause_ext = 0;
  1477. if (int_cause & INT_EXT) {
  1478. int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
  1479. & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
  1480. wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
  1481. }
  1482. if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
  1483. handle_link_event(mp);
  1484. /*
  1485. * RxBuffer or RxError set for any of the 8 queues?
  1486. */
  1487. #ifdef MV643XX_ETH_NAPI
  1488. if (int_cause & INT_RX) {
  1489. wrl(mp, INT_MASK(mp->port_num), 0x00000000);
  1490. rdl(mp, INT_MASK(mp->port_num));
  1491. netif_rx_schedule(dev, &mp->napi);
  1492. }
  1493. #else
  1494. if (int_cause & INT_RX) {
  1495. int i;
  1496. for (i = 7; i >= 0; i--)
  1497. if (mp->rxq_mask & (1 << i))
  1498. rxq_process(mp->rxq + i, INT_MAX);
  1499. }
  1500. #endif
  1501. /*
  1502. * TxBuffer or TxError set for any of the 8 queues?
  1503. */
  1504. if (int_cause_ext & INT_EXT_TX) {
  1505. int i;
  1506. for (i = 0; i < 8; i++)
  1507. if (mp->txq_mask & (1 << i))
  1508. txq_reclaim(mp->txq + i, 0);
  1509. /*
  1510. * Enough space again in the primary TX queue for a
  1511. * full packet?
  1512. */
  1513. if (netif_carrier_ok(dev)) {
  1514. spin_lock(&mp->lock);
  1515. __txq_maybe_wake(mp->txq + mp->txq_primary);
  1516. spin_unlock(&mp->lock);
  1517. }
  1518. }
  1519. /*
  1520. * Any TxEnd interrupts?
  1521. */
  1522. if (int_cause & INT_TX_END) {
  1523. int i;
  1524. wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
  1525. spin_lock(&mp->lock);
  1526. for (i = 0; i < 8; i++) {
  1527. struct tx_queue *txq = mp->txq + i;
  1528. u32 hw_desc_ptr;
  1529. u32 expected_ptr;
  1530. if ((int_cause & (INT_TX_END_0 << i)) == 0)
  1531. continue;
  1532. hw_desc_ptr =
  1533. rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
  1534. expected_ptr = (u32)txq->tx_desc_dma +
  1535. txq->tx_curr_desc * sizeof(struct tx_desc);
  1536. if (hw_desc_ptr != expected_ptr)
  1537. txq_enable(txq);
  1538. }
  1539. spin_unlock(&mp->lock);
  1540. }
  1541. return IRQ_HANDLED;
  1542. }
  1543. static void phy_reset(struct mv643xx_eth_private *mp)
  1544. {
  1545. unsigned int data;
  1546. smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
  1547. data |= BMCR_RESET;
  1548. smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
  1549. do {
  1550. udelay(1);
  1551. smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
  1552. } while (data & BMCR_RESET);
  1553. }
  1554. static void port_start(struct mv643xx_eth_private *mp)
  1555. {
  1556. u32 pscr;
  1557. int i;
  1558. /*
  1559. * Perform PHY reset, if there is a PHY.
  1560. */
  1561. if (mp->phy_addr != -1) {
  1562. struct ethtool_cmd cmd;
  1563. mv643xx_eth_get_settings(mp->dev, &cmd);
  1564. phy_reset(mp);
  1565. mv643xx_eth_set_settings(mp->dev, &cmd);
  1566. }
  1567. /*
  1568. * Configure basic link parameters.
  1569. */
  1570. pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
  1571. pscr |= SERIAL_PORT_ENABLE;
  1572. wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
  1573. pscr |= DO_NOT_FORCE_LINK_FAIL;
  1574. if (mp->phy_addr == -1)
  1575. pscr |= FORCE_LINK_PASS;
  1576. wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
  1577. wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
  1578. /*
  1579. * Configure TX path and queues.
  1580. */
  1581. tx_set_rate(mp, 1000000000, 16777216);
  1582. for (i = 0; i < 8; i++) {
  1583. struct tx_queue *txq = mp->txq + i;
  1584. if ((mp->txq_mask & (1 << i)) == 0)
  1585. continue;
  1586. txq_reset_hw_ptr(txq);
  1587. txq_set_rate(txq, 1000000000, 16777216);
  1588. txq_set_fixed_prio_mode(txq);
  1589. }
  1590. /*
  1591. * Add configured unicast address to address filter table.
  1592. */
  1593. uc_addr_set(mp, mp->dev->dev_addr);
  1594. /*
  1595. * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
  1596. * frames to RX queue #0.
  1597. */
  1598. wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
  1599. /*
  1600. * Treat BPDUs as normal multicasts, and disable partition mode.
  1601. */
  1602. wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
  1603. /*
  1604. * Enable the receive queues.
  1605. */
  1606. for (i = 0; i < 8; i++) {
  1607. struct rx_queue *rxq = mp->rxq + i;
  1608. int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
  1609. u32 addr;
  1610. if ((mp->rxq_mask & (1 << i)) == 0)
  1611. continue;
  1612. addr = (u32)rxq->rx_desc_dma;
  1613. addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
  1614. wrl(mp, off, addr);
  1615. rxq_enable(rxq);
  1616. }
  1617. }
  1618. static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
  1619. {
  1620. unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
  1621. u32 val;
  1622. val = rdl(mp, SDMA_CONFIG(mp->port_num));
  1623. if (mp->shared->extended_rx_coal_limit) {
  1624. if (coal > 0xffff)
  1625. coal = 0xffff;
  1626. val &= ~0x023fff80;
  1627. val |= (coal & 0x8000) << 10;
  1628. val |= (coal & 0x7fff) << 7;
  1629. } else {
  1630. if (coal > 0x3fff)
  1631. coal = 0x3fff;
  1632. val &= ~0x003fff00;
  1633. val |= (coal & 0x3fff) << 8;
  1634. }
  1635. wrl(mp, SDMA_CONFIG(mp->port_num), val);
  1636. }
  1637. static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
  1638. {
  1639. unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
  1640. if (coal > 0x3fff)
  1641. coal = 0x3fff;
  1642. wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
  1643. }
  1644. static int mv643xx_eth_open(struct net_device *dev)
  1645. {
  1646. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1647. int err;
  1648. int i;
  1649. wrl(mp, INT_CAUSE(mp->port_num), 0);
  1650. wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
  1651. rdl(mp, INT_CAUSE_EXT(mp->port_num));
  1652. err = request_irq(dev->irq, mv643xx_eth_irq,
  1653. IRQF_SHARED | IRQF_SAMPLE_RANDOM,
  1654. dev->name, dev);
  1655. if (err) {
  1656. dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
  1657. return -EAGAIN;
  1658. }
  1659. init_mac_tables(mp);
  1660. for (i = 0; i < 8; i++) {
  1661. if ((mp->rxq_mask & (1 << i)) == 0)
  1662. continue;
  1663. err = rxq_init(mp, i);
  1664. if (err) {
  1665. while (--i >= 0)
  1666. if (mp->rxq_mask & (1 << i))
  1667. rxq_deinit(mp->rxq + i);
  1668. goto out;
  1669. }
  1670. rxq_refill(mp->rxq + i);
  1671. }
  1672. for (i = 0; i < 8; i++) {
  1673. if ((mp->txq_mask & (1 << i)) == 0)
  1674. continue;
  1675. err = txq_init(mp, i);
  1676. if (err) {
  1677. while (--i >= 0)
  1678. if (mp->txq_mask & (1 << i))
  1679. txq_deinit(mp->txq + i);
  1680. goto out_free;
  1681. }
  1682. }
  1683. #ifdef MV643XX_ETH_NAPI
  1684. napi_enable(&mp->napi);
  1685. #endif
  1686. netif_carrier_off(dev);
  1687. netif_stop_queue(dev);
  1688. port_start(mp);
  1689. set_rx_coal(mp, 0);
  1690. set_tx_coal(mp, 0);
  1691. wrl(mp, INT_MASK_EXT(mp->port_num),
  1692. INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
  1693. wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
  1694. return 0;
  1695. out_free:
  1696. for (i = 0; i < 8; i++)
  1697. if (mp->rxq_mask & (1 << i))
  1698. rxq_deinit(mp->rxq + i);
  1699. out:
  1700. free_irq(dev->irq, dev);
  1701. return err;
  1702. }
  1703. static void port_reset(struct mv643xx_eth_private *mp)
  1704. {
  1705. unsigned int data;
  1706. int i;
  1707. for (i = 0; i < 8; i++) {
  1708. if (mp->rxq_mask & (1 << i))
  1709. rxq_disable(mp->rxq + i);
  1710. if (mp->txq_mask & (1 << i))
  1711. txq_disable(mp->txq + i);
  1712. }
  1713. while (1) {
  1714. u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
  1715. if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
  1716. break;
  1717. udelay(10);
  1718. }
  1719. /* Reset the Enable bit in the Configuration Register */
  1720. data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
  1721. data &= ~(SERIAL_PORT_ENABLE |
  1722. DO_NOT_FORCE_LINK_FAIL |
  1723. FORCE_LINK_PASS);
  1724. wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
  1725. }
  1726. static int mv643xx_eth_stop(struct net_device *dev)
  1727. {
  1728. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1729. int i;
  1730. wrl(mp, INT_MASK(mp->port_num), 0x00000000);
  1731. rdl(mp, INT_MASK(mp->port_num));
  1732. #ifdef MV643XX_ETH_NAPI
  1733. napi_disable(&mp->napi);
  1734. #endif
  1735. netif_carrier_off(dev);
  1736. netif_stop_queue(dev);
  1737. free_irq(dev->irq, dev);
  1738. port_reset(mp);
  1739. mib_counters_update(mp);
  1740. for (i = 0; i < 8; i++) {
  1741. if (mp->rxq_mask & (1 << i))
  1742. rxq_deinit(mp->rxq + i);
  1743. if (mp->txq_mask & (1 << i))
  1744. txq_deinit(mp->txq + i);
  1745. }
  1746. return 0;
  1747. }
  1748. static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1749. {
  1750. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1751. if (mp->phy_addr != -1)
  1752. return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
  1753. return -EOPNOTSUPP;
  1754. }
  1755. static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
  1756. {
  1757. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1758. if (new_mtu < 64 || new_mtu > 9500)
  1759. return -EINVAL;
  1760. dev->mtu = new_mtu;
  1761. tx_set_rate(mp, 1000000000, 16777216);
  1762. if (!netif_running(dev))
  1763. return 0;
  1764. /*
  1765. * Stop and then re-open the interface. This will allocate RX
  1766. * skbs of the new MTU.
  1767. * There is a possible danger that the open will not succeed,
  1768. * due to memory being full.
  1769. */
  1770. mv643xx_eth_stop(dev);
  1771. if (mv643xx_eth_open(dev)) {
  1772. dev_printk(KERN_ERR, &dev->dev,
  1773. "fatal error on re-opening device after "
  1774. "MTU change\n");
  1775. }
  1776. return 0;
  1777. }
  1778. static void tx_timeout_task(struct work_struct *ugly)
  1779. {
  1780. struct mv643xx_eth_private *mp;
  1781. mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
  1782. if (netif_running(mp->dev)) {
  1783. netif_stop_queue(mp->dev);
  1784. port_reset(mp);
  1785. port_start(mp);
  1786. __txq_maybe_wake(mp->txq + mp->txq_primary);
  1787. }
  1788. }
  1789. static void mv643xx_eth_tx_timeout(struct net_device *dev)
  1790. {
  1791. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1792. dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
  1793. schedule_work(&mp->tx_timeout_task);
  1794. }
  1795. #ifdef CONFIG_NET_POLL_CONTROLLER
  1796. static void mv643xx_eth_netpoll(struct net_device *dev)
  1797. {
  1798. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1799. wrl(mp, INT_MASK(mp->port_num), 0x00000000);
  1800. rdl(mp, INT_MASK(mp->port_num));
  1801. mv643xx_eth_irq(dev->irq, dev);
  1802. wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
  1803. }
  1804. #endif
  1805. static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
  1806. {
  1807. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1808. int val;
  1809. smi_reg_read(mp, addr, reg, &val);
  1810. return val;
  1811. }
  1812. static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
  1813. {
  1814. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1815. smi_reg_write(mp, addr, reg, val);
  1816. }
  1817. /* platform glue ************************************************************/
  1818. static void
  1819. mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
  1820. struct mbus_dram_target_info *dram)
  1821. {
  1822. void __iomem *base = msp->base;
  1823. u32 win_enable;
  1824. u32 win_protect;
  1825. int i;
  1826. for (i = 0; i < 6; i++) {
  1827. writel(0, base + WINDOW_BASE(i));
  1828. writel(0, base + WINDOW_SIZE(i));
  1829. if (i < 4)
  1830. writel(0, base + WINDOW_REMAP_HIGH(i));
  1831. }
  1832. win_enable = 0x3f;
  1833. win_protect = 0;
  1834. for (i = 0; i < dram->num_cs; i++) {
  1835. struct mbus_dram_window *cs = dram->cs + i;
  1836. writel((cs->base & 0xffff0000) |
  1837. (cs->mbus_attr << 8) |
  1838. dram->mbus_dram_target_id, base + WINDOW_BASE(i));
  1839. writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
  1840. win_enable &= ~(1 << i);
  1841. win_protect |= 3 << (2 * i);
  1842. }
  1843. writel(win_enable, base + WINDOW_BAR_ENABLE);
  1844. msp->win_protect = win_protect;
  1845. }
  1846. static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
  1847. {
  1848. /*
  1849. * Check whether we have a 14-bit coal limit field in bits
  1850. * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
  1851. * SDMA config register.
  1852. */
  1853. writel(0x02000000, msp->base + SDMA_CONFIG(0));
  1854. if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
  1855. msp->extended_rx_coal_limit = 1;
  1856. else
  1857. msp->extended_rx_coal_limit = 0;
  1858. /*
  1859. * Check whether the TX rate control registers are in the
  1860. * old or the new place.
  1861. */
  1862. writel(1, msp->base + TX_BW_MTU_MOVED(0));
  1863. if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
  1864. msp->tx_bw_control_moved = 1;
  1865. else
  1866. msp->tx_bw_control_moved = 0;
  1867. }
  1868. static int mv643xx_eth_shared_probe(struct platform_device *pdev)
  1869. {
  1870. static int mv643xx_eth_version_printed = 0;
  1871. struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
  1872. struct mv643xx_eth_shared_private *msp;
  1873. struct resource *res;
  1874. int ret;
  1875. if (!mv643xx_eth_version_printed++)
  1876. printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
  1877. "driver version %s\n", mv643xx_eth_driver_version);
  1878. ret = -EINVAL;
  1879. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1880. if (res == NULL)
  1881. goto out;
  1882. ret = -ENOMEM;
  1883. msp = kmalloc(sizeof(*msp), GFP_KERNEL);
  1884. if (msp == NULL)
  1885. goto out;
  1886. memset(msp, 0, sizeof(*msp));
  1887. msp->base = ioremap(res->start, res->end - res->start + 1);
  1888. if (msp->base == NULL)
  1889. goto out_free;
  1890. spin_lock_init(&msp->phy_lock);
  1891. /*
  1892. * (Re-)program MBUS remapping windows if we are asked to.
  1893. */
  1894. if (pd != NULL && pd->dram != NULL)
  1895. mv643xx_eth_conf_mbus_windows(msp, pd->dram);
  1896. /*
  1897. * Detect hardware parameters.
  1898. */
  1899. msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
  1900. infer_hw_params(msp);
  1901. platform_set_drvdata(pdev, msp);
  1902. return 0;
  1903. out_free:
  1904. kfree(msp);
  1905. out:
  1906. return ret;
  1907. }
  1908. static int mv643xx_eth_shared_remove(struct platform_device *pdev)
  1909. {
  1910. struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
  1911. iounmap(msp->base);
  1912. kfree(msp);
  1913. return 0;
  1914. }
  1915. static struct platform_driver mv643xx_eth_shared_driver = {
  1916. .probe = mv643xx_eth_shared_probe,
  1917. .remove = mv643xx_eth_shared_remove,
  1918. .driver = {
  1919. .name = MV643XX_ETH_SHARED_NAME,
  1920. .owner = THIS_MODULE,
  1921. },
  1922. };
  1923. static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
  1924. {
  1925. int addr_shift = 5 * mp->port_num;
  1926. u32 data;
  1927. data = rdl(mp, PHY_ADDR);
  1928. data &= ~(0x1f << addr_shift);
  1929. data |= (phy_addr & 0x1f) << addr_shift;
  1930. wrl(mp, PHY_ADDR, data);
  1931. }
  1932. static int phy_addr_get(struct mv643xx_eth_private *mp)
  1933. {
  1934. unsigned int data;
  1935. data = rdl(mp, PHY_ADDR);
  1936. return (data >> (5 * mp->port_num)) & 0x1f;
  1937. }
  1938. static void set_params(struct mv643xx_eth_private *mp,
  1939. struct mv643xx_eth_platform_data *pd)
  1940. {
  1941. struct net_device *dev = mp->dev;
  1942. if (is_valid_ether_addr(pd->mac_addr))
  1943. memcpy(dev->dev_addr, pd->mac_addr, 6);
  1944. else
  1945. uc_addr_get(mp, dev->dev_addr);
  1946. if (pd->phy_addr == -1) {
  1947. mp->shared_smi = NULL;
  1948. mp->phy_addr = -1;
  1949. } else {
  1950. mp->shared_smi = mp->shared;
  1951. if (pd->shared_smi != NULL)
  1952. mp->shared_smi = platform_get_drvdata(pd->shared_smi);
  1953. if (pd->force_phy_addr || pd->phy_addr) {
  1954. mp->phy_addr = pd->phy_addr & 0x3f;
  1955. phy_addr_set(mp, mp->phy_addr);
  1956. } else {
  1957. mp->phy_addr = phy_addr_get(mp);
  1958. }
  1959. }
  1960. mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
  1961. if (pd->rx_queue_size)
  1962. mp->default_rx_ring_size = pd->rx_queue_size;
  1963. mp->rx_desc_sram_addr = pd->rx_sram_addr;
  1964. mp->rx_desc_sram_size = pd->rx_sram_size;
  1965. if (pd->rx_queue_mask)
  1966. mp->rxq_mask = pd->rx_queue_mask;
  1967. else
  1968. mp->rxq_mask = 0x01;
  1969. mp->rxq_primary = fls(mp->rxq_mask) - 1;
  1970. mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
  1971. if (pd->tx_queue_size)
  1972. mp->default_tx_ring_size = pd->tx_queue_size;
  1973. mp->tx_desc_sram_addr = pd->tx_sram_addr;
  1974. mp->tx_desc_sram_size = pd->tx_sram_size;
  1975. if (pd->tx_queue_mask)
  1976. mp->txq_mask = pd->tx_queue_mask;
  1977. else
  1978. mp->txq_mask = 0x01;
  1979. mp->txq_primary = fls(mp->txq_mask) - 1;
  1980. }
  1981. static int phy_detect(struct mv643xx_eth_private *mp)
  1982. {
  1983. unsigned int data;
  1984. unsigned int data2;
  1985. smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
  1986. smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
  1987. smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
  1988. if (((data ^ data2) & BMCR_ANENABLE) == 0)
  1989. return -ENODEV;
  1990. smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
  1991. return 0;
  1992. }
  1993. static int phy_init(struct mv643xx_eth_private *mp,
  1994. struct mv643xx_eth_platform_data *pd)
  1995. {
  1996. struct ethtool_cmd cmd;
  1997. int err;
  1998. err = phy_detect(mp);
  1999. if (err) {
  2000. dev_printk(KERN_INFO, &mp->dev->dev,
  2001. "no PHY detected at addr %d\n", mp->phy_addr);
  2002. return err;
  2003. }
  2004. phy_reset(mp);
  2005. mp->mii.phy_id = mp->phy_addr;
  2006. mp->mii.phy_id_mask = 0x3f;
  2007. mp->mii.reg_num_mask = 0x1f;
  2008. mp->mii.dev = mp->dev;
  2009. mp->mii.mdio_read = mv643xx_eth_mdio_read;
  2010. mp->mii.mdio_write = mv643xx_eth_mdio_write;
  2011. mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
  2012. memset(&cmd, 0, sizeof(cmd));
  2013. cmd.port = PORT_MII;
  2014. cmd.transceiver = XCVR_INTERNAL;
  2015. cmd.phy_address = mp->phy_addr;
  2016. if (pd->speed == 0) {
  2017. cmd.autoneg = AUTONEG_ENABLE;
  2018. cmd.speed = SPEED_100;
  2019. cmd.advertising = ADVERTISED_10baseT_Half |
  2020. ADVERTISED_10baseT_Full |
  2021. ADVERTISED_100baseT_Half |
  2022. ADVERTISED_100baseT_Full;
  2023. if (mp->mii.supports_gmii)
  2024. cmd.advertising |= ADVERTISED_1000baseT_Full;
  2025. } else {
  2026. cmd.autoneg = AUTONEG_DISABLE;
  2027. cmd.speed = pd->speed;
  2028. cmd.duplex = pd->duplex;
  2029. }
  2030. mv643xx_eth_set_settings(mp->dev, &cmd);
  2031. return 0;
  2032. }
  2033. static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
  2034. {
  2035. u32 pscr;
  2036. pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
  2037. if (pscr & SERIAL_PORT_ENABLE) {
  2038. pscr &= ~SERIAL_PORT_ENABLE;
  2039. wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
  2040. }
  2041. pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
  2042. if (mp->phy_addr == -1) {
  2043. pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
  2044. if (speed == SPEED_1000)
  2045. pscr |= SET_GMII_SPEED_TO_1000;
  2046. else if (speed == SPEED_100)
  2047. pscr |= SET_MII_SPEED_TO_100;
  2048. pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
  2049. pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
  2050. if (duplex == DUPLEX_FULL)
  2051. pscr |= SET_FULL_DUPLEX_MODE;
  2052. }
  2053. wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
  2054. }
  2055. static int mv643xx_eth_probe(struct platform_device *pdev)
  2056. {
  2057. struct mv643xx_eth_platform_data *pd;
  2058. struct mv643xx_eth_private *mp;
  2059. struct net_device *dev;
  2060. struct resource *res;
  2061. DECLARE_MAC_BUF(mac);
  2062. int err;
  2063. pd = pdev->dev.platform_data;
  2064. if (pd == NULL) {
  2065. dev_printk(KERN_ERR, &pdev->dev,
  2066. "no mv643xx_eth_platform_data\n");
  2067. return -ENODEV;
  2068. }
  2069. if (pd->shared == NULL) {
  2070. dev_printk(KERN_ERR, &pdev->dev,
  2071. "no mv643xx_eth_platform_data->shared\n");
  2072. return -ENODEV;
  2073. }
  2074. dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
  2075. if (!dev)
  2076. return -ENOMEM;
  2077. mp = netdev_priv(dev);
  2078. platform_set_drvdata(pdev, mp);
  2079. mp->shared = platform_get_drvdata(pd->shared);
  2080. mp->port_num = pd->port_number;
  2081. mp->dev = dev;
  2082. #ifdef MV643XX_ETH_NAPI
  2083. netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
  2084. #endif
  2085. set_params(mp, pd);
  2086. spin_lock_init(&mp->lock);
  2087. mib_counters_clear(mp);
  2088. INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
  2089. if (mp->phy_addr != -1) {
  2090. err = phy_init(mp, pd);
  2091. if (err)
  2092. goto out;
  2093. SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
  2094. } else {
  2095. SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
  2096. }
  2097. init_pscr(mp, pd->speed, pd->duplex);
  2098. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  2099. BUG_ON(!res);
  2100. dev->irq = res->start;
  2101. dev->hard_start_xmit = mv643xx_eth_xmit;
  2102. dev->open = mv643xx_eth_open;
  2103. dev->stop = mv643xx_eth_stop;
  2104. dev->set_multicast_list = mv643xx_eth_set_rx_mode;
  2105. dev->set_mac_address = mv643xx_eth_set_mac_address;
  2106. dev->do_ioctl = mv643xx_eth_ioctl;
  2107. dev->change_mtu = mv643xx_eth_change_mtu;
  2108. dev->tx_timeout = mv643xx_eth_tx_timeout;
  2109. #ifdef CONFIG_NET_POLL_CONTROLLER
  2110. dev->poll_controller = mv643xx_eth_netpoll;
  2111. #endif
  2112. dev->watchdog_timeo = 2 * HZ;
  2113. dev->base_addr = 0;
  2114. #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
  2115. /*
  2116. * Zero copy can only work if we use Discovery II memory. Else, we will
  2117. * have to map the buffers to ISA memory which is only 16 MB
  2118. */
  2119. dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
  2120. dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
  2121. #endif
  2122. SET_NETDEV_DEV(dev, &pdev->dev);
  2123. if (mp->shared->win_protect)
  2124. wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
  2125. err = register_netdev(dev);
  2126. if (err)
  2127. goto out;
  2128. dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
  2129. mp->port_num, print_mac(mac, dev->dev_addr));
  2130. if (dev->features & NETIF_F_SG)
  2131. dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
  2132. if (dev->features & NETIF_F_IP_CSUM)
  2133. dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
  2134. #ifdef MV643XX_ETH_NAPI
  2135. dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
  2136. #endif
  2137. if (mp->tx_desc_sram_size > 0)
  2138. dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
  2139. return 0;
  2140. out:
  2141. free_netdev(dev);
  2142. return err;
  2143. }
  2144. static int mv643xx_eth_remove(struct platform_device *pdev)
  2145. {
  2146. struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
  2147. unregister_netdev(mp->dev);
  2148. flush_scheduled_work();
  2149. free_netdev(mp->dev);
  2150. platform_set_drvdata(pdev, NULL);
  2151. return 0;
  2152. }
  2153. static void mv643xx_eth_shutdown(struct platform_device *pdev)
  2154. {
  2155. struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
  2156. /* Mask all interrupts on ethernet port */
  2157. wrl(mp, INT_MASK(mp->port_num), 0);
  2158. rdl(mp, INT_MASK(mp->port_num));
  2159. if (netif_running(mp->dev))
  2160. port_reset(mp);
  2161. }
  2162. static struct platform_driver mv643xx_eth_driver = {
  2163. .probe = mv643xx_eth_probe,
  2164. .remove = mv643xx_eth_remove,
  2165. .shutdown = mv643xx_eth_shutdown,
  2166. .driver = {
  2167. .name = MV643XX_ETH_NAME,
  2168. .owner = THIS_MODULE,
  2169. },
  2170. };
  2171. static int __init mv643xx_eth_init_module(void)
  2172. {
  2173. int rc;
  2174. rc = platform_driver_register(&mv643xx_eth_shared_driver);
  2175. if (!rc) {
  2176. rc = platform_driver_register(&mv643xx_eth_driver);
  2177. if (rc)
  2178. platform_driver_unregister(&mv643xx_eth_shared_driver);
  2179. }
  2180. return rc;
  2181. }
  2182. module_init(mv643xx_eth_init_module);
  2183. static void __exit mv643xx_eth_cleanup_module(void)
  2184. {
  2185. platform_driver_unregister(&mv643xx_eth_driver);
  2186. platform_driver_unregister(&mv643xx_eth_shared_driver);
  2187. }
  2188. module_exit(mv643xx_eth_cleanup_module);
  2189. MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
  2190. "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
  2191. MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
  2192. MODULE_LICENSE("GPL");
  2193. MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
  2194. MODULE_ALIAS("platform:" MV643XX_ETH_NAME);