gianfar.c 56 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121
  1. /*
  2. * drivers/net/gianfar.c
  3. *
  4. * Gianfar Ethernet Driver
  5. * This driver is designed for the non-CPM ethernet controllers
  6. * on the 85xx and 83xx family of integrated processors
  7. * Based on 8260_io/fcc_enet.c
  8. *
  9. * Author: Andy Fleming
  10. * Maintainer: Kumar Gala
  11. *
  12. * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13. * Copyright (c) 2007 MontaVista Software, Inc.
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * Gianfar: AKA Lambda Draconis, "Dragon"
  21. * RA 11 31 24.2
  22. * Dec +69 19 52
  23. * V 3.84
  24. * B-V +1.62
  25. *
  26. * Theory of operation
  27. *
  28. * The driver is initialized through platform_device. Structures which
  29. * define the configuration needed by the board are defined in a
  30. * board structure in arch/ppc/platforms (though I do not
  31. * discount the possibility that other architectures could one
  32. * day be supported.
  33. *
  34. * The Gianfar Ethernet Controller uses a ring of buffer
  35. * descriptors. The beginning is indicated by a register
  36. * pointing to the physical address of the start of the ring.
  37. * The end is determined by a "wrap" bit being set in the
  38. * last descriptor of the ring.
  39. *
  40. * When a packet is received, the RXF bit in the
  41. * IEVENT register is set, triggering an interrupt when the
  42. * corresponding bit in the IMASK register is also set (if
  43. * interrupt coalescing is active, then the interrupt may not
  44. * happen immediately, but will wait until either a set number
  45. * of frames or amount of time have passed). In NAPI, the
  46. * interrupt handler will signal there is work to be done, and
  47. * exit. This method will start at the last known empty
  48. * descriptor, and process every subsequent descriptor until there
  49. * are none left with data (NAPI will stop after a set number of
  50. * packets to give time to other tasks, but will eventually
  51. * process all the packets). The data arrives inside a
  52. * pre-allocated skb, and so after the skb is passed up to the
  53. * stack, a new skb must be allocated, and the address field in
  54. * the buffer descriptor must be updated to indicate this new
  55. * skb.
  56. *
  57. * When the kernel requests that a packet be transmitted, the
  58. * driver starts where it left off last time, and points the
  59. * descriptor at the buffer which was passed in. The driver
  60. * then informs the DMA engine that there are packets ready to
  61. * be transmitted. Once the controller is finished transmitting
  62. * the packet, an interrupt may be triggered (under the same
  63. * conditions as for reception, but depending on the TXF bit).
  64. * The driver then cleans up the buffer.
  65. */
  66. #include <linux/kernel.h>
  67. #include <linux/string.h>
  68. #include <linux/errno.h>
  69. #include <linux/unistd.h>
  70. #include <linux/slab.h>
  71. #include <linux/interrupt.h>
  72. #include <linux/init.h>
  73. #include <linux/delay.h>
  74. #include <linux/netdevice.h>
  75. #include <linux/etherdevice.h>
  76. #include <linux/skbuff.h>
  77. #include <linux/if_vlan.h>
  78. #include <linux/spinlock.h>
  79. #include <linux/mm.h>
  80. #include <linux/platform_device.h>
  81. #include <linux/ip.h>
  82. #include <linux/tcp.h>
  83. #include <linux/udp.h>
  84. #include <linux/in.h>
  85. #include <asm/io.h>
  86. #include <asm/irq.h>
  87. #include <asm/uaccess.h>
  88. #include <linux/module.h>
  89. #include <linux/dma-mapping.h>
  90. #include <linux/crc32.h>
  91. #include <linux/mii.h>
  92. #include <linux/phy.h>
  93. #include "gianfar.h"
  94. #include "gianfar_mii.h"
  95. #define TX_TIMEOUT (1*HZ)
  96. #undef BRIEF_GFAR_ERRORS
  97. #undef VERBOSE_GFAR_ERRORS
  98. const char gfar_driver_name[] = "Gianfar Ethernet";
  99. const char gfar_driver_version[] = "1.3";
  100. static int gfar_enet_open(struct net_device *dev);
  101. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
  102. static void gfar_timeout(struct net_device *dev);
  103. static int gfar_close(struct net_device *dev);
  104. struct sk_buff *gfar_new_skb(struct net_device *dev);
  105. static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
  106. struct sk_buff *skb);
  107. static int gfar_set_mac_address(struct net_device *dev);
  108. static int gfar_change_mtu(struct net_device *dev, int new_mtu);
  109. static irqreturn_t gfar_error(int irq, void *dev_id);
  110. static irqreturn_t gfar_transmit(int irq, void *dev_id);
  111. static irqreturn_t gfar_interrupt(int irq, void *dev_id);
  112. static void adjust_link(struct net_device *dev);
  113. static void init_registers(struct net_device *dev);
  114. static int init_phy(struct net_device *dev);
  115. static int gfar_probe(struct platform_device *pdev);
  116. static int gfar_remove(struct platform_device *pdev);
  117. static void free_skb_resources(struct gfar_private *priv);
  118. static void gfar_set_multi(struct net_device *dev);
  119. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
  120. static void gfar_configure_serdes(struct net_device *dev);
  121. static int gfar_poll(struct napi_struct *napi, int budget);
  122. #ifdef CONFIG_NET_POLL_CONTROLLER
  123. static void gfar_netpoll(struct net_device *dev);
  124. #endif
  125. int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
  126. static int gfar_clean_tx_ring(struct net_device *dev);
  127. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
  128. static void gfar_vlan_rx_register(struct net_device *netdev,
  129. struct vlan_group *grp);
  130. void gfar_halt(struct net_device *dev);
  131. static void gfar_halt_nodisable(struct net_device *dev);
  132. void gfar_start(struct net_device *dev);
  133. static void gfar_clear_exact_match(struct net_device *dev);
  134. static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
  135. extern const struct ethtool_ops gfar_ethtool_ops;
  136. MODULE_AUTHOR("Freescale Semiconductor, Inc");
  137. MODULE_DESCRIPTION("Gianfar Ethernet Driver");
  138. MODULE_LICENSE("GPL");
  139. /* Returns 1 if incoming frames use an FCB */
  140. static inline int gfar_uses_fcb(struct gfar_private *priv)
  141. {
  142. return (priv->vlan_enable || priv->rx_csum_enable);
  143. }
  144. /* Set up the ethernet device structure, private data,
  145. * and anything else we need before we start */
  146. static int gfar_probe(struct platform_device *pdev)
  147. {
  148. u32 tempval;
  149. struct net_device *dev = NULL;
  150. struct gfar_private *priv = NULL;
  151. struct gianfar_platform_data *einfo;
  152. struct resource *r;
  153. int err = 0;
  154. DECLARE_MAC_BUF(mac);
  155. einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
  156. if (NULL == einfo) {
  157. printk(KERN_ERR "gfar %d: Missing additional data!\n",
  158. pdev->id);
  159. return -ENODEV;
  160. }
  161. /* Create an ethernet device instance */
  162. dev = alloc_etherdev(sizeof (*priv));
  163. if (NULL == dev)
  164. return -ENOMEM;
  165. priv = netdev_priv(dev);
  166. priv->dev = dev;
  167. /* Set the info in the priv to the current info */
  168. priv->einfo = einfo;
  169. /* fill out IRQ fields */
  170. if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  171. priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
  172. priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
  173. priv->interruptError = platform_get_irq_byname(pdev, "error");
  174. if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
  175. goto regs_fail;
  176. } else {
  177. priv->interruptTransmit = platform_get_irq(pdev, 0);
  178. if (priv->interruptTransmit < 0)
  179. goto regs_fail;
  180. }
  181. /* get a pointer to the register memory */
  182. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  183. priv->regs = ioremap(r->start, sizeof (struct gfar));
  184. if (NULL == priv->regs) {
  185. err = -ENOMEM;
  186. goto regs_fail;
  187. }
  188. spin_lock_init(&priv->txlock);
  189. spin_lock_init(&priv->rxlock);
  190. spin_lock_init(&priv->bflock);
  191. platform_set_drvdata(pdev, dev);
  192. /* Stop the DMA engine now, in case it was running before */
  193. /* (The firmware could have used it, and left it running). */
  194. /* To do this, we write Graceful Receive Stop and Graceful */
  195. /* Transmit Stop, and then wait until the corresponding bits */
  196. /* in IEVENT indicate the stops have completed. */
  197. tempval = gfar_read(&priv->regs->dmactrl);
  198. tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
  199. gfar_write(&priv->regs->dmactrl, tempval);
  200. tempval = gfar_read(&priv->regs->dmactrl);
  201. tempval |= (DMACTRL_GRS | DMACTRL_GTS);
  202. gfar_write(&priv->regs->dmactrl, tempval);
  203. while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
  204. cpu_relax();
  205. /* Reset MAC layer */
  206. gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  207. tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
  208. gfar_write(&priv->regs->maccfg1, tempval);
  209. /* Initialize MACCFG2. */
  210. gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
  211. /* Initialize ECNTRL */
  212. gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
  213. /* Copy the station address into the dev structure, */
  214. memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
  215. /* Set the dev->base_addr to the gfar reg region */
  216. dev->base_addr = (unsigned long) (priv->regs);
  217. SET_NETDEV_DEV(dev, &pdev->dev);
  218. /* Fill in the dev structure */
  219. dev->open = gfar_enet_open;
  220. dev->hard_start_xmit = gfar_start_xmit;
  221. dev->tx_timeout = gfar_timeout;
  222. dev->watchdog_timeo = TX_TIMEOUT;
  223. netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
  224. #ifdef CONFIG_NET_POLL_CONTROLLER
  225. dev->poll_controller = gfar_netpoll;
  226. #endif
  227. dev->stop = gfar_close;
  228. dev->change_mtu = gfar_change_mtu;
  229. dev->mtu = 1500;
  230. dev->set_multicast_list = gfar_set_multi;
  231. dev->ethtool_ops = &gfar_ethtool_ops;
  232. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
  233. priv->rx_csum_enable = 1;
  234. dev->features |= NETIF_F_IP_CSUM;
  235. } else
  236. priv->rx_csum_enable = 0;
  237. priv->vlgrp = NULL;
  238. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
  239. dev->vlan_rx_register = gfar_vlan_rx_register;
  240. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  241. priv->vlan_enable = 1;
  242. }
  243. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
  244. priv->extended_hash = 1;
  245. priv->hash_width = 9;
  246. priv->hash_regs[0] = &priv->regs->igaddr0;
  247. priv->hash_regs[1] = &priv->regs->igaddr1;
  248. priv->hash_regs[2] = &priv->regs->igaddr2;
  249. priv->hash_regs[3] = &priv->regs->igaddr3;
  250. priv->hash_regs[4] = &priv->regs->igaddr4;
  251. priv->hash_regs[5] = &priv->regs->igaddr5;
  252. priv->hash_regs[6] = &priv->regs->igaddr6;
  253. priv->hash_regs[7] = &priv->regs->igaddr7;
  254. priv->hash_regs[8] = &priv->regs->gaddr0;
  255. priv->hash_regs[9] = &priv->regs->gaddr1;
  256. priv->hash_regs[10] = &priv->regs->gaddr2;
  257. priv->hash_regs[11] = &priv->regs->gaddr3;
  258. priv->hash_regs[12] = &priv->regs->gaddr4;
  259. priv->hash_regs[13] = &priv->regs->gaddr5;
  260. priv->hash_regs[14] = &priv->regs->gaddr6;
  261. priv->hash_regs[15] = &priv->regs->gaddr7;
  262. } else {
  263. priv->extended_hash = 0;
  264. priv->hash_width = 8;
  265. priv->hash_regs[0] = &priv->regs->gaddr0;
  266. priv->hash_regs[1] = &priv->regs->gaddr1;
  267. priv->hash_regs[2] = &priv->regs->gaddr2;
  268. priv->hash_regs[3] = &priv->regs->gaddr3;
  269. priv->hash_regs[4] = &priv->regs->gaddr4;
  270. priv->hash_regs[5] = &priv->regs->gaddr5;
  271. priv->hash_regs[6] = &priv->regs->gaddr6;
  272. priv->hash_regs[7] = &priv->regs->gaddr7;
  273. }
  274. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
  275. priv->padding = DEFAULT_PADDING;
  276. else
  277. priv->padding = 0;
  278. if (dev->features & NETIF_F_IP_CSUM)
  279. dev->hard_header_len += GMAC_FCB_LEN;
  280. priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
  281. priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
  282. priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
  283. priv->txcoalescing = DEFAULT_TX_COALESCE;
  284. priv->txcount = DEFAULT_TXCOUNT;
  285. priv->txtime = DEFAULT_TXTIME;
  286. priv->rxcoalescing = DEFAULT_RX_COALESCE;
  287. priv->rxcount = DEFAULT_RXCOUNT;
  288. priv->rxtime = DEFAULT_RXTIME;
  289. /* Enable most messages by default */
  290. priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  291. err = register_netdev(dev);
  292. if (err) {
  293. printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
  294. dev->name);
  295. goto register_fail;
  296. }
  297. /* Create all the sysfs files */
  298. gfar_init_sysfs(dev);
  299. /* Print out the device info */
  300. printk(KERN_INFO DEVICE_NAME "%s\n",
  301. dev->name, print_mac(mac, dev->dev_addr));
  302. /* Even more device info helps when determining which kernel */
  303. /* provided which set of benchmarks. */
  304. printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
  305. printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
  306. dev->name, priv->rx_ring_size, priv->tx_ring_size);
  307. return 0;
  308. register_fail:
  309. iounmap(priv->regs);
  310. regs_fail:
  311. free_netdev(dev);
  312. return err;
  313. }
  314. static int gfar_remove(struct platform_device *pdev)
  315. {
  316. struct net_device *dev = platform_get_drvdata(pdev);
  317. struct gfar_private *priv = netdev_priv(dev);
  318. platform_set_drvdata(pdev, NULL);
  319. iounmap(priv->regs);
  320. free_netdev(dev);
  321. return 0;
  322. }
  323. #ifdef CONFIG_PM
  324. static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
  325. {
  326. struct net_device *dev = platform_get_drvdata(pdev);
  327. struct gfar_private *priv = netdev_priv(dev);
  328. unsigned long flags;
  329. u32 tempval;
  330. int magic_packet = priv->wol_en &&
  331. (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  332. netif_device_detach(dev);
  333. if (netif_running(dev)) {
  334. spin_lock_irqsave(&priv->txlock, flags);
  335. spin_lock(&priv->rxlock);
  336. gfar_halt_nodisable(dev);
  337. /* Disable Tx, and Rx if wake-on-LAN is disabled. */
  338. tempval = gfar_read(&priv->regs->maccfg1);
  339. tempval &= ~MACCFG1_TX_EN;
  340. if (!magic_packet)
  341. tempval &= ~MACCFG1_RX_EN;
  342. gfar_write(&priv->regs->maccfg1, tempval);
  343. spin_unlock(&priv->rxlock);
  344. spin_unlock_irqrestore(&priv->txlock, flags);
  345. napi_disable(&priv->napi);
  346. if (magic_packet) {
  347. /* Enable interrupt on Magic Packet */
  348. gfar_write(&priv->regs->imask, IMASK_MAG);
  349. /* Enable Magic Packet mode */
  350. tempval = gfar_read(&priv->regs->maccfg2);
  351. tempval |= MACCFG2_MPEN;
  352. gfar_write(&priv->regs->maccfg2, tempval);
  353. } else {
  354. phy_stop(priv->phydev);
  355. }
  356. }
  357. return 0;
  358. }
  359. static int gfar_resume(struct platform_device *pdev)
  360. {
  361. struct net_device *dev = platform_get_drvdata(pdev);
  362. struct gfar_private *priv = netdev_priv(dev);
  363. unsigned long flags;
  364. u32 tempval;
  365. int magic_packet = priv->wol_en &&
  366. (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  367. if (!netif_running(dev)) {
  368. netif_device_attach(dev);
  369. return 0;
  370. }
  371. if (!magic_packet && priv->phydev)
  372. phy_start(priv->phydev);
  373. /* Disable Magic Packet mode, in case something
  374. * else woke us up.
  375. */
  376. spin_lock_irqsave(&priv->txlock, flags);
  377. spin_lock(&priv->rxlock);
  378. tempval = gfar_read(&priv->regs->maccfg2);
  379. tempval &= ~MACCFG2_MPEN;
  380. gfar_write(&priv->regs->maccfg2, tempval);
  381. gfar_start(dev);
  382. spin_unlock(&priv->rxlock);
  383. spin_unlock_irqrestore(&priv->txlock, flags);
  384. netif_device_attach(dev);
  385. napi_enable(&priv->napi);
  386. return 0;
  387. }
  388. #else
  389. #define gfar_suspend NULL
  390. #define gfar_resume NULL
  391. #endif
  392. /* Reads the controller's registers to determine what interface
  393. * connects it to the PHY.
  394. */
  395. static phy_interface_t gfar_get_interface(struct net_device *dev)
  396. {
  397. struct gfar_private *priv = netdev_priv(dev);
  398. u32 ecntrl = gfar_read(&priv->regs->ecntrl);
  399. if (ecntrl & ECNTRL_SGMII_MODE)
  400. return PHY_INTERFACE_MODE_SGMII;
  401. if (ecntrl & ECNTRL_TBI_MODE) {
  402. if (ecntrl & ECNTRL_REDUCED_MODE)
  403. return PHY_INTERFACE_MODE_RTBI;
  404. else
  405. return PHY_INTERFACE_MODE_TBI;
  406. }
  407. if (ecntrl & ECNTRL_REDUCED_MODE) {
  408. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  409. return PHY_INTERFACE_MODE_RMII;
  410. else {
  411. phy_interface_t interface = priv->einfo->interface;
  412. /*
  413. * This isn't autodetected right now, so it must
  414. * be set by the device tree or platform code.
  415. */
  416. if (interface == PHY_INTERFACE_MODE_RGMII_ID)
  417. return PHY_INTERFACE_MODE_RGMII_ID;
  418. return PHY_INTERFACE_MODE_RGMII;
  419. }
  420. }
  421. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
  422. return PHY_INTERFACE_MODE_GMII;
  423. return PHY_INTERFACE_MODE_MII;
  424. }
  425. /* Initializes driver's PHY state, and attaches to the PHY.
  426. * Returns 0 on success.
  427. */
  428. static int init_phy(struct net_device *dev)
  429. {
  430. struct gfar_private *priv = netdev_priv(dev);
  431. uint gigabit_support =
  432. priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
  433. SUPPORTED_1000baseT_Full : 0;
  434. struct phy_device *phydev;
  435. char phy_id[BUS_ID_SIZE];
  436. phy_interface_t interface;
  437. priv->oldlink = 0;
  438. priv->oldspeed = 0;
  439. priv->oldduplex = -1;
  440. snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
  441. interface = gfar_get_interface(dev);
  442. phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
  443. if (interface == PHY_INTERFACE_MODE_SGMII)
  444. gfar_configure_serdes(dev);
  445. if (IS_ERR(phydev)) {
  446. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  447. return PTR_ERR(phydev);
  448. }
  449. /* Remove any features not supported by the controller */
  450. phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
  451. phydev->advertising = phydev->supported;
  452. priv->phydev = phydev;
  453. return 0;
  454. }
  455. /*
  456. * Initialize TBI PHY interface for communicating with the
  457. * SERDES lynx PHY on the chip. We communicate with this PHY
  458. * through the MDIO bus on each controller, treating it as a
  459. * "normal" PHY at the address found in the TBIPA register. We assume
  460. * that the TBIPA register is valid. Either the MDIO bus code will set
  461. * it to a value that doesn't conflict with other PHYs on the bus, or the
  462. * value doesn't matter, as there are no other PHYs on the bus.
  463. */
  464. static void gfar_configure_serdes(struct net_device *dev)
  465. {
  466. struct gfar_private *priv = netdev_priv(dev);
  467. struct gfar_mii __iomem *regs =
  468. (void __iomem *)&priv->regs->gfar_mii_regs;
  469. int tbipa = gfar_read(&priv->regs->tbipa);
  470. /* Single clk mode, mii mode off(for serdes communication) */
  471. gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
  472. gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
  473. ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
  474. ADVERTISE_1000XPSE_ASYM);
  475. gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
  476. BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
  477. }
  478. static void init_registers(struct net_device *dev)
  479. {
  480. struct gfar_private *priv = netdev_priv(dev);
  481. /* Clear IEVENT */
  482. gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
  483. /* Initialize IMASK */
  484. gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
  485. /* Init hash registers to zero */
  486. gfar_write(&priv->regs->igaddr0, 0);
  487. gfar_write(&priv->regs->igaddr1, 0);
  488. gfar_write(&priv->regs->igaddr2, 0);
  489. gfar_write(&priv->regs->igaddr3, 0);
  490. gfar_write(&priv->regs->igaddr4, 0);
  491. gfar_write(&priv->regs->igaddr5, 0);
  492. gfar_write(&priv->regs->igaddr6, 0);
  493. gfar_write(&priv->regs->igaddr7, 0);
  494. gfar_write(&priv->regs->gaddr0, 0);
  495. gfar_write(&priv->regs->gaddr1, 0);
  496. gfar_write(&priv->regs->gaddr2, 0);
  497. gfar_write(&priv->regs->gaddr3, 0);
  498. gfar_write(&priv->regs->gaddr4, 0);
  499. gfar_write(&priv->regs->gaddr5, 0);
  500. gfar_write(&priv->regs->gaddr6, 0);
  501. gfar_write(&priv->regs->gaddr7, 0);
  502. /* Zero out the rmon mib registers if it has them */
  503. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
  504. memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
  505. /* Mask off the CAM interrupts */
  506. gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
  507. gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
  508. }
  509. /* Initialize the max receive buffer length */
  510. gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
  511. /* Initialize the Minimum Frame Length Register */
  512. gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
  513. }
  514. /* Halt the receive and transmit queues */
  515. static void gfar_halt_nodisable(struct net_device *dev)
  516. {
  517. struct gfar_private *priv = netdev_priv(dev);
  518. struct gfar __iomem *regs = priv->regs;
  519. u32 tempval;
  520. /* Mask all interrupts */
  521. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  522. /* Clear all interrupts */
  523. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  524. /* Stop the DMA, and wait for it to stop */
  525. tempval = gfar_read(&priv->regs->dmactrl);
  526. if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
  527. != (DMACTRL_GRS | DMACTRL_GTS)) {
  528. tempval |= (DMACTRL_GRS | DMACTRL_GTS);
  529. gfar_write(&priv->regs->dmactrl, tempval);
  530. while (!(gfar_read(&priv->regs->ievent) &
  531. (IEVENT_GRSC | IEVENT_GTSC)))
  532. cpu_relax();
  533. }
  534. }
  535. /* Halt the receive and transmit queues */
  536. void gfar_halt(struct net_device *dev)
  537. {
  538. struct gfar_private *priv = netdev_priv(dev);
  539. struct gfar __iomem *regs = priv->regs;
  540. u32 tempval;
  541. gfar_halt_nodisable(dev);
  542. /* Disable Rx and Tx */
  543. tempval = gfar_read(&regs->maccfg1);
  544. tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
  545. gfar_write(&regs->maccfg1, tempval);
  546. }
  547. void stop_gfar(struct net_device *dev)
  548. {
  549. struct gfar_private *priv = netdev_priv(dev);
  550. struct gfar __iomem *regs = priv->regs;
  551. unsigned long flags;
  552. phy_stop(priv->phydev);
  553. /* Lock it down */
  554. spin_lock_irqsave(&priv->txlock, flags);
  555. spin_lock(&priv->rxlock);
  556. gfar_halt(dev);
  557. spin_unlock(&priv->rxlock);
  558. spin_unlock_irqrestore(&priv->txlock, flags);
  559. /* Free the IRQs */
  560. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  561. free_irq(priv->interruptError, dev);
  562. free_irq(priv->interruptTransmit, dev);
  563. free_irq(priv->interruptReceive, dev);
  564. } else {
  565. free_irq(priv->interruptTransmit, dev);
  566. }
  567. free_skb_resources(priv);
  568. dma_free_coherent(&dev->dev,
  569. sizeof(struct txbd8)*priv->tx_ring_size
  570. + sizeof(struct rxbd8)*priv->rx_ring_size,
  571. priv->tx_bd_base,
  572. gfar_read(&regs->tbase0));
  573. }
  574. /* If there are any tx skbs or rx skbs still around, free them.
  575. * Then free tx_skbuff and rx_skbuff */
  576. static void free_skb_resources(struct gfar_private *priv)
  577. {
  578. struct rxbd8 *rxbdp;
  579. struct txbd8 *txbdp;
  580. int i;
  581. /* Go through all the buffer descriptors and free their data buffers */
  582. txbdp = priv->tx_bd_base;
  583. for (i = 0; i < priv->tx_ring_size; i++) {
  584. if (priv->tx_skbuff[i]) {
  585. dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
  586. txbdp->length,
  587. DMA_TO_DEVICE);
  588. dev_kfree_skb_any(priv->tx_skbuff[i]);
  589. priv->tx_skbuff[i] = NULL;
  590. }
  591. txbdp++;
  592. }
  593. kfree(priv->tx_skbuff);
  594. rxbdp = priv->rx_bd_base;
  595. /* rx_skbuff is not guaranteed to be allocated, so only
  596. * free it and its contents if it is allocated */
  597. if(priv->rx_skbuff != NULL) {
  598. for (i = 0; i < priv->rx_ring_size; i++) {
  599. if (priv->rx_skbuff[i]) {
  600. dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
  601. priv->rx_buffer_size,
  602. DMA_FROM_DEVICE);
  603. dev_kfree_skb_any(priv->rx_skbuff[i]);
  604. priv->rx_skbuff[i] = NULL;
  605. }
  606. rxbdp->status = 0;
  607. rxbdp->length = 0;
  608. rxbdp->bufPtr = 0;
  609. rxbdp++;
  610. }
  611. kfree(priv->rx_skbuff);
  612. }
  613. }
  614. void gfar_start(struct net_device *dev)
  615. {
  616. struct gfar_private *priv = netdev_priv(dev);
  617. struct gfar __iomem *regs = priv->regs;
  618. u32 tempval;
  619. /* Enable Rx and Tx in MACCFG1 */
  620. tempval = gfar_read(&regs->maccfg1);
  621. tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
  622. gfar_write(&regs->maccfg1, tempval);
  623. /* Initialize DMACTRL to have WWR and WOP */
  624. tempval = gfar_read(&priv->regs->dmactrl);
  625. tempval |= DMACTRL_INIT_SETTINGS;
  626. gfar_write(&priv->regs->dmactrl, tempval);
  627. /* Make sure we aren't stopped */
  628. tempval = gfar_read(&priv->regs->dmactrl);
  629. tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
  630. gfar_write(&priv->regs->dmactrl, tempval);
  631. /* Clear THLT/RHLT, so that the DMA starts polling now */
  632. gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
  633. gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
  634. /* Unmask the interrupts we look for */
  635. gfar_write(&regs->imask, IMASK_DEFAULT);
  636. }
  637. /* Bring the controller up and running */
  638. int startup_gfar(struct net_device *dev)
  639. {
  640. struct txbd8 *txbdp;
  641. struct rxbd8 *rxbdp;
  642. dma_addr_t addr = 0;
  643. unsigned long vaddr;
  644. int i;
  645. struct gfar_private *priv = netdev_priv(dev);
  646. struct gfar __iomem *regs = priv->regs;
  647. int err = 0;
  648. u32 rctrl = 0;
  649. u32 attrs = 0;
  650. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  651. /* Allocate memory for the buffer descriptors */
  652. vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
  653. sizeof (struct txbd8) * priv->tx_ring_size +
  654. sizeof (struct rxbd8) * priv->rx_ring_size,
  655. &addr, GFP_KERNEL);
  656. if (vaddr == 0) {
  657. if (netif_msg_ifup(priv))
  658. printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
  659. dev->name);
  660. return -ENOMEM;
  661. }
  662. priv->tx_bd_base = (struct txbd8 *) vaddr;
  663. /* enet DMA only understands physical addresses */
  664. gfar_write(&regs->tbase0, addr);
  665. /* Start the rx descriptor ring where the tx ring leaves off */
  666. addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
  667. vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
  668. priv->rx_bd_base = (struct rxbd8 *) vaddr;
  669. gfar_write(&regs->rbase0, addr);
  670. /* Setup the skbuff rings */
  671. priv->tx_skbuff =
  672. (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
  673. priv->tx_ring_size, GFP_KERNEL);
  674. if (NULL == priv->tx_skbuff) {
  675. if (netif_msg_ifup(priv))
  676. printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
  677. dev->name);
  678. err = -ENOMEM;
  679. goto tx_skb_fail;
  680. }
  681. for (i = 0; i < priv->tx_ring_size; i++)
  682. priv->tx_skbuff[i] = NULL;
  683. priv->rx_skbuff =
  684. (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
  685. priv->rx_ring_size, GFP_KERNEL);
  686. if (NULL == priv->rx_skbuff) {
  687. if (netif_msg_ifup(priv))
  688. printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
  689. dev->name);
  690. err = -ENOMEM;
  691. goto rx_skb_fail;
  692. }
  693. for (i = 0; i < priv->rx_ring_size; i++)
  694. priv->rx_skbuff[i] = NULL;
  695. /* Initialize some variables in our dev structure */
  696. priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
  697. priv->cur_rx = priv->rx_bd_base;
  698. priv->skb_curtx = priv->skb_dirtytx = 0;
  699. priv->skb_currx = 0;
  700. /* Initialize Transmit Descriptor Ring */
  701. txbdp = priv->tx_bd_base;
  702. for (i = 0; i < priv->tx_ring_size; i++) {
  703. txbdp->status = 0;
  704. txbdp->length = 0;
  705. txbdp->bufPtr = 0;
  706. txbdp++;
  707. }
  708. /* Set the last descriptor in the ring to indicate wrap */
  709. txbdp--;
  710. txbdp->status |= TXBD_WRAP;
  711. rxbdp = priv->rx_bd_base;
  712. for (i = 0; i < priv->rx_ring_size; i++) {
  713. struct sk_buff *skb;
  714. skb = gfar_new_skb(dev);
  715. if (!skb) {
  716. printk(KERN_ERR "%s: Can't allocate RX buffers\n",
  717. dev->name);
  718. goto err_rxalloc_fail;
  719. }
  720. priv->rx_skbuff[i] = skb;
  721. gfar_new_rxbdp(dev, rxbdp, skb);
  722. rxbdp++;
  723. }
  724. /* Set the last descriptor in the ring to wrap */
  725. rxbdp--;
  726. rxbdp->status |= RXBD_WRAP;
  727. /* If the device has multiple interrupts, register for
  728. * them. Otherwise, only register for the one */
  729. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  730. /* Install our interrupt handlers for Error,
  731. * Transmit, and Receive */
  732. if (request_irq(priv->interruptError, gfar_error,
  733. 0, "enet_error", dev) < 0) {
  734. if (netif_msg_intr(priv))
  735. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  736. dev->name, priv->interruptError);
  737. err = -1;
  738. goto err_irq_fail;
  739. }
  740. if (request_irq(priv->interruptTransmit, gfar_transmit,
  741. 0, "enet_tx", dev) < 0) {
  742. if (netif_msg_intr(priv))
  743. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  744. dev->name, priv->interruptTransmit);
  745. err = -1;
  746. goto tx_irq_fail;
  747. }
  748. if (request_irq(priv->interruptReceive, gfar_receive,
  749. 0, "enet_rx", dev) < 0) {
  750. if (netif_msg_intr(priv))
  751. printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
  752. dev->name, priv->interruptReceive);
  753. err = -1;
  754. goto rx_irq_fail;
  755. }
  756. } else {
  757. if (request_irq(priv->interruptTransmit, gfar_interrupt,
  758. 0, "gfar_interrupt", dev) < 0) {
  759. if (netif_msg_intr(priv))
  760. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  761. dev->name, priv->interruptError);
  762. err = -1;
  763. goto err_irq_fail;
  764. }
  765. }
  766. phy_start(priv->phydev);
  767. /* Configure the coalescing support */
  768. if (priv->txcoalescing)
  769. gfar_write(&regs->txic,
  770. mk_ic_value(priv->txcount, priv->txtime));
  771. else
  772. gfar_write(&regs->txic, 0);
  773. if (priv->rxcoalescing)
  774. gfar_write(&regs->rxic,
  775. mk_ic_value(priv->rxcount, priv->rxtime));
  776. else
  777. gfar_write(&regs->rxic, 0);
  778. if (priv->rx_csum_enable)
  779. rctrl |= RCTRL_CHECKSUMMING;
  780. if (priv->extended_hash) {
  781. rctrl |= RCTRL_EXTHASH;
  782. gfar_clear_exact_match(dev);
  783. rctrl |= RCTRL_EMEN;
  784. }
  785. if (priv->vlan_enable)
  786. rctrl |= RCTRL_VLAN;
  787. if (priv->padding) {
  788. rctrl &= ~RCTRL_PAL_MASK;
  789. rctrl |= RCTRL_PADDING(priv->padding);
  790. }
  791. /* Init rctrl based on our settings */
  792. gfar_write(&priv->regs->rctrl, rctrl);
  793. if (dev->features & NETIF_F_IP_CSUM)
  794. gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
  795. /* Set the extraction length and index */
  796. attrs = ATTRELI_EL(priv->rx_stash_size) |
  797. ATTRELI_EI(priv->rx_stash_index);
  798. gfar_write(&priv->regs->attreli, attrs);
  799. /* Start with defaults, and add stashing or locking
  800. * depending on the approprate variables */
  801. attrs = ATTR_INIT_SETTINGS;
  802. if (priv->bd_stash_en)
  803. attrs |= ATTR_BDSTASH;
  804. if (priv->rx_stash_size != 0)
  805. attrs |= ATTR_BUFSTASH;
  806. gfar_write(&priv->regs->attr, attrs);
  807. gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
  808. gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
  809. gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
  810. /* Start the controller */
  811. gfar_start(dev);
  812. return 0;
  813. rx_irq_fail:
  814. free_irq(priv->interruptTransmit, dev);
  815. tx_irq_fail:
  816. free_irq(priv->interruptError, dev);
  817. err_irq_fail:
  818. err_rxalloc_fail:
  819. rx_skb_fail:
  820. free_skb_resources(priv);
  821. tx_skb_fail:
  822. dma_free_coherent(&dev->dev,
  823. sizeof(struct txbd8)*priv->tx_ring_size
  824. + sizeof(struct rxbd8)*priv->rx_ring_size,
  825. priv->tx_bd_base,
  826. gfar_read(&regs->tbase0));
  827. return err;
  828. }
  829. /* Called when something needs to use the ethernet device */
  830. /* Returns 0 for success. */
  831. static int gfar_enet_open(struct net_device *dev)
  832. {
  833. struct gfar_private *priv = netdev_priv(dev);
  834. int err;
  835. napi_enable(&priv->napi);
  836. /* Initialize a bunch of registers */
  837. init_registers(dev);
  838. gfar_set_mac_address(dev);
  839. err = init_phy(dev);
  840. if(err) {
  841. napi_disable(&priv->napi);
  842. return err;
  843. }
  844. err = startup_gfar(dev);
  845. if (err) {
  846. napi_disable(&priv->napi);
  847. return err;
  848. }
  849. netif_start_queue(dev);
  850. return err;
  851. }
  852. static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
  853. {
  854. struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
  855. memset(fcb, 0, GMAC_FCB_LEN);
  856. return fcb;
  857. }
  858. static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
  859. {
  860. u8 flags = 0;
  861. /* If we're here, it's a IP packet with a TCP or UDP
  862. * payload. We set it to checksum, using a pseudo-header
  863. * we provide
  864. */
  865. flags = TXFCB_DEFAULT;
  866. /* Tell the controller what the protocol is */
  867. /* And provide the already calculated phcs */
  868. if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
  869. flags |= TXFCB_UDP;
  870. fcb->phcs = udp_hdr(skb)->check;
  871. } else
  872. fcb->phcs = tcp_hdr(skb)->check;
  873. /* l3os is the distance between the start of the
  874. * frame (skb->data) and the start of the IP hdr.
  875. * l4os is the distance between the start of the
  876. * l3 hdr and the l4 hdr */
  877. fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
  878. fcb->l4os = skb_network_header_len(skb);
  879. fcb->flags = flags;
  880. }
  881. void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
  882. {
  883. fcb->flags |= TXFCB_VLN;
  884. fcb->vlctl = vlan_tx_tag_get(skb);
  885. }
  886. /* This is called by the kernel when a frame is ready for transmission. */
  887. /* It is pointed to by the dev->hard_start_xmit function pointer */
  888. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
  889. {
  890. struct gfar_private *priv = netdev_priv(dev);
  891. struct txfcb *fcb = NULL;
  892. struct txbd8 *txbdp;
  893. u16 status;
  894. unsigned long flags;
  895. /* Update transmit stats */
  896. dev->stats.tx_bytes += skb->len;
  897. /* Lock priv now */
  898. spin_lock_irqsave(&priv->txlock, flags);
  899. /* Point at the first free tx descriptor */
  900. txbdp = priv->cur_tx;
  901. /* Clear all but the WRAP status flags */
  902. status = txbdp->status & TXBD_WRAP;
  903. /* Set up checksumming */
  904. if (likely((dev->features & NETIF_F_IP_CSUM)
  905. && (CHECKSUM_PARTIAL == skb->ip_summed))) {
  906. fcb = gfar_add_fcb(skb, txbdp);
  907. status |= TXBD_TOE;
  908. gfar_tx_checksum(skb, fcb);
  909. }
  910. if (priv->vlan_enable &&
  911. unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
  912. if (unlikely(NULL == fcb)) {
  913. fcb = gfar_add_fcb(skb, txbdp);
  914. status |= TXBD_TOE;
  915. }
  916. gfar_tx_vlan(skb, fcb);
  917. }
  918. /* Set buffer length and pointer */
  919. txbdp->length = skb->len;
  920. txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
  921. skb->len, DMA_TO_DEVICE);
  922. /* Save the skb pointer so we can free it later */
  923. priv->tx_skbuff[priv->skb_curtx] = skb;
  924. /* Update the current skb pointer (wrapping if this was the last) */
  925. priv->skb_curtx =
  926. (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
  927. /* Flag the BD as interrupt-causing */
  928. status |= TXBD_INTERRUPT;
  929. /* Flag the BD as ready to go, last in frame, and */
  930. /* in need of CRC */
  931. status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
  932. dev->trans_start = jiffies;
  933. /* The powerpc-specific eieio() is used, as wmb() has too strong
  934. * semantics (it requires synchronization between cacheable and
  935. * uncacheable mappings, which eieio doesn't provide and which we
  936. * don't need), thus requiring a more expensive sync instruction. At
  937. * some point, the set of architecture-independent barrier functions
  938. * should be expanded to include weaker barriers.
  939. */
  940. eieio();
  941. txbdp->status = status;
  942. /* If this was the last BD in the ring, the next one */
  943. /* is at the beginning of the ring */
  944. if (txbdp->status & TXBD_WRAP)
  945. txbdp = priv->tx_bd_base;
  946. else
  947. txbdp++;
  948. /* If the next BD still needs to be cleaned up, then the bds
  949. are full. We need to tell the kernel to stop sending us stuff. */
  950. if (txbdp == priv->dirty_tx) {
  951. netif_stop_queue(dev);
  952. dev->stats.tx_fifo_errors++;
  953. }
  954. /* Update the current txbd to the next one */
  955. priv->cur_tx = txbdp;
  956. /* Tell the DMA to go go go */
  957. gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
  958. /* Unlock priv */
  959. spin_unlock_irqrestore(&priv->txlock, flags);
  960. return 0;
  961. }
  962. /* Stops the kernel queue, and halts the controller */
  963. static int gfar_close(struct net_device *dev)
  964. {
  965. struct gfar_private *priv = netdev_priv(dev);
  966. napi_disable(&priv->napi);
  967. stop_gfar(dev);
  968. /* Disconnect from the PHY */
  969. phy_disconnect(priv->phydev);
  970. priv->phydev = NULL;
  971. netif_stop_queue(dev);
  972. return 0;
  973. }
  974. /* Changes the mac address if the controller is not running. */
  975. static int gfar_set_mac_address(struct net_device *dev)
  976. {
  977. gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
  978. return 0;
  979. }
  980. /* Enables and disables VLAN insertion/extraction */
  981. static void gfar_vlan_rx_register(struct net_device *dev,
  982. struct vlan_group *grp)
  983. {
  984. struct gfar_private *priv = netdev_priv(dev);
  985. unsigned long flags;
  986. u32 tempval;
  987. spin_lock_irqsave(&priv->rxlock, flags);
  988. priv->vlgrp = grp;
  989. if (grp) {
  990. /* Enable VLAN tag insertion */
  991. tempval = gfar_read(&priv->regs->tctrl);
  992. tempval |= TCTRL_VLINS;
  993. gfar_write(&priv->regs->tctrl, tempval);
  994. /* Enable VLAN tag extraction */
  995. tempval = gfar_read(&priv->regs->rctrl);
  996. tempval |= RCTRL_VLEX;
  997. gfar_write(&priv->regs->rctrl, tempval);
  998. } else {
  999. /* Disable VLAN tag insertion */
  1000. tempval = gfar_read(&priv->regs->tctrl);
  1001. tempval &= ~TCTRL_VLINS;
  1002. gfar_write(&priv->regs->tctrl, tempval);
  1003. /* Disable VLAN tag extraction */
  1004. tempval = gfar_read(&priv->regs->rctrl);
  1005. tempval &= ~RCTRL_VLEX;
  1006. gfar_write(&priv->regs->rctrl, tempval);
  1007. }
  1008. spin_unlock_irqrestore(&priv->rxlock, flags);
  1009. }
  1010. static int gfar_change_mtu(struct net_device *dev, int new_mtu)
  1011. {
  1012. int tempsize, tempval;
  1013. struct gfar_private *priv = netdev_priv(dev);
  1014. int oldsize = priv->rx_buffer_size;
  1015. int frame_size = new_mtu + ETH_HLEN;
  1016. if (priv->vlan_enable)
  1017. frame_size += VLAN_HLEN;
  1018. if (gfar_uses_fcb(priv))
  1019. frame_size += GMAC_FCB_LEN;
  1020. frame_size += priv->padding;
  1021. if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
  1022. if (netif_msg_drv(priv))
  1023. printk(KERN_ERR "%s: Invalid MTU setting\n",
  1024. dev->name);
  1025. return -EINVAL;
  1026. }
  1027. tempsize =
  1028. (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
  1029. INCREMENTAL_BUFFER_SIZE;
  1030. /* Only stop and start the controller if it isn't already
  1031. * stopped, and we changed something */
  1032. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  1033. stop_gfar(dev);
  1034. priv->rx_buffer_size = tempsize;
  1035. dev->mtu = new_mtu;
  1036. gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
  1037. gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
  1038. /* If the mtu is larger than the max size for standard
  1039. * ethernet frames (ie, a jumbo frame), then set maccfg2
  1040. * to allow huge frames, and to check the length */
  1041. tempval = gfar_read(&priv->regs->maccfg2);
  1042. if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
  1043. tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  1044. else
  1045. tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  1046. gfar_write(&priv->regs->maccfg2, tempval);
  1047. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  1048. startup_gfar(dev);
  1049. return 0;
  1050. }
  1051. /* gfar_timeout gets called when a packet has not been
  1052. * transmitted after a set amount of time.
  1053. * For now, assume that clearing out all the structures, and
  1054. * starting over will fix the problem. */
  1055. static void gfar_timeout(struct net_device *dev)
  1056. {
  1057. dev->stats.tx_errors++;
  1058. if (dev->flags & IFF_UP) {
  1059. stop_gfar(dev);
  1060. startup_gfar(dev);
  1061. }
  1062. netif_tx_schedule_all(dev);
  1063. }
  1064. /* Interrupt Handler for Transmit complete */
  1065. static int gfar_clean_tx_ring(struct net_device *dev)
  1066. {
  1067. struct txbd8 *bdp;
  1068. struct gfar_private *priv = netdev_priv(dev);
  1069. int howmany = 0;
  1070. bdp = priv->dirty_tx;
  1071. while ((bdp->status & TXBD_READY) == 0) {
  1072. /* If dirty_tx and cur_tx are the same, then either the */
  1073. /* ring is empty or full now (it could only be full in the beginning, */
  1074. /* obviously). If it is empty, we are done. */
  1075. if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
  1076. break;
  1077. howmany++;
  1078. /* Deferred means some collisions occurred during transmit, */
  1079. /* but we eventually sent the packet. */
  1080. if (bdp->status & TXBD_DEF)
  1081. dev->stats.collisions++;
  1082. /* Free the sk buffer associated with this TxBD */
  1083. dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
  1084. priv->tx_skbuff[priv->skb_dirtytx] = NULL;
  1085. priv->skb_dirtytx =
  1086. (priv->skb_dirtytx +
  1087. 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
  1088. /* Clean BD length for empty detection */
  1089. bdp->length = 0;
  1090. /* update bdp to point at next bd in the ring (wrapping if necessary) */
  1091. if (bdp->status & TXBD_WRAP)
  1092. bdp = priv->tx_bd_base;
  1093. else
  1094. bdp++;
  1095. /* Move dirty_tx to be the next bd */
  1096. priv->dirty_tx = bdp;
  1097. /* We freed a buffer, so now we can restart transmission */
  1098. if (netif_queue_stopped(dev))
  1099. netif_wake_queue(dev);
  1100. } /* while ((bdp->status & TXBD_READY) == 0) */
  1101. dev->stats.tx_packets += howmany;
  1102. return howmany;
  1103. }
  1104. /* Interrupt Handler for Transmit complete */
  1105. static irqreturn_t gfar_transmit(int irq, void *dev_id)
  1106. {
  1107. struct net_device *dev = (struct net_device *) dev_id;
  1108. struct gfar_private *priv = netdev_priv(dev);
  1109. /* Clear IEVENT */
  1110. gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
  1111. /* Lock priv */
  1112. spin_lock(&priv->txlock);
  1113. gfar_clean_tx_ring(dev);
  1114. /* If we are coalescing the interrupts, reset the timer */
  1115. /* Otherwise, clear it */
  1116. if (likely(priv->txcoalescing)) {
  1117. gfar_write(&priv->regs->txic, 0);
  1118. gfar_write(&priv->regs->txic,
  1119. mk_ic_value(priv->txcount, priv->txtime));
  1120. }
  1121. spin_unlock(&priv->txlock);
  1122. return IRQ_HANDLED;
  1123. }
  1124. static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
  1125. struct sk_buff *skb)
  1126. {
  1127. struct gfar_private *priv = netdev_priv(dev);
  1128. u32 * status_len = (u32 *)bdp;
  1129. u16 flags;
  1130. bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
  1131. priv->rx_buffer_size, DMA_FROM_DEVICE);
  1132. flags = RXBD_EMPTY | RXBD_INTERRUPT;
  1133. if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
  1134. flags |= RXBD_WRAP;
  1135. eieio();
  1136. *status_len = (u32)flags << 16;
  1137. }
  1138. struct sk_buff * gfar_new_skb(struct net_device *dev)
  1139. {
  1140. unsigned int alignamount;
  1141. struct gfar_private *priv = netdev_priv(dev);
  1142. struct sk_buff *skb = NULL;
  1143. /* We have to allocate the skb, so keep trying till we succeed */
  1144. skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
  1145. if (!skb)
  1146. return NULL;
  1147. alignamount = RXBUF_ALIGNMENT -
  1148. (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
  1149. /* We need the data buffer to be aligned properly. We will reserve
  1150. * as many bytes as needed to align the data properly
  1151. */
  1152. skb_reserve(skb, alignamount);
  1153. return skb;
  1154. }
  1155. static inline void count_errors(unsigned short status, struct net_device *dev)
  1156. {
  1157. struct gfar_private *priv = netdev_priv(dev);
  1158. struct net_device_stats *stats = &dev->stats;
  1159. struct gfar_extra_stats *estats = &priv->extra_stats;
  1160. /* If the packet was truncated, none of the other errors
  1161. * matter */
  1162. if (status & RXBD_TRUNCATED) {
  1163. stats->rx_length_errors++;
  1164. estats->rx_trunc++;
  1165. return;
  1166. }
  1167. /* Count the errors, if there were any */
  1168. if (status & (RXBD_LARGE | RXBD_SHORT)) {
  1169. stats->rx_length_errors++;
  1170. if (status & RXBD_LARGE)
  1171. estats->rx_large++;
  1172. else
  1173. estats->rx_short++;
  1174. }
  1175. if (status & RXBD_NONOCTET) {
  1176. stats->rx_frame_errors++;
  1177. estats->rx_nonoctet++;
  1178. }
  1179. if (status & RXBD_CRCERR) {
  1180. estats->rx_crcerr++;
  1181. stats->rx_crc_errors++;
  1182. }
  1183. if (status & RXBD_OVERRUN) {
  1184. estats->rx_overrun++;
  1185. stats->rx_crc_errors++;
  1186. }
  1187. }
  1188. irqreturn_t gfar_receive(int irq, void *dev_id)
  1189. {
  1190. struct net_device *dev = (struct net_device *) dev_id;
  1191. struct gfar_private *priv = netdev_priv(dev);
  1192. u32 tempval;
  1193. /* support NAPI */
  1194. /* Clear IEVENT, so interrupts aren't called again
  1195. * because of the packets that have already arrived */
  1196. gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
  1197. if (netif_rx_schedule_prep(dev, &priv->napi)) {
  1198. tempval = gfar_read(&priv->regs->imask);
  1199. tempval &= IMASK_RTX_DISABLED;
  1200. gfar_write(&priv->regs->imask, tempval);
  1201. __netif_rx_schedule(dev, &priv->napi);
  1202. } else {
  1203. if (netif_msg_rx_err(priv))
  1204. printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
  1205. dev->name, gfar_read(&priv->regs->ievent),
  1206. gfar_read(&priv->regs->imask));
  1207. }
  1208. return IRQ_HANDLED;
  1209. }
  1210. static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
  1211. {
  1212. /* If valid headers were found, and valid sums
  1213. * were verified, then we tell the kernel that no
  1214. * checksumming is necessary. Otherwise, it is */
  1215. if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
  1216. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1217. else
  1218. skb->ip_summed = CHECKSUM_NONE;
  1219. }
  1220. static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
  1221. {
  1222. struct rxfcb *fcb = (struct rxfcb *)skb->data;
  1223. /* Remove the FCB from the skb */
  1224. skb_pull(skb, GMAC_FCB_LEN);
  1225. return fcb;
  1226. }
  1227. /* gfar_process_frame() -- handle one incoming packet if skb
  1228. * isn't NULL. */
  1229. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  1230. int length)
  1231. {
  1232. struct gfar_private *priv = netdev_priv(dev);
  1233. struct rxfcb *fcb = NULL;
  1234. if (NULL == skb) {
  1235. if (netif_msg_rx_err(priv))
  1236. printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
  1237. dev->stats.rx_dropped++;
  1238. priv->extra_stats.rx_skbmissing++;
  1239. } else {
  1240. int ret;
  1241. /* Prep the skb for the packet */
  1242. skb_put(skb, length);
  1243. /* Grab the FCB if there is one */
  1244. if (gfar_uses_fcb(priv))
  1245. fcb = gfar_get_fcb(skb);
  1246. /* Remove the padded bytes, if there are any */
  1247. if (priv->padding)
  1248. skb_pull(skb, priv->padding);
  1249. if (priv->rx_csum_enable)
  1250. gfar_rx_checksum(skb, fcb);
  1251. /* Tell the skb what kind of packet this is */
  1252. skb->protocol = eth_type_trans(skb, dev);
  1253. /* Send the packet up the stack */
  1254. if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
  1255. ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
  1256. fcb->vlctl);
  1257. } else
  1258. ret = netif_receive_skb(skb);
  1259. if (NET_RX_DROP == ret)
  1260. priv->extra_stats.kernel_dropped++;
  1261. }
  1262. return 0;
  1263. }
  1264. /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
  1265. * until the budget/quota has been reached. Returns the number
  1266. * of frames handled
  1267. */
  1268. int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
  1269. {
  1270. struct rxbd8 *bdp;
  1271. struct sk_buff *skb;
  1272. u16 pkt_len;
  1273. int howmany = 0;
  1274. struct gfar_private *priv = netdev_priv(dev);
  1275. /* Get the first full descriptor */
  1276. bdp = priv->cur_rx;
  1277. while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
  1278. struct sk_buff *newskb;
  1279. rmb();
  1280. /* Add another skb for the future */
  1281. newskb = gfar_new_skb(dev);
  1282. skb = priv->rx_skbuff[priv->skb_currx];
  1283. /* We drop the frame if we failed to allocate a new buffer */
  1284. if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
  1285. bdp->status & RXBD_ERR)) {
  1286. count_errors(bdp->status, dev);
  1287. if (unlikely(!newskb))
  1288. newskb = skb;
  1289. if (skb) {
  1290. dma_unmap_single(&priv->dev->dev,
  1291. bdp->bufPtr,
  1292. priv->rx_buffer_size,
  1293. DMA_FROM_DEVICE);
  1294. dev_kfree_skb_any(skb);
  1295. }
  1296. } else {
  1297. /* Increment the number of packets */
  1298. dev->stats.rx_packets++;
  1299. howmany++;
  1300. /* Remove the FCS from the packet length */
  1301. pkt_len = bdp->length - 4;
  1302. gfar_process_frame(dev, skb, pkt_len);
  1303. dev->stats.rx_bytes += pkt_len;
  1304. }
  1305. dev->last_rx = jiffies;
  1306. priv->rx_skbuff[priv->skb_currx] = newskb;
  1307. /* Setup the new bdp */
  1308. gfar_new_rxbdp(dev, bdp, newskb);
  1309. /* Update to the next pointer */
  1310. if (bdp->status & RXBD_WRAP)
  1311. bdp = priv->rx_bd_base;
  1312. else
  1313. bdp++;
  1314. /* update to point at the next skb */
  1315. priv->skb_currx =
  1316. (priv->skb_currx + 1) &
  1317. RX_RING_MOD_MASK(priv->rx_ring_size);
  1318. }
  1319. /* Update the current rxbd pointer to be the next one */
  1320. priv->cur_rx = bdp;
  1321. return howmany;
  1322. }
  1323. static int gfar_poll(struct napi_struct *napi, int budget)
  1324. {
  1325. struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
  1326. struct net_device *dev = priv->dev;
  1327. int howmany;
  1328. unsigned long flags;
  1329. /* If we fail to get the lock, don't bother with the TX BDs */
  1330. if (spin_trylock_irqsave(&priv->txlock, flags)) {
  1331. gfar_clean_tx_ring(dev);
  1332. spin_unlock_irqrestore(&priv->txlock, flags);
  1333. }
  1334. howmany = gfar_clean_rx_ring(dev, budget);
  1335. if (howmany < budget) {
  1336. netif_rx_complete(dev, napi);
  1337. /* Clear the halt bit in RSTAT */
  1338. gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
  1339. gfar_write(&priv->regs->imask, IMASK_DEFAULT);
  1340. /* If we are coalescing interrupts, update the timer */
  1341. /* Otherwise, clear it */
  1342. if (likely(priv->rxcoalescing)) {
  1343. gfar_write(&priv->regs->rxic, 0);
  1344. gfar_write(&priv->regs->rxic,
  1345. mk_ic_value(priv->rxcount, priv->rxtime));
  1346. }
  1347. }
  1348. return howmany;
  1349. }
  1350. #ifdef CONFIG_NET_POLL_CONTROLLER
  1351. /*
  1352. * Polling 'interrupt' - used by things like netconsole to send skbs
  1353. * without having to re-enable interrupts. It's not called while
  1354. * the interrupt routine is executing.
  1355. */
  1356. static void gfar_netpoll(struct net_device *dev)
  1357. {
  1358. struct gfar_private *priv = netdev_priv(dev);
  1359. /* If the device has multiple interrupts, run tx/rx */
  1360. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1361. disable_irq(priv->interruptTransmit);
  1362. disable_irq(priv->interruptReceive);
  1363. disable_irq(priv->interruptError);
  1364. gfar_interrupt(priv->interruptTransmit, dev);
  1365. enable_irq(priv->interruptError);
  1366. enable_irq(priv->interruptReceive);
  1367. enable_irq(priv->interruptTransmit);
  1368. } else {
  1369. disable_irq(priv->interruptTransmit);
  1370. gfar_interrupt(priv->interruptTransmit, dev);
  1371. enable_irq(priv->interruptTransmit);
  1372. }
  1373. }
  1374. #endif
  1375. /* The interrupt handler for devices with one interrupt */
  1376. static irqreturn_t gfar_interrupt(int irq, void *dev_id)
  1377. {
  1378. struct net_device *dev = dev_id;
  1379. struct gfar_private *priv = netdev_priv(dev);
  1380. /* Save ievent for future reference */
  1381. u32 events = gfar_read(&priv->regs->ievent);
  1382. /* Check for reception */
  1383. if (events & IEVENT_RX_MASK)
  1384. gfar_receive(irq, dev_id);
  1385. /* Check for transmit completion */
  1386. if (events & IEVENT_TX_MASK)
  1387. gfar_transmit(irq, dev_id);
  1388. /* Check for errors */
  1389. if (events & IEVENT_ERR_MASK)
  1390. gfar_error(irq, dev_id);
  1391. return IRQ_HANDLED;
  1392. }
  1393. /* Called every time the controller might need to be made
  1394. * aware of new link state. The PHY code conveys this
  1395. * information through variables in the phydev structure, and this
  1396. * function converts those variables into the appropriate
  1397. * register values, and can bring down the device if needed.
  1398. */
  1399. static void adjust_link(struct net_device *dev)
  1400. {
  1401. struct gfar_private *priv = netdev_priv(dev);
  1402. struct gfar __iomem *regs = priv->regs;
  1403. unsigned long flags;
  1404. struct phy_device *phydev = priv->phydev;
  1405. int new_state = 0;
  1406. spin_lock_irqsave(&priv->txlock, flags);
  1407. if (phydev->link) {
  1408. u32 tempval = gfar_read(&regs->maccfg2);
  1409. u32 ecntrl = gfar_read(&regs->ecntrl);
  1410. /* Now we make sure that we can be in full duplex mode.
  1411. * If not, we operate in half-duplex mode. */
  1412. if (phydev->duplex != priv->oldduplex) {
  1413. new_state = 1;
  1414. if (!(phydev->duplex))
  1415. tempval &= ~(MACCFG2_FULL_DUPLEX);
  1416. else
  1417. tempval |= MACCFG2_FULL_DUPLEX;
  1418. priv->oldduplex = phydev->duplex;
  1419. }
  1420. if (phydev->speed != priv->oldspeed) {
  1421. new_state = 1;
  1422. switch (phydev->speed) {
  1423. case 1000:
  1424. tempval =
  1425. ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
  1426. break;
  1427. case 100:
  1428. case 10:
  1429. tempval =
  1430. ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
  1431. /* Reduced mode distinguishes
  1432. * between 10 and 100 */
  1433. if (phydev->speed == SPEED_100)
  1434. ecntrl |= ECNTRL_R100;
  1435. else
  1436. ecntrl &= ~(ECNTRL_R100);
  1437. break;
  1438. default:
  1439. if (netif_msg_link(priv))
  1440. printk(KERN_WARNING
  1441. "%s: Ack! Speed (%d) is not 10/100/1000!\n",
  1442. dev->name, phydev->speed);
  1443. break;
  1444. }
  1445. priv->oldspeed = phydev->speed;
  1446. }
  1447. gfar_write(&regs->maccfg2, tempval);
  1448. gfar_write(&regs->ecntrl, ecntrl);
  1449. if (!priv->oldlink) {
  1450. new_state = 1;
  1451. priv->oldlink = 1;
  1452. }
  1453. } else if (priv->oldlink) {
  1454. new_state = 1;
  1455. priv->oldlink = 0;
  1456. priv->oldspeed = 0;
  1457. priv->oldduplex = -1;
  1458. }
  1459. if (new_state && netif_msg_link(priv))
  1460. phy_print_status(phydev);
  1461. spin_unlock_irqrestore(&priv->txlock, flags);
  1462. }
  1463. /* Update the hash table based on the current list of multicast
  1464. * addresses we subscribe to. Also, change the promiscuity of
  1465. * the device based on the flags (this function is called
  1466. * whenever dev->flags is changed */
  1467. static void gfar_set_multi(struct net_device *dev)
  1468. {
  1469. struct dev_mc_list *mc_ptr;
  1470. struct gfar_private *priv = netdev_priv(dev);
  1471. struct gfar __iomem *regs = priv->regs;
  1472. u32 tempval;
  1473. if(dev->flags & IFF_PROMISC) {
  1474. /* Set RCTRL to PROM */
  1475. tempval = gfar_read(&regs->rctrl);
  1476. tempval |= RCTRL_PROM;
  1477. gfar_write(&regs->rctrl, tempval);
  1478. } else {
  1479. /* Set RCTRL to not PROM */
  1480. tempval = gfar_read(&regs->rctrl);
  1481. tempval &= ~(RCTRL_PROM);
  1482. gfar_write(&regs->rctrl, tempval);
  1483. }
  1484. if(dev->flags & IFF_ALLMULTI) {
  1485. /* Set the hash to rx all multicast frames */
  1486. gfar_write(&regs->igaddr0, 0xffffffff);
  1487. gfar_write(&regs->igaddr1, 0xffffffff);
  1488. gfar_write(&regs->igaddr2, 0xffffffff);
  1489. gfar_write(&regs->igaddr3, 0xffffffff);
  1490. gfar_write(&regs->igaddr4, 0xffffffff);
  1491. gfar_write(&regs->igaddr5, 0xffffffff);
  1492. gfar_write(&regs->igaddr6, 0xffffffff);
  1493. gfar_write(&regs->igaddr7, 0xffffffff);
  1494. gfar_write(&regs->gaddr0, 0xffffffff);
  1495. gfar_write(&regs->gaddr1, 0xffffffff);
  1496. gfar_write(&regs->gaddr2, 0xffffffff);
  1497. gfar_write(&regs->gaddr3, 0xffffffff);
  1498. gfar_write(&regs->gaddr4, 0xffffffff);
  1499. gfar_write(&regs->gaddr5, 0xffffffff);
  1500. gfar_write(&regs->gaddr6, 0xffffffff);
  1501. gfar_write(&regs->gaddr7, 0xffffffff);
  1502. } else {
  1503. int em_num;
  1504. int idx;
  1505. /* zero out the hash */
  1506. gfar_write(&regs->igaddr0, 0x0);
  1507. gfar_write(&regs->igaddr1, 0x0);
  1508. gfar_write(&regs->igaddr2, 0x0);
  1509. gfar_write(&regs->igaddr3, 0x0);
  1510. gfar_write(&regs->igaddr4, 0x0);
  1511. gfar_write(&regs->igaddr5, 0x0);
  1512. gfar_write(&regs->igaddr6, 0x0);
  1513. gfar_write(&regs->igaddr7, 0x0);
  1514. gfar_write(&regs->gaddr0, 0x0);
  1515. gfar_write(&regs->gaddr1, 0x0);
  1516. gfar_write(&regs->gaddr2, 0x0);
  1517. gfar_write(&regs->gaddr3, 0x0);
  1518. gfar_write(&regs->gaddr4, 0x0);
  1519. gfar_write(&regs->gaddr5, 0x0);
  1520. gfar_write(&regs->gaddr6, 0x0);
  1521. gfar_write(&regs->gaddr7, 0x0);
  1522. /* If we have extended hash tables, we need to
  1523. * clear the exact match registers to prepare for
  1524. * setting them */
  1525. if (priv->extended_hash) {
  1526. em_num = GFAR_EM_NUM + 1;
  1527. gfar_clear_exact_match(dev);
  1528. idx = 1;
  1529. } else {
  1530. idx = 0;
  1531. em_num = 0;
  1532. }
  1533. if(dev->mc_count == 0)
  1534. return;
  1535. /* Parse the list, and set the appropriate bits */
  1536. for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
  1537. if (idx < em_num) {
  1538. gfar_set_mac_for_addr(dev, idx,
  1539. mc_ptr->dmi_addr);
  1540. idx++;
  1541. } else
  1542. gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
  1543. }
  1544. }
  1545. return;
  1546. }
  1547. /* Clears each of the exact match registers to zero, so they
  1548. * don't interfere with normal reception */
  1549. static void gfar_clear_exact_match(struct net_device *dev)
  1550. {
  1551. int idx;
  1552. u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
  1553. for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
  1554. gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
  1555. }
  1556. /* Set the appropriate hash bit for the given addr */
  1557. /* The algorithm works like so:
  1558. * 1) Take the Destination Address (ie the multicast address), and
  1559. * do a CRC on it (little endian), and reverse the bits of the
  1560. * result.
  1561. * 2) Use the 8 most significant bits as a hash into a 256-entry
  1562. * table. The table is controlled through 8 32-bit registers:
  1563. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
  1564. * gaddr7. This means that the 3 most significant bits in the
  1565. * hash index which gaddr register to use, and the 5 other bits
  1566. * indicate which bit (assuming an IBM numbering scheme, which
  1567. * for PowerPC (tm) is usually the case) in the register holds
  1568. * the entry. */
  1569. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
  1570. {
  1571. u32 tempval;
  1572. struct gfar_private *priv = netdev_priv(dev);
  1573. u32 result = ether_crc(MAC_ADDR_LEN, addr);
  1574. int width = priv->hash_width;
  1575. u8 whichbit = (result >> (32 - width)) & 0x1f;
  1576. u8 whichreg = result >> (32 - width + 5);
  1577. u32 value = (1 << (31-whichbit));
  1578. tempval = gfar_read(priv->hash_regs[whichreg]);
  1579. tempval |= value;
  1580. gfar_write(priv->hash_regs[whichreg], tempval);
  1581. return;
  1582. }
  1583. /* There are multiple MAC Address register pairs on some controllers
  1584. * This function sets the numth pair to a given address
  1585. */
  1586. static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
  1587. {
  1588. struct gfar_private *priv = netdev_priv(dev);
  1589. int idx;
  1590. char tmpbuf[MAC_ADDR_LEN];
  1591. u32 tempval;
  1592. u32 __iomem *macptr = &priv->regs->macstnaddr1;
  1593. macptr += num*2;
  1594. /* Now copy it into the mac registers backwards, cuz */
  1595. /* little endian is silly */
  1596. for (idx = 0; idx < MAC_ADDR_LEN; idx++)
  1597. tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
  1598. gfar_write(macptr, *((u32 *) (tmpbuf)));
  1599. tempval = *((u32 *) (tmpbuf + 4));
  1600. gfar_write(macptr+1, tempval);
  1601. }
  1602. /* GFAR error interrupt handler */
  1603. static irqreturn_t gfar_error(int irq, void *dev_id)
  1604. {
  1605. struct net_device *dev = dev_id;
  1606. struct gfar_private *priv = netdev_priv(dev);
  1607. /* Save ievent for future reference */
  1608. u32 events = gfar_read(&priv->regs->ievent);
  1609. /* Clear IEVENT */
  1610. gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
  1611. /* Magic Packet is not an error. */
  1612. if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
  1613. (events & IEVENT_MAG))
  1614. events &= ~IEVENT_MAG;
  1615. /* Hmm... */
  1616. if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
  1617. printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
  1618. dev->name, events, gfar_read(&priv->regs->imask));
  1619. /* Update the error counters */
  1620. if (events & IEVENT_TXE) {
  1621. dev->stats.tx_errors++;
  1622. if (events & IEVENT_LC)
  1623. dev->stats.tx_window_errors++;
  1624. if (events & IEVENT_CRL)
  1625. dev->stats.tx_aborted_errors++;
  1626. if (events & IEVENT_XFUN) {
  1627. if (netif_msg_tx_err(priv))
  1628. printk(KERN_DEBUG "%s: TX FIFO underrun, "
  1629. "packet dropped.\n", dev->name);
  1630. dev->stats.tx_dropped++;
  1631. priv->extra_stats.tx_underrun++;
  1632. /* Reactivate the Tx Queues */
  1633. gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
  1634. }
  1635. if (netif_msg_tx_err(priv))
  1636. printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
  1637. }
  1638. if (events & IEVENT_BSY) {
  1639. dev->stats.rx_errors++;
  1640. priv->extra_stats.rx_bsy++;
  1641. gfar_receive(irq, dev_id);
  1642. if (netif_msg_rx_err(priv))
  1643. printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
  1644. dev->name, gfar_read(&priv->regs->rstat));
  1645. }
  1646. if (events & IEVENT_BABR) {
  1647. dev->stats.rx_errors++;
  1648. priv->extra_stats.rx_babr++;
  1649. if (netif_msg_rx_err(priv))
  1650. printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
  1651. }
  1652. if (events & IEVENT_EBERR) {
  1653. priv->extra_stats.eberr++;
  1654. if (netif_msg_rx_err(priv))
  1655. printk(KERN_DEBUG "%s: bus error\n", dev->name);
  1656. }
  1657. if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
  1658. printk(KERN_DEBUG "%s: control frame\n", dev->name);
  1659. if (events & IEVENT_BABT) {
  1660. priv->extra_stats.tx_babt++;
  1661. if (netif_msg_tx_err(priv))
  1662. printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
  1663. }
  1664. return IRQ_HANDLED;
  1665. }
  1666. /* work with hotplug and coldplug */
  1667. MODULE_ALIAS("platform:fsl-gianfar");
  1668. /* Structure for a device driver */
  1669. static struct platform_driver gfar_driver = {
  1670. .probe = gfar_probe,
  1671. .remove = gfar_remove,
  1672. .suspend = gfar_suspend,
  1673. .resume = gfar_resume,
  1674. .driver = {
  1675. .name = "fsl-gianfar",
  1676. .owner = THIS_MODULE,
  1677. },
  1678. };
  1679. static int __init gfar_init(void)
  1680. {
  1681. int err = gfar_mdio_init();
  1682. if (err)
  1683. return err;
  1684. err = platform_driver_register(&gfar_driver);
  1685. if (err)
  1686. gfar_mdio_exit();
  1687. return err;
  1688. }
  1689. static void __exit gfar_exit(void)
  1690. {
  1691. platform_driver_unregister(&gfar_driver);
  1692. gfar_mdio_exit();
  1693. }
  1694. module_init(gfar_init);
  1695. module_exit(gfar_exit);