cpmac.c 34 KB

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  1. /*
  2. * Copyright (C) 2006, 2007 Eugene Konev
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. */
  18. #include <linux/module.h>
  19. #include <linux/init.h>
  20. #include <linux/moduleparam.h>
  21. #include <linux/sched.h>
  22. #include <linux/kernel.h>
  23. #include <linux/slab.h>
  24. #include <linux/errno.h>
  25. #include <linux/types.h>
  26. #include <linux/delay.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/ethtool.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/mii.h>
  32. #include <linux/phy.h>
  33. #include <linux/phy_fixed.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/dma-mapping.h>
  36. #include <asm/gpio.h>
  37. #include <asm/atomic.h>
  38. MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
  39. MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  40. MODULE_LICENSE("GPL");
  41. MODULE_ALIAS("platform:cpmac");
  42. static int debug_level = 8;
  43. static int dumb_switch;
  44. /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
  45. module_param(debug_level, int, 0444);
  46. module_param(dumb_switch, int, 0444);
  47. MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  48. MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
  49. #define CPMAC_VERSION "0.5.0"
  50. /* frame size + 802.1q tag */
  51. #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
  52. #define CPMAC_QUEUES 8
  53. /* Ethernet registers */
  54. #define CPMAC_TX_CONTROL 0x0004
  55. #define CPMAC_TX_TEARDOWN 0x0008
  56. #define CPMAC_RX_CONTROL 0x0014
  57. #define CPMAC_RX_TEARDOWN 0x0018
  58. #define CPMAC_MBP 0x0100
  59. # define MBP_RXPASSCRC 0x40000000
  60. # define MBP_RXQOS 0x20000000
  61. # define MBP_RXNOCHAIN 0x10000000
  62. # define MBP_RXCMF 0x01000000
  63. # define MBP_RXSHORT 0x00800000
  64. # define MBP_RXCEF 0x00400000
  65. # define MBP_RXPROMISC 0x00200000
  66. # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
  67. # define MBP_RXBCAST 0x00002000
  68. # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
  69. # define MBP_RXMCAST 0x00000020
  70. # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
  71. #define CPMAC_UNICAST_ENABLE 0x0104
  72. #define CPMAC_UNICAST_CLEAR 0x0108
  73. #define CPMAC_MAX_LENGTH 0x010c
  74. #define CPMAC_BUFFER_OFFSET 0x0110
  75. #define CPMAC_MAC_CONTROL 0x0160
  76. # define MAC_TXPTYPE 0x00000200
  77. # define MAC_TXPACE 0x00000040
  78. # define MAC_MII 0x00000020
  79. # define MAC_TXFLOW 0x00000010
  80. # define MAC_RXFLOW 0x00000008
  81. # define MAC_MTEST 0x00000004
  82. # define MAC_LOOPBACK 0x00000002
  83. # define MAC_FDX 0x00000001
  84. #define CPMAC_MAC_STATUS 0x0164
  85. # define MAC_STATUS_QOS 0x00000004
  86. # define MAC_STATUS_RXFLOW 0x00000002
  87. # define MAC_STATUS_TXFLOW 0x00000001
  88. #define CPMAC_TX_INT_ENABLE 0x0178
  89. #define CPMAC_TX_INT_CLEAR 0x017c
  90. #define CPMAC_MAC_INT_VECTOR 0x0180
  91. # define MAC_INT_STATUS 0x00080000
  92. # define MAC_INT_HOST 0x00040000
  93. # define MAC_INT_RX 0x00020000
  94. # define MAC_INT_TX 0x00010000
  95. #define CPMAC_MAC_EOI_VECTOR 0x0184
  96. #define CPMAC_RX_INT_ENABLE 0x0198
  97. #define CPMAC_RX_INT_CLEAR 0x019c
  98. #define CPMAC_MAC_INT_ENABLE 0x01a8
  99. #define CPMAC_MAC_INT_CLEAR 0x01ac
  100. #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
  101. #define CPMAC_MAC_ADDR_MID 0x01d0
  102. #define CPMAC_MAC_ADDR_HI 0x01d4
  103. #define CPMAC_MAC_HASH_LO 0x01d8
  104. #define CPMAC_MAC_HASH_HI 0x01dc
  105. #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
  106. #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
  107. #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
  108. #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
  109. #define CPMAC_REG_END 0x0680
  110. /*
  111. * Rx/Tx statistics
  112. * TODO: use some of them to fill stats in cpmac_stats()
  113. */
  114. #define CPMAC_STATS_RX_GOOD 0x0200
  115. #define CPMAC_STATS_RX_BCAST 0x0204
  116. #define CPMAC_STATS_RX_MCAST 0x0208
  117. #define CPMAC_STATS_RX_PAUSE 0x020c
  118. #define CPMAC_STATS_RX_CRC 0x0210
  119. #define CPMAC_STATS_RX_ALIGN 0x0214
  120. #define CPMAC_STATS_RX_OVER 0x0218
  121. #define CPMAC_STATS_RX_JABBER 0x021c
  122. #define CPMAC_STATS_RX_UNDER 0x0220
  123. #define CPMAC_STATS_RX_FRAG 0x0224
  124. #define CPMAC_STATS_RX_FILTER 0x0228
  125. #define CPMAC_STATS_RX_QOSFILTER 0x022c
  126. #define CPMAC_STATS_RX_OCTETS 0x0230
  127. #define CPMAC_STATS_TX_GOOD 0x0234
  128. #define CPMAC_STATS_TX_BCAST 0x0238
  129. #define CPMAC_STATS_TX_MCAST 0x023c
  130. #define CPMAC_STATS_TX_PAUSE 0x0240
  131. #define CPMAC_STATS_TX_DEFER 0x0244
  132. #define CPMAC_STATS_TX_COLLISION 0x0248
  133. #define CPMAC_STATS_TX_SINGLECOLL 0x024c
  134. #define CPMAC_STATS_TX_MULTICOLL 0x0250
  135. #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
  136. #define CPMAC_STATS_TX_LATECOLL 0x0258
  137. #define CPMAC_STATS_TX_UNDERRUN 0x025c
  138. #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
  139. #define CPMAC_STATS_TX_OCTETS 0x0264
  140. #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
  141. #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
  142. (reg)))
  143. /* MDIO bus */
  144. #define CPMAC_MDIO_VERSION 0x0000
  145. #define CPMAC_MDIO_CONTROL 0x0004
  146. # define MDIOC_IDLE 0x80000000
  147. # define MDIOC_ENABLE 0x40000000
  148. # define MDIOC_PREAMBLE 0x00100000
  149. # define MDIOC_FAULT 0x00080000
  150. # define MDIOC_FAULTDETECT 0x00040000
  151. # define MDIOC_INTTEST 0x00020000
  152. # define MDIOC_CLKDIV(div) ((div) & 0xff)
  153. #define CPMAC_MDIO_ALIVE 0x0008
  154. #define CPMAC_MDIO_LINK 0x000c
  155. #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
  156. # define MDIO_BUSY 0x80000000
  157. # define MDIO_WRITE 0x40000000
  158. # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
  159. # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
  160. # define MDIO_DATA(data) ((data) & 0xffff)
  161. #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
  162. # define PHYSEL_LINKSEL 0x00000040
  163. # define PHYSEL_LINKINT 0x00000020
  164. struct cpmac_desc {
  165. u32 hw_next;
  166. u32 hw_data;
  167. u16 buflen;
  168. u16 bufflags;
  169. u16 datalen;
  170. u16 dataflags;
  171. #define CPMAC_SOP 0x8000
  172. #define CPMAC_EOP 0x4000
  173. #define CPMAC_OWN 0x2000
  174. #define CPMAC_EOQ 0x1000
  175. struct sk_buff *skb;
  176. struct cpmac_desc *next;
  177. struct cpmac_desc *prev;
  178. dma_addr_t mapping;
  179. dma_addr_t data_mapping;
  180. };
  181. struct cpmac_priv {
  182. spinlock_t lock;
  183. spinlock_t rx_lock;
  184. struct cpmac_desc *rx_head;
  185. int ring_size;
  186. struct cpmac_desc *desc_ring;
  187. dma_addr_t dma_ring;
  188. void __iomem *regs;
  189. struct mii_bus *mii_bus;
  190. struct phy_device *phy;
  191. char phy_name[BUS_ID_SIZE];
  192. int oldlink, oldspeed, oldduplex;
  193. u32 msg_enable;
  194. struct net_device *dev;
  195. struct work_struct reset_work;
  196. struct platform_device *pdev;
  197. struct napi_struct napi;
  198. atomic_t reset_pending;
  199. };
  200. static irqreturn_t cpmac_irq(int, void *);
  201. static void cpmac_hw_start(struct net_device *dev);
  202. static void cpmac_hw_stop(struct net_device *dev);
  203. static int cpmac_stop(struct net_device *dev);
  204. static int cpmac_open(struct net_device *dev);
  205. static void cpmac_dump_regs(struct net_device *dev)
  206. {
  207. int i;
  208. struct cpmac_priv *priv = netdev_priv(dev);
  209. for (i = 0; i < CPMAC_REG_END; i += 4) {
  210. if (i % 16 == 0) {
  211. if (i)
  212. printk("\n");
  213. printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
  214. priv->regs + i);
  215. }
  216. printk(" %08x", cpmac_read(priv->regs, i));
  217. }
  218. printk("\n");
  219. }
  220. static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
  221. {
  222. int i;
  223. printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
  224. for (i = 0; i < sizeof(*desc) / 4; i++)
  225. printk(" %08x", ((u32 *)desc)[i]);
  226. printk("\n");
  227. }
  228. static void cpmac_dump_all_desc(struct net_device *dev)
  229. {
  230. struct cpmac_priv *priv = netdev_priv(dev);
  231. struct cpmac_desc *dump = priv->rx_head;
  232. do {
  233. cpmac_dump_desc(dev, dump);
  234. dump = dump->next;
  235. } while (dump != priv->rx_head);
  236. }
  237. static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
  238. {
  239. int i;
  240. printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
  241. for (i = 0; i < skb->len; i++) {
  242. if (i % 16 == 0) {
  243. if (i)
  244. printk("\n");
  245. printk(KERN_DEBUG "%s: data[%p]:", dev->name,
  246. skb->data + i);
  247. }
  248. printk(" %02x", ((u8 *)skb->data)[i]);
  249. }
  250. printk("\n");
  251. }
  252. static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
  253. {
  254. u32 val;
  255. while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
  256. cpu_relax();
  257. cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
  258. MDIO_PHY(phy_id));
  259. while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
  260. cpu_relax();
  261. return MDIO_DATA(val);
  262. }
  263. static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
  264. int reg, u16 val)
  265. {
  266. while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
  267. cpu_relax();
  268. cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
  269. MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
  270. return 0;
  271. }
  272. static int cpmac_mdio_reset(struct mii_bus *bus)
  273. {
  274. ar7_device_reset(AR7_RESET_BIT_MDIO);
  275. cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
  276. MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
  277. return 0;
  278. }
  279. static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
  280. static struct mii_bus cpmac_mii = {
  281. .name = "cpmac-mii",
  282. .read = cpmac_mdio_read,
  283. .write = cpmac_mdio_write,
  284. .reset = cpmac_mdio_reset,
  285. .irq = mii_irqs,
  286. };
  287. static int cpmac_config(struct net_device *dev, struct ifmap *map)
  288. {
  289. if (dev->flags & IFF_UP)
  290. return -EBUSY;
  291. /* Don't allow changing the I/O address */
  292. if (map->base_addr != dev->base_addr)
  293. return -EOPNOTSUPP;
  294. /* ignore other fields */
  295. return 0;
  296. }
  297. static void cpmac_set_multicast_list(struct net_device *dev)
  298. {
  299. struct dev_mc_list *iter;
  300. int i;
  301. u8 tmp;
  302. u32 mbp, bit, hash[2] = { 0, };
  303. struct cpmac_priv *priv = netdev_priv(dev);
  304. mbp = cpmac_read(priv->regs, CPMAC_MBP);
  305. if (dev->flags & IFF_PROMISC) {
  306. cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
  307. MBP_RXPROMISC);
  308. } else {
  309. cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
  310. if (dev->flags & IFF_ALLMULTI) {
  311. /* enable all multicast mode */
  312. cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
  313. cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
  314. } else {
  315. /*
  316. * cpmac uses some strange mac address hashing
  317. * (not crc32)
  318. */
  319. for (i = 0, iter = dev->mc_list; i < dev->mc_count;
  320. i++, iter = iter->next) {
  321. bit = 0;
  322. tmp = iter->dmi_addr[0];
  323. bit ^= (tmp >> 2) ^ (tmp << 4);
  324. tmp = iter->dmi_addr[1];
  325. bit ^= (tmp >> 4) ^ (tmp << 2);
  326. tmp = iter->dmi_addr[2];
  327. bit ^= (tmp >> 6) ^ tmp;
  328. tmp = iter->dmi_addr[3];
  329. bit ^= (tmp >> 2) ^ (tmp << 4);
  330. tmp = iter->dmi_addr[4];
  331. bit ^= (tmp >> 4) ^ (tmp << 2);
  332. tmp = iter->dmi_addr[5];
  333. bit ^= (tmp >> 6) ^ tmp;
  334. bit &= 0x3f;
  335. hash[bit / 32] |= 1 << (bit % 32);
  336. }
  337. cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
  338. cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
  339. }
  340. }
  341. }
  342. static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
  343. struct cpmac_desc *desc)
  344. {
  345. struct sk_buff *skb, *result = NULL;
  346. if (unlikely(netif_msg_hw(priv)))
  347. cpmac_dump_desc(priv->dev, desc);
  348. cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
  349. if (unlikely(!desc->datalen)) {
  350. if (netif_msg_rx_err(priv) && net_ratelimit())
  351. printk(KERN_WARNING "%s: rx: spurious interrupt\n",
  352. priv->dev->name);
  353. return NULL;
  354. }
  355. skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
  356. if (likely(skb)) {
  357. skb_reserve(skb, 2);
  358. skb_put(desc->skb, desc->datalen);
  359. desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
  360. desc->skb->ip_summed = CHECKSUM_NONE;
  361. priv->dev->stats.rx_packets++;
  362. priv->dev->stats.rx_bytes += desc->datalen;
  363. result = desc->skb;
  364. dma_unmap_single(&priv->dev->dev, desc->data_mapping,
  365. CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
  366. desc->skb = skb;
  367. desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
  368. CPMAC_SKB_SIZE,
  369. DMA_FROM_DEVICE);
  370. desc->hw_data = (u32)desc->data_mapping;
  371. if (unlikely(netif_msg_pktdata(priv))) {
  372. printk(KERN_DEBUG "%s: received packet:\n",
  373. priv->dev->name);
  374. cpmac_dump_skb(priv->dev, result);
  375. }
  376. } else {
  377. if (netif_msg_rx_err(priv) && net_ratelimit())
  378. printk(KERN_WARNING
  379. "%s: low on skbs, dropping packet\n",
  380. priv->dev->name);
  381. priv->dev->stats.rx_dropped++;
  382. }
  383. desc->buflen = CPMAC_SKB_SIZE;
  384. desc->dataflags = CPMAC_OWN;
  385. return result;
  386. }
  387. static int cpmac_poll(struct napi_struct *napi, int budget)
  388. {
  389. struct sk_buff *skb;
  390. struct cpmac_desc *desc, *restart;
  391. struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
  392. int received = 0, processed = 0;
  393. spin_lock(&priv->rx_lock);
  394. if (unlikely(!priv->rx_head)) {
  395. if (netif_msg_rx_err(priv) && net_ratelimit())
  396. printk(KERN_WARNING "%s: rx: polling, but no queue\n",
  397. priv->dev->name);
  398. spin_unlock(&priv->rx_lock);
  399. netif_rx_complete(priv->dev, napi);
  400. return 0;
  401. }
  402. desc = priv->rx_head;
  403. restart = NULL;
  404. while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
  405. processed++;
  406. if ((desc->dataflags & CPMAC_EOQ) != 0) {
  407. /* The last update to eoq->hw_next didn't happen
  408. * soon enough, and the receiver stopped here.
  409. *Remember this descriptor so we can restart
  410. * the receiver after freeing some space.
  411. */
  412. if (unlikely(restart)) {
  413. if (netif_msg_rx_err(priv))
  414. printk(KERN_ERR "%s: poll found a"
  415. " duplicate EOQ: %p and %p\n",
  416. priv->dev->name, restart, desc);
  417. goto fatal_error;
  418. }
  419. restart = desc->next;
  420. }
  421. skb = cpmac_rx_one(priv, desc);
  422. if (likely(skb)) {
  423. netif_receive_skb(skb);
  424. received++;
  425. }
  426. desc = desc->next;
  427. }
  428. if (desc != priv->rx_head) {
  429. /* We freed some buffers, but not the whole ring,
  430. * add what we did free to the rx list */
  431. desc->prev->hw_next = (u32)0;
  432. priv->rx_head->prev->hw_next = priv->rx_head->mapping;
  433. }
  434. /* Optimization: If we did not actually process an EOQ (perhaps because
  435. * of quota limits), check to see if the tail of the queue has EOQ set.
  436. * We should immediately restart in that case so that the receiver can
  437. * restart and run in parallel with more packet processing.
  438. * This lets us handle slightly larger bursts before running
  439. * out of ring space (assuming dev->weight < ring_size) */
  440. if (!restart &&
  441. (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
  442. == CPMAC_EOQ &&
  443. (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
  444. /* reset EOQ so the poll loop (above) doesn't try to
  445. * restart this when it eventually gets to this descriptor.
  446. */
  447. priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
  448. restart = priv->rx_head;
  449. }
  450. if (restart) {
  451. priv->dev->stats.rx_errors++;
  452. priv->dev->stats.rx_fifo_errors++;
  453. if (netif_msg_rx_err(priv) && net_ratelimit())
  454. printk(KERN_WARNING "%s: rx dma ring overrun\n",
  455. priv->dev->name);
  456. if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
  457. if (netif_msg_drv(priv))
  458. printk(KERN_ERR "%s: cpmac_poll is trying to "
  459. "restart rx from a descriptor that's "
  460. "not free: %p\n",
  461. priv->dev->name, restart);
  462. goto fatal_error;
  463. }
  464. cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
  465. }
  466. priv->rx_head = desc;
  467. spin_unlock(&priv->rx_lock);
  468. if (unlikely(netif_msg_rx_status(priv)))
  469. printk(KERN_DEBUG "%s: poll processed %d packets\n",
  470. priv->dev->name, received);
  471. if (processed == 0) {
  472. /* we ran out of packets to read,
  473. * revert to interrupt-driven mode */
  474. netif_rx_complete(priv->dev, napi);
  475. cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
  476. return 0;
  477. }
  478. return 1;
  479. fatal_error:
  480. /* Something went horribly wrong.
  481. * Reset hardware to try to recover rather than wedging. */
  482. if (netif_msg_drv(priv)) {
  483. printk(KERN_ERR "%s: cpmac_poll is confused. "
  484. "Resetting hardware\n", priv->dev->name);
  485. cpmac_dump_all_desc(priv->dev);
  486. printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
  487. priv->dev->name,
  488. cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
  489. cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
  490. }
  491. spin_unlock(&priv->rx_lock);
  492. netif_rx_complete(priv->dev, napi);
  493. netif_tx_stop_all_queues(priv->dev);
  494. napi_disable(&priv->napi);
  495. atomic_inc(&priv->reset_pending);
  496. cpmac_hw_stop(priv->dev);
  497. if (!schedule_work(&priv->reset_work))
  498. atomic_dec(&priv->reset_pending);
  499. return 0;
  500. }
  501. static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
  502. {
  503. int queue, len;
  504. struct cpmac_desc *desc;
  505. struct cpmac_priv *priv = netdev_priv(dev);
  506. if (unlikely(atomic_read(&priv->reset_pending)))
  507. return NETDEV_TX_BUSY;
  508. if (unlikely(skb_padto(skb, ETH_ZLEN)))
  509. return NETDEV_TX_OK;
  510. len = max(skb->len, ETH_ZLEN);
  511. queue = skb_get_queue_mapping(skb);
  512. netif_stop_subqueue(dev, queue);
  513. desc = &priv->desc_ring[queue];
  514. if (unlikely(desc->dataflags & CPMAC_OWN)) {
  515. if (netif_msg_tx_err(priv) && net_ratelimit())
  516. printk(KERN_WARNING "%s: tx dma ring full\n",
  517. dev->name);
  518. return NETDEV_TX_BUSY;
  519. }
  520. spin_lock(&priv->lock);
  521. dev->trans_start = jiffies;
  522. spin_unlock(&priv->lock);
  523. desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
  524. desc->skb = skb;
  525. desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
  526. DMA_TO_DEVICE);
  527. desc->hw_data = (u32)desc->data_mapping;
  528. desc->datalen = len;
  529. desc->buflen = len;
  530. if (unlikely(netif_msg_tx_queued(priv)))
  531. printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
  532. skb->len);
  533. if (unlikely(netif_msg_hw(priv)))
  534. cpmac_dump_desc(dev, desc);
  535. if (unlikely(netif_msg_pktdata(priv)))
  536. cpmac_dump_skb(dev, skb);
  537. cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
  538. return NETDEV_TX_OK;
  539. }
  540. static void cpmac_end_xmit(struct net_device *dev, int queue)
  541. {
  542. struct cpmac_desc *desc;
  543. struct cpmac_priv *priv = netdev_priv(dev);
  544. desc = &priv->desc_ring[queue];
  545. cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
  546. if (likely(desc->skb)) {
  547. spin_lock(&priv->lock);
  548. dev->stats.tx_packets++;
  549. dev->stats.tx_bytes += desc->skb->len;
  550. spin_unlock(&priv->lock);
  551. dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
  552. DMA_TO_DEVICE);
  553. if (unlikely(netif_msg_tx_done(priv)))
  554. printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
  555. desc->skb, desc->skb->len);
  556. dev_kfree_skb_irq(desc->skb);
  557. desc->skb = NULL;
  558. if (netif_subqueue_stopped(dev, queue))
  559. netif_wake_subqueue(dev, queue);
  560. } else {
  561. if (netif_msg_tx_err(priv) && net_ratelimit())
  562. printk(KERN_WARNING
  563. "%s: end_xmit: spurious interrupt\n", dev->name);
  564. if (netif_subqueue_stopped(dev, queue))
  565. netif_wake_subqueue(dev, queue);
  566. }
  567. }
  568. static void cpmac_hw_stop(struct net_device *dev)
  569. {
  570. int i;
  571. struct cpmac_priv *priv = netdev_priv(dev);
  572. struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
  573. ar7_device_reset(pdata->reset_bit);
  574. cpmac_write(priv->regs, CPMAC_RX_CONTROL,
  575. cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
  576. cpmac_write(priv->regs, CPMAC_TX_CONTROL,
  577. cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
  578. for (i = 0; i < 8; i++) {
  579. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  580. cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
  581. }
  582. cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
  583. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
  584. cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
  585. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  586. cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
  587. cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
  588. }
  589. static void cpmac_hw_start(struct net_device *dev)
  590. {
  591. int i;
  592. struct cpmac_priv *priv = netdev_priv(dev);
  593. struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
  594. ar7_device_reset(pdata->reset_bit);
  595. for (i = 0; i < 8; i++) {
  596. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  597. cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
  598. }
  599. cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
  600. cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
  601. MBP_RXMCAST);
  602. cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
  603. for (i = 0; i < 8; i++)
  604. cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
  605. cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
  606. cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
  607. (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
  608. (dev->dev_addr[3] << 24));
  609. cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
  610. cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
  611. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
  612. cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
  613. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  614. cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
  615. cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
  616. cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
  617. cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
  618. cpmac_write(priv->regs, CPMAC_RX_CONTROL,
  619. cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
  620. cpmac_write(priv->regs, CPMAC_TX_CONTROL,
  621. cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
  622. cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
  623. cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
  624. MAC_FDX);
  625. }
  626. static void cpmac_clear_rx(struct net_device *dev)
  627. {
  628. struct cpmac_priv *priv = netdev_priv(dev);
  629. struct cpmac_desc *desc;
  630. int i;
  631. if (unlikely(!priv->rx_head))
  632. return;
  633. desc = priv->rx_head;
  634. for (i = 0; i < priv->ring_size; i++) {
  635. if ((desc->dataflags & CPMAC_OWN) == 0) {
  636. if (netif_msg_rx_err(priv) && net_ratelimit())
  637. printk(KERN_WARNING "%s: packet dropped\n",
  638. dev->name);
  639. if (unlikely(netif_msg_hw(priv)))
  640. cpmac_dump_desc(dev, desc);
  641. desc->dataflags = CPMAC_OWN;
  642. dev->stats.rx_dropped++;
  643. }
  644. desc->hw_next = desc->next->mapping;
  645. desc = desc->next;
  646. }
  647. priv->rx_head->prev->hw_next = 0;
  648. }
  649. static void cpmac_clear_tx(struct net_device *dev)
  650. {
  651. struct cpmac_priv *priv = netdev_priv(dev);
  652. int i;
  653. if (unlikely(!priv->desc_ring))
  654. return;
  655. for (i = 0; i < CPMAC_QUEUES; i++) {
  656. priv->desc_ring[i].dataflags = 0;
  657. if (priv->desc_ring[i].skb) {
  658. dev_kfree_skb_any(priv->desc_ring[i].skb);
  659. priv->desc_ring[i].skb = NULL;
  660. }
  661. }
  662. }
  663. static void cpmac_hw_error(struct work_struct *work)
  664. {
  665. int i;
  666. struct cpmac_priv *priv =
  667. container_of(work, struct cpmac_priv, reset_work);
  668. spin_lock(&priv->rx_lock);
  669. cpmac_clear_rx(priv->dev);
  670. spin_unlock(&priv->rx_lock);
  671. cpmac_clear_tx(priv->dev);
  672. cpmac_hw_start(priv->dev);
  673. barrier();
  674. atomic_dec(&priv->reset_pending);
  675. netif_tx_wake_all_queues(priv->dev);
  676. cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
  677. }
  678. static void cpmac_check_status(struct net_device *dev)
  679. {
  680. struct cpmac_priv *priv = netdev_priv(dev);
  681. u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
  682. int rx_channel = (macstatus >> 8) & 7;
  683. int rx_code = (macstatus >> 12) & 15;
  684. int tx_channel = (macstatus >> 16) & 7;
  685. int tx_code = (macstatus >> 20) & 15;
  686. if (rx_code || tx_code) {
  687. if (netif_msg_drv(priv) && net_ratelimit()) {
  688. /* Can't find any documentation on what these
  689. *error codes actually are. So just log them and hope..
  690. */
  691. if (rx_code)
  692. printk(KERN_WARNING "%s: host error %d on rx "
  693. "channel %d (macstatus %08x), resetting\n",
  694. dev->name, rx_code, rx_channel, macstatus);
  695. if (tx_code)
  696. printk(KERN_WARNING "%s: host error %d on tx "
  697. "channel %d (macstatus %08x), resetting\n",
  698. dev->name, tx_code, tx_channel, macstatus);
  699. }
  700. netif_tx_stop_all_queues(dev);
  701. cpmac_hw_stop(dev);
  702. if (schedule_work(&priv->reset_work))
  703. atomic_inc(&priv->reset_pending);
  704. if (unlikely(netif_msg_hw(priv)))
  705. cpmac_dump_regs(dev);
  706. }
  707. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  708. }
  709. static irqreturn_t cpmac_irq(int irq, void *dev_id)
  710. {
  711. struct net_device *dev = dev_id;
  712. struct cpmac_priv *priv;
  713. int queue;
  714. u32 status;
  715. priv = netdev_priv(dev);
  716. status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
  717. if (unlikely(netif_msg_intr(priv)))
  718. printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
  719. status);
  720. if (status & MAC_INT_TX)
  721. cpmac_end_xmit(dev, (status & 7));
  722. if (status & MAC_INT_RX) {
  723. queue = (status >> 8) & 7;
  724. if (netif_rx_schedule_prep(dev, &priv->napi)) {
  725. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
  726. __netif_rx_schedule(dev, &priv->napi);
  727. }
  728. }
  729. cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
  730. if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
  731. cpmac_check_status(dev);
  732. return IRQ_HANDLED;
  733. }
  734. static void cpmac_tx_timeout(struct net_device *dev)
  735. {
  736. int i;
  737. struct cpmac_priv *priv = netdev_priv(dev);
  738. spin_lock(&priv->lock);
  739. dev->stats.tx_errors++;
  740. spin_unlock(&priv->lock);
  741. if (netif_msg_tx_err(priv) && net_ratelimit())
  742. printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
  743. atomic_inc(&priv->reset_pending);
  744. barrier();
  745. cpmac_clear_tx(dev);
  746. barrier();
  747. atomic_dec(&priv->reset_pending);
  748. netif_tx_wake_all_queues(priv->dev);
  749. }
  750. static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  751. {
  752. struct cpmac_priv *priv = netdev_priv(dev);
  753. if (!(netif_running(dev)))
  754. return -EINVAL;
  755. if (!priv->phy)
  756. return -EINVAL;
  757. if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
  758. (cmd == SIOCSMIIREG))
  759. return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
  760. return -EOPNOTSUPP;
  761. }
  762. static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  763. {
  764. struct cpmac_priv *priv = netdev_priv(dev);
  765. if (priv->phy)
  766. return phy_ethtool_gset(priv->phy, cmd);
  767. return -EINVAL;
  768. }
  769. static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  770. {
  771. struct cpmac_priv *priv = netdev_priv(dev);
  772. if (!capable(CAP_NET_ADMIN))
  773. return -EPERM;
  774. if (priv->phy)
  775. return phy_ethtool_sset(priv->phy, cmd);
  776. return -EINVAL;
  777. }
  778. static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  779. {
  780. struct cpmac_priv *priv = netdev_priv(dev);
  781. ring->rx_max_pending = 1024;
  782. ring->rx_mini_max_pending = 1;
  783. ring->rx_jumbo_max_pending = 1;
  784. ring->tx_max_pending = 1;
  785. ring->rx_pending = priv->ring_size;
  786. ring->rx_mini_pending = 1;
  787. ring->rx_jumbo_pending = 1;
  788. ring->tx_pending = 1;
  789. }
  790. static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  791. {
  792. struct cpmac_priv *priv = netdev_priv(dev);
  793. if (netif_running(dev))
  794. return -EBUSY;
  795. priv->ring_size = ring->rx_pending;
  796. return 0;
  797. }
  798. static void cpmac_get_drvinfo(struct net_device *dev,
  799. struct ethtool_drvinfo *info)
  800. {
  801. strcpy(info->driver, "cpmac");
  802. strcpy(info->version, CPMAC_VERSION);
  803. info->fw_version[0] = '\0';
  804. sprintf(info->bus_info, "%s", "cpmac");
  805. info->regdump_len = 0;
  806. }
  807. static const struct ethtool_ops cpmac_ethtool_ops = {
  808. .get_settings = cpmac_get_settings,
  809. .set_settings = cpmac_set_settings,
  810. .get_drvinfo = cpmac_get_drvinfo,
  811. .get_link = ethtool_op_get_link,
  812. .get_ringparam = cpmac_get_ringparam,
  813. .set_ringparam = cpmac_set_ringparam,
  814. };
  815. static void cpmac_adjust_link(struct net_device *dev)
  816. {
  817. struct cpmac_priv *priv = netdev_priv(dev);
  818. int new_state = 0;
  819. spin_lock(&priv->lock);
  820. if (priv->phy->link) {
  821. netif_tx_start_all_queues(dev);
  822. if (priv->phy->duplex != priv->oldduplex) {
  823. new_state = 1;
  824. priv->oldduplex = priv->phy->duplex;
  825. }
  826. if (priv->phy->speed != priv->oldspeed) {
  827. new_state = 1;
  828. priv->oldspeed = priv->phy->speed;
  829. }
  830. if (!priv->oldlink) {
  831. new_state = 1;
  832. priv->oldlink = 1;
  833. }
  834. } else if (priv->oldlink) {
  835. new_state = 1;
  836. priv->oldlink = 0;
  837. priv->oldspeed = 0;
  838. priv->oldduplex = -1;
  839. }
  840. if (new_state && netif_msg_link(priv) && net_ratelimit())
  841. phy_print_status(priv->phy);
  842. spin_unlock(&priv->lock);
  843. }
  844. static int cpmac_open(struct net_device *dev)
  845. {
  846. int i, size, res;
  847. struct cpmac_priv *priv = netdev_priv(dev);
  848. struct resource *mem;
  849. struct cpmac_desc *desc;
  850. struct sk_buff *skb;
  851. mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
  852. if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
  853. if (netif_msg_drv(priv))
  854. printk(KERN_ERR "%s: failed to request registers\n",
  855. dev->name);
  856. res = -ENXIO;
  857. goto fail_reserve;
  858. }
  859. priv->regs = ioremap(mem->start, mem->end - mem->start);
  860. if (!priv->regs) {
  861. if (netif_msg_drv(priv))
  862. printk(KERN_ERR "%s: failed to remap registers\n",
  863. dev->name);
  864. res = -ENXIO;
  865. goto fail_remap;
  866. }
  867. size = priv->ring_size + CPMAC_QUEUES;
  868. priv->desc_ring = dma_alloc_coherent(&dev->dev,
  869. sizeof(struct cpmac_desc) * size,
  870. &priv->dma_ring,
  871. GFP_KERNEL);
  872. if (!priv->desc_ring) {
  873. res = -ENOMEM;
  874. goto fail_alloc;
  875. }
  876. for (i = 0; i < size; i++)
  877. priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
  878. priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
  879. for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
  880. skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
  881. if (unlikely(!skb)) {
  882. res = -ENOMEM;
  883. goto fail_desc;
  884. }
  885. skb_reserve(skb, 2);
  886. desc->skb = skb;
  887. desc->data_mapping = dma_map_single(&dev->dev, skb->data,
  888. CPMAC_SKB_SIZE,
  889. DMA_FROM_DEVICE);
  890. desc->hw_data = (u32)desc->data_mapping;
  891. desc->buflen = CPMAC_SKB_SIZE;
  892. desc->dataflags = CPMAC_OWN;
  893. desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
  894. desc->next->prev = desc;
  895. desc->hw_next = (u32)desc->next->mapping;
  896. }
  897. priv->rx_head->prev->hw_next = (u32)0;
  898. if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
  899. dev->name, dev))) {
  900. if (netif_msg_drv(priv))
  901. printk(KERN_ERR "%s: failed to obtain irq\n",
  902. dev->name);
  903. goto fail_irq;
  904. }
  905. atomic_set(&priv->reset_pending, 0);
  906. INIT_WORK(&priv->reset_work, cpmac_hw_error);
  907. cpmac_hw_start(dev);
  908. napi_enable(&priv->napi);
  909. priv->phy->state = PHY_CHANGELINK;
  910. phy_start(priv->phy);
  911. return 0;
  912. fail_irq:
  913. fail_desc:
  914. for (i = 0; i < priv->ring_size; i++) {
  915. if (priv->rx_head[i].skb) {
  916. dma_unmap_single(&dev->dev,
  917. priv->rx_head[i].data_mapping,
  918. CPMAC_SKB_SIZE,
  919. DMA_FROM_DEVICE);
  920. kfree_skb(priv->rx_head[i].skb);
  921. }
  922. }
  923. fail_alloc:
  924. kfree(priv->desc_ring);
  925. iounmap(priv->regs);
  926. fail_remap:
  927. release_mem_region(mem->start, mem->end - mem->start);
  928. fail_reserve:
  929. return res;
  930. }
  931. static int cpmac_stop(struct net_device *dev)
  932. {
  933. int i;
  934. struct cpmac_priv *priv = netdev_priv(dev);
  935. struct resource *mem;
  936. netif_tx_stop_all_queues(dev);
  937. cancel_work_sync(&priv->reset_work);
  938. napi_disable(&priv->napi);
  939. phy_stop(priv->phy);
  940. cpmac_hw_stop(dev);
  941. for (i = 0; i < 8; i++)
  942. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  943. cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
  944. cpmac_write(priv->regs, CPMAC_MBP, 0);
  945. free_irq(dev->irq, dev);
  946. iounmap(priv->regs);
  947. mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
  948. release_mem_region(mem->start, mem->end - mem->start);
  949. priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
  950. for (i = 0; i < priv->ring_size; i++) {
  951. if (priv->rx_head[i].skb) {
  952. dma_unmap_single(&dev->dev,
  953. priv->rx_head[i].data_mapping,
  954. CPMAC_SKB_SIZE,
  955. DMA_FROM_DEVICE);
  956. kfree_skb(priv->rx_head[i].skb);
  957. }
  958. }
  959. dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
  960. (CPMAC_QUEUES + priv->ring_size),
  961. priv->desc_ring, priv->dma_ring);
  962. return 0;
  963. }
  964. static int external_switch;
  965. static int __devinit cpmac_probe(struct platform_device *pdev)
  966. {
  967. int rc, phy_id, i;
  968. char *mdio_bus_id = "0";
  969. struct resource *mem;
  970. struct cpmac_priv *priv;
  971. struct net_device *dev;
  972. struct plat_cpmac_data *pdata;
  973. DECLARE_MAC_BUF(mac);
  974. pdata = pdev->dev.platform_data;
  975. for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
  976. if (!(pdata->phy_mask & (1 << phy_id)))
  977. continue;
  978. if (!cpmac_mii.phy_map[phy_id])
  979. continue;
  980. break;
  981. }
  982. if (phy_id == PHY_MAX_ADDR) {
  983. if (external_switch || dumb_switch) {
  984. mdio_bus_id = 0; /* fixed phys bus */
  985. phy_id = pdev->id;
  986. } else {
  987. dev_err(&pdev->dev, "no PHY present\n");
  988. return -ENODEV;
  989. }
  990. }
  991. dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
  992. if (!dev) {
  993. printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
  994. return -ENOMEM;
  995. }
  996. platform_set_drvdata(pdev, dev);
  997. priv = netdev_priv(dev);
  998. priv->pdev = pdev;
  999. mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  1000. if (!mem) {
  1001. rc = -ENODEV;
  1002. goto fail;
  1003. }
  1004. dev->irq = platform_get_irq_byname(pdev, "irq");
  1005. dev->open = cpmac_open;
  1006. dev->stop = cpmac_stop;
  1007. dev->set_config = cpmac_config;
  1008. dev->hard_start_xmit = cpmac_start_xmit;
  1009. dev->do_ioctl = cpmac_ioctl;
  1010. dev->set_multicast_list = cpmac_set_multicast_list;
  1011. dev->tx_timeout = cpmac_tx_timeout;
  1012. dev->ethtool_ops = &cpmac_ethtool_ops;
  1013. netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
  1014. spin_lock_init(&priv->lock);
  1015. spin_lock_init(&priv->rx_lock);
  1016. priv->dev = dev;
  1017. priv->ring_size = 64;
  1018. priv->msg_enable = netif_msg_init(debug_level, 0xff);
  1019. memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
  1020. priv->phy = phy_connect(dev, cpmac_mii.phy_map[phy_id]->dev.bus_id,
  1021. &cpmac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
  1022. if (IS_ERR(priv->phy)) {
  1023. if (netif_msg_drv(priv))
  1024. printk(KERN_ERR "%s: Could not attach to PHY\n",
  1025. dev->name);
  1026. return PTR_ERR(priv->phy);
  1027. }
  1028. if ((rc = register_netdev(dev))) {
  1029. printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
  1030. dev->name);
  1031. goto fail;
  1032. }
  1033. if (netif_msg_probe(priv)) {
  1034. printk(KERN_INFO
  1035. "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
  1036. "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
  1037. priv->phy_name, print_mac(mac, dev->dev_addr));
  1038. }
  1039. return 0;
  1040. fail:
  1041. free_netdev(dev);
  1042. return rc;
  1043. }
  1044. static int __devexit cpmac_remove(struct platform_device *pdev)
  1045. {
  1046. struct net_device *dev = platform_get_drvdata(pdev);
  1047. unregister_netdev(dev);
  1048. free_netdev(dev);
  1049. return 0;
  1050. }
  1051. static struct platform_driver cpmac_driver = {
  1052. .driver.name = "cpmac",
  1053. .driver.owner = THIS_MODULE,
  1054. .probe = cpmac_probe,
  1055. .remove = __devexit_p(cpmac_remove),
  1056. };
  1057. int __devinit cpmac_init(void)
  1058. {
  1059. u32 mask;
  1060. int i, res;
  1061. cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
  1062. if (!cpmac_mii.priv) {
  1063. printk(KERN_ERR "Can't ioremap mdio registers\n");
  1064. return -ENXIO;
  1065. }
  1066. #warning FIXME: unhardcode gpio&reset bits
  1067. ar7_gpio_disable(26);
  1068. ar7_gpio_disable(27);
  1069. ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
  1070. ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
  1071. ar7_device_reset(AR7_RESET_BIT_EPHY);
  1072. cpmac_mii.reset(&cpmac_mii);
  1073. for (i = 0; i < 300000; i++)
  1074. if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
  1075. break;
  1076. else
  1077. cpu_relax();
  1078. mask &= 0x7fffffff;
  1079. if (mask & (mask - 1)) {
  1080. external_switch = 1;
  1081. mask = 0;
  1082. }
  1083. cpmac_mii.phy_mask = ~(mask | 0x80000000);
  1084. snprintf(cpmac_mii.id, MII_BUS_ID_SIZE, "0");
  1085. res = mdiobus_register(&cpmac_mii);
  1086. if (res)
  1087. goto fail_mii;
  1088. res = platform_driver_register(&cpmac_driver);
  1089. if (res)
  1090. goto fail_cpmac;
  1091. return 0;
  1092. fail_cpmac:
  1093. mdiobus_unregister(&cpmac_mii);
  1094. fail_mii:
  1095. iounmap(cpmac_mii.priv);
  1096. return res;
  1097. }
  1098. void __devexit cpmac_exit(void)
  1099. {
  1100. platform_driver_unregister(&cpmac_driver);
  1101. mdiobus_unregister(&cpmac_mii);
  1102. iounmap(cpmac_mii.priv);
  1103. }
  1104. module_init(cpmac_init);
  1105. module_exit(cpmac_exit);