bnx2x.h 33 KB

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  1. /* bnx2x.h: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2008 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. */
  13. #ifndef BNX2X_H
  14. #define BNX2X_H
  15. /* compilation time flags */
  16. /* define this to make the driver freeze on error to allow getting debug info
  17. * (you will need to reboot afterwards) */
  18. /* #define BNX2X_STOP_ON_ERROR */
  19. /* error/debug prints */
  20. #define DRV_MODULE_NAME "bnx2x"
  21. #define PFX DRV_MODULE_NAME ": "
  22. /* for messages that are currently off */
  23. #define BNX2X_MSG_OFF 0
  24. #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
  25. #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
  26. #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
  27. #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
  28. #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
  29. #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
  30. #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
  31. /* regular debug print */
  32. #define DP(__mask, __fmt, __args...) do { \
  33. if (bp->msglevel & (__mask)) \
  34. printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  35. bp->dev ? (bp->dev->name) : "?", ##__args); \
  36. } while (0)
  37. /* errors debug print */
  38. #define BNX2X_DBG_ERR(__fmt, __args...) do { \
  39. if (bp->msglevel & NETIF_MSG_PROBE) \
  40. printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  41. bp->dev ? (bp->dev->name) : "?", ##__args); \
  42. } while (0)
  43. /* for errors (never masked) */
  44. #define BNX2X_ERR(__fmt, __args...) do { \
  45. printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  46. bp->dev ? (bp->dev->name) : "?", ##__args); \
  47. } while (0)
  48. /* before we have a dev->name use dev_info() */
  49. #define BNX2X_DEV_INFO(__fmt, __args...) do { \
  50. if (bp->msglevel & NETIF_MSG_PROBE) \
  51. dev_info(&bp->pdev->dev, __fmt, ##__args); \
  52. } while (0)
  53. #ifdef BNX2X_STOP_ON_ERROR
  54. #define bnx2x_panic() do { \
  55. bp->panic = 1; \
  56. BNX2X_ERR("driver assert\n"); \
  57. bnx2x_int_disable(bp); \
  58. bnx2x_panic_dump(bp); \
  59. } while (0)
  60. #else
  61. #define bnx2x_panic() do { \
  62. BNX2X_ERR("driver assert\n"); \
  63. bnx2x_panic_dump(bp); \
  64. } while (0)
  65. #endif
  66. #ifdef NETIF_F_HW_VLAN_TX
  67. #define BCM_VLAN 1
  68. #endif
  69. #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
  70. #define U64_HI(x) (u32)(((u64)(x)) >> 32)
  71. #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
  72. #define REG_ADDR(bp, offset) (bp->regview + offset)
  73. #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
  74. #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
  75. #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
  76. #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
  77. #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
  78. #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
  79. #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
  80. #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
  81. #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
  82. #define REG_RD_DMAE(bp, offset, valp, len32) \
  83. do { \
  84. bnx2x_read_dmae(bp, offset, len32);\
  85. memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
  86. } while (0)
  87. #define REG_WR_DMAE(bp, offset, valp, len32) \
  88. do { \
  89. memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
  90. bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
  91. offset, len32); \
  92. } while (0)
  93. #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
  94. offsetof(struct shmem_region, field))
  95. #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
  96. #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
  97. #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
  98. #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
  99. /* fast path */
  100. struct sw_rx_bd {
  101. struct sk_buff *skb;
  102. DECLARE_PCI_UNMAP_ADDR(mapping)
  103. };
  104. struct sw_tx_bd {
  105. struct sk_buff *skb;
  106. u16 first_bd;
  107. };
  108. struct sw_rx_page {
  109. struct page *page;
  110. DECLARE_PCI_UNMAP_ADDR(mapping)
  111. };
  112. /* MC hsi */
  113. #define BCM_PAGE_SHIFT 12
  114. #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
  115. #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
  116. #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
  117. #define PAGES_PER_SGE_SHIFT 0
  118. #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
  119. /* SGE ring related macros */
  120. #define NUM_RX_SGE_PAGES 2
  121. #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
  122. #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
  123. /* RX_SGE_CNT is promised to be a power of 2 */
  124. #define RX_SGE_MASK (RX_SGE_CNT - 1)
  125. #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
  126. #define MAX_RX_SGE (NUM_RX_SGE - 1)
  127. #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
  128. (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
  129. #define RX_SGE(x) ((x) & MAX_RX_SGE)
  130. /* SGE producer mask related macros */
  131. /* Number of bits in one sge_mask array element */
  132. #define RX_SGE_MASK_ELEM_SZ 64
  133. #define RX_SGE_MASK_ELEM_SHIFT 6
  134. #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
  135. /* Creates a bitmask of all ones in less significant bits.
  136. idx - index of the most significant bit in the created mask */
  137. #define RX_SGE_ONES_MASK(idx) \
  138. (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
  139. #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
  140. /* Number of u64 elements in SGE mask array */
  141. #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
  142. RX_SGE_MASK_ELEM_SZ)
  143. #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
  144. #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
  145. struct bnx2x_fastpath {
  146. struct napi_struct napi;
  147. struct host_status_block *status_blk;
  148. dma_addr_t status_blk_mapping;
  149. struct eth_tx_db_data *hw_tx_prods;
  150. dma_addr_t tx_prods_mapping;
  151. struct sw_tx_bd *tx_buf_ring;
  152. struct eth_tx_bd *tx_desc_ring;
  153. dma_addr_t tx_desc_mapping;
  154. struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
  155. struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
  156. struct eth_rx_bd *rx_desc_ring;
  157. dma_addr_t rx_desc_mapping;
  158. union eth_rx_cqe *rx_comp_ring;
  159. dma_addr_t rx_comp_mapping;
  160. /* SGE ring */
  161. struct eth_rx_sge *rx_sge_ring;
  162. dma_addr_t rx_sge_mapping;
  163. u64 sge_mask[RX_SGE_MASK_LEN];
  164. int state;
  165. #define BNX2X_FP_STATE_CLOSED 0
  166. #define BNX2X_FP_STATE_IRQ 0x80000
  167. #define BNX2X_FP_STATE_OPENING 0x90000
  168. #define BNX2X_FP_STATE_OPEN 0xa0000
  169. #define BNX2X_FP_STATE_HALTING 0xb0000
  170. #define BNX2X_FP_STATE_HALTED 0xc0000
  171. u8 index; /* number in fp array */
  172. u8 cl_id; /* eth client id */
  173. u8 sb_id; /* status block number in HW */
  174. #define FP_IDX(fp) (fp->index)
  175. #define FP_CL_ID(fp) (fp->cl_id)
  176. #define BP_CL_ID(bp) (bp->fp[0].cl_id)
  177. #define FP_SB_ID(fp) (fp->sb_id)
  178. #define CNIC_SB_ID 0
  179. u16 tx_pkt_prod;
  180. u16 tx_pkt_cons;
  181. u16 tx_bd_prod;
  182. u16 tx_bd_cons;
  183. u16 *tx_cons_sb;
  184. u16 fp_c_idx;
  185. u16 fp_u_idx;
  186. u16 rx_bd_prod;
  187. u16 rx_bd_cons;
  188. u16 rx_comp_prod;
  189. u16 rx_comp_cons;
  190. u16 rx_sge_prod;
  191. /* The last maximal completed SGE */
  192. u16 last_max_sge;
  193. u16 *rx_cons_sb;
  194. u16 *rx_bd_cons_sb;
  195. unsigned long tx_pkt,
  196. rx_pkt,
  197. rx_calls;
  198. /* TPA related */
  199. struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
  200. u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
  201. #define BNX2X_TPA_START 1
  202. #define BNX2X_TPA_STOP 2
  203. u8 disable_tpa;
  204. #ifdef BNX2X_STOP_ON_ERROR
  205. u64 tpa_queue_used;
  206. #endif
  207. struct bnx2x *bp; /* parent */
  208. };
  209. #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
  210. #define BNX2X_HAS_TX_WORK(fp) \
  211. ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
  212. (fp->tx_pkt_prod != fp->tx_pkt_cons))
  213. #define BNX2X_HAS_RX_WORK(fp) \
  214. (fp->rx_comp_cons != rx_cons_sb)
  215. #define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
  216. /* MC hsi */
  217. #define MAX_FETCH_BD 13 /* HW max BDs per packet */
  218. #define RX_COPY_THRESH 92
  219. #define NUM_TX_RINGS 16
  220. #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
  221. #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
  222. #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
  223. #define MAX_TX_BD (NUM_TX_BD - 1)
  224. #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
  225. #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
  226. (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
  227. #define TX_BD(x) ((x) & MAX_TX_BD)
  228. #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
  229. /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
  230. #define NUM_RX_RINGS 8
  231. #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
  232. #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
  233. #define RX_DESC_MASK (RX_DESC_CNT - 1)
  234. #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
  235. #define MAX_RX_BD (NUM_RX_BD - 1)
  236. #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
  237. #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
  238. (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
  239. #define RX_BD(x) ((x) & MAX_RX_BD)
  240. /* As long as CQE is 4 times bigger than BD entry we have to allocate
  241. 4 times more pages for CQ ring in order to keep it balanced with
  242. BD ring */
  243. #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
  244. #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
  245. #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
  246. #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
  247. #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
  248. #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
  249. #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
  250. (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
  251. #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
  252. /* This is needed for determining of last_max */
  253. #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
  254. #define __SGE_MASK_SET_BIT(el, bit) \
  255. do { \
  256. el = ((el) | ((u64)0x1 << (bit))); \
  257. } while (0)
  258. #define __SGE_MASK_CLEAR_BIT(el, bit) \
  259. do { \
  260. el = ((el) & (~((u64)0x1 << (bit)))); \
  261. } while (0)
  262. #define SGE_MASK_SET_BIT(fp, idx) \
  263. __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
  264. ((idx) & RX_SGE_MASK_ELEM_MASK))
  265. #define SGE_MASK_CLEAR_BIT(fp, idx) \
  266. __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
  267. ((idx) & RX_SGE_MASK_ELEM_MASK))
  268. /* used on a CID received from the HW */
  269. #define SW_CID(x) (le32_to_cpu(x) & \
  270. (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
  271. #define CQE_CMD(x) (le32_to_cpu(x) >> \
  272. COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
  273. #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
  274. le32_to_cpu((bd)->addr_lo))
  275. #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
  276. #define DPM_TRIGER_TYPE 0x40
  277. #define DOORBELL(bp, cid, val) \
  278. do { \
  279. writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
  280. DPM_TRIGER_TYPE); \
  281. } while (0)
  282. /* TX CSUM helpers */
  283. #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
  284. skb->csum_offset)
  285. #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
  286. skb->csum_offset))
  287. #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
  288. #define XMIT_PLAIN 0
  289. #define XMIT_CSUM_V4 0x1
  290. #define XMIT_CSUM_V6 0x2
  291. #define XMIT_CSUM_TCP 0x4
  292. #define XMIT_GSO_V4 0x8
  293. #define XMIT_GSO_V6 0x10
  294. #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
  295. #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
  296. /* stuff added to make the code fit 80Col */
  297. #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
  298. #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
  299. #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
  300. #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
  301. (TPA_TYPE_START | TPA_TYPE_END))
  302. #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
  303. #define BNX2X_IP_CSUM_ERR(cqe) \
  304. (!((cqe)->fast_path_cqe.status_flags & \
  305. ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
  306. ((cqe)->fast_path_cqe.type_error_flags & \
  307. ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
  308. #define BNX2X_L4_CSUM_ERR(cqe) \
  309. (!((cqe)->fast_path_cqe.status_flags & \
  310. ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
  311. ((cqe)->fast_path_cqe.type_error_flags & \
  312. ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
  313. #define BNX2X_RX_CSUM_OK(cqe) \
  314. (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
  315. #define BNX2X_RX_SUM_FIX(cqe) \
  316. ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
  317. PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
  318. (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
  319. #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
  320. #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
  321. #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
  322. #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
  323. #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
  324. #define BNX2X_RX_SB_INDEX \
  325. (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
  326. #define BNX2X_RX_SB_BD_INDEX \
  327. (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
  328. #define BNX2X_RX_SB_INDEX_NUM \
  329. (((U_SB_ETH_RX_CQ_INDEX << \
  330. USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
  331. USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
  332. ((U_SB_ETH_RX_BD_INDEX << \
  333. USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
  334. USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
  335. #define BNX2X_TX_SB_INDEX \
  336. (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
  337. /* end of fast path */
  338. /* common */
  339. struct bnx2x_common {
  340. u32 chip_id;
  341. /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
  342. #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
  343. #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
  344. #define CHIP_NUM_57710 0x164e
  345. #define CHIP_NUM_57711 0x164f
  346. #define CHIP_NUM_57711E 0x1650
  347. #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
  348. #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
  349. #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
  350. #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
  351. CHIP_IS_57711E(bp))
  352. #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
  353. #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
  354. #define CHIP_REV_Ax 0x00000000
  355. /* assume maximum 5 revisions */
  356. #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
  357. /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
  358. #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
  359. !(CHIP_REV(bp) & 0x00001000))
  360. /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
  361. #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
  362. (CHIP_REV(bp) & 0x00001000))
  363. #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
  364. ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
  365. #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
  366. #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
  367. int flash_size;
  368. #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
  369. #define NVRAM_TIMEOUT_COUNT 30000
  370. #define NVRAM_PAGE_SIZE 256
  371. u32 shmem_base;
  372. u32 hw_config;
  373. u32 board;
  374. u32 bc_ver;
  375. char *name;
  376. };
  377. /* end of common */
  378. /* port */
  379. struct nig_stats {
  380. u32 brb_discard;
  381. u32 brb_packet;
  382. u32 brb_truncate;
  383. u32 flow_ctrl_discard;
  384. u32 flow_ctrl_octets;
  385. u32 flow_ctrl_packet;
  386. u32 mng_discard;
  387. u32 mng_octet_inp;
  388. u32 mng_octet_out;
  389. u32 mng_packet_inp;
  390. u32 mng_packet_out;
  391. u32 pbf_octets;
  392. u32 pbf_packet;
  393. u32 safc_inp;
  394. u32 egress_mac_pkt0_lo;
  395. u32 egress_mac_pkt0_hi;
  396. u32 egress_mac_pkt1_lo;
  397. u32 egress_mac_pkt1_hi;
  398. };
  399. struct bnx2x_port {
  400. u32 pmf;
  401. u32 link_config;
  402. u32 supported;
  403. /* link settings - missing defines */
  404. #define SUPPORTED_2500baseX_Full (1 << 15)
  405. u32 advertising;
  406. /* link settings - missing defines */
  407. #define ADVERTISED_2500baseX_Full (1 << 15)
  408. u32 phy_addr;
  409. /* used to synchronize phy accesses */
  410. struct mutex phy_mutex;
  411. u32 port_stx;
  412. struct nig_stats old_nig_stats;
  413. };
  414. /* end of port */
  415. enum bnx2x_stats_event {
  416. STATS_EVENT_PMF = 0,
  417. STATS_EVENT_LINK_UP,
  418. STATS_EVENT_UPDATE,
  419. STATS_EVENT_STOP,
  420. STATS_EVENT_MAX
  421. };
  422. enum bnx2x_stats_state {
  423. STATS_STATE_DISABLED = 0,
  424. STATS_STATE_ENABLED,
  425. STATS_STATE_MAX
  426. };
  427. struct bnx2x_eth_stats {
  428. u32 total_bytes_received_hi;
  429. u32 total_bytes_received_lo;
  430. u32 total_bytes_transmitted_hi;
  431. u32 total_bytes_transmitted_lo;
  432. u32 total_unicast_packets_received_hi;
  433. u32 total_unicast_packets_received_lo;
  434. u32 total_multicast_packets_received_hi;
  435. u32 total_multicast_packets_received_lo;
  436. u32 total_broadcast_packets_received_hi;
  437. u32 total_broadcast_packets_received_lo;
  438. u32 total_unicast_packets_transmitted_hi;
  439. u32 total_unicast_packets_transmitted_lo;
  440. u32 total_multicast_packets_transmitted_hi;
  441. u32 total_multicast_packets_transmitted_lo;
  442. u32 total_broadcast_packets_transmitted_hi;
  443. u32 total_broadcast_packets_transmitted_lo;
  444. u32 valid_bytes_received_hi;
  445. u32 valid_bytes_received_lo;
  446. u32 error_bytes_received_hi;
  447. u32 error_bytes_received_lo;
  448. u32 rx_stat_ifhcinbadoctets_hi;
  449. u32 rx_stat_ifhcinbadoctets_lo;
  450. u32 tx_stat_ifhcoutbadoctets_hi;
  451. u32 tx_stat_ifhcoutbadoctets_lo;
  452. u32 rx_stat_dot3statsfcserrors_hi;
  453. u32 rx_stat_dot3statsfcserrors_lo;
  454. u32 rx_stat_dot3statsalignmenterrors_hi;
  455. u32 rx_stat_dot3statsalignmenterrors_lo;
  456. u32 rx_stat_dot3statscarriersenseerrors_hi;
  457. u32 rx_stat_dot3statscarriersenseerrors_lo;
  458. u32 rx_stat_falsecarriererrors_hi;
  459. u32 rx_stat_falsecarriererrors_lo;
  460. u32 rx_stat_etherstatsundersizepkts_hi;
  461. u32 rx_stat_etherstatsundersizepkts_lo;
  462. u32 rx_stat_dot3statsframestoolong_hi;
  463. u32 rx_stat_dot3statsframestoolong_lo;
  464. u32 rx_stat_etherstatsfragments_hi;
  465. u32 rx_stat_etherstatsfragments_lo;
  466. u32 rx_stat_etherstatsjabbers_hi;
  467. u32 rx_stat_etherstatsjabbers_lo;
  468. u32 rx_stat_maccontrolframesreceived_hi;
  469. u32 rx_stat_maccontrolframesreceived_lo;
  470. u32 rx_stat_bmac_xpf_hi;
  471. u32 rx_stat_bmac_xpf_lo;
  472. u32 rx_stat_bmac_xcf_hi;
  473. u32 rx_stat_bmac_xcf_lo;
  474. u32 rx_stat_xoffstateentered_hi;
  475. u32 rx_stat_xoffstateentered_lo;
  476. u32 rx_stat_xonpauseframesreceived_hi;
  477. u32 rx_stat_xonpauseframesreceived_lo;
  478. u32 rx_stat_xoffpauseframesreceived_hi;
  479. u32 rx_stat_xoffpauseframesreceived_lo;
  480. u32 tx_stat_outxonsent_hi;
  481. u32 tx_stat_outxonsent_lo;
  482. u32 tx_stat_outxoffsent_hi;
  483. u32 tx_stat_outxoffsent_lo;
  484. u32 tx_stat_flowcontroldone_hi;
  485. u32 tx_stat_flowcontroldone_lo;
  486. u32 tx_stat_etherstatscollisions_hi;
  487. u32 tx_stat_etherstatscollisions_lo;
  488. u32 tx_stat_dot3statssinglecollisionframes_hi;
  489. u32 tx_stat_dot3statssinglecollisionframes_lo;
  490. u32 tx_stat_dot3statsmultiplecollisionframes_hi;
  491. u32 tx_stat_dot3statsmultiplecollisionframes_lo;
  492. u32 tx_stat_dot3statsdeferredtransmissions_hi;
  493. u32 tx_stat_dot3statsdeferredtransmissions_lo;
  494. u32 tx_stat_dot3statsexcessivecollisions_hi;
  495. u32 tx_stat_dot3statsexcessivecollisions_lo;
  496. u32 tx_stat_dot3statslatecollisions_hi;
  497. u32 tx_stat_dot3statslatecollisions_lo;
  498. u32 tx_stat_etherstatspkts64octets_hi;
  499. u32 tx_stat_etherstatspkts64octets_lo;
  500. u32 tx_stat_etherstatspkts65octetsto127octets_hi;
  501. u32 tx_stat_etherstatspkts65octetsto127octets_lo;
  502. u32 tx_stat_etherstatspkts128octetsto255octets_hi;
  503. u32 tx_stat_etherstatspkts128octetsto255octets_lo;
  504. u32 tx_stat_etherstatspkts256octetsto511octets_hi;
  505. u32 tx_stat_etherstatspkts256octetsto511octets_lo;
  506. u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
  507. u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
  508. u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
  509. u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
  510. u32 tx_stat_etherstatspktsover1522octets_hi;
  511. u32 tx_stat_etherstatspktsover1522octets_lo;
  512. u32 tx_stat_bmac_2047_hi;
  513. u32 tx_stat_bmac_2047_lo;
  514. u32 tx_stat_bmac_4095_hi;
  515. u32 tx_stat_bmac_4095_lo;
  516. u32 tx_stat_bmac_9216_hi;
  517. u32 tx_stat_bmac_9216_lo;
  518. u32 tx_stat_bmac_16383_hi;
  519. u32 tx_stat_bmac_16383_lo;
  520. u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
  521. u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
  522. u32 tx_stat_bmac_ufl_hi;
  523. u32 tx_stat_bmac_ufl_lo;
  524. u32 brb_drop_hi;
  525. u32 brb_drop_lo;
  526. u32 brb_truncate_hi;
  527. u32 brb_truncate_lo;
  528. u32 jabber_packets_received;
  529. u32 etherstatspkts1024octetsto1522octets_hi;
  530. u32 etherstatspkts1024octetsto1522octets_lo;
  531. u32 etherstatspktsover1522octets_hi;
  532. u32 etherstatspktsover1522octets_lo;
  533. u32 no_buff_discard;
  534. u32 mac_filter_discard;
  535. u32 xxoverflow_discard;
  536. u32 brb_truncate_discard;
  537. u32 mac_discard;
  538. u32 driver_xoff;
  539. u32 rx_err_discard_pkt;
  540. u32 rx_skb_alloc_failed;
  541. u32 hw_csum_err;
  542. };
  543. #define STATS_OFFSET32(stat_name) \
  544. (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
  545. #ifdef BNX2X_MULTI
  546. #define MAX_CONTEXT 16
  547. #else
  548. #define MAX_CONTEXT 1
  549. #endif
  550. union cdu_context {
  551. struct eth_context eth;
  552. char pad[1024];
  553. };
  554. #define MAX_DMAE_C 8
  555. /* DMA memory not used in fastpath */
  556. struct bnx2x_slowpath {
  557. union cdu_context context[MAX_CONTEXT];
  558. struct eth_stats_query fw_stats;
  559. struct mac_configuration_cmd mac_config;
  560. struct mac_configuration_cmd mcast_config;
  561. /* used by dmae command executer */
  562. struct dmae_command dmae[MAX_DMAE_C];
  563. u32 stats_comp;
  564. union mac_stats mac_stats;
  565. struct nig_stats nig_stats;
  566. struct host_port_stats port_stats;
  567. struct host_func_stats func_stats;
  568. u32 wb_comp;
  569. u32 wb_data[4];
  570. };
  571. #define bnx2x_sp(bp, var) (&bp->slowpath->var)
  572. #define bnx2x_sp_mapping(bp, var) \
  573. (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
  574. /* attn group wiring */
  575. #define MAX_DYNAMIC_ATTN_GRPS 8
  576. struct attn_route {
  577. u32 sig[4];
  578. };
  579. struct bnx2x {
  580. /* Fields used in the tx and intr/napi performance paths
  581. * are grouped together in the beginning of the structure
  582. */
  583. struct bnx2x_fastpath fp[MAX_CONTEXT];
  584. void __iomem *regview;
  585. void __iomem *doorbells;
  586. #define BNX2X_DB_SIZE (16*2048)
  587. struct net_device *dev;
  588. struct pci_dev *pdev;
  589. atomic_t intr_sem;
  590. struct msix_entry msix_table[MAX_CONTEXT+1];
  591. int tx_ring_size;
  592. #ifdef BCM_VLAN
  593. struct vlan_group *vlgrp;
  594. #endif
  595. u32 rx_csum;
  596. u32 rx_offset;
  597. u32 rx_buf_use_size; /* useable size */
  598. u32 rx_buf_size; /* with alignment */
  599. #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
  600. #define ETH_MIN_PACKET_SIZE 60
  601. #define ETH_MAX_PACKET_SIZE 1500
  602. #define ETH_MAX_JUMBO_PACKET_SIZE 9600
  603. struct host_def_status_block *def_status_blk;
  604. #define DEF_SB_ID 16
  605. u16 def_c_idx;
  606. u16 def_u_idx;
  607. u16 def_x_idx;
  608. u16 def_t_idx;
  609. u16 def_att_idx;
  610. u32 attn_state;
  611. struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
  612. u32 nig_mask;
  613. /* slow path ring */
  614. struct eth_spe *spq;
  615. dma_addr_t spq_mapping;
  616. u16 spq_prod_idx;
  617. struct eth_spe *spq_prod_bd;
  618. struct eth_spe *spq_last_bd;
  619. u16 *dsb_sp_prod;
  620. u16 spq_left; /* serialize spq */
  621. /* used to synchronize spq accesses */
  622. spinlock_t spq_lock;
  623. /* Flags for marking that there is a STAT_QUERY or
  624. SET_MAC ramrod pending */
  625. u8 stats_pending;
  626. u8 set_mac_pending;
  627. /* End of fields used in the performance code paths */
  628. int panic;
  629. int msglevel;
  630. u32 flags;
  631. #define PCIX_FLAG 1
  632. #define PCI_32BIT_FLAG 2
  633. #define ONE_TDMA_FLAG 4 /* no longer used */
  634. #define NO_WOL_FLAG 8
  635. #define USING_DAC_FLAG 0x10
  636. #define USING_MSIX_FLAG 0x20
  637. #define ASF_ENABLE_FLAG 0x40
  638. #define TPA_ENABLE_FLAG 0x80
  639. #define NO_MCP_FLAG 0x100
  640. #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
  641. int func;
  642. #define BP_PORT(bp) (bp->func % PORT_MAX)
  643. #define BP_FUNC(bp) (bp->func)
  644. #define BP_E1HVN(bp) (bp->func >> 1)
  645. #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
  646. int pm_cap;
  647. int pcie_cap;
  648. struct work_struct sp_task;
  649. struct work_struct reset_task;
  650. struct timer_list timer;
  651. int timer_interval;
  652. int current_interval;
  653. u16 fw_seq;
  654. u16 fw_drv_pulse_wr_seq;
  655. u32 func_stx;
  656. struct link_params link_params;
  657. struct link_vars link_vars;
  658. struct bnx2x_common common;
  659. struct bnx2x_port port;
  660. u32 mf_config;
  661. u16 e1hov;
  662. u8 e1hmf;
  663. #define IS_E1HMF(bp) (bp->e1hmf != 0)
  664. u8 wol;
  665. int rx_ring_size;
  666. u16 tx_quick_cons_trip_int;
  667. u16 tx_quick_cons_trip;
  668. u16 tx_ticks_int;
  669. u16 tx_ticks;
  670. u16 rx_quick_cons_trip_int;
  671. u16 rx_quick_cons_trip;
  672. u16 rx_ticks_int;
  673. u16 rx_ticks;
  674. u32 lin_cnt;
  675. int state;
  676. #define BNX2X_STATE_CLOSED 0x0
  677. #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
  678. #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
  679. #define BNX2X_STATE_OPEN 0x3000
  680. #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
  681. #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
  682. #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
  683. #define BNX2X_STATE_DISABLED 0xd000
  684. #define BNX2X_STATE_DIAG 0xe000
  685. #define BNX2X_STATE_ERROR 0xf000
  686. int num_queues;
  687. #define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
  688. u32 rx_mode;
  689. #define BNX2X_RX_MODE_NONE 0
  690. #define BNX2X_RX_MODE_NORMAL 1
  691. #define BNX2X_RX_MODE_ALLMULTI 2
  692. #define BNX2X_RX_MODE_PROMISC 3
  693. #define BNX2X_MAX_MULTICAST 64
  694. #define BNX2X_MAX_EMUL_MULTI 16
  695. dma_addr_t def_status_blk_mapping;
  696. struct bnx2x_slowpath *slowpath;
  697. dma_addr_t slowpath_mapping;
  698. #ifdef BCM_ISCSI
  699. void *t1;
  700. dma_addr_t t1_mapping;
  701. void *t2;
  702. dma_addr_t t2_mapping;
  703. void *timers;
  704. dma_addr_t timers_mapping;
  705. void *qm;
  706. dma_addr_t qm_mapping;
  707. #endif
  708. int dmae_ready;
  709. /* used to synchronize dmae accesses */
  710. struct mutex dmae_mutex;
  711. struct dmae_command init_dmae;
  712. /* used to synchronize stats collecting */
  713. int stats_state;
  714. /* used by dmae command loader */
  715. struct dmae_command stats_dmae;
  716. int executer_idx;
  717. u16 stats_counter;
  718. struct tstorm_per_client_stats old_tclient;
  719. struct xstorm_per_client_stats old_xclient;
  720. struct bnx2x_eth_stats eth_stats;
  721. struct z_stream_s *strm;
  722. void *gunzip_buf;
  723. dma_addr_t gunzip_mapping;
  724. int gunzip_outlen;
  725. #define FW_BUF_SIZE 0x8000
  726. };
  727. #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
  728. #define for_each_nondefault_queue(bp, var) \
  729. for (var = 1; var < bp->num_queues; var++)
  730. #define is_multi(bp) (bp->num_queues > 1)
  731. void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
  732. void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
  733. u32 len32);
  734. int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
  735. static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
  736. int wait)
  737. {
  738. u32 val;
  739. do {
  740. val = REG_RD(bp, reg);
  741. if (val == expected)
  742. break;
  743. ms -= wait;
  744. msleep(wait);
  745. } while (ms > 0);
  746. return val;
  747. }
  748. /* load/unload mode */
  749. #define LOAD_NORMAL 0
  750. #define LOAD_OPEN 1
  751. #define LOAD_DIAG 2
  752. #define UNLOAD_NORMAL 0
  753. #define UNLOAD_CLOSE 1
  754. /* DMAE command defines */
  755. #define DMAE_CMD_SRC_PCI 0
  756. #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
  757. #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
  758. #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
  759. #define DMAE_CMD_C_DST_PCI 0
  760. #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
  761. #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
  762. #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
  763. #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
  764. #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
  765. #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
  766. #define DMAE_CMD_PORT_0 0
  767. #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
  768. #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
  769. #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
  770. #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
  771. #define DMAE_LEN32_RD_MAX 0x80
  772. #define DMAE_LEN32_WR_MAX 0x400
  773. #define DMAE_COMP_VAL 0xe0d0d0ae
  774. #define MAX_DMAE_C_PER_PORT 8
  775. #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
  776. BP_E1HVN(bp))
  777. #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
  778. E1HVN_MAX)
  779. /* PCIE link and speed */
  780. #define PCICFG_LINK_WIDTH 0x1f00000
  781. #define PCICFG_LINK_WIDTH_SHIFT 20
  782. #define PCICFG_LINK_SPEED 0xf0000
  783. #define PCICFG_LINK_SPEED_SHIFT 16
  784. #define BNX2X_NUM_STATS 42
  785. #define BNX2X_NUM_TESTS 8
  786. #define BNX2X_MAC_LOOPBACK 0
  787. #define BNX2X_PHY_LOOPBACK 1
  788. #define BNX2X_MAC_LOOPBACK_FAILED 1
  789. #define BNX2X_PHY_LOOPBACK_FAILED 2
  790. #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
  791. BNX2X_PHY_LOOPBACK_FAILED)
  792. #define STROM_ASSERT_ARRAY_SIZE 50
  793. /* must be used on a CID before placing it on a HW ring */
  794. #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
  795. #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
  796. #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
  797. #define BNX2X_BTR 3
  798. #define MAX_SPQ_PENDING 8
  799. /* CMNG constants
  800. derived from lab experiments, and not from system spec calculations !!! */
  801. #define DEF_MIN_RATE 100
  802. /* resolution of the rate shaping timer - 100 usec */
  803. #define RS_PERIODIC_TIMEOUT_USEC 100
  804. /* resolution of fairness algorithm in usecs -
  805. coefficient for calculating the actual t fair */
  806. #define T_FAIR_COEF 10000000
  807. /* number of bytes in single QM arbitration cycle -
  808. coefficient for calculating the fairness timer */
  809. #define QM_ARB_BYTES 40000
  810. #define FAIR_MEM 2
  811. #define ATTN_NIG_FOR_FUNC (1L << 8)
  812. #define ATTN_SW_TIMER_4_FUNC (1L << 9)
  813. #define GPIO_2_FUNC (1L << 10)
  814. #define GPIO_3_FUNC (1L << 11)
  815. #define GPIO_4_FUNC (1L << 12)
  816. #define ATTN_GENERAL_ATTN_1 (1L << 13)
  817. #define ATTN_GENERAL_ATTN_2 (1L << 14)
  818. #define ATTN_GENERAL_ATTN_3 (1L << 15)
  819. #define ATTN_GENERAL_ATTN_4 (1L << 13)
  820. #define ATTN_GENERAL_ATTN_5 (1L << 14)
  821. #define ATTN_GENERAL_ATTN_6 (1L << 15)
  822. #define ATTN_HARD_WIRED_MASK 0xff00
  823. #define ATTENTION_ID 4
  824. /* stuff added to make the code fit 80Col */
  825. #define BNX2X_PMF_LINK_ASSERT \
  826. GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
  827. #define BNX2X_MC_ASSERT_BITS \
  828. (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
  829. GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
  830. GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
  831. GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
  832. #define BNX2X_MCP_ASSERT \
  833. GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
  834. #define BNX2X_DOORQ_ASSERT \
  835. AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
  836. #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
  837. #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
  838. GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
  839. GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
  840. GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
  841. GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
  842. GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
  843. #define HW_INTERRUT_ASSERT_SET_0 \
  844. (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
  845. AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
  846. AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
  847. AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
  848. #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
  849. AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
  850. AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
  851. AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
  852. AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
  853. #define HW_INTERRUT_ASSERT_SET_1 \
  854. (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
  855. AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
  856. AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
  857. AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
  858. AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
  859. AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
  860. AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
  861. AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
  862. AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
  863. AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
  864. AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
  865. #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
  866. AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
  867. AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
  868. AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
  869. AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
  870. AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
  871. AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
  872. AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
  873. AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
  874. AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
  875. AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
  876. #define HW_INTERRUT_ASSERT_SET_2 \
  877. (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
  878. AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
  879. AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
  880. AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
  881. AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
  882. #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
  883. AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
  884. AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
  885. AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
  886. AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
  887. AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
  888. AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
  889. #define MULTI_FLAGS \
  890. (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
  891. TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
  892. TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
  893. TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
  894. TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
  895. #define MULTI_MASK 0x7f
  896. #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
  897. #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
  898. #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
  899. #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
  900. #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
  901. #define BNX2X_SP_DSB_INDEX \
  902. (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
  903. #define CAM_IS_INVALID(x) \
  904. (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
  905. #define CAM_INVALIDATE(x) \
  906. (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
  907. /* Number of u32 elements in MC hash array */
  908. #define MC_HASH_SIZE 8
  909. #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
  910. TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
  911. #ifndef PXP2_REG_PXP2_INT_STS
  912. #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
  913. #endif
  914. /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
  915. #endif /* bnx2x.h */