bnx2.c 191 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937
  1. /* bnx2.c: Broadcom NX2 network driver.
  2. *
  3. * Copyright (c) 2004-2008 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Written by: Michael Chan (mchan@broadcom.com)
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/kernel.h>
  14. #include <linux/timer.h>
  15. #include <linux/errno.h>
  16. #include <linux/ioport.h>
  17. #include <linux/slab.h>
  18. #include <linux/vmalloc.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/pci.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/skbuff.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/bitops.h>
  27. #include <asm/io.h>
  28. #include <asm/irq.h>
  29. #include <linux/delay.h>
  30. #include <asm/byteorder.h>
  31. #include <asm/page.h>
  32. #include <linux/time.h>
  33. #include <linux/ethtool.h>
  34. #include <linux/mii.h>
  35. #include <linux/if_vlan.h>
  36. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  37. #define BCM_VLAN 1
  38. #endif
  39. #include <net/ip.h>
  40. #include <net/tcp.h>
  41. #include <net/checksum.h>
  42. #include <linux/workqueue.h>
  43. #include <linux/crc32.h>
  44. #include <linux/prefetch.h>
  45. #include <linux/cache.h>
  46. #include <linux/zlib.h>
  47. #include <linux/log2.h>
  48. #include "bnx2.h"
  49. #include "bnx2_fw.h"
  50. #include "bnx2_fw2.h"
  51. #define FW_BUF_SIZE 0x10000
  52. #define DRV_MODULE_NAME "bnx2"
  53. #define PFX DRV_MODULE_NAME ": "
  54. #define DRV_MODULE_VERSION "1.8.0"
  55. #define DRV_MODULE_RELDATE "Aug 14, 2008"
  56. #define RUN_AT(x) (jiffies + (x))
  57. /* Time in jiffies before concluding the transmitter is hung. */
  58. #define TX_TIMEOUT (5*HZ)
  59. static char version[] __devinitdata =
  60. "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  61. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  62. MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709 Driver");
  63. MODULE_LICENSE("GPL");
  64. MODULE_VERSION(DRV_MODULE_VERSION);
  65. static int disable_msi = 0;
  66. module_param(disable_msi, int, 0);
  67. MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  68. typedef enum {
  69. BCM5706 = 0,
  70. NC370T,
  71. NC370I,
  72. BCM5706S,
  73. NC370F,
  74. BCM5708,
  75. BCM5708S,
  76. BCM5709,
  77. BCM5709S,
  78. BCM5716,
  79. } board_t;
  80. /* indexed by board_t, above */
  81. static struct {
  82. char *name;
  83. } board_info[] __devinitdata = {
  84. { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  85. { "HP NC370T Multifunction Gigabit Server Adapter" },
  86. { "HP NC370i Multifunction Gigabit Server Adapter" },
  87. { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  88. { "HP NC370F Multifunction Gigabit Server Adapter" },
  89. { "Broadcom NetXtreme II BCM5708 1000Base-T" },
  90. { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
  91. { "Broadcom NetXtreme II BCM5709 1000Base-T" },
  92. { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
  93. { "Broadcom NetXtreme II BCM5716 1000Base-T" },
  94. };
  95. static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
  96. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  97. PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  98. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  99. PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  100. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  101. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  102. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
  103. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
  104. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  105. PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  106. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  107. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  108. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
  109. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
  110. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
  111. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
  112. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
  113. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
  114. { PCI_VENDOR_ID_BROADCOM, 0x163b,
  115. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
  116. { 0, }
  117. };
  118. static struct flash_spec flash_table[] =
  119. {
  120. #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
  121. #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
  122. /* Slow EEPROM */
  123. {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  124. BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  125. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  126. "EEPROM - slow"},
  127. /* Expansion entry 0001 */
  128. {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  129. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  130. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  131. "Entry 0001"},
  132. /* Saifun SA25F010 (non-buffered flash) */
  133. /* strap, cfg1, & write1 need updates */
  134. {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  135. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  136. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  137. "Non-buffered flash (128kB)"},
  138. /* Saifun SA25F020 (non-buffered flash) */
  139. /* strap, cfg1, & write1 need updates */
  140. {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
  141. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  142. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
  143. "Non-buffered flash (256kB)"},
  144. /* Expansion entry 0100 */
  145. {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
  146. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  147. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  148. "Entry 0100"},
  149. /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
  150. {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
  151. NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  152. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
  153. "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
  154. /* Entry 0110: ST M45PE20 (non-buffered flash)*/
  155. {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
  156. NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  157. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
  158. "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
  159. /* Saifun SA25F005 (non-buffered flash) */
  160. /* strap, cfg1, & write1 need updates */
  161. {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
  162. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  163. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
  164. "Non-buffered flash (64kB)"},
  165. /* Fast EEPROM */
  166. {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
  167. BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  168. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  169. "EEPROM - fast"},
  170. /* Expansion entry 1001 */
  171. {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
  172. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  173. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  174. "Entry 1001"},
  175. /* Expansion entry 1010 */
  176. {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
  177. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  178. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  179. "Entry 1010"},
  180. /* ATMEL AT45DB011B (buffered flash) */
  181. {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
  182. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  183. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
  184. "Buffered flash (128kB)"},
  185. /* Expansion entry 1100 */
  186. {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
  187. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  188. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  189. "Entry 1100"},
  190. /* Expansion entry 1101 */
  191. {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
  192. NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  193. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  194. "Entry 1101"},
  195. /* Ateml Expansion entry 1110 */
  196. {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
  197. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  198. BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
  199. "Entry 1110 (Atmel)"},
  200. /* ATMEL AT45DB021B (buffered flash) */
  201. {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
  202. BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  203. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
  204. "Buffered flash (256kB)"},
  205. };
  206. static struct flash_spec flash_5709 = {
  207. .flags = BNX2_NV_BUFFERED,
  208. .page_bits = BCM5709_FLASH_PAGE_BITS,
  209. .page_size = BCM5709_FLASH_PAGE_SIZE,
  210. .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
  211. .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
  212. .name = "5709 Buffered flash (256kB)",
  213. };
  214. MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
  215. static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
  216. {
  217. u32 diff;
  218. smp_mb();
  219. /* The ring uses 256 indices for 255 entries, one of them
  220. * needs to be skipped.
  221. */
  222. diff = txr->tx_prod - txr->tx_cons;
  223. if (unlikely(diff >= TX_DESC_CNT)) {
  224. diff &= 0xffff;
  225. if (diff == TX_DESC_CNT)
  226. diff = MAX_TX_DESC_CNT;
  227. }
  228. return (bp->tx_ring_size - diff);
  229. }
  230. static u32
  231. bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
  232. {
  233. u32 val;
  234. spin_lock_bh(&bp->indirect_lock);
  235. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  236. val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
  237. spin_unlock_bh(&bp->indirect_lock);
  238. return val;
  239. }
  240. static void
  241. bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
  242. {
  243. spin_lock_bh(&bp->indirect_lock);
  244. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  245. REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
  246. spin_unlock_bh(&bp->indirect_lock);
  247. }
  248. static void
  249. bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
  250. {
  251. bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
  252. }
  253. static u32
  254. bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
  255. {
  256. return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
  257. }
  258. static void
  259. bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
  260. {
  261. offset += cid_addr;
  262. spin_lock_bh(&bp->indirect_lock);
  263. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  264. int i;
  265. REG_WR(bp, BNX2_CTX_CTX_DATA, val);
  266. REG_WR(bp, BNX2_CTX_CTX_CTRL,
  267. offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
  268. for (i = 0; i < 5; i++) {
  269. val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
  270. if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
  271. break;
  272. udelay(5);
  273. }
  274. } else {
  275. REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
  276. REG_WR(bp, BNX2_CTX_DATA, val);
  277. }
  278. spin_unlock_bh(&bp->indirect_lock);
  279. }
  280. static int
  281. bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
  282. {
  283. u32 val1;
  284. int i, ret;
  285. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  286. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  287. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  288. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  289. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  290. udelay(40);
  291. }
  292. val1 = (bp->phy_addr << 21) | (reg << 16) |
  293. BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
  294. BNX2_EMAC_MDIO_COMM_START_BUSY;
  295. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  296. for (i = 0; i < 50; i++) {
  297. udelay(10);
  298. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  299. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  300. udelay(5);
  301. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  302. val1 &= BNX2_EMAC_MDIO_COMM_DATA;
  303. break;
  304. }
  305. }
  306. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
  307. *val = 0x0;
  308. ret = -EBUSY;
  309. }
  310. else {
  311. *val = val1;
  312. ret = 0;
  313. }
  314. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  315. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  316. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  317. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  318. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  319. udelay(40);
  320. }
  321. return ret;
  322. }
  323. static int
  324. bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
  325. {
  326. u32 val1;
  327. int i, ret;
  328. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  329. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  330. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  331. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  332. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  333. udelay(40);
  334. }
  335. val1 = (bp->phy_addr << 21) | (reg << 16) | val |
  336. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
  337. BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
  338. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  339. for (i = 0; i < 50; i++) {
  340. udelay(10);
  341. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  342. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  343. udelay(5);
  344. break;
  345. }
  346. }
  347. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
  348. ret = -EBUSY;
  349. else
  350. ret = 0;
  351. if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
  352. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  353. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  354. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  355. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  356. udelay(40);
  357. }
  358. return ret;
  359. }
  360. static void
  361. bnx2_disable_int(struct bnx2 *bp)
  362. {
  363. int i;
  364. struct bnx2_napi *bnapi;
  365. for (i = 0; i < bp->irq_nvecs; i++) {
  366. bnapi = &bp->bnx2_napi[i];
  367. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  368. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  369. }
  370. REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  371. }
  372. static void
  373. bnx2_enable_int(struct bnx2 *bp)
  374. {
  375. int i;
  376. struct bnx2_napi *bnapi;
  377. for (i = 0; i < bp->irq_nvecs; i++) {
  378. bnapi = &bp->bnx2_napi[i];
  379. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  380. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  381. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  382. bnapi->last_status_idx);
  383. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  384. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  385. bnapi->last_status_idx);
  386. }
  387. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  388. }
  389. static void
  390. bnx2_disable_int_sync(struct bnx2 *bp)
  391. {
  392. int i;
  393. atomic_inc(&bp->intr_sem);
  394. bnx2_disable_int(bp);
  395. for (i = 0; i < bp->irq_nvecs; i++)
  396. synchronize_irq(bp->irq_tbl[i].vector);
  397. }
  398. static void
  399. bnx2_napi_disable(struct bnx2 *bp)
  400. {
  401. int i;
  402. for (i = 0; i < bp->irq_nvecs; i++)
  403. napi_disable(&bp->bnx2_napi[i].napi);
  404. }
  405. static void
  406. bnx2_napi_enable(struct bnx2 *bp)
  407. {
  408. int i;
  409. for (i = 0; i < bp->irq_nvecs; i++)
  410. napi_enable(&bp->bnx2_napi[i].napi);
  411. }
  412. static void
  413. bnx2_netif_stop(struct bnx2 *bp)
  414. {
  415. bnx2_disable_int_sync(bp);
  416. if (netif_running(bp->dev)) {
  417. bnx2_napi_disable(bp);
  418. netif_tx_disable(bp->dev);
  419. bp->dev->trans_start = jiffies; /* prevent tx timeout */
  420. }
  421. }
  422. static void
  423. bnx2_netif_start(struct bnx2 *bp)
  424. {
  425. if (atomic_dec_and_test(&bp->intr_sem)) {
  426. if (netif_running(bp->dev)) {
  427. netif_tx_wake_all_queues(bp->dev);
  428. bnx2_napi_enable(bp);
  429. bnx2_enable_int(bp);
  430. }
  431. }
  432. }
  433. static void
  434. bnx2_free_tx_mem(struct bnx2 *bp)
  435. {
  436. int i;
  437. for (i = 0; i < bp->num_tx_rings; i++) {
  438. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  439. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  440. if (txr->tx_desc_ring) {
  441. pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
  442. txr->tx_desc_ring,
  443. txr->tx_desc_mapping);
  444. txr->tx_desc_ring = NULL;
  445. }
  446. kfree(txr->tx_buf_ring);
  447. txr->tx_buf_ring = NULL;
  448. }
  449. }
  450. static void
  451. bnx2_free_rx_mem(struct bnx2 *bp)
  452. {
  453. int i;
  454. for (i = 0; i < bp->num_rx_rings; i++) {
  455. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  456. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  457. int j;
  458. for (j = 0; j < bp->rx_max_ring; j++) {
  459. if (rxr->rx_desc_ring[j])
  460. pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
  461. rxr->rx_desc_ring[j],
  462. rxr->rx_desc_mapping[j]);
  463. rxr->rx_desc_ring[j] = NULL;
  464. }
  465. if (rxr->rx_buf_ring)
  466. vfree(rxr->rx_buf_ring);
  467. rxr->rx_buf_ring = NULL;
  468. for (j = 0; j < bp->rx_max_pg_ring; j++) {
  469. if (rxr->rx_pg_desc_ring[j])
  470. pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
  471. rxr->rx_pg_desc_ring[i],
  472. rxr->rx_pg_desc_mapping[i]);
  473. rxr->rx_pg_desc_ring[i] = NULL;
  474. }
  475. if (rxr->rx_pg_ring)
  476. vfree(rxr->rx_pg_ring);
  477. rxr->rx_pg_ring = NULL;
  478. }
  479. }
  480. static int
  481. bnx2_alloc_tx_mem(struct bnx2 *bp)
  482. {
  483. int i;
  484. for (i = 0; i < bp->num_tx_rings; i++) {
  485. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  486. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  487. txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
  488. if (txr->tx_buf_ring == NULL)
  489. return -ENOMEM;
  490. txr->tx_desc_ring =
  491. pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
  492. &txr->tx_desc_mapping);
  493. if (txr->tx_desc_ring == NULL)
  494. return -ENOMEM;
  495. }
  496. return 0;
  497. }
  498. static int
  499. bnx2_alloc_rx_mem(struct bnx2 *bp)
  500. {
  501. int i;
  502. for (i = 0; i < bp->num_rx_rings; i++) {
  503. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  504. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  505. int j;
  506. rxr->rx_buf_ring =
  507. vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
  508. if (rxr->rx_buf_ring == NULL)
  509. return -ENOMEM;
  510. memset(rxr->rx_buf_ring, 0,
  511. SW_RXBD_RING_SIZE * bp->rx_max_ring);
  512. for (j = 0; j < bp->rx_max_ring; j++) {
  513. rxr->rx_desc_ring[j] =
  514. pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
  515. &rxr->rx_desc_mapping[j]);
  516. if (rxr->rx_desc_ring[j] == NULL)
  517. return -ENOMEM;
  518. }
  519. if (bp->rx_pg_ring_size) {
  520. rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
  521. bp->rx_max_pg_ring);
  522. if (rxr->rx_pg_ring == NULL)
  523. return -ENOMEM;
  524. memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
  525. bp->rx_max_pg_ring);
  526. }
  527. for (j = 0; j < bp->rx_max_pg_ring; j++) {
  528. rxr->rx_pg_desc_ring[j] =
  529. pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
  530. &rxr->rx_pg_desc_mapping[j]);
  531. if (rxr->rx_pg_desc_ring[j] == NULL)
  532. return -ENOMEM;
  533. }
  534. }
  535. return 0;
  536. }
  537. static void
  538. bnx2_free_mem(struct bnx2 *bp)
  539. {
  540. int i;
  541. struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
  542. bnx2_free_tx_mem(bp);
  543. bnx2_free_rx_mem(bp);
  544. for (i = 0; i < bp->ctx_pages; i++) {
  545. if (bp->ctx_blk[i]) {
  546. pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
  547. bp->ctx_blk[i],
  548. bp->ctx_blk_mapping[i]);
  549. bp->ctx_blk[i] = NULL;
  550. }
  551. }
  552. if (bnapi->status_blk.msi) {
  553. pci_free_consistent(bp->pdev, bp->status_stats_size,
  554. bnapi->status_blk.msi,
  555. bp->status_blk_mapping);
  556. bnapi->status_blk.msi = NULL;
  557. bp->stats_blk = NULL;
  558. }
  559. }
  560. static int
  561. bnx2_alloc_mem(struct bnx2 *bp)
  562. {
  563. int i, status_blk_size, err;
  564. struct bnx2_napi *bnapi;
  565. void *status_blk;
  566. /* Combine status and statistics blocks into one allocation. */
  567. status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
  568. if (bp->flags & BNX2_FLAG_MSIX_CAP)
  569. status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
  570. BNX2_SBLK_MSIX_ALIGN_SIZE);
  571. bp->status_stats_size = status_blk_size +
  572. sizeof(struct statistics_block);
  573. status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
  574. &bp->status_blk_mapping);
  575. if (status_blk == NULL)
  576. goto alloc_mem_err;
  577. memset(status_blk, 0, bp->status_stats_size);
  578. bnapi = &bp->bnx2_napi[0];
  579. bnapi->status_blk.msi = status_blk;
  580. bnapi->hw_tx_cons_ptr =
  581. &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
  582. bnapi->hw_rx_cons_ptr =
  583. &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
  584. if (bp->flags & BNX2_FLAG_MSIX_CAP) {
  585. for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
  586. struct status_block_msix *sblk;
  587. bnapi = &bp->bnx2_napi[i];
  588. sblk = (void *) (status_blk +
  589. BNX2_SBLK_MSIX_ALIGN_SIZE * i);
  590. bnapi->status_blk.msix = sblk;
  591. bnapi->hw_tx_cons_ptr =
  592. &sblk->status_tx_quick_consumer_index;
  593. bnapi->hw_rx_cons_ptr =
  594. &sblk->status_rx_quick_consumer_index;
  595. bnapi->int_num = i << 24;
  596. }
  597. }
  598. bp->stats_blk = status_blk + status_blk_size;
  599. bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
  600. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  601. bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
  602. if (bp->ctx_pages == 0)
  603. bp->ctx_pages = 1;
  604. for (i = 0; i < bp->ctx_pages; i++) {
  605. bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
  606. BCM_PAGE_SIZE,
  607. &bp->ctx_blk_mapping[i]);
  608. if (bp->ctx_blk[i] == NULL)
  609. goto alloc_mem_err;
  610. }
  611. }
  612. err = bnx2_alloc_rx_mem(bp);
  613. if (err)
  614. goto alloc_mem_err;
  615. err = bnx2_alloc_tx_mem(bp);
  616. if (err)
  617. goto alloc_mem_err;
  618. return 0;
  619. alloc_mem_err:
  620. bnx2_free_mem(bp);
  621. return -ENOMEM;
  622. }
  623. static void
  624. bnx2_report_fw_link(struct bnx2 *bp)
  625. {
  626. u32 fw_link_status = 0;
  627. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  628. return;
  629. if (bp->link_up) {
  630. u32 bmsr;
  631. switch (bp->line_speed) {
  632. case SPEED_10:
  633. if (bp->duplex == DUPLEX_HALF)
  634. fw_link_status = BNX2_LINK_STATUS_10HALF;
  635. else
  636. fw_link_status = BNX2_LINK_STATUS_10FULL;
  637. break;
  638. case SPEED_100:
  639. if (bp->duplex == DUPLEX_HALF)
  640. fw_link_status = BNX2_LINK_STATUS_100HALF;
  641. else
  642. fw_link_status = BNX2_LINK_STATUS_100FULL;
  643. break;
  644. case SPEED_1000:
  645. if (bp->duplex == DUPLEX_HALF)
  646. fw_link_status = BNX2_LINK_STATUS_1000HALF;
  647. else
  648. fw_link_status = BNX2_LINK_STATUS_1000FULL;
  649. break;
  650. case SPEED_2500:
  651. if (bp->duplex == DUPLEX_HALF)
  652. fw_link_status = BNX2_LINK_STATUS_2500HALF;
  653. else
  654. fw_link_status = BNX2_LINK_STATUS_2500FULL;
  655. break;
  656. }
  657. fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
  658. if (bp->autoneg) {
  659. fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
  660. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  661. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  662. if (!(bmsr & BMSR_ANEGCOMPLETE) ||
  663. bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
  664. fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
  665. else
  666. fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
  667. }
  668. }
  669. else
  670. fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
  671. bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
  672. }
  673. static char *
  674. bnx2_xceiver_str(struct bnx2 *bp)
  675. {
  676. return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
  677. ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
  678. "Copper"));
  679. }
  680. static void
  681. bnx2_report_link(struct bnx2 *bp)
  682. {
  683. if (bp->link_up) {
  684. netif_carrier_on(bp->dev);
  685. printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
  686. bnx2_xceiver_str(bp));
  687. printk("%d Mbps ", bp->line_speed);
  688. if (bp->duplex == DUPLEX_FULL)
  689. printk("full duplex");
  690. else
  691. printk("half duplex");
  692. if (bp->flow_ctrl) {
  693. if (bp->flow_ctrl & FLOW_CTRL_RX) {
  694. printk(", receive ");
  695. if (bp->flow_ctrl & FLOW_CTRL_TX)
  696. printk("& transmit ");
  697. }
  698. else {
  699. printk(", transmit ");
  700. }
  701. printk("flow control ON");
  702. }
  703. printk("\n");
  704. }
  705. else {
  706. netif_carrier_off(bp->dev);
  707. printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
  708. bnx2_xceiver_str(bp));
  709. }
  710. bnx2_report_fw_link(bp);
  711. }
  712. static void
  713. bnx2_resolve_flow_ctrl(struct bnx2 *bp)
  714. {
  715. u32 local_adv, remote_adv;
  716. bp->flow_ctrl = 0;
  717. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  718. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  719. if (bp->duplex == DUPLEX_FULL) {
  720. bp->flow_ctrl = bp->req_flow_ctrl;
  721. }
  722. return;
  723. }
  724. if (bp->duplex != DUPLEX_FULL) {
  725. return;
  726. }
  727. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  728. (CHIP_NUM(bp) == CHIP_NUM_5708)) {
  729. u32 val;
  730. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  731. if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
  732. bp->flow_ctrl |= FLOW_CTRL_TX;
  733. if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
  734. bp->flow_ctrl |= FLOW_CTRL_RX;
  735. return;
  736. }
  737. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  738. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  739. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  740. u32 new_local_adv = 0;
  741. u32 new_remote_adv = 0;
  742. if (local_adv & ADVERTISE_1000XPAUSE)
  743. new_local_adv |= ADVERTISE_PAUSE_CAP;
  744. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  745. new_local_adv |= ADVERTISE_PAUSE_ASYM;
  746. if (remote_adv & ADVERTISE_1000XPAUSE)
  747. new_remote_adv |= ADVERTISE_PAUSE_CAP;
  748. if (remote_adv & ADVERTISE_1000XPSE_ASYM)
  749. new_remote_adv |= ADVERTISE_PAUSE_ASYM;
  750. local_adv = new_local_adv;
  751. remote_adv = new_remote_adv;
  752. }
  753. /* See Table 28B-3 of 802.3ab-1999 spec. */
  754. if (local_adv & ADVERTISE_PAUSE_CAP) {
  755. if(local_adv & ADVERTISE_PAUSE_ASYM) {
  756. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  757. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  758. }
  759. else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
  760. bp->flow_ctrl = FLOW_CTRL_RX;
  761. }
  762. }
  763. else {
  764. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  765. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  766. }
  767. }
  768. }
  769. else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  770. if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
  771. (remote_adv & ADVERTISE_PAUSE_ASYM)) {
  772. bp->flow_ctrl = FLOW_CTRL_TX;
  773. }
  774. }
  775. }
  776. static int
  777. bnx2_5709s_linkup(struct bnx2 *bp)
  778. {
  779. u32 val, speed;
  780. bp->link_up = 1;
  781. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
  782. bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
  783. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  784. if ((bp->autoneg & AUTONEG_SPEED) == 0) {
  785. bp->line_speed = bp->req_line_speed;
  786. bp->duplex = bp->req_duplex;
  787. return 0;
  788. }
  789. speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
  790. switch (speed) {
  791. case MII_BNX2_GP_TOP_AN_SPEED_10:
  792. bp->line_speed = SPEED_10;
  793. break;
  794. case MII_BNX2_GP_TOP_AN_SPEED_100:
  795. bp->line_speed = SPEED_100;
  796. break;
  797. case MII_BNX2_GP_TOP_AN_SPEED_1G:
  798. case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
  799. bp->line_speed = SPEED_1000;
  800. break;
  801. case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
  802. bp->line_speed = SPEED_2500;
  803. break;
  804. }
  805. if (val & MII_BNX2_GP_TOP_AN_FD)
  806. bp->duplex = DUPLEX_FULL;
  807. else
  808. bp->duplex = DUPLEX_HALF;
  809. return 0;
  810. }
  811. static int
  812. bnx2_5708s_linkup(struct bnx2 *bp)
  813. {
  814. u32 val;
  815. bp->link_up = 1;
  816. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  817. switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
  818. case BCM5708S_1000X_STAT1_SPEED_10:
  819. bp->line_speed = SPEED_10;
  820. break;
  821. case BCM5708S_1000X_STAT1_SPEED_100:
  822. bp->line_speed = SPEED_100;
  823. break;
  824. case BCM5708S_1000X_STAT1_SPEED_1G:
  825. bp->line_speed = SPEED_1000;
  826. break;
  827. case BCM5708S_1000X_STAT1_SPEED_2G5:
  828. bp->line_speed = SPEED_2500;
  829. break;
  830. }
  831. if (val & BCM5708S_1000X_STAT1_FD)
  832. bp->duplex = DUPLEX_FULL;
  833. else
  834. bp->duplex = DUPLEX_HALF;
  835. return 0;
  836. }
  837. static int
  838. bnx2_5706s_linkup(struct bnx2 *bp)
  839. {
  840. u32 bmcr, local_adv, remote_adv, common;
  841. bp->link_up = 1;
  842. bp->line_speed = SPEED_1000;
  843. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  844. if (bmcr & BMCR_FULLDPLX) {
  845. bp->duplex = DUPLEX_FULL;
  846. }
  847. else {
  848. bp->duplex = DUPLEX_HALF;
  849. }
  850. if (!(bmcr & BMCR_ANENABLE)) {
  851. return 0;
  852. }
  853. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  854. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  855. common = local_adv & remote_adv;
  856. if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
  857. if (common & ADVERTISE_1000XFULL) {
  858. bp->duplex = DUPLEX_FULL;
  859. }
  860. else {
  861. bp->duplex = DUPLEX_HALF;
  862. }
  863. }
  864. return 0;
  865. }
  866. static int
  867. bnx2_copper_linkup(struct bnx2 *bp)
  868. {
  869. u32 bmcr;
  870. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  871. if (bmcr & BMCR_ANENABLE) {
  872. u32 local_adv, remote_adv, common;
  873. bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
  874. bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
  875. common = local_adv & (remote_adv >> 2);
  876. if (common & ADVERTISE_1000FULL) {
  877. bp->line_speed = SPEED_1000;
  878. bp->duplex = DUPLEX_FULL;
  879. }
  880. else if (common & ADVERTISE_1000HALF) {
  881. bp->line_speed = SPEED_1000;
  882. bp->duplex = DUPLEX_HALF;
  883. }
  884. else {
  885. bnx2_read_phy(bp, bp->mii_adv, &local_adv);
  886. bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
  887. common = local_adv & remote_adv;
  888. if (common & ADVERTISE_100FULL) {
  889. bp->line_speed = SPEED_100;
  890. bp->duplex = DUPLEX_FULL;
  891. }
  892. else if (common & ADVERTISE_100HALF) {
  893. bp->line_speed = SPEED_100;
  894. bp->duplex = DUPLEX_HALF;
  895. }
  896. else if (common & ADVERTISE_10FULL) {
  897. bp->line_speed = SPEED_10;
  898. bp->duplex = DUPLEX_FULL;
  899. }
  900. else if (common & ADVERTISE_10HALF) {
  901. bp->line_speed = SPEED_10;
  902. bp->duplex = DUPLEX_HALF;
  903. }
  904. else {
  905. bp->line_speed = 0;
  906. bp->link_up = 0;
  907. }
  908. }
  909. }
  910. else {
  911. if (bmcr & BMCR_SPEED100) {
  912. bp->line_speed = SPEED_100;
  913. }
  914. else {
  915. bp->line_speed = SPEED_10;
  916. }
  917. if (bmcr & BMCR_FULLDPLX) {
  918. bp->duplex = DUPLEX_FULL;
  919. }
  920. else {
  921. bp->duplex = DUPLEX_HALF;
  922. }
  923. }
  924. return 0;
  925. }
  926. static void
  927. bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
  928. {
  929. u32 val, rx_cid_addr = GET_CID_ADDR(cid);
  930. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
  931. val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
  932. val |= 0x02 << 8;
  933. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  934. u32 lo_water, hi_water;
  935. if (bp->flow_ctrl & FLOW_CTRL_TX)
  936. lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
  937. else
  938. lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
  939. if (lo_water >= bp->rx_ring_size)
  940. lo_water = 0;
  941. hi_water = bp->rx_ring_size / 4;
  942. if (hi_water <= lo_water)
  943. lo_water = 0;
  944. hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
  945. lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
  946. if (hi_water > 0xf)
  947. hi_water = 0xf;
  948. else if (hi_water == 0)
  949. lo_water = 0;
  950. val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
  951. }
  952. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  953. }
  954. static void
  955. bnx2_init_all_rx_contexts(struct bnx2 *bp)
  956. {
  957. int i;
  958. u32 cid;
  959. for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
  960. if (i == 1)
  961. cid = RX_RSS_CID;
  962. bnx2_init_rx_context(bp, cid);
  963. }
  964. }
  965. static int
  966. bnx2_set_mac_link(struct bnx2 *bp)
  967. {
  968. u32 val;
  969. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
  970. if (bp->link_up && (bp->line_speed == SPEED_1000) &&
  971. (bp->duplex == DUPLEX_HALF)) {
  972. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
  973. }
  974. /* Configure the EMAC mode register. */
  975. val = REG_RD(bp, BNX2_EMAC_MODE);
  976. val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  977. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  978. BNX2_EMAC_MODE_25G_MODE);
  979. if (bp->link_up) {
  980. switch (bp->line_speed) {
  981. case SPEED_10:
  982. if (CHIP_NUM(bp) != CHIP_NUM_5706) {
  983. val |= BNX2_EMAC_MODE_PORT_MII_10M;
  984. break;
  985. }
  986. /* fall through */
  987. case SPEED_100:
  988. val |= BNX2_EMAC_MODE_PORT_MII;
  989. break;
  990. case SPEED_2500:
  991. val |= BNX2_EMAC_MODE_25G_MODE;
  992. /* fall through */
  993. case SPEED_1000:
  994. val |= BNX2_EMAC_MODE_PORT_GMII;
  995. break;
  996. }
  997. }
  998. else {
  999. val |= BNX2_EMAC_MODE_PORT_GMII;
  1000. }
  1001. /* Set the MAC to operate in the appropriate duplex mode. */
  1002. if (bp->duplex == DUPLEX_HALF)
  1003. val |= BNX2_EMAC_MODE_HALF_DUPLEX;
  1004. REG_WR(bp, BNX2_EMAC_MODE, val);
  1005. /* Enable/disable rx PAUSE. */
  1006. bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
  1007. if (bp->flow_ctrl & FLOW_CTRL_RX)
  1008. bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
  1009. REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
  1010. /* Enable/disable tx PAUSE. */
  1011. val = REG_RD(bp, BNX2_EMAC_TX_MODE);
  1012. val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
  1013. if (bp->flow_ctrl & FLOW_CTRL_TX)
  1014. val |= BNX2_EMAC_TX_MODE_FLOW_EN;
  1015. REG_WR(bp, BNX2_EMAC_TX_MODE, val);
  1016. /* Acknowledge the interrupt. */
  1017. REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
  1018. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1019. bnx2_init_all_rx_contexts(bp);
  1020. return 0;
  1021. }
  1022. static void
  1023. bnx2_enable_bmsr1(struct bnx2 *bp)
  1024. {
  1025. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1026. (CHIP_NUM(bp) == CHIP_NUM_5709))
  1027. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1028. MII_BNX2_BLK_ADDR_GP_STATUS);
  1029. }
  1030. static void
  1031. bnx2_disable_bmsr1(struct bnx2 *bp)
  1032. {
  1033. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1034. (CHIP_NUM(bp) == CHIP_NUM_5709))
  1035. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1036. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1037. }
  1038. static int
  1039. bnx2_test_and_enable_2g5(struct bnx2 *bp)
  1040. {
  1041. u32 up1;
  1042. int ret = 1;
  1043. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1044. return 0;
  1045. if (bp->autoneg & AUTONEG_SPEED)
  1046. bp->advertising |= ADVERTISED_2500baseX_Full;
  1047. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1048. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1049. bnx2_read_phy(bp, bp->mii_up1, &up1);
  1050. if (!(up1 & BCM5708S_UP1_2G5)) {
  1051. up1 |= BCM5708S_UP1_2G5;
  1052. bnx2_write_phy(bp, bp->mii_up1, up1);
  1053. ret = 0;
  1054. }
  1055. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1056. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1057. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1058. return ret;
  1059. }
  1060. static int
  1061. bnx2_test_and_disable_2g5(struct bnx2 *bp)
  1062. {
  1063. u32 up1;
  1064. int ret = 0;
  1065. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1066. return 0;
  1067. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1068. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1069. bnx2_read_phy(bp, bp->mii_up1, &up1);
  1070. if (up1 & BCM5708S_UP1_2G5) {
  1071. up1 &= ~BCM5708S_UP1_2G5;
  1072. bnx2_write_phy(bp, bp->mii_up1, up1);
  1073. ret = 1;
  1074. }
  1075. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1076. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1077. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1078. return ret;
  1079. }
  1080. static void
  1081. bnx2_enable_forced_2g5(struct bnx2 *bp)
  1082. {
  1083. u32 bmcr;
  1084. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1085. return;
  1086. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  1087. u32 val;
  1088. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1089. MII_BNX2_BLK_ADDR_SERDES_DIG);
  1090. bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
  1091. val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
  1092. val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
  1093. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
  1094. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1095. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1096. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1097. } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  1098. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1099. bmcr |= BCM5708S_BMCR_FORCE_2500;
  1100. }
  1101. if (bp->autoneg & AUTONEG_SPEED) {
  1102. bmcr &= ~BMCR_ANENABLE;
  1103. if (bp->req_duplex == DUPLEX_FULL)
  1104. bmcr |= BMCR_FULLDPLX;
  1105. }
  1106. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1107. }
  1108. static void
  1109. bnx2_disable_forced_2g5(struct bnx2 *bp)
  1110. {
  1111. u32 bmcr;
  1112. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  1113. return;
  1114. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  1115. u32 val;
  1116. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1117. MII_BNX2_BLK_ADDR_SERDES_DIG);
  1118. bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
  1119. val &= ~MII_BNX2_SD_MISC1_FORCE;
  1120. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
  1121. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
  1122. MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1123. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1124. } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  1125. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1126. bmcr &= ~BCM5708S_BMCR_FORCE_2500;
  1127. }
  1128. if (bp->autoneg & AUTONEG_SPEED)
  1129. bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
  1130. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1131. }
  1132. static void
  1133. bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
  1134. {
  1135. u32 val;
  1136. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
  1137. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
  1138. if (start)
  1139. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
  1140. else
  1141. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
  1142. }
  1143. static int
  1144. bnx2_set_link(struct bnx2 *bp)
  1145. {
  1146. u32 bmsr;
  1147. u8 link_up;
  1148. if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
  1149. bp->link_up = 1;
  1150. return 0;
  1151. }
  1152. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  1153. return 0;
  1154. link_up = bp->link_up;
  1155. bnx2_enable_bmsr1(bp);
  1156. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  1157. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  1158. bnx2_disable_bmsr1(bp);
  1159. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1160. (CHIP_NUM(bp) == CHIP_NUM_5706)) {
  1161. u32 val, an_dbg;
  1162. if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
  1163. bnx2_5706s_force_link_dn(bp, 0);
  1164. bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
  1165. }
  1166. val = REG_RD(bp, BNX2_EMAC_STATUS);
  1167. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  1168. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  1169. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  1170. if ((val & BNX2_EMAC_STATUS_LINK) &&
  1171. !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
  1172. bmsr |= BMSR_LSTATUS;
  1173. else
  1174. bmsr &= ~BMSR_LSTATUS;
  1175. }
  1176. if (bmsr & BMSR_LSTATUS) {
  1177. bp->link_up = 1;
  1178. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1179. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  1180. bnx2_5706s_linkup(bp);
  1181. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  1182. bnx2_5708s_linkup(bp);
  1183. else if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1184. bnx2_5709s_linkup(bp);
  1185. }
  1186. else {
  1187. bnx2_copper_linkup(bp);
  1188. }
  1189. bnx2_resolve_flow_ctrl(bp);
  1190. }
  1191. else {
  1192. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  1193. (bp->autoneg & AUTONEG_SPEED))
  1194. bnx2_disable_forced_2g5(bp);
  1195. if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
  1196. u32 bmcr;
  1197. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1198. bmcr |= BMCR_ANENABLE;
  1199. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  1200. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  1201. }
  1202. bp->link_up = 0;
  1203. }
  1204. if (bp->link_up != link_up) {
  1205. bnx2_report_link(bp);
  1206. }
  1207. bnx2_set_mac_link(bp);
  1208. return 0;
  1209. }
  1210. static int
  1211. bnx2_reset_phy(struct bnx2 *bp)
  1212. {
  1213. int i;
  1214. u32 reg;
  1215. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
  1216. #define PHY_RESET_MAX_WAIT 100
  1217. for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
  1218. udelay(10);
  1219. bnx2_read_phy(bp, bp->mii_bmcr, &reg);
  1220. if (!(reg & BMCR_RESET)) {
  1221. udelay(20);
  1222. break;
  1223. }
  1224. }
  1225. if (i == PHY_RESET_MAX_WAIT) {
  1226. return -EBUSY;
  1227. }
  1228. return 0;
  1229. }
  1230. static u32
  1231. bnx2_phy_get_pause_adv(struct bnx2 *bp)
  1232. {
  1233. u32 adv = 0;
  1234. if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
  1235. (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
  1236. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1237. adv = ADVERTISE_1000XPAUSE;
  1238. }
  1239. else {
  1240. adv = ADVERTISE_PAUSE_CAP;
  1241. }
  1242. }
  1243. else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
  1244. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1245. adv = ADVERTISE_1000XPSE_ASYM;
  1246. }
  1247. else {
  1248. adv = ADVERTISE_PAUSE_ASYM;
  1249. }
  1250. }
  1251. else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
  1252. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1253. adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1254. }
  1255. else {
  1256. adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1257. }
  1258. }
  1259. return adv;
  1260. }
  1261. static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
  1262. static int
  1263. bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
  1264. {
  1265. u32 speed_arg = 0, pause_adv;
  1266. pause_adv = bnx2_phy_get_pause_adv(bp);
  1267. if (bp->autoneg & AUTONEG_SPEED) {
  1268. speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
  1269. if (bp->advertising & ADVERTISED_10baseT_Half)
  1270. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
  1271. if (bp->advertising & ADVERTISED_10baseT_Full)
  1272. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
  1273. if (bp->advertising & ADVERTISED_100baseT_Half)
  1274. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
  1275. if (bp->advertising & ADVERTISED_100baseT_Full)
  1276. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
  1277. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1278. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
  1279. if (bp->advertising & ADVERTISED_2500baseX_Full)
  1280. speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
  1281. } else {
  1282. if (bp->req_line_speed == SPEED_2500)
  1283. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
  1284. else if (bp->req_line_speed == SPEED_1000)
  1285. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
  1286. else if (bp->req_line_speed == SPEED_100) {
  1287. if (bp->req_duplex == DUPLEX_FULL)
  1288. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
  1289. else
  1290. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
  1291. } else if (bp->req_line_speed == SPEED_10) {
  1292. if (bp->req_duplex == DUPLEX_FULL)
  1293. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
  1294. else
  1295. speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
  1296. }
  1297. }
  1298. if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
  1299. speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
  1300. if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
  1301. speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
  1302. if (port == PORT_TP)
  1303. speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
  1304. BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
  1305. bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
  1306. spin_unlock_bh(&bp->phy_lock);
  1307. bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
  1308. spin_lock_bh(&bp->phy_lock);
  1309. return 0;
  1310. }
  1311. static int
  1312. bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
  1313. {
  1314. u32 adv, bmcr;
  1315. u32 new_adv = 0;
  1316. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  1317. return (bnx2_setup_remote_phy(bp, port));
  1318. if (!(bp->autoneg & AUTONEG_SPEED)) {
  1319. u32 new_bmcr;
  1320. int force_link_down = 0;
  1321. if (bp->req_line_speed == SPEED_2500) {
  1322. if (!bnx2_test_and_enable_2g5(bp))
  1323. force_link_down = 1;
  1324. } else if (bp->req_line_speed == SPEED_1000) {
  1325. if (bnx2_test_and_disable_2g5(bp))
  1326. force_link_down = 1;
  1327. }
  1328. bnx2_read_phy(bp, bp->mii_adv, &adv);
  1329. adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
  1330. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1331. new_bmcr = bmcr & ~BMCR_ANENABLE;
  1332. new_bmcr |= BMCR_SPEED1000;
  1333. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  1334. if (bp->req_line_speed == SPEED_2500)
  1335. bnx2_enable_forced_2g5(bp);
  1336. else if (bp->req_line_speed == SPEED_1000) {
  1337. bnx2_disable_forced_2g5(bp);
  1338. new_bmcr &= ~0x2000;
  1339. }
  1340. } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  1341. if (bp->req_line_speed == SPEED_2500)
  1342. new_bmcr |= BCM5708S_BMCR_FORCE_2500;
  1343. else
  1344. new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
  1345. }
  1346. if (bp->req_duplex == DUPLEX_FULL) {
  1347. adv |= ADVERTISE_1000XFULL;
  1348. new_bmcr |= BMCR_FULLDPLX;
  1349. }
  1350. else {
  1351. adv |= ADVERTISE_1000XHALF;
  1352. new_bmcr &= ~BMCR_FULLDPLX;
  1353. }
  1354. if ((new_bmcr != bmcr) || (force_link_down)) {
  1355. /* Force a link down visible on the other side */
  1356. if (bp->link_up) {
  1357. bnx2_write_phy(bp, bp->mii_adv, adv &
  1358. ~(ADVERTISE_1000XFULL |
  1359. ADVERTISE_1000XHALF));
  1360. bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
  1361. BMCR_ANRESTART | BMCR_ANENABLE);
  1362. bp->link_up = 0;
  1363. netif_carrier_off(bp->dev);
  1364. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1365. bnx2_report_link(bp);
  1366. }
  1367. bnx2_write_phy(bp, bp->mii_adv, adv);
  1368. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1369. } else {
  1370. bnx2_resolve_flow_ctrl(bp);
  1371. bnx2_set_mac_link(bp);
  1372. }
  1373. return 0;
  1374. }
  1375. bnx2_test_and_enable_2g5(bp);
  1376. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1377. new_adv |= ADVERTISE_1000XFULL;
  1378. new_adv |= bnx2_phy_get_pause_adv(bp);
  1379. bnx2_read_phy(bp, bp->mii_adv, &adv);
  1380. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1381. bp->serdes_an_pending = 0;
  1382. if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
  1383. /* Force a link down visible on the other side */
  1384. if (bp->link_up) {
  1385. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  1386. spin_unlock_bh(&bp->phy_lock);
  1387. msleep(20);
  1388. spin_lock_bh(&bp->phy_lock);
  1389. }
  1390. bnx2_write_phy(bp, bp->mii_adv, new_adv);
  1391. bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
  1392. BMCR_ANENABLE);
  1393. /* Speed up link-up time when the link partner
  1394. * does not autonegotiate which is very common
  1395. * in blade servers. Some blade servers use
  1396. * IPMI for kerboard input and it's important
  1397. * to minimize link disruptions. Autoneg. involves
  1398. * exchanging base pages plus 3 next pages and
  1399. * normally completes in about 120 msec.
  1400. */
  1401. bp->current_interval = SERDES_AN_TIMEOUT;
  1402. bp->serdes_an_pending = 1;
  1403. mod_timer(&bp->timer, jiffies + bp->current_interval);
  1404. } else {
  1405. bnx2_resolve_flow_ctrl(bp);
  1406. bnx2_set_mac_link(bp);
  1407. }
  1408. return 0;
  1409. }
  1410. #define ETHTOOL_ALL_FIBRE_SPEED \
  1411. (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
  1412. (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
  1413. (ADVERTISED_1000baseT_Full)
  1414. #define ETHTOOL_ALL_COPPER_SPEED \
  1415. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
  1416. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
  1417. ADVERTISED_1000baseT_Full)
  1418. #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
  1419. ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
  1420. #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
  1421. static void
  1422. bnx2_set_default_remote_link(struct bnx2 *bp)
  1423. {
  1424. u32 link;
  1425. if (bp->phy_port == PORT_TP)
  1426. link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
  1427. else
  1428. link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
  1429. if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
  1430. bp->req_line_speed = 0;
  1431. bp->autoneg |= AUTONEG_SPEED;
  1432. bp->advertising = ADVERTISED_Autoneg;
  1433. if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
  1434. bp->advertising |= ADVERTISED_10baseT_Half;
  1435. if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
  1436. bp->advertising |= ADVERTISED_10baseT_Full;
  1437. if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
  1438. bp->advertising |= ADVERTISED_100baseT_Half;
  1439. if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
  1440. bp->advertising |= ADVERTISED_100baseT_Full;
  1441. if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
  1442. bp->advertising |= ADVERTISED_1000baseT_Full;
  1443. if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
  1444. bp->advertising |= ADVERTISED_2500baseX_Full;
  1445. } else {
  1446. bp->autoneg = 0;
  1447. bp->advertising = 0;
  1448. bp->req_duplex = DUPLEX_FULL;
  1449. if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
  1450. bp->req_line_speed = SPEED_10;
  1451. if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
  1452. bp->req_duplex = DUPLEX_HALF;
  1453. }
  1454. if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
  1455. bp->req_line_speed = SPEED_100;
  1456. if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
  1457. bp->req_duplex = DUPLEX_HALF;
  1458. }
  1459. if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
  1460. bp->req_line_speed = SPEED_1000;
  1461. if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
  1462. bp->req_line_speed = SPEED_2500;
  1463. }
  1464. }
  1465. static void
  1466. bnx2_set_default_link(struct bnx2 *bp)
  1467. {
  1468. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  1469. bnx2_set_default_remote_link(bp);
  1470. return;
  1471. }
  1472. bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
  1473. bp->req_line_speed = 0;
  1474. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1475. u32 reg;
  1476. bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
  1477. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
  1478. reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
  1479. if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
  1480. bp->autoneg = 0;
  1481. bp->req_line_speed = bp->line_speed = SPEED_1000;
  1482. bp->req_duplex = DUPLEX_FULL;
  1483. }
  1484. } else
  1485. bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
  1486. }
  1487. static void
  1488. bnx2_send_heart_beat(struct bnx2 *bp)
  1489. {
  1490. u32 msg;
  1491. u32 addr;
  1492. spin_lock(&bp->indirect_lock);
  1493. msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
  1494. addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
  1495. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
  1496. REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
  1497. spin_unlock(&bp->indirect_lock);
  1498. }
  1499. static void
  1500. bnx2_remote_phy_event(struct bnx2 *bp)
  1501. {
  1502. u32 msg;
  1503. u8 link_up = bp->link_up;
  1504. u8 old_port;
  1505. msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
  1506. if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
  1507. bnx2_send_heart_beat(bp);
  1508. msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
  1509. if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
  1510. bp->link_up = 0;
  1511. else {
  1512. u32 speed;
  1513. bp->link_up = 1;
  1514. speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
  1515. bp->duplex = DUPLEX_FULL;
  1516. switch (speed) {
  1517. case BNX2_LINK_STATUS_10HALF:
  1518. bp->duplex = DUPLEX_HALF;
  1519. case BNX2_LINK_STATUS_10FULL:
  1520. bp->line_speed = SPEED_10;
  1521. break;
  1522. case BNX2_LINK_STATUS_100HALF:
  1523. bp->duplex = DUPLEX_HALF;
  1524. case BNX2_LINK_STATUS_100BASE_T4:
  1525. case BNX2_LINK_STATUS_100FULL:
  1526. bp->line_speed = SPEED_100;
  1527. break;
  1528. case BNX2_LINK_STATUS_1000HALF:
  1529. bp->duplex = DUPLEX_HALF;
  1530. case BNX2_LINK_STATUS_1000FULL:
  1531. bp->line_speed = SPEED_1000;
  1532. break;
  1533. case BNX2_LINK_STATUS_2500HALF:
  1534. bp->duplex = DUPLEX_HALF;
  1535. case BNX2_LINK_STATUS_2500FULL:
  1536. bp->line_speed = SPEED_2500;
  1537. break;
  1538. default:
  1539. bp->line_speed = 0;
  1540. break;
  1541. }
  1542. bp->flow_ctrl = 0;
  1543. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  1544. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  1545. if (bp->duplex == DUPLEX_FULL)
  1546. bp->flow_ctrl = bp->req_flow_ctrl;
  1547. } else {
  1548. if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
  1549. bp->flow_ctrl |= FLOW_CTRL_TX;
  1550. if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
  1551. bp->flow_ctrl |= FLOW_CTRL_RX;
  1552. }
  1553. old_port = bp->phy_port;
  1554. if (msg & BNX2_LINK_STATUS_SERDES_LINK)
  1555. bp->phy_port = PORT_FIBRE;
  1556. else
  1557. bp->phy_port = PORT_TP;
  1558. if (old_port != bp->phy_port)
  1559. bnx2_set_default_link(bp);
  1560. }
  1561. if (bp->link_up != link_up)
  1562. bnx2_report_link(bp);
  1563. bnx2_set_mac_link(bp);
  1564. }
  1565. static int
  1566. bnx2_set_remote_link(struct bnx2 *bp)
  1567. {
  1568. u32 evt_code;
  1569. evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
  1570. switch (evt_code) {
  1571. case BNX2_FW_EVT_CODE_LINK_EVENT:
  1572. bnx2_remote_phy_event(bp);
  1573. break;
  1574. case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
  1575. default:
  1576. bnx2_send_heart_beat(bp);
  1577. break;
  1578. }
  1579. return 0;
  1580. }
  1581. static int
  1582. bnx2_setup_copper_phy(struct bnx2 *bp)
  1583. {
  1584. u32 bmcr;
  1585. u32 new_bmcr;
  1586. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  1587. if (bp->autoneg & AUTONEG_SPEED) {
  1588. u32 adv_reg, adv1000_reg;
  1589. u32 new_adv_reg = 0;
  1590. u32 new_adv1000_reg = 0;
  1591. bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
  1592. adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
  1593. ADVERTISE_PAUSE_ASYM);
  1594. bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
  1595. adv1000_reg &= PHY_ALL_1000_SPEED;
  1596. if (bp->advertising & ADVERTISED_10baseT_Half)
  1597. new_adv_reg |= ADVERTISE_10HALF;
  1598. if (bp->advertising & ADVERTISED_10baseT_Full)
  1599. new_adv_reg |= ADVERTISE_10FULL;
  1600. if (bp->advertising & ADVERTISED_100baseT_Half)
  1601. new_adv_reg |= ADVERTISE_100HALF;
  1602. if (bp->advertising & ADVERTISED_100baseT_Full)
  1603. new_adv_reg |= ADVERTISE_100FULL;
  1604. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1605. new_adv1000_reg |= ADVERTISE_1000FULL;
  1606. new_adv_reg |= ADVERTISE_CSMA;
  1607. new_adv_reg |= bnx2_phy_get_pause_adv(bp);
  1608. if ((adv1000_reg != new_adv1000_reg) ||
  1609. (adv_reg != new_adv_reg) ||
  1610. ((bmcr & BMCR_ANENABLE) == 0)) {
  1611. bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
  1612. bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
  1613. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
  1614. BMCR_ANENABLE);
  1615. }
  1616. else if (bp->link_up) {
  1617. /* Flow ctrl may have changed from auto to forced */
  1618. /* or vice-versa. */
  1619. bnx2_resolve_flow_ctrl(bp);
  1620. bnx2_set_mac_link(bp);
  1621. }
  1622. return 0;
  1623. }
  1624. new_bmcr = 0;
  1625. if (bp->req_line_speed == SPEED_100) {
  1626. new_bmcr |= BMCR_SPEED100;
  1627. }
  1628. if (bp->req_duplex == DUPLEX_FULL) {
  1629. new_bmcr |= BMCR_FULLDPLX;
  1630. }
  1631. if (new_bmcr != bmcr) {
  1632. u32 bmsr;
  1633. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1634. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1635. if (bmsr & BMSR_LSTATUS) {
  1636. /* Force link down */
  1637. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  1638. spin_unlock_bh(&bp->phy_lock);
  1639. msleep(50);
  1640. spin_lock_bh(&bp->phy_lock);
  1641. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1642. bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
  1643. }
  1644. bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
  1645. /* Normally, the new speed is setup after the link has
  1646. * gone down and up again. In some cases, link will not go
  1647. * down so we need to set up the new speed here.
  1648. */
  1649. if (bmsr & BMSR_LSTATUS) {
  1650. bp->line_speed = bp->req_line_speed;
  1651. bp->duplex = bp->req_duplex;
  1652. bnx2_resolve_flow_ctrl(bp);
  1653. bnx2_set_mac_link(bp);
  1654. }
  1655. } else {
  1656. bnx2_resolve_flow_ctrl(bp);
  1657. bnx2_set_mac_link(bp);
  1658. }
  1659. return 0;
  1660. }
  1661. static int
  1662. bnx2_setup_phy(struct bnx2 *bp, u8 port)
  1663. {
  1664. if (bp->loopback == MAC_LOOPBACK)
  1665. return 0;
  1666. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1667. return (bnx2_setup_serdes_phy(bp, port));
  1668. }
  1669. else {
  1670. return (bnx2_setup_copper_phy(bp));
  1671. }
  1672. }
  1673. static int
  1674. bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
  1675. {
  1676. u32 val;
  1677. bp->mii_bmcr = MII_BMCR + 0x10;
  1678. bp->mii_bmsr = MII_BMSR + 0x10;
  1679. bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
  1680. bp->mii_adv = MII_ADVERTISE + 0x10;
  1681. bp->mii_lpa = MII_LPA + 0x10;
  1682. bp->mii_up1 = MII_BNX2_OVER1G_UP1;
  1683. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
  1684. bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
  1685. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1686. if (reset_phy)
  1687. bnx2_reset_phy(bp);
  1688. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
  1689. bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
  1690. val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
  1691. val |= MII_BNX2_SD_1000XCTL1_FIBER;
  1692. bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
  1693. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
  1694. bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
  1695. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
  1696. val |= BCM5708S_UP1_2G5;
  1697. else
  1698. val &= ~BCM5708S_UP1_2G5;
  1699. bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
  1700. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
  1701. bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
  1702. val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
  1703. bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
  1704. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
  1705. val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
  1706. MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
  1707. bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
  1708. bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
  1709. return 0;
  1710. }
  1711. static int
  1712. bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
  1713. {
  1714. u32 val;
  1715. if (reset_phy)
  1716. bnx2_reset_phy(bp);
  1717. bp->mii_up1 = BCM5708S_UP1;
  1718. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
  1719. bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
  1720. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1721. bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
  1722. val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
  1723. bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
  1724. bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
  1725. val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
  1726. bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
  1727. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
  1728. bnx2_read_phy(bp, BCM5708S_UP1, &val);
  1729. val |= BCM5708S_UP1_2G5;
  1730. bnx2_write_phy(bp, BCM5708S_UP1, val);
  1731. }
  1732. if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
  1733. (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
  1734. (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
  1735. /* increase tx signal amplitude */
  1736. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1737. BCM5708S_BLK_ADDR_TX_MISC);
  1738. bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
  1739. val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
  1740. bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
  1741. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1742. }
  1743. val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
  1744. BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
  1745. if (val) {
  1746. u32 is_backplane;
  1747. is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
  1748. if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
  1749. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1750. BCM5708S_BLK_ADDR_TX_MISC);
  1751. bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
  1752. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1753. BCM5708S_BLK_ADDR_DIG);
  1754. }
  1755. }
  1756. return 0;
  1757. }
  1758. static int
  1759. bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
  1760. {
  1761. if (reset_phy)
  1762. bnx2_reset_phy(bp);
  1763. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  1764. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  1765. REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
  1766. if (bp->dev->mtu > 1500) {
  1767. u32 val;
  1768. /* Set extended packet length bit */
  1769. bnx2_write_phy(bp, 0x18, 0x7);
  1770. bnx2_read_phy(bp, 0x18, &val);
  1771. bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
  1772. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1773. bnx2_read_phy(bp, 0x1c, &val);
  1774. bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
  1775. }
  1776. else {
  1777. u32 val;
  1778. bnx2_write_phy(bp, 0x18, 0x7);
  1779. bnx2_read_phy(bp, 0x18, &val);
  1780. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  1781. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1782. bnx2_read_phy(bp, 0x1c, &val);
  1783. bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
  1784. }
  1785. return 0;
  1786. }
  1787. static int
  1788. bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
  1789. {
  1790. u32 val;
  1791. if (reset_phy)
  1792. bnx2_reset_phy(bp);
  1793. if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
  1794. bnx2_write_phy(bp, 0x18, 0x0c00);
  1795. bnx2_write_phy(bp, 0x17, 0x000a);
  1796. bnx2_write_phy(bp, 0x15, 0x310b);
  1797. bnx2_write_phy(bp, 0x17, 0x201f);
  1798. bnx2_write_phy(bp, 0x15, 0x9506);
  1799. bnx2_write_phy(bp, 0x17, 0x401f);
  1800. bnx2_write_phy(bp, 0x15, 0x14e2);
  1801. bnx2_write_phy(bp, 0x18, 0x0400);
  1802. }
  1803. if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
  1804. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
  1805. MII_BNX2_DSP_EXPAND_REG | 0x8);
  1806. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
  1807. val &= ~(1 << 8);
  1808. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
  1809. }
  1810. if (bp->dev->mtu > 1500) {
  1811. /* Set extended packet length bit */
  1812. bnx2_write_phy(bp, 0x18, 0x7);
  1813. bnx2_read_phy(bp, 0x18, &val);
  1814. bnx2_write_phy(bp, 0x18, val | 0x4000);
  1815. bnx2_read_phy(bp, 0x10, &val);
  1816. bnx2_write_phy(bp, 0x10, val | 0x1);
  1817. }
  1818. else {
  1819. bnx2_write_phy(bp, 0x18, 0x7);
  1820. bnx2_read_phy(bp, 0x18, &val);
  1821. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  1822. bnx2_read_phy(bp, 0x10, &val);
  1823. bnx2_write_phy(bp, 0x10, val & ~0x1);
  1824. }
  1825. /* ethernet@wirespeed */
  1826. bnx2_write_phy(bp, 0x18, 0x7007);
  1827. bnx2_read_phy(bp, 0x18, &val);
  1828. bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
  1829. return 0;
  1830. }
  1831. static int
  1832. bnx2_init_phy(struct bnx2 *bp, int reset_phy)
  1833. {
  1834. u32 val;
  1835. int rc = 0;
  1836. bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
  1837. bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
  1838. bp->mii_bmcr = MII_BMCR;
  1839. bp->mii_bmsr = MII_BMSR;
  1840. bp->mii_bmsr1 = MII_BMSR;
  1841. bp->mii_adv = MII_ADVERTISE;
  1842. bp->mii_lpa = MII_LPA;
  1843. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  1844. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  1845. goto setup_phy;
  1846. bnx2_read_phy(bp, MII_PHYSID1, &val);
  1847. bp->phy_id = val << 16;
  1848. bnx2_read_phy(bp, MII_PHYSID2, &val);
  1849. bp->phy_id |= val & 0xffff;
  1850. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  1851. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  1852. rc = bnx2_init_5706s_phy(bp, reset_phy);
  1853. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  1854. rc = bnx2_init_5708s_phy(bp, reset_phy);
  1855. else if (CHIP_NUM(bp) == CHIP_NUM_5709)
  1856. rc = bnx2_init_5709s_phy(bp, reset_phy);
  1857. }
  1858. else {
  1859. rc = bnx2_init_copper_phy(bp, reset_phy);
  1860. }
  1861. setup_phy:
  1862. if (!rc)
  1863. rc = bnx2_setup_phy(bp, bp->phy_port);
  1864. return rc;
  1865. }
  1866. static int
  1867. bnx2_set_mac_loopback(struct bnx2 *bp)
  1868. {
  1869. u32 mac_mode;
  1870. mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
  1871. mac_mode &= ~BNX2_EMAC_MODE_PORT;
  1872. mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
  1873. REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
  1874. bp->link_up = 1;
  1875. return 0;
  1876. }
  1877. static int bnx2_test_link(struct bnx2 *);
  1878. static int
  1879. bnx2_set_phy_loopback(struct bnx2 *bp)
  1880. {
  1881. u32 mac_mode;
  1882. int rc, i;
  1883. spin_lock_bh(&bp->phy_lock);
  1884. rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
  1885. BMCR_SPEED1000);
  1886. spin_unlock_bh(&bp->phy_lock);
  1887. if (rc)
  1888. return rc;
  1889. for (i = 0; i < 10; i++) {
  1890. if (bnx2_test_link(bp) == 0)
  1891. break;
  1892. msleep(100);
  1893. }
  1894. mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
  1895. mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  1896. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  1897. BNX2_EMAC_MODE_25G_MODE);
  1898. mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
  1899. REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
  1900. bp->link_up = 1;
  1901. return 0;
  1902. }
  1903. static int
  1904. bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
  1905. {
  1906. int i;
  1907. u32 val;
  1908. bp->fw_wr_seq++;
  1909. msg_data |= bp->fw_wr_seq;
  1910. bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
  1911. if (!ack)
  1912. return 0;
  1913. /* wait for an acknowledgement. */
  1914. for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
  1915. msleep(10);
  1916. val = bnx2_shmem_rd(bp, BNX2_FW_MB);
  1917. if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
  1918. break;
  1919. }
  1920. if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
  1921. return 0;
  1922. /* If we timed out, inform the firmware that this is the case. */
  1923. if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
  1924. if (!silent)
  1925. printk(KERN_ERR PFX "fw sync timeout, reset code = "
  1926. "%x\n", msg_data);
  1927. msg_data &= ~BNX2_DRV_MSG_CODE;
  1928. msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
  1929. bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
  1930. return -EBUSY;
  1931. }
  1932. if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
  1933. return -EIO;
  1934. return 0;
  1935. }
  1936. static int
  1937. bnx2_init_5709_context(struct bnx2 *bp)
  1938. {
  1939. int i, ret = 0;
  1940. u32 val;
  1941. val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
  1942. val |= (BCM_PAGE_BITS - 8) << 16;
  1943. REG_WR(bp, BNX2_CTX_COMMAND, val);
  1944. for (i = 0; i < 10; i++) {
  1945. val = REG_RD(bp, BNX2_CTX_COMMAND);
  1946. if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
  1947. break;
  1948. udelay(2);
  1949. }
  1950. if (val & BNX2_CTX_COMMAND_MEM_INIT)
  1951. return -EBUSY;
  1952. for (i = 0; i < bp->ctx_pages; i++) {
  1953. int j;
  1954. if (bp->ctx_blk[i])
  1955. memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
  1956. else
  1957. return -ENOMEM;
  1958. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  1959. (bp->ctx_blk_mapping[i] & 0xffffffff) |
  1960. BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
  1961. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  1962. (u64) bp->ctx_blk_mapping[i] >> 32);
  1963. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
  1964. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  1965. for (j = 0; j < 10; j++) {
  1966. val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  1967. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  1968. break;
  1969. udelay(5);
  1970. }
  1971. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  1972. ret = -EBUSY;
  1973. break;
  1974. }
  1975. }
  1976. return ret;
  1977. }
  1978. static void
  1979. bnx2_init_context(struct bnx2 *bp)
  1980. {
  1981. u32 vcid;
  1982. vcid = 96;
  1983. while (vcid) {
  1984. u32 vcid_addr, pcid_addr, offset;
  1985. int i;
  1986. vcid--;
  1987. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  1988. u32 new_vcid;
  1989. vcid_addr = GET_PCID_ADDR(vcid);
  1990. if (vcid & 0x8) {
  1991. new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
  1992. }
  1993. else {
  1994. new_vcid = vcid;
  1995. }
  1996. pcid_addr = GET_PCID_ADDR(new_vcid);
  1997. }
  1998. else {
  1999. vcid_addr = GET_CID_ADDR(vcid);
  2000. pcid_addr = vcid_addr;
  2001. }
  2002. for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
  2003. vcid_addr += (i << PHY_CTX_SHIFT);
  2004. pcid_addr += (i << PHY_CTX_SHIFT);
  2005. REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
  2006. REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
  2007. /* Zero out the context. */
  2008. for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
  2009. bnx2_ctx_wr(bp, vcid_addr, offset, 0);
  2010. }
  2011. }
  2012. }
  2013. static int
  2014. bnx2_alloc_bad_rbuf(struct bnx2 *bp)
  2015. {
  2016. u16 *good_mbuf;
  2017. u32 good_mbuf_cnt;
  2018. u32 val;
  2019. good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
  2020. if (good_mbuf == NULL) {
  2021. printk(KERN_ERR PFX "Failed to allocate memory in "
  2022. "bnx2_alloc_bad_rbuf\n");
  2023. return -ENOMEM;
  2024. }
  2025. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  2026. BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
  2027. good_mbuf_cnt = 0;
  2028. /* Allocate a bunch of mbufs and save the good ones in an array. */
  2029. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
  2030. while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
  2031. bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
  2032. BNX2_RBUF_COMMAND_ALLOC_REQ);
  2033. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
  2034. val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
  2035. /* The addresses with Bit 9 set are bad memory blocks. */
  2036. if (!(val & (1 << 9))) {
  2037. good_mbuf[good_mbuf_cnt] = (u16) val;
  2038. good_mbuf_cnt++;
  2039. }
  2040. val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
  2041. }
  2042. /* Free the good ones back to the mbuf pool thus discarding
  2043. * all the bad ones. */
  2044. while (good_mbuf_cnt) {
  2045. good_mbuf_cnt--;
  2046. val = good_mbuf[good_mbuf_cnt];
  2047. val = (val << 9) | val | 1;
  2048. bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
  2049. }
  2050. kfree(good_mbuf);
  2051. return 0;
  2052. }
  2053. static void
  2054. bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
  2055. {
  2056. u32 val;
  2057. val = (mac_addr[0] << 8) | mac_addr[1];
  2058. REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
  2059. val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
  2060. (mac_addr[4] << 8) | mac_addr[5];
  2061. REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
  2062. }
  2063. static inline int
  2064. bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
  2065. {
  2066. dma_addr_t mapping;
  2067. struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
  2068. struct rx_bd *rxbd =
  2069. &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
  2070. struct page *page = alloc_page(GFP_ATOMIC);
  2071. if (!page)
  2072. return -ENOMEM;
  2073. mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
  2074. PCI_DMA_FROMDEVICE);
  2075. rx_pg->page = page;
  2076. pci_unmap_addr_set(rx_pg, mapping, mapping);
  2077. rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
  2078. rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  2079. return 0;
  2080. }
  2081. static void
  2082. bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
  2083. {
  2084. struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
  2085. struct page *page = rx_pg->page;
  2086. if (!page)
  2087. return;
  2088. pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
  2089. PCI_DMA_FROMDEVICE);
  2090. __free_page(page);
  2091. rx_pg->page = NULL;
  2092. }
  2093. static inline int
  2094. bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
  2095. {
  2096. struct sk_buff *skb;
  2097. struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
  2098. dma_addr_t mapping;
  2099. struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
  2100. unsigned long align;
  2101. skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
  2102. if (skb == NULL) {
  2103. return -ENOMEM;
  2104. }
  2105. if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
  2106. skb_reserve(skb, BNX2_RX_ALIGN - align);
  2107. mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
  2108. PCI_DMA_FROMDEVICE);
  2109. rx_buf->skb = skb;
  2110. pci_unmap_addr_set(rx_buf, mapping, mapping);
  2111. rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
  2112. rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  2113. rxr->rx_prod_bseq += bp->rx_buf_use_size;
  2114. return 0;
  2115. }
  2116. static int
  2117. bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
  2118. {
  2119. struct status_block *sblk = bnapi->status_blk.msi;
  2120. u32 new_link_state, old_link_state;
  2121. int is_set = 1;
  2122. new_link_state = sblk->status_attn_bits & event;
  2123. old_link_state = sblk->status_attn_bits_ack & event;
  2124. if (new_link_state != old_link_state) {
  2125. if (new_link_state)
  2126. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
  2127. else
  2128. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
  2129. } else
  2130. is_set = 0;
  2131. return is_set;
  2132. }
  2133. static void
  2134. bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2135. {
  2136. spin_lock(&bp->phy_lock);
  2137. if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
  2138. bnx2_set_link(bp);
  2139. if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
  2140. bnx2_set_remote_link(bp);
  2141. spin_unlock(&bp->phy_lock);
  2142. }
  2143. static inline u16
  2144. bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
  2145. {
  2146. u16 cons;
  2147. /* Tell compiler that status block fields can change. */
  2148. barrier();
  2149. cons = *bnapi->hw_tx_cons_ptr;
  2150. if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
  2151. cons++;
  2152. return cons;
  2153. }
  2154. static int
  2155. bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
  2156. {
  2157. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2158. u16 hw_cons, sw_cons, sw_ring_cons;
  2159. int tx_pkt = 0, index;
  2160. struct netdev_queue *txq;
  2161. index = (bnapi - bp->bnx2_napi);
  2162. txq = netdev_get_tx_queue(bp->dev, index);
  2163. hw_cons = bnx2_get_hw_tx_cons(bnapi);
  2164. sw_cons = txr->tx_cons;
  2165. while (sw_cons != hw_cons) {
  2166. struct sw_bd *tx_buf;
  2167. struct sk_buff *skb;
  2168. int i, last;
  2169. sw_ring_cons = TX_RING_IDX(sw_cons);
  2170. tx_buf = &txr->tx_buf_ring[sw_ring_cons];
  2171. skb = tx_buf->skb;
  2172. /* partial BD completions possible with TSO packets */
  2173. if (skb_is_gso(skb)) {
  2174. u16 last_idx, last_ring_idx;
  2175. last_idx = sw_cons +
  2176. skb_shinfo(skb)->nr_frags + 1;
  2177. last_ring_idx = sw_ring_cons +
  2178. skb_shinfo(skb)->nr_frags + 1;
  2179. if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
  2180. last_idx++;
  2181. }
  2182. if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
  2183. break;
  2184. }
  2185. }
  2186. pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
  2187. skb_headlen(skb), PCI_DMA_TODEVICE);
  2188. tx_buf->skb = NULL;
  2189. last = skb_shinfo(skb)->nr_frags;
  2190. for (i = 0; i < last; i++) {
  2191. sw_cons = NEXT_TX_BD(sw_cons);
  2192. pci_unmap_page(bp->pdev,
  2193. pci_unmap_addr(
  2194. &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
  2195. mapping),
  2196. skb_shinfo(skb)->frags[i].size,
  2197. PCI_DMA_TODEVICE);
  2198. }
  2199. sw_cons = NEXT_TX_BD(sw_cons);
  2200. dev_kfree_skb(skb);
  2201. tx_pkt++;
  2202. if (tx_pkt == budget)
  2203. break;
  2204. hw_cons = bnx2_get_hw_tx_cons(bnapi);
  2205. }
  2206. txr->hw_tx_cons = hw_cons;
  2207. txr->tx_cons = sw_cons;
  2208. /* Need to make the tx_cons update visible to bnx2_start_xmit()
  2209. * before checking for netif_tx_queue_stopped(). Without the
  2210. * memory barrier, there is a small possibility that bnx2_start_xmit()
  2211. * will miss it and cause the queue to be stopped forever.
  2212. */
  2213. smp_mb();
  2214. if (unlikely(netif_tx_queue_stopped(txq)) &&
  2215. (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
  2216. __netif_tx_lock(txq, smp_processor_id());
  2217. if ((netif_tx_queue_stopped(txq)) &&
  2218. (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
  2219. netif_tx_wake_queue(txq);
  2220. __netif_tx_unlock(txq);
  2221. }
  2222. return tx_pkt;
  2223. }
  2224. static void
  2225. bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
  2226. struct sk_buff *skb, int count)
  2227. {
  2228. struct sw_pg *cons_rx_pg, *prod_rx_pg;
  2229. struct rx_bd *cons_bd, *prod_bd;
  2230. dma_addr_t mapping;
  2231. int i;
  2232. u16 hw_prod = rxr->rx_pg_prod, prod;
  2233. u16 cons = rxr->rx_pg_cons;
  2234. for (i = 0; i < count; i++) {
  2235. prod = RX_PG_RING_IDX(hw_prod);
  2236. prod_rx_pg = &rxr->rx_pg_ring[prod];
  2237. cons_rx_pg = &rxr->rx_pg_ring[cons];
  2238. cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
  2239. prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
  2240. if (i == 0 && skb) {
  2241. struct page *page;
  2242. struct skb_shared_info *shinfo;
  2243. shinfo = skb_shinfo(skb);
  2244. shinfo->nr_frags--;
  2245. page = shinfo->frags[shinfo->nr_frags].page;
  2246. shinfo->frags[shinfo->nr_frags].page = NULL;
  2247. mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
  2248. PCI_DMA_FROMDEVICE);
  2249. cons_rx_pg->page = page;
  2250. pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
  2251. dev_kfree_skb(skb);
  2252. }
  2253. if (prod != cons) {
  2254. prod_rx_pg->page = cons_rx_pg->page;
  2255. cons_rx_pg->page = NULL;
  2256. pci_unmap_addr_set(prod_rx_pg, mapping,
  2257. pci_unmap_addr(cons_rx_pg, mapping));
  2258. prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
  2259. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  2260. }
  2261. cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
  2262. hw_prod = NEXT_RX_BD(hw_prod);
  2263. }
  2264. rxr->rx_pg_prod = hw_prod;
  2265. rxr->rx_pg_cons = cons;
  2266. }
  2267. static inline void
  2268. bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
  2269. struct sk_buff *skb, u16 cons, u16 prod)
  2270. {
  2271. struct sw_bd *cons_rx_buf, *prod_rx_buf;
  2272. struct rx_bd *cons_bd, *prod_bd;
  2273. cons_rx_buf = &rxr->rx_buf_ring[cons];
  2274. prod_rx_buf = &rxr->rx_buf_ring[prod];
  2275. pci_dma_sync_single_for_device(bp->pdev,
  2276. pci_unmap_addr(cons_rx_buf, mapping),
  2277. BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
  2278. rxr->rx_prod_bseq += bp->rx_buf_use_size;
  2279. prod_rx_buf->skb = skb;
  2280. if (cons == prod)
  2281. return;
  2282. pci_unmap_addr_set(prod_rx_buf, mapping,
  2283. pci_unmap_addr(cons_rx_buf, mapping));
  2284. cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
  2285. prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
  2286. prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
  2287. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  2288. }
  2289. static int
  2290. bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
  2291. unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
  2292. u32 ring_idx)
  2293. {
  2294. int err;
  2295. u16 prod = ring_idx & 0xffff;
  2296. err = bnx2_alloc_rx_skb(bp, rxr, prod);
  2297. if (unlikely(err)) {
  2298. bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
  2299. if (hdr_len) {
  2300. unsigned int raw_len = len + 4;
  2301. int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
  2302. bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
  2303. }
  2304. return err;
  2305. }
  2306. skb_reserve(skb, BNX2_RX_OFFSET);
  2307. pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
  2308. PCI_DMA_FROMDEVICE);
  2309. if (hdr_len == 0) {
  2310. skb_put(skb, len);
  2311. return 0;
  2312. } else {
  2313. unsigned int i, frag_len, frag_size, pages;
  2314. struct sw_pg *rx_pg;
  2315. u16 pg_cons = rxr->rx_pg_cons;
  2316. u16 pg_prod = rxr->rx_pg_prod;
  2317. frag_size = len + 4 - hdr_len;
  2318. pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
  2319. skb_put(skb, hdr_len);
  2320. for (i = 0; i < pages; i++) {
  2321. frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
  2322. if (unlikely(frag_len <= 4)) {
  2323. unsigned int tail = 4 - frag_len;
  2324. rxr->rx_pg_cons = pg_cons;
  2325. rxr->rx_pg_prod = pg_prod;
  2326. bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
  2327. pages - i);
  2328. skb->len -= tail;
  2329. if (i == 0) {
  2330. skb->tail -= tail;
  2331. } else {
  2332. skb_frag_t *frag =
  2333. &skb_shinfo(skb)->frags[i - 1];
  2334. frag->size -= tail;
  2335. skb->data_len -= tail;
  2336. skb->truesize -= tail;
  2337. }
  2338. return 0;
  2339. }
  2340. rx_pg = &rxr->rx_pg_ring[pg_cons];
  2341. pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
  2342. PAGE_SIZE, PCI_DMA_FROMDEVICE);
  2343. if (i == pages - 1)
  2344. frag_len -= 4;
  2345. skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
  2346. rx_pg->page = NULL;
  2347. err = bnx2_alloc_rx_page(bp, rxr,
  2348. RX_PG_RING_IDX(pg_prod));
  2349. if (unlikely(err)) {
  2350. rxr->rx_pg_cons = pg_cons;
  2351. rxr->rx_pg_prod = pg_prod;
  2352. bnx2_reuse_rx_skb_pages(bp, rxr, skb,
  2353. pages - i);
  2354. return err;
  2355. }
  2356. frag_size -= frag_len;
  2357. skb->data_len += frag_len;
  2358. skb->truesize += frag_len;
  2359. skb->len += frag_len;
  2360. pg_prod = NEXT_RX_BD(pg_prod);
  2361. pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
  2362. }
  2363. rxr->rx_pg_prod = pg_prod;
  2364. rxr->rx_pg_cons = pg_cons;
  2365. }
  2366. return 0;
  2367. }
  2368. static inline u16
  2369. bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
  2370. {
  2371. u16 cons;
  2372. /* Tell compiler that status block fields can change. */
  2373. barrier();
  2374. cons = *bnapi->hw_rx_cons_ptr;
  2375. if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
  2376. cons++;
  2377. return cons;
  2378. }
  2379. static int
  2380. bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
  2381. {
  2382. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2383. u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
  2384. struct l2_fhdr *rx_hdr;
  2385. int rx_pkt = 0, pg_ring_used = 0;
  2386. hw_cons = bnx2_get_hw_rx_cons(bnapi);
  2387. sw_cons = rxr->rx_cons;
  2388. sw_prod = rxr->rx_prod;
  2389. /* Memory barrier necessary as speculative reads of the rx
  2390. * buffer can be ahead of the index in the status block
  2391. */
  2392. rmb();
  2393. while (sw_cons != hw_cons) {
  2394. unsigned int len, hdr_len;
  2395. u32 status;
  2396. struct sw_bd *rx_buf;
  2397. struct sk_buff *skb;
  2398. dma_addr_t dma_addr;
  2399. u16 vtag = 0;
  2400. int hw_vlan __maybe_unused = 0;
  2401. sw_ring_cons = RX_RING_IDX(sw_cons);
  2402. sw_ring_prod = RX_RING_IDX(sw_prod);
  2403. rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
  2404. skb = rx_buf->skb;
  2405. rx_buf->skb = NULL;
  2406. dma_addr = pci_unmap_addr(rx_buf, mapping);
  2407. pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
  2408. BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
  2409. PCI_DMA_FROMDEVICE);
  2410. rx_hdr = (struct l2_fhdr *) skb->data;
  2411. len = rx_hdr->l2_fhdr_pkt_len;
  2412. if ((status = rx_hdr->l2_fhdr_status) &
  2413. (L2_FHDR_ERRORS_BAD_CRC |
  2414. L2_FHDR_ERRORS_PHY_DECODE |
  2415. L2_FHDR_ERRORS_ALIGNMENT |
  2416. L2_FHDR_ERRORS_TOO_SHORT |
  2417. L2_FHDR_ERRORS_GIANT_FRAME)) {
  2418. bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
  2419. sw_ring_prod);
  2420. goto next_rx;
  2421. }
  2422. hdr_len = 0;
  2423. if (status & L2_FHDR_STATUS_SPLIT) {
  2424. hdr_len = rx_hdr->l2_fhdr_ip_xsum;
  2425. pg_ring_used = 1;
  2426. } else if (len > bp->rx_jumbo_thresh) {
  2427. hdr_len = bp->rx_jumbo_thresh;
  2428. pg_ring_used = 1;
  2429. }
  2430. len -= 4;
  2431. if (len <= bp->rx_copy_thresh) {
  2432. struct sk_buff *new_skb;
  2433. new_skb = netdev_alloc_skb(bp->dev, len + 6);
  2434. if (new_skb == NULL) {
  2435. bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
  2436. sw_ring_prod);
  2437. goto next_rx;
  2438. }
  2439. /* aligned copy */
  2440. skb_copy_from_linear_data_offset(skb,
  2441. BNX2_RX_OFFSET - 6,
  2442. new_skb->data, len + 6);
  2443. skb_reserve(new_skb, 6);
  2444. skb_put(new_skb, len);
  2445. bnx2_reuse_rx_skb(bp, rxr, skb,
  2446. sw_ring_cons, sw_ring_prod);
  2447. skb = new_skb;
  2448. } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
  2449. dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
  2450. goto next_rx;
  2451. if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
  2452. !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
  2453. vtag = rx_hdr->l2_fhdr_vlan_tag;
  2454. #ifdef BCM_VLAN
  2455. if (bp->vlgrp)
  2456. hw_vlan = 1;
  2457. else
  2458. #endif
  2459. {
  2460. struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
  2461. __skb_push(skb, 4);
  2462. memmove(ve, skb->data + 4, ETH_ALEN * 2);
  2463. ve->h_vlan_proto = htons(ETH_P_8021Q);
  2464. ve->h_vlan_TCI = htons(vtag);
  2465. len += 4;
  2466. }
  2467. }
  2468. skb->protocol = eth_type_trans(skb, bp->dev);
  2469. if ((len > (bp->dev->mtu + ETH_HLEN)) &&
  2470. (ntohs(skb->protocol) != 0x8100)) {
  2471. dev_kfree_skb(skb);
  2472. goto next_rx;
  2473. }
  2474. skb->ip_summed = CHECKSUM_NONE;
  2475. if (bp->rx_csum &&
  2476. (status & (L2_FHDR_STATUS_TCP_SEGMENT |
  2477. L2_FHDR_STATUS_UDP_DATAGRAM))) {
  2478. if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
  2479. L2_FHDR_ERRORS_UDP_XSUM)) == 0))
  2480. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2481. }
  2482. #ifdef BCM_VLAN
  2483. if (hw_vlan)
  2484. vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
  2485. else
  2486. #endif
  2487. netif_receive_skb(skb);
  2488. bp->dev->last_rx = jiffies;
  2489. rx_pkt++;
  2490. next_rx:
  2491. sw_cons = NEXT_RX_BD(sw_cons);
  2492. sw_prod = NEXT_RX_BD(sw_prod);
  2493. if ((rx_pkt == budget))
  2494. break;
  2495. /* Refresh hw_cons to see if there is new work */
  2496. if (sw_cons == hw_cons) {
  2497. hw_cons = bnx2_get_hw_rx_cons(bnapi);
  2498. rmb();
  2499. }
  2500. }
  2501. rxr->rx_cons = sw_cons;
  2502. rxr->rx_prod = sw_prod;
  2503. if (pg_ring_used)
  2504. REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
  2505. REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
  2506. REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
  2507. mmiowb();
  2508. return rx_pkt;
  2509. }
  2510. /* MSI ISR - The only difference between this and the INTx ISR
  2511. * is that the MSI interrupt is always serviced.
  2512. */
  2513. static irqreturn_t
  2514. bnx2_msi(int irq, void *dev_instance)
  2515. {
  2516. struct bnx2_napi *bnapi = dev_instance;
  2517. struct bnx2 *bp = bnapi->bp;
  2518. struct net_device *dev = bp->dev;
  2519. prefetch(bnapi->status_blk.msi);
  2520. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2521. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  2522. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2523. /* Return here if interrupt is disabled. */
  2524. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2525. return IRQ_HANDLED;
  2526. netif_rx_schedule(dev, &bnapi->napi);
  2527. return IRQ_HANDLED;
  2528. }
  2529. static irqreturn_t
  2530. bnx2_msi_1shot(int irq, void *dev_instance)
  2531. {
  2532. struct bnx2_napi *bnapi = dev_instance;
  2533. struct bnx2 *bp = bnapi->bp;
  2534. struct net_device *dev = bp->dev;
  2535. prefetch(bnapi->status_blk.msi);
  2536. /* Return here if interrupt is disabled. */
  2537. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2538. return IRQ_HANDLED;
  2539. netif_rx_schedule(dev, &bnapi->napi);
  2540. return IRQ_HANDLED;
  2541. }
  2542. static irqreturn_t
  2543. bnx2_interrupt(int irq, void *dev_instance)
  2544. {
  2545. struct bnx2_napi *bnapi = dev_instance;
  2546. struct bnx2 *bp = bnapi->bp;
  2547. struct net_device *dev = bp->dev;
  2548. struct status_block *sblk = bnapi->status_blk.msi;
  2549. /* When using INTx, it is possible for the interrupt to arrive
  2550. * at the CPU before the status block posted prior to the
  2551. * interrupt. Reading a register will flush the status block.
  2552. * When using MSI, the MSI message will always complete after
  2553. * the status block write.
  2554. */
  2555. if ((sblk->status_idx == bnapi->last_status_idx) &&
  2556. (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
  2557. BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
  2558. return IRQ_NONE;
  2559. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2560. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  2561. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2562. /* Read back to deassert IRQ immediately to avoid too many
  2563. * spurious interrupts.
  2564. */
  2565. REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  2566. /* Return here if interrupt is shared and is disabled. */
  2567. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  2568. return IRQ_HANDLED;
  2569. if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
  2570. bnapi->last_status_idx = sblk->status_idx;
  2571. __netif_rx_schedule(dev, &bnapi->napi);
  2572. }
  2573. return IRQ_HANDLED;
  2574. }
  2575. static inline int
  2576. bnx2_has_fast_work(struct bnx2_napi *bnapi)
  2577. {
  2578. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2579. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2580. if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
  2581. (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
  2582. return 1;
  2583. return 0;
  2584. }
  2585. #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
  2586. STATUS_ATTN_BITS_TIMER_ABORT)
  2587. static inline int
  2588. bnx2_has_work(struct bnx2_napi *bnapi)
  2589. {
  2590. struct status_block *sblk = bnapi->status_blk.msi;
  2591. if (bnx2_has_fast_work(bnapi))
  2592. return 1;
  2593. if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
  2594. (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
  2595. return 1;
  2596. return 0;
  2597. }
  2598. static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
  2599. {
  2600. struct status_block *sblk = bnapi->status_blk.msi;
  2601. u32 status_attn_bits = sblk->status_attn_bits;
  2602. u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
  2603. if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
  2604. (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
  2605. bnx2_phy_int(bp, bnapi);
  2606. /* This is needed to take care of transient status
  2607. * during link changes.
  2608. */
  2609. REG_WR(bp, BNX2_HC_COMMAND,
  2610. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2611. REG_RD(bp, BNX2_HC_COMMAND);
  2612. }
  2613. }
  2614. static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
  2615. int work_done, int budget)
  2616. {
  2617. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  2618. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  2619. if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
  2620. bnx2_tx_int(bp, bnapi, 0);
  2621. if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
  2622. work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
  2623. return work_done;
  2624. }
  2625. static int bnx2_poll_msix(struct napi_struct *napi, int budget)
  2626. {
  2627. struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
  2628. struct bnx2 *bp = bnapi->bp;
  2629. int work_done = 0;
  2630. struct status_block_msix *sblk = bnapi->status_blk.msix;
  2631. while (1) {
  2632. work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
  2633. if (unlikely(work_done >= budget))
  2634. break;
  2635. bnapi->last_status_idx = sblk->status_idx;
  2636. /* status idx must be read before checking for more work. */
  2637. rmb();
  2638. if (likely(!bnx2_has_fast_work(bnapi))) {
  2639. netif_rx_complete(bp->dev, napi);
  2640. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
  2641. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2642. bnapi->last_status_idx);
  2643. break;
  2644. }
  2645. }
  2646. return work_done;
  2647. }
  2648. static int bnx2_poll(struct napi_struct *napi, int budget)
  2649. {
  2650. struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
  2651. struct bnx2 *bp = bnapi->bp;
  2652. int work_done = 0;
  2653. struct status_block *sblk = bnapi->status_blk.msi;
  2654. while (1) {
  2655. bnx2_poll_link(bp, bnapi);
  2656. work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
  2657. if (unlikely(work_done >= budget))
  2658. break;
  2659. /* bnapi->last_status_idx is used below to tell the hw how
  2660. * much work has been processed, so we must read it before
  2661. * checking for more work.
  2662. */
  2663. bnapi->last_status_idx = sblk->status_idx;
  2664. rmb();
  2665. if (likely(!bnx2_has_work(bnapi))) {
  2666. netif_rx_complete(bp->dev, napi);
  2667. if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
  2668. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2669. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2670. bnapi->last_status_idx);
  2671. break;
  2672. }
  2673. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2674. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2675. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  2676. bnapi->last_status_idx);
  2677. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2678. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2679. bnapi->last_status_idx);
  2680. break;
  2681. }
  2682. }
  2683. return work_done;
  2684. }
  2685. /* Called with rtnl_lock from vlan functions and also netif_tx_lock
  2686. * from set_multicast.
  2687. */
  2688. static void
  2689. bnx2_set_rx_mode(struct net_device *dev)
  2690. {
  2691. struct bnx2 *bp = netdev_priv(dev);
  2692. u32 rx_mode, sort_mode;
  2693. struct dev_addr_list *uc_ptr;
  2694. int i;
  2695. spin_lock_bh(&bp->phy_lock);
  2696. rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
  2697. BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
  2698. sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
  2699. #ifdef BCM_VLAN
  2700. if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
  2701. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  2702. #else
  2703. if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
  2704. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  2705. #endif
  2706. if (dev->flags & IFF_PROMISC) {
  2707. /* Promiscuous mode. */
  2708. rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
  2709. sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
  2710. BNX2_RPM_SORT_USER0_PROM_VLAN;
  2711. }
  2712. else if (dev->flags & IFF_ALLMULTI) {
  2713. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  2714. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  2715. 0xffffffff);
  2716. }
  2717. sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
  2718. }
  2719. else {
  2720. /* Accept one or more multicast(s). */
  2721. struct dev_mc_list *mclist;
  2722. u32 mc_filter[NUM_MC_HASH_REGISTERS];
  2723. u32 regidx;
  2724. u32 bit;
  2725. u32 crc;
  2726. memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
  2727. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2728. i++, mclist = mclist->next) {
  2729. crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
  2730. bit = crc & 0xff;
  2731. regidx = (bit & 0xe0) >> 5;
  2732. bit &= 0x1f;
  2733. mc_filter[regidx] |= (1 << bit);
  2734. }
  2735. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  2736. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  2737. mc_filter[i]);
  2738. }
  2739. sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
  2740. }
  2741. uc_ptr = NULL;
  2742. if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
  2743. rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
  2744. sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
  2745. BNX2_RPM_SORT_USER0_PROM_VLAN;
  2746. } else if (!(dev->flags & IFF_PROMISC)) {
  2747. uc_ptr = dev->uc_list;
  2748. /* Add all entries into to the match filter list */
  2749. for (i = 0; i < dev->uc_count; i++) {
  2750. bnx2_set_mac_addr(bp, uc_ptr->da_addr,
  2751. i + BNX2_START_UNICAST_ADDRESS_INDEX);
  2752. sort_mode |= (1 <<
  2753. (i + BNX2_START_UNICAST_ADDRESS_INDEX));
  2754. uc_ptr = uc_ptr->next;
  2755. }
  2756. }
  2757. if (rx_mode != bp->rx_mode) {
  2758. bp->rx_mode = rx_mode;
  2759. REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
  2760. }
  2761. REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  2762. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
  2763. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
  2764. spin_unlock_bh(&bp->phy_lock);
  2765. }
  2766. static void
  2767. load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
  2768. u32 rv2p_proc)
  2769. {
  2770. int i;
  2771. u32 val;
  2772. if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
  2773. val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
  2774. val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
  2775. val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
  2776. rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
  2777. }
  2778. for (i = 0; i < rv2p_code_len; i += 8) {
  2779. REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
  2780. rv2p_code++;
  2781. REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
  2782. rv2p_code++;
  2783. if (rv2p_proc == RV2P_PROC1) {
  2784. val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
  2785. REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
  2786. }
  2787. else {
  2788. val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
  2789. REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
  2790. }
  2791. }
  2792. /* Reset the processor, un-stall is done later. */
  2793. if (rv2p_proc == RV2P_PROC1) {
  2794. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
  2795. }
  2796. else {
  2797. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
  2798. }
  2799. }
  2800. static int
  2801. load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
  2802. {
  2803. u32 offset;
  2804. u32 val;
  2805. int rc;
  2806. /* Halt the CPU. */
  2807. val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
  2808. val |= cpu_reg->mode_value_halt;
  2809. bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
  2810. bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
  2811. /* Load the Text area. */
  2812. offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
  2813. if (fw->gz_text) {
  2814. int j;
  2815. rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
  2816. fw->gz_text_len);
  2817. if (rc < 0)
  2818. return rc;
  2819. for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
  2820. bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
  2821. }
  2822. }
  2823. /* Load the Data area. */
  2824. offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
  2825. if (fw->data) {
  2826. int j;
  2827. for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
  2828. bnx2_reg_wr_ind(bp, offset, fw->data[j]);
  2829. }
  2830. }
  2831. /* Load the SBSS area. */
  2832. offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
  2833. if (fw->sbss_len) {
  2834. int j;
  2835. for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
  2836. bnx2_reg_wr_ind(bp, offset, 0);
  2837. }
  2838. }
  2839. /* Load the BSS area. */
  2840. offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
  2841. if (fw->bss_len) {
  2842. int j;
  2843. for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
  2844. bnx2_reg_wr_ind(bp, offset, 0);
  2845. }
  2846. }
  2847. /* Load the Read-Only area. */
  2848. offset = cpu_reg->spad_base +
  2849. (fw->rodata_addr - cpu_reg->mips_view_base);
  2850. if (fw->rodata) {
  2851. int j;
  2852. for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
  2853. bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
  2854. }
  2855. }
  2856. /* Clear the pre-fetch instruction. */
  2857. bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
  2858. bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
  2859. /* Start the CPU. */
  2860. val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
  2861. val &= ~cpu_reg->mode_value_halt;
  2862. bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
  2863. bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
  2864. return 0;
  2865. }
  2866. static int
  2867. bnx2_init_cpus(struct bnx2 *bp)
  2868. {
  2869. struct fw_info *fw;
  2870. int rc, rv2p_len;
  2871. void *text, *rv2p;
  2872. /* Initialize the RV2P processor. */
  2873. text = vmalloc(FW_BUF_SIZE);
  2874. if (!text)
  2875. return -ENOMEM;
  2876. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  2877. rv2p = bnx2_xi_rv2p_proc1;
  2878. rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
  2879. } else {
  2880. rv2p = bnx2_rv2p_proc1;
  2881. rv2p_len = sizeof(bnx2_rv2p_proc1);
  2882. }
  2883. rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
  2884. if (rc < 0)
  2885. goto init_cpu_err;
  2886. load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
  2887. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  2888. rv2p = bnx2_xi_rv2p_proc2;
  2889. rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
  2890. } else {
  2891. rv2p = bnx2_rv2p_proc2;
  2892. rv2p_len = sizeof(bnx2_rv2p_proc2);
  2893. }
  2894. rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
  2895. if (rc < 0)
  2896. goto init_cpu_err;
  2897. load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
  2898. /* Initialize the RX Processor. */
  2899. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2900. fw = &bnx2_rxp_fw_09;
  2901. else
  2902. fw = &bnx2_rxp_fw_06;
  2903. fw->text = text;
  2904. rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
  2905. if (rc)
  2906. goto init_cpu_err;
  2907. /* Initialize the TX Processor. */
  2908. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2909. fw = &bnx2_txp_fw_09;
  2910. else
  2911. fw = &bnx2_txp_fw_06;
  2912. fw->text = text;
  2913. rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
  2914. if (rc)
  2915. goto init_cpu_err;
  2916. /* Initialize the TX Patch-up Processor. */
  2917. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2918. fw = &bnx2_tpat_fw_09;
  2919. else
  2920. fw = &bnx2_tpat_fw_06;
  2921. fw->text = text;
  2922. rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
  2923. if (rc)
  2924. goto init_cpu_err;
  2925. /* Initialize the Completion Processor. */
  2926. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2927. fw = &bnx2_com_fw_09;
  2928. else
  2929. fw = &bnx2_com_fw_06;
  2930. fw->text = text;
  2931. rc = load_cpu_fw(bp, &cpu_reg_com, fw);
  2932. if (rc)
  2933. goto init_cpu_err;
  2934. /* Initialize the Command Processor. */
  2935. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2936. fw = &bnx2_cp_fw_09;
  2937. else
  2938. fw = &bnx2_cp_fw_06;
  2939. fw->text = text;
  2940. rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
  2941. init_cpu_err:
  2942. vfree(text);
  2943. return rc;
  2944. }
  2945. static int
  2946. bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
  2947. {
  2948. u16 pmcsr;
  2949. pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
  2950. switch (state) {
  2951. case PCI_D0: {
  2952. u32 val;
  2953. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
  2954. (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
  2955. PCI_PM_CTRL_PME_STATUS);
  2956. if (pmcsr & PCI_PM_CTRL_STATE_MASK)
  2957. /* delay required during transition out of D3hot */
  2958. msleep(20);
  2959. val = REG_RD(bp, BNX2_EMAC_MODE);
  2960. val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
  2961. val &= ~BNX2_EMAC_MODE_MPKT;
  2962. REG_WR(bp, BNX2_EMAC_MODE, val);
  2963. val = REG_RD(bp, BNX2_RPM_CONFIG);
  2964. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  2965. REG_WR(bp, BNX2_RPM_CONFIG, val);
  2966. break;
  2967. }
  2968. case PCI_D3hot: {
  2969. int i;
  2970. u32 val, wol_msg;
  2971. if (bp->wol) {
  2972. u32 advertising;
  2973. u8 autoneg;
  2974. autoneg = bp->autoneg;
  2975. advertising = bp->advertising;
  2976. if (bp->phy_port == PORT_TP) {
  2977. bp->autoneg = AUTONEG_SPEED;
  2978. bp->advertising = ADVERTISED_10baseT_Half |
  2979. ADVERTISED_10baseT_Full |
  2980. ADVERTISED_100baseT_Half |
  2981. ADVERTISED_100baseT_Full |
  2982. ADVERTISED_Autoneg;
  2983. }
  2984. spin_lock_bh(&bp->phy_lock);
  2985. bnx2_setup_phy(bp, bp->phy_port);
  2986. spin_unlock_bh(&bp->phy_lock);
  2987. bp->autoneg = autoneg;
  2988. bp->advertising = advertising;
  2989. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  2990. val = REG_RD(bp, BNX2_EMAC_MODE);
  2991. /* Enable port mode. */
  2992. val &= ~BNX2_EMAC_MODE_PORT;
  2993. val |= BNX2_EMAC_MODE_MPKT_RCVD |
  2994. BNX2_EMAC_MODE_ACPI_RCVD |
  2995. BNX2_EMAC_MODE_MPKT;
  2996. if (bp->phy_port == PORT_TP)
  2997. val |= BNX2_EMAC_MODE_PORT_MII;
  2998. else {
  2999. val |= BNX2_EMAC_MODE_PORT_GMII;
  3000. if (bp->line_speed == SPEED_2500)
  3001. val |= BNX2_EMAC_MODE_25G_MODE;
  3002. }
  3003. REG_WR(bp, BNX2_EMAC_MODE, val);
  3004. /* receive all multicast */
  3005. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  3006. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  3007. 0xffffffff);
  3008. }
  3009. REG_WR(bp, BNX2_EMAC_RX_MODE,
  3010. BNX2_EMAC_RX_MODE_SORT_MODE);
  3011. val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
  3012. BNX2_RPM_SORT_USER0_MC_EN;
  3013. REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  3014. REG_WR(bp, BNX2_RPM_SORT_USER0, val);
  3015. REG_WR(bp, BNX2_RPM_SORT_USER0, val |
  3016. BNX2_RPM_SORT_USER0_ENA);
  3017. /* Need to enable EMAC and RPM for WOL. */
  3018. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  3019. BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
  3020. BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
  3021. BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
  3022. val = REG_RD(bp, BNX2_RPM_CONFIG);
  3023. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  3024. REG_WR(bp, BNX2_RPM_CONFIG, val);
  3025. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  3026. }
  3027. else {
  3028. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  3029. }
  3030. if (!(bp->flags & BNX2_FLAG_NO_WOL))
  3031. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
  3032. 1, 0);
  3033. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  3034. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  3035. (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
  3036. if (bp->wol)
  3037. pmcsr |= 3;
  3038. }
  3039. else {
  3040. pmcsr |= 3;
  3041. }
  3042. if (bp->wol) {
  3043. pmcsr |= PCI_PM_CTRL_PME_ENABLE;
  3044. }
  3045. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
  3046. pmcsr);
  3047. /* No more memory access after this point until
  3048. * device is brought back to D0.
  3049. */
  3050. udelay(50);
  3051. break;
  3052. }
  3053. default:
  3054. return -EINVAL;
  3055. }
  3056. return 0;
  3057. }
  3058. static int
  3059. bnx2_acquire_nvram_lock(struct bnx2 *bp)
  3060. {
  3061. u32 val;
  3062. int j;
  3063. /* Request access to the flash interface. */
  3064. REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
  3065. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3066. val = REG_RD(bp, BNX2_NVM_SW_ARB);
  3067. if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
  3068. break;
  3069. udelay(5);
  3070. }
  3071. if (j >= NVRAM_TIMEOUT_COUNT)
  3072. return -EBUSY;
  3073. return 0;
  3074. }
  3075. static int
  3076. bnx2_release_nvram_lock(struct bnx2 *bp)
  3077. {
  3078. int j;
  3079. u32 val;
  3080. /* Relinquish nvram interface. */
  3081. REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
  3082. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3083. val = REG_RD(bp, BNX2_NVM_SW_ARB);
  3084. if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
  3085. break;
  3086. udelay(5);
  3087. }
  3088. if (j >= NVRAM_TIMEOUT_COUNT)
  3089. return -EBUSY;
  3090. return 0;
  3091. }
  3092. static int
  3093. bnx2_enable_nvram_write(struct bnx2 *bp)
  3094. {
  3095. u32 val;
  3096. val = REG_RD(bp, BNX2_MISC_CFG);
  3097. REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
  3098. if (bp->flash_info->flags & BNX2_NV_WREN) {
  3099. int j;
  3100. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3101. REG_WR(bp, BNX2_NVM_COMMAND,
  3102. BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
  3103. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3104. udelay(5);
  3105. val = REG_RD(bp, BNX2_NVM_COMMAND);
  3106. if (val & BNX2_NVM_COMMAND_DONE)
  3107. break;
  3108. }
  3109. if (j >= NVRAM_TIMEOUT_COUNT)
  3110. return -EBUSY;
  3111. }
  3112. return 0;
  3113. }
  3114. static void
  3115. bnx2_disable_nvram_write(struct bnx2 *bp)
  3116. {
  3117. u32 val;
  3118. val = REG_RD(bp, BNX2_MISC_CFG);
  3119. REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
  3120. }
  3121. static void
  3122. bnx2_enable_nvram_access(struct bnx2 *bp)
  3123. {
  3124. u32 val;
  3125. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  3126. /* Enable both bits, even on read. */
  3127. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  3128. val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
  3129. }
  3130. static void
  3131. bnx2_disable_nvram_access(struct bnx2 *bp)
  3132. {
  3133. u32 val;
  3134. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  3135. /* Disable both bits, even after read. */
  3136. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  3137. val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
  3138. BNX2_NVM_ACCESS_ENABLE_WR_EN));
  3139. }
  3140. static int
  3141. bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
  3142. {
  3143. u32 cmd;
  3144. int j;
  3145. if (bp->flash_info->flags & BNX2_NV_BUFFERED)
  3146. /* Buffered flash, no erase needed */
  3147. return 0;
  3148. /* Build an erase command */
  3149. cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
  3150. BNX2_NVM_COMMAND_DOIT;
  3151. /* Need to clear DONE bit separately. */
  3152. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3153. /* Address of the NVRAM to read from. */
  3154. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3155. /* Issue an erase command. */
  3156. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  3157. /* Wait for completion. */
  3158. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3159. u32 val;
  3160. udelay(5);
  3161. val = REG_RD(bp, BNX2_NVM_COMMAND);
  3162. if (val & BNX2_NVM_COMMAND_DONE)
  3163. break;
  3164. }
  3165. if (j >= NVRAM_TIMEOUT_COUNT)
  3166. return -EBUSY;
  3167. return 0;
  3168. }
  3169. static int
  3170. bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
  3171. {
  3172. u32 cmd;
  3173. int j;
  3174. /* Build the command word. */
  3175. cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
  3176. /* Calculate an offset of a buffered flash, not needed for 5709. */
  3177. if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
  3178. offset = ((offset / bp->flash_info->page_size) <<
  3179. bp->flash_info->page_bits) +
  3180. (offset % bp->flash_info->page_size);
  3181. }
  3182. /* Need to clear DONE bit separately. */
  3183. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3184. /* Address of the NVRAM to read from. */
  3185. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3186. /* Issue a read command. */
  3187. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  3188. /* Wait for completion. */
  3189. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3190. u32 val;
  3191. udelay(5);
  3192. val = REG_RD(bp, BNX2_NVM_COMMAND);
  3193. if (val & BNX2_NVM_COMMAND_DONE) {
  3194. __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
  3195. memcpy(ret_val, &v, 4);
  3196. break;
  3197. }
  3198. }
  3199. if (j >= NVRAM_TIMEOUT_COUNT)
  3200. return -EBUSY;
  3201. return 0;
  3202. }
  3203. static int
  3204. bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
  3205. {
  3206. u32 cmd;
  3207. __be32 val32;
  3208. int j;
  3209. /* Build the command word. */
  3210. cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
  3211. /* Calculate an offset of a buffered flash, not needed for 5709. */
  3212. if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
  3213. offset = ((offset / bp->flash_info->page_size) <<
  3214. bp->flash_info->page_bits) +
  3215. (offset % bp->flash_info->page_size);
  3216. }
  3217. /* Need to clear DONE bit separately. */
  3218. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  3219. memcpy(&val32, val, 4);
  3220. /* Write the data. */
  3221. REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
  3222. /* Address of the NVRAM to write to. */
  3223. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  3224. /* Issue the write command. */
  3225. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  3226. /* Wait for completion. */
  3227. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  3228. udelay(5);
  3229. if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
  3230. break;
  3231. }
  3232. if (j >= NVRAM_TIMEOUT_COUNT)
  3233. return -EBUSY;
  3234. return 0;
  3235. }
  3236. static int
  3237. bnx2_init_nvram(struct bnx2 *bp)
  3238. {
  3239. u32 val;
  3240. int j, entry_count, rc = 0;
  3241. struct flash_spec *flash;
  3242. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3243. bp->flash_info = &flash_5709;
  3244. goto get_flash_size;
  3245. }
  3246. /* Determine the selected interface. */
  3247. val = REG_RD(bp, BNX2_NVM_CFG1);
  3248. entry_count = ARRAY_SIZE(flash_table);
  3249. if (val & 0x40000000) {
  3250. /* Flash interface has been reconfigured */
  3251. for (j = 0, flash = &flash_table[0]; j < entry_count;
  3252. j++, flash++) {
  3253. if ((val & FLASH_BACKUP_STRAP_MASK) ==
  3254. (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
  3255. bp->flash_info = flash;
  3256. break;
  3257. }
  3258. }
  3259. }
  3260. else {
  3261. u32 mask;
  3262. /* Not yet been reconfigured */
  3263. if (val & (1 << 23))
  3264. mask = FLASH_BACKUP_STRAP_MASK;
  3265. else
  3266. mask = FLASH_STRAP_MASK;
  3267. for (j = 0, flash = &flash_table[0]; j < entry_count;
  3268. j++, flash++) {
  3269. if ((val & mask) == (flash->strapping & mask)) {
  3270. bp->flash_info = flash;
  3271. /* Request access to the flash interface. */
  3272. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3273. return rc;
  3274. /* Enable access to flash interface */
  3275. bnx2_enable_nvram_access(bp);
  3276. /* Reconfigure the flash interface */
  3277. REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
  3278. REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
  3279. REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
  3280. REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
  3281. /* Disable access to flash interface */
  3282. bnx2_disable_nvram_access(bp);
  3283. bnx2_release_nvram_lock(bp);
  3284. break;
  3285. }
  3286. }
  3287. } /* if (val & 0x40000000) */
  3288. if (j == entry_count) {
  3289. bp->flash_info = NULL;
  3290. printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
  3291. return -ENODEV;
  3292. }
  3293. get_flash_size:
  3294. val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
  3295. val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
  3296. if (val)
  3297. bp->flash_size = val;
  3298. else
  3299. bp->flash_size = bp->flash_info->total_size;
  3300. return rc;
  3301. }
  3302. static int
  3303. bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
  3304. int buf_size)
  3305. {
  3306. int rc = 0;
  3307. u32 cmd_flags, offset32, len32, extra;
  3308. if (buf_size == 0)
  3309. return 0;
  3310. /* Request access to the flash interface. */
  3311. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3312. return rc;
  3313. /* Enable access to flash interface */
  3314. bnx2_enable_nvram_access(bp);
  3315. len32 = buf_size;
  3316. offset32 = offset;
  3317. extra = 0;
  3318. cmd_flags = 0;
  3319. if (offset32 & 3) {
  3320. u8 buf[4];
  3321. u32 pre_len;
  3322. offset32 &= ~3;
  3323. pre_len = 4 - (offset & 3);
  3324. if (pre_len >= len32) {
  3325. pre_len = len32;
  3326. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  3327. BNX2_NVM_COMMAND_LAST;
  3328. }
  3329. else {
  3330. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3331. }
  3332. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3333. if (rc)
  3334. return rc;
  3335. memcpy(ret_buf, buf + (offset & 3), pre_len);
  3336. offset32 += 4;
  3337. ret_buf += pre_len;
  3338. len32 -= pre_len;
  3339. }
  3340. if (len32 & 3) {
  3341. extra = 4 - (len32 & 3);
  3342. len32 = (len32 + 4) & ~3;
  3343. }
  3344. if (len32 == 4) {
  3345. u8 buf[4];
  3346. if (cmd_flags)
  3347. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3348. else
  3349. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  3350. BNX2_NVM_COMMAND_LAST;
  3351. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3352. memcpy(ret_buf, buf, 4 - extra);
  3353. }
  3354. else if (len32 > 0) {
  3355. u8 buf[4];
  3356. /* Read the first word. */
  3357. if (cmd_flags)
  3358. cmd_flags = 0;
  3359. else
  3360. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3361. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
  3362. /* Advance to the next dword. */
  3363. offset32 += 4;
  3364. ret_buf += 4;
  3365. len32 -= 4;
  3366. while (len32 > 4 && rc == 0) {
  3367. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
  3368. /* Advance to the next dword. */
  3369. offset32 += 4;
  3370. ret_buf += 4;
  3371. len32 -= 4;
  3372. }
  3373. if (rc)
  3374. return rc;
  3375. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3376. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  3377. memcpy(ret_buf, buf, 4 - extra);
  3378. }
  3379. /* Disable access to flash interface */
  3380. bnx2_disable_nvram_access(bp);
  3381. bnx2_release_nvram_lock(bp);
  3382. return rc;
  3383. }
  3384. static int
  3385. bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
  3386. int buf_size)
  3387. {
  3388. u32 written, offset32, len32;
  3389. u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
  3390. int rc = 0;
  3391. int align_start, align_end;
  3392. buf = data_buf;
  3393. offset32 = offset;
  3394. len32 = buf_size;
  3395. align_start = align_end = 0;
  3396. if ((align_start = (offset32 & 3))) {
  3397. offset32 &= ~3;
  3398. len32 += align_start;
  3399. if (len32 < 4)
  3400. len32 = 4;
  3401. if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
  3402. return rc;
  3403. }
  3404. if (len32 & 3) {
  3405. align_end = 4 - (len32 & 3);
  3406. len32 += align_end;
  3407. if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
  3408. return rc;
  3409. }
  3410. if (align_start || align_end) {
  3411. align_buf = kmalloc(len32, GFP_KERNEL);
  3412. if (align_buf == NULL)
  3413. return -ENOMEM;
  3414. if (align_start) {
  3415. memcpy(align_buf, start, 4);
  3416. }
  3417. if (align_end) {
  3418. memcpy(align_buf + len32 - 4, end, 4);
  3419. }
  3420. memcpy(align_buf + align_start, data_buf, buf_size);
  3421. buf = align_buf;
  3422. }
  3423. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3424. flash_buffer = kmalloc(264, GFP_KERNEL);
  3425. if (flash_buffer == NULL) {
  3426. rc = -ENOMEM;
  3427. goto nvram_write_end;
  3428. }
  3429. }
  3430. written = 0;
  3431. while ((written < len32) && (rc == 0)) {
  3432. u32 page_start, page_end, data_start, data_end;
  3433. u32 addr, cmd_flags;
  3434. int i;
  3435. /* Find the page_start addr */
  3436. page_start = offset32 + written;
  3437. page_start -= (page_start % bp->flash_info->page_size);
  3438. /* Find the page_end addr */
  3439. page_end = page_start + bp->flash_info->page_size;
  3440. /* Find the data_start addr */
  3441. data_start = (written == 0) ? offset32 : page_start;
  3442. /* Find the data_end addr */
  3443. data_end = (page_end > offset32 + len32) ?
  3444. (offset32 + len32) : page_end;
  3445. /* Request access to the flash interface. */
  3446. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  3447. goto nvram_write_end;
  3448. /* Enable access to flash interface */
  3449. bnx2_enable_nvram_access(bp);
  3450. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  3451. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3452. int j;
  3453. /* Read the whole page into the buffer
  3454. * (non-buffer flash only) */
  3455. for (j = 0; j < bp->flash_info->page_size; j += 4) {
  3456. if (j == (bp->flash_info->page_size - 4)) {
  3457. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  3458. }
  3459. rc = bnx2_nvram_read_dword(bp,
  3460. page_start + j,
  3461. &flash_buffer[j],
  3462. cmd_flags);
  3463. if (rc)
  3464. goto nvram_write_end;
  3465. cmd_flags = 0;
  3466. }
  3467. }
  3468. /* Enable writes to flash interface (unlock write-protect) */
  3469. if ((rc = bnx2_enable_nvram_write(bp)) != 0)
  3470. goto nvram_write_end;
  3471. /* Loop to write back the buffer data from page_start to
  3472. * data_start */
  3473. i = 0;
  3474. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3475. /* Erase the page */
  3476. if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
  3477. goto nvram_write_end;
  3478. /* Re-enable the write again for the actual write */
  3479. bnx2_enable_nvram_write(bp);
  3480. for (addr = page_start; addr < data_start;
  3481. addr += 4, i += 4) {
  3482. rc = bnx2_nvram_write_dword(bp, addr,
  3483. &flash_buffer[i], cmd_flags);
  3484. if (rc != 0)
  3485. goto nvram_write_end;
  3486. cmd_flags = 0;
  3487. }
  3488. }
  3489. /* Loop to write the new data from data_start to data_end */
  3490. for (addr = data_start; addr < data_end; addr += 4, i += 4) {
  3491. if ((addr == page_end - 4) ||
  3492. ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
  3493. (addr == data_end - 4))) {
  3494. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  3495. }
  3496. rc = bnx2_nvram_write_dword(bp, addr, buf,
  3497. cmd_flags);
  3498. if (rc != 0)
  3499. goto nvram_write_end;
  3500. cmd_flags = 0;
  3501. buf += 4;
  3502. }
  3503. /* Loop to write back the buffer data from data_end
  3504. * to page_end */
  3505. if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
  3506. for (addr = data_end; addr < page_end;
  3507. addr += 4, i += 4) {
  3508. if (addr == page_end-4) {
  3509. cmd_flags = BNX2_NVM_COMMAND_LAST;
  3510. }
  3511. rc = bnx2_nvram_write_dword(bp, addr,
  3512. &flash_buffer[i], cmd_flags);
  3513. if (rc != 0)
  3514. goto nvram_write_end;
  3515. cmd_flags = 0;
  3516. }
  3517. }
  3518. /* Disable writes to flash interface (lock write-protect) */
  3519. bnx2_disable_nvram_write(bp);
  3520. /* Disable access to flash interface */
  3521. bnx2_disable_nvram_access(bp);
  3522. bnx2_release_nvram_lock(bp);
  3523. /* Increment written */
  3524. written += data_end - data_start;
  3525. }
  3526. nvram_write_end:
  3527. kfree(flash_buffer);
  3528. kfree(align_buf);
  3529. return rc;
  3530. }
  3531. static void
  3532. bnx2_init_fw_cap(struct bnx2 *bp)
  3533. {
  3534. u32 val, sig = 0;
  3535. bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
  3536. bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
  3537. if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
  3538. bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
  3539. val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
  3540. if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
  3541. return;
  3542. if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
  3543. bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
  3544. sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
  3545. }
  3546. if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
  3547. (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
  3548. u32 link;
  3549. bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
  3550. link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
  3551. if (link & BNX2_LINK_STATUS_SERDES_LINK)
  3552. bp->phy_port = PORT_FIBRE;
  3553. else
  3554. bp->phy_port = PORT_TP;
  3555. sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
  3556. BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
  3557. }
  3558. if (netif_running(bp->dev) && sig)
  3559. bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
  3560. }
  3561. static void
  3562. bnx2_setup_msix_tbl(struct bnx2 *bp)
  3563. {
  3564. REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
  3565. REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
  3566. REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
  3567. }
  3568. static int
  3569. bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
  3570. {
  3571. u32 val;
  3572. int i, rc = 0;
  3573. u8 old_port;
  3574. /* Wait for the current PCI transaction to complete before
  3575. * issuing a reset. */
  3576. REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
  3577. BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
  3578. BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
  3579. BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
  3580. BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
  3581. val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
  3582. udelay(5);
  3583. /* Wait for the firmware to tell us it is ok to issue a reset. */
  3584. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
  3585. /* Deposit a driver reset signature so the firmware knows that
  3586. * this is a soft reset. */
  3587. bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
  3588. BNX2_DRV_RESET_SIGNATURE_MAGIC);
  3589. /* Do a dummy read to force the chip to complete all current transaction
  3590. * before we issue a reset. */
  3591. val = REG_RD(bp, BNX2_MISC_ID);
  3592. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3593. REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
  3594. REG_RD(bp, BNX2_MISC_COMMAND);
  3595. udelay(5);
  3596. val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  3597. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  3598. pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
  3599. } else {
  3600. val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3601. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  3602. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  3603. /* Chip reset. */
  3604. REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
  3605. /* Reading back any register after chip reset will hang the
  3606. * bus on 5706 A0 and A1. The msleep below provides plenty
  3607. * of margin for write posting.
  3608. */
  3609. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  3610. (CHIP_ID(bp) == CHIP_ID_5706_A1))
  3611. msleep(20);
  3612. /* Reset takes approximate 30 usec */
  3613. for (i = 0; i < 10; i++) {
  3614. val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
  3615. if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3616. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
  3617. break;
  3618. udelay(10);
  3619. }
  3620. if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  3621. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
  3622. printk(KERN_ERR PFX "Chip reset did not complete\n");
  3623. return -EBUSY;
  3624. }
  3625. }
  3626. /* Make sure byte swapping is properly configured. */
  3627. val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
  3628. if (val != 0x01020304) {
  3629. printk(KERN_ERR PFX "Chip not in correct endian mode\n");
  3630. return -ENODEV;
  3631. }
  3632. /* Wait for the firmware to finish its initialization. */
  3633. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
  3634. if (rc)
  3635. return rc;
  3636. spin_lock_bh(&bp->phy_lock);
  3637. old_port = bp->phy_port;
  3638. bnx2_init_fw_cap(bp);
  3639. if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
  3640. old_port != bp->phy_port)
  3641. bnx2_set_default_remote_link(bp);
  3642. spin_unlock_bh(&bp->phy_lock);
  3643. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  3644. /* Adjust the voltage regular to two steps lower. The default
  3645. * of this register is 0x0000000e. */
  3646. REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
  3647. /* Remove bad rbuf memory from the free pool. */
  3648. rc = bnx2_alloc_bad_rbuf(bp);
  3649. }
  3650. if (bp->flags & BNX2_FLAG_USING_MSIX)
  3651. bnx2_setup_msix_tbl(bp);
  3652. return rc;
  3653. }
  3654. static int
  3655. bnx2_init_chip(struct bnx2 *bp)
  3656. {
  3657. u32 val;
  3658. int rc, i;
  3659. /* Make sure the interrupt is not active. */
  3660. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3661. val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
  3662. BNX2_DMA_CONFIG_DATA_WORD_SWAP |
  3663. #ifdef __BIG_ENDIAN
  3664. BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
  3665. #endif
  3666. BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
  3667. DMA_READ_CHANS << 12 |
  3668. DMA_WRITE_CHANS << 16;
  3669. val |= (0x2 << 20) | (1 << 11);
  3670. if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
  3671. val |= (1 << 23);
  3672. if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
  3673. (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
  3674. val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
  3675. REG_WR(bp, BNX2_DMA_CONFIG, val);
  3676. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  3677. val = REG_RD(bp, BNX2_TDMA_CONFIG);
  3678. val |= BNX2_TDMA_CONFIG_ONE_DMA;
  3679. REG_WR(bp, BNX2_TDMA_CONFIG, val);
  3680. }
  3681. if (bp->flags & BNX2_FLAG_PCIX) {
  3682. u16 val16;
  3683. pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  3684. &val16);
  3685. pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  3686. val16 & ~PCI_X_CMD_ERO);
  3687. }
  3688. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  3689. BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
  3690. BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
  3691. BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
  3692. /* Initialize context mapping and zero out the quick contexts. The
  3693. * context block must have already been enabled. */
  3694. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3695. rc = bnx2_init_5709_context(bp);
  3696. if (rc)
  3697. return rc;
  3698. } else
  3699. bnx2_init_context(bp);
  3700. if ((rc = bnx2_init_cpus(bp)) != 0)
  3701. return rc;
  3702. bnx2_init_nvram(bp);
  3703. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  3704. val = REG_RD(bp, BNX2_MQ_CONFIG);
  3705. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3706. val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
  3707. if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
  3708. val |= BNX2_MQ_CONFIG_HALT_DIS;
  3709. REG_WR(bp, BNX2_MQ_CONFIG, val);
  3710. val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
  3711. REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
  3712. REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
  3713. val = (BCM_PAGE_BITS - 8) << 24;
  3714. REG_WR(bp, BNX2_RV2P_CONFIG, val);
  3715. /* Configure page size. */
  3716. val = REG_RD(bp, BNX2_TBDR_CONFIG);
  3717. val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
  3718. val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
  3719. REG_WR(bp, BNX2_TBDR_CONFIG, val);
  3720. val = bp->mac_addr[0] +
  3721. (bp->mac_addr[1] << 8) +
  3722. (bp->mac_addr[2] << 16) +
  3723. bp->mac_addr[3] +
  3724. (bp->mac_addr[4] << 8) +
  3725. (bp->mac_addr[5] << 16);
  3726. REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
  3727. /* Program the MTU. Also include 4 bytes for CRC32. */
  3728. val = bp->dev->mtu + ETH_HLEN + 4;
  3729. if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
  3730. val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
  3731. REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
  3732. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
  3733. bp->bnx2_napi[i].last_status_idx = 0;
  3734. bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
  3735. /* Set up how to generate a link change interrupt. */
  3736. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  3737. REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
  3738. (u64) bp->status_blk_mapping & 0xffffffff);
  3739. REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
  3740. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
  3741. (u64) bp->stats_blk_mapping & 0xffffffff);
  3742. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
  3743. (u64) bp->stats_blk_mapping >> 32);
  3744. REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
  3745. (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
  3746. REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
  3747. (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
  3748. REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
  3749. (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
  3750. REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
  3751. REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
  3752. REG_WR(bp, BNX2_HC_COM_TICKS,
  3753. (bp->com_ticks_int << 16) | bp->com_ticks);
  3754. REG_WR(bp, BNX2_HC_CMD_TICKS,
  3755. (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
  3756. if (CHIP_NUM(bp) == CHIP_NUM_5708)
  3757. REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
  3758. else
  3759. REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
  3760. REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
  3761. if (CHIP_ID(bp) == CHIP_ID_5706_A1)
  3762. val = BNX2_HC_CONFIG_COLLECT_STATS;
  3763. else {
  3764. val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
  3765. BNX2_HC_CONFIG_COLLECT_STATS;
  3766. }
  3767. if (bp->irq_nvecs > 1) {
  3768. REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
  3769. BNX2_HC_MSIX_BIT_VECTOR_VAL);
  3770. val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
  3771. }
  3772. if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
  3773. val |= BNX2_HC_CONFIG_ONE_SHOT;
  3774. REG_WR(bp, BNX2_HC_CONFIG, val);
  3775. for (i = 1; i < bp->irq_nvecs; i++) {
  3776. u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3777. BNX2_HC_SB_CONFIG_1;
  3778. REG_WR(bp, base,
  3779. BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
  3780. BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
  3781. BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3782. REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
  3783. (bp->tx_quick_cons_trip_int << 16) |
  3784. bp->tx_quick_cons_trip);
  3785. REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
  3786. (bp->tx_ticks_int << 16) | bp->tx_ticks);
  3787. REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
  3788. (bp->rx_quick_cons_trip_int << 16) |
  3789. bp->rx_quick_cons_trip);
  3790. REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
  3791. (bp->rx_ticks_int << 16) | bp->rx_ticks);
  3792. }
  3793. /* Clear internal stats counters. */
  3794. REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
  3795. REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
  3796. /* Initialize the receive filter. */
  3797. bnx2_set_rx_mode(bp->dev);
  3798. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3799. val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
  3800. val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
  3801. REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
  3802. }
  3803. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
  3804. 1, 0);
  3805. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
  3806. REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
  3807. udelay(20);
  3808. bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
  3809. return rc;
  3810. }
  3811. static void
  3812. bnx2_clear_ring_states(struct bnx2 *bp)
  3813. {
  3814. struct bnx2_napi *bnapi;
  3815. struct bnx2_tx_ring_info *txr;
  3816. struct bnx2_rx_ring_info *rxr;
  3817. int i;
  3818. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
  3819. bnapi = &bp->bnx2_napi[i];
  3820. txr = &bnapi->tx_ring;
  3821. rxr = &bnapi->rx_ring;
  3822. txr->tx_cons = 0;
  3823. txr->hw_tx_cons = 0;
  3824. rxr->rx_prod_bseq = 0;
  3825. rxr->rx_prod = 0;
  3826. rxr->rx_cons = 0;
  3827. rxr->rx_pg_prod = 0;
  3828. rxr->rx_pg_cons = 0;
  3829. }
  3830. }
  3831. static void
  3832. bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
  3833. {
  3834. u32 val, offset0, offset1, offset2, offset3;
  3835. u32 cid_addr = GET_CID_ADDR(cid);
  3836. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3837. offset0 = BNX2_L2CTX_TYPE_XI;
  3838. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3839. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3840. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3841. } else {
  3842. offset0 = BNX2_L2CTX_TYPE;
  3843. offset1 = BNX2_L2CTX_CMD_TYPE;
  3844. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3845. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3846. }
  3847. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3848. bnx2_ctx_wr(bp, cid_addr, offset0, val);
  3849. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3850. bnx2_ctx_wr(bp, cid_addr, offset1, val);
  3851. val = (u64) txr->tx_desc_mapping >> 32;
  3852. bnx2_ctx_wr(bp, cid_addr, offset2, val);
  3853. val = (u64) txr->tx_desc_mapping & 0xffffffff;
  3854. bnx2_ctx_wr(bp, cid_addr, offset3, val);
  3855. }
  3856. static void
  3857. bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
  3858. {
  3859. struct tx_bd *txbd;
  3860. u32 cid = TX_CID;
  3861. struct bnx2_napi *bnapi;
  3862. struct bnx2_tx_ring_info *txr;
  3863. bnapi = &bp->bnx2_napi[ring_num];
  3864. txr = &bnapi->tx_ring;
  3865. if (ring_num == 0)
  3866. cid = TX_CID;
  3867. else
  3868. cid = TX_TSS_CID + ring_num - 1;
  3869. bp->tx_wake_thresh = bp->tx_ring_size / 2;
  3870. txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
  3871. txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
  3872. txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
  3873. txr->tx_prod = 0;
  3874. txr->tx_prod_bseq = 0;
  3875. txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
  3876. txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
  3877. bnx2_init_tx_context(bp, cid, txr);
  3878. }
  3879. static void
  3880. bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
  3881. int num_rings)
  3882. {
  3883. int i;
  3884. struct rx_bd *rxbd;
  3885. for (i = 0; i < num_rings; i++) {
  3886. int j;
  3887. rxbd = &rx_ring[i][0];
  3888. for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
  3889. rxbd->rx_bd_len = buf_size;
  3890. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3891. }
  3892. if (i == (num_rings - 1))
  3893. j = 0;
  3894. else
  3895. j = i + 1;
  3896. rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
  3897. rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
  3898. }
  3899. }
  3900. static void
  3901. bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
  3902. {
  3903. int i;
  3904. u16 prod, ring_prod;
  3905. u32 cid, rx_cid_addr, val;
  3906. struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
  3907. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  3908. if (ring_num == 0)
  3909. cid = RX_CID;
  3910. else
  3911. cid = RX_RSS_CID + ring_num - 1;
  3912. rx_cid_addr = GET_CID_ADDR(cid);
  3913. bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
  3914. bp->rx_buf_use_size, bp->rx_max_ring);
  3915. bnx2_init_rx_context(bp, cid);
  3916. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  3917. val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
  3918. REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
  3919. }
  3920. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
  3921. if (bp->rx_pg_ring_size) {
  3922. bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
  3923. rxr->rx_pg_desc_mapping,
  3924. PAGE_SIZE, bp->rx_max_pg_ring);
  3925. val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
  3926. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
  3927. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
  3928. BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
  3929. val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
  3930. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
  3931. val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
  3932. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
  3933. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  3934. REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
  3935. }
  3936. val = (u64) rxr->rx_desc_mapping[0] >> 32;
  3937. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3938. val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
  3939. bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3940. ring_prod = prod = rxr->rx_pg_prod;
  3941. for (i = 0; i < bp->rx_pg_ring_size; i++) {
  3942. if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
  3943. break;
  3944. prod = NEXT_RX_BD(prod);
  3945. ring_prod = RX_PG_RING_IDX(prod);
  3946. }
  3947. rxr->rx_pg_prod = prod;
  3948. ring_prod = prod = rxr->rx_prod;
  3949. for (i = 0; i < bp->rx_ring_size; i++) {
  3950. if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
  3951. break;
  3952. prod = NEXT_RX_BD(prod);
  3953. ring_prod = RX_RING_IDX(prod);
  3954. }
  3955. rxr->rx_prod = prod;
  3956. rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
  3957. rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
  3958. rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
  3959. REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
  3960. REG_WR16(bp, rxr->rx_bidx_addr, prod);
  3961. REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
  3962. }
  3963. static void
  3964. bnx2_init_all_rings(struct bnx2 *bp)
  3965. {
  3966. int i;
  3967. u32 val;
  3968. bnx2_clear_ring_states(bp);
  3969. REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
  3970. for (i = 0; i < bp->num_tx_rings; i++)
  3971. bnx2_init_tx_ring(bp, i);
  3972. if (bp->num_tx_rings > 1)
  3973. REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
  3974. (TX_TSS_CID << 7));
  3975. REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
  3976. bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
  3977. for (i = 0; i < bp->num_rx_rings; i++)
  3978. bnx2_init_rx_ring(bp, i);
  3979. if (bp->num_rx_rings > 1) {
  3980. u32 tbl_32;
  3981. u8 *tbl = (u8 *) &tbl_32;
  3982. bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
  3983. BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
  3984. for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
  3985. tbl[i % 4] = i % (bp->num_rx_rings - 1);
  3986. if ((i % 4) == 3)
  3987. bnx2_reg_wr_ind(bp,
  3988. BNX2_RXP_SCRATCH_RSS_TBL + i,
  3989. cpu_to_be32(tbl_32));
  3990. }
  3991. val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
  3992. BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
  3993. REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
  3994. }
  3995. }
  3996. static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
  3997. {
  3998. u32 max, num_rings = 1;
  3999. while (ring_size > MAX_RX_DESC_CNT) {
  4000. ring_size -= MAX_RX_DESC_CNT;
  4001. num_rings++;
  4002. }
  4003. /* round to next power of 2 */
  4004. max = max_size;
  4005. while ((max & num_rings) == 0)
  4006. max >>= 1;
  4007. if (num_rings != max)
  4008. max <<= 1;
  4009. return max;
  4010. }
  4011. static void
  4012. bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
  4013. {
  4014. u32 rx_size, rx_space, jumbo_size;
  4015. /* 8 for CRC and VLAN */
  4016. rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
  4017. rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
  4018. sizeof(struct skb_shared_info);
  4019. bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
  4020. bp->rx_pg_ring_size = 0;
  4021. bp->rx_max_pg_ring = 0;
  4022. bp->rx_max_pg_ring_idx = 0;
  4023. if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
  4024. int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
  4025. jumbo_size = size * pages;
  4026. if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
  4027. jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
  4028. bp->rx_pg_ring_size = jumbo_size;
  4029. bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
  4030. MAX_RX_PG_RINGS);
  4031. bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
  4032. rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
  4033. bp->rx_copy_thresh = 0;
  4034. }
  4035. bp->rx_buf_use_size = rx_size;
  4036. /* hw alignment */
  4037. bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
  4038. bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
  4039. bp->rx_ring_size = size;
  4040. bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
  4041. bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
  4042. }
  4043. static void
  4044. bnx2_free_tx_skbs(struct bnx2 *bp)
  4045. {
  4046. int i;
  4047. for (i = 0; i < bp->num_tx_rings; i++) {
  4048. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  4049. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  4050. int j;
  4051. if (txr->tx_buf_ring == NULL)
  4052. continue;
  4053. for (j = 0; j < TX_DESC_CNT; ) {
  4054. struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
  4055. struct sk_buff *skb = tx_buf->skb;
  4056. int k, last;
  4057. if (skb == NULL) {
  4058. j++;
  4059. continue;
  4060. }
  4061. pci_unmap_single(bp->pdev,
  4062. pci_unmap_addr(tx_buf, mapping),
  4063. skb_headlen(skb), PCI_DMA_TODEVICE);
  4064. tx_buf->skb = NULL;
  4065. last = skb_shinfo(skb)->nr_frags;
  4066. for (k = 0; k < last; k++) {
  4067. tx_buf = &txr->tx_buf_ring[j + k + 1];
  4068. pci_unmap_page(bp->pdev,
  4069. pci_unmap_addr(tx_buf, mapping),
  4070. skb_shinfo(skb)->frags[j].size,
  4071. PCI_DMA_TODEVICE);
  4072. }
  4073. dev_kfree_skb(skb);
  4074. j += k + 1;
  4075. }
  4076. }
  4077. }
  4078. static void
  4079. bnx2_free_rx_skbs(struct bnx2 *bp)
  4080. {
  4081. int i;
  4082. for (i = 0; i < bp->num_rx_rings; i++) {
  4083. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  4084. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  4085. int j;
  4086. if (rxr->rx_buf_ring == NULL)
  4087. return;
  4088. for (j = 0; j < bp->rx_max_ring_idx; j++) {
  4089. struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
  4090. struct sk_buff *skb = rx_buf->skb;
  4091. if (skb == NULL)
  4092. continue;
  4093. pci_unmap_single(bp->pdev,
  4094. pci_unmap_addr(rx_buf, mapping),
  4095. bp->rx_buf_use_size,
  4096. PCI_DMA_FROMDEVICE);
  4097. rx_buf->skb = NULL;
  4098. dev_kfree_skb(skb);
  4099. }
  4100. for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
  4101. bnx2_free_rx_page(bp, rxr, j);
  4102. }
  4103. }
  4104. static void
  4105. bnx2_free_skbs(struct bnx2 *bp)
  4106. {
  4107. bnx2_free_tx_skbs(bp);
  4108. bnx2_free_rx_skbs(bp);
  4109. }
  4110. static int
  4111. bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
  4112. {
  4113. int rc;
  4114. rc = bnx2_reset_chip(bp, reset_code);
  4115. bnx2_free_skbs(bp);
  4116. if (rc)
  4117. return rc;
  4118. if ((rc = bnx2_init_chip(bp)) != 0)
  4119. return rc;
  4120. bnx2_init_all_rings(bp);
  4121. return 0;
  4122. }
  4123. static int
  4124. bnx2_init_nic(struct bnx2 *bp, int reset_phy)
  4125. {
  4126. int rc;
  4127. if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
  4128. return rc;
  4129. spin_lock_bh(&bp->phy_lock);
  4130. bnx2_init_phy(bp, reset_phy);
  4131. bnx2_set_link(bp);
  4132. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4133. bnx2_remote_phy_event(bp);
  4134. spin_unlock_bh(&bp->phy_lock);
  4135. return 0;
  4136. }
  4137. static int
  4138. bnx2_test_registers(struct bnx2 *bp)
  4139. {
  4140. int ret;
  4141. int i, is_5709;
  4142. static const struct {
  4143. u16 offset;
  4144. u16 flags;
  4145. #define BNX2_FL_NOT_5709 1
  4146. u32 rw_mask;
  4147. u32 ro_mask;
  4148. } reg_tbl[] = {
  4149. { 0x006c, 0, 0x00000000, 0x0000003f },
  4150. { 0x0090, 0, 0xffffffff, 0x00000000 },
  4151. { 0x0094, 0, 0x00000000, 0x00000000 },
  4152. { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
  4153. { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4154. { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4155. { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
  4156. { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
  4157. { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
  4158. { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
  4159. { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4160. { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4161. { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4162. { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
  4163. { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4164. { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4165. { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4166. { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
  4167. { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
  4168. { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
  4169. { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
  4170. { 0x1000, 0, 0x00000000, 0x00000001 },
  4171. { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
  4172. { 0x1408, 0, 0x01c00800, 0x00000000 },
  4173. { 0x149c, 0, 0x8000ffff, 0x00000000 },
  4174. { 0x14a8, 0, 0x00000000, 0x000001ff },
  4175. { 0x14ac, 0, 0x0fffffff, 0x10000000 },
  4176. { 0x14b0, 0, 0x00000002, 0x00000001 },
  4177. { 0x14b8, 0, 0x00000000, 0x00000000 },
  4178. { 0x14c0, 0, 0x00000000, 0x00000009 },
  4179. { 0x14c4, 0, 0x00003fff, 0x00000000 },
  4180. { 0x14cc, 0, 0x00000000, 0x00000001 },
  4181. { 0x14d0, 0, 0xffffffff, 0x00000000 },
  4182. { 0x1800, 0, 0x00000000, 0x00000001 },
  4183. { 0x1804, 0, 0x00000000, 0x00000003 },
  4184. { 0x2800, 0, 0x00000000, 0x00000001 },
  4185. { 0x2804, 0, 0x00000000, 0x00003f01 },
  4186. { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
  4187. { 0x2810, 0, 0xffff0000, 0x00000000 },
  4188. { 0x2814, 0, 0xffff0000, 0x00000000 },
  4189. { 0x2818, 0, 0xffff0000, 0x00000000 },
  4190. { 0x281c, 0, 0xffff0000, 0x00000000 },
  4191. { 0x2834, 0, 0xffffffff, 0x00000000 },
  4192. { 0x2840, 0, 0x00000000, 0xffffffff },
  4193. { 0x2844, 0, 0x00000000, 0xffffffff },
  4194. { 0x2848, 0, 0xffffffff, 0x00000000 },
  4195. { 0x284c, 0, 0xf800f800, 0x07ff07ff },
  4196. { 0x2c00, 0, 0x00000000, 0x00000011 },
  4197. { 0x2c04, 0, 0x00000000, 0x00030007 },
  4198. { 0x3c00, 0, 0x00000000, 0x00000001 },
  4199. { 0x3c04, 0, 0x00000000, 0x00070000 },
  4200. { 0x3c08, 0, 0x00007f71, 0x07f00000 },
  4201. { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
  4202. { 0x3c10, 0, 0xffffffff, 0x00000000 },
  4203. { 0x3c14, 0, 0x00000000, 0xffffffff },
  4204. { 0x3c18, 0, 0x00000000, 0xffffffff },
  4205. { 0x3c1c, 0, 0xfffff000, 0x00000000 },
  4206. { 0x3c20, 0, 0xffffff00, 0x00000000 },
  4207. { 0x5004, 0, 0x00000000, 0x0000007f },
  4208. { 0x5008, 0, 0x0f0007ff, 0x00000000 },
  4209. { 0x5c00, 0, 0x00000000, 0x00000001 },
  4210. { 0x5c04, 0, 0x00000000, 0x0003000f },
  4211. { 0x5c08, 0, 0x00000003, 0x00000000 },
  4212. { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
  4213. { 0x5c10, 0, 0x00000000, 0xffffffff },
  4214. { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
  4215. { 0x5c84, 0, 0x00000000, 0x0000f333 },
  4216. { 0x5c88, 0, 0x00000000, 0x00077373 },
  4217. { 0x5c8c, 0, 0x00000000, 0x0007f737 },
  4218. { 0x6808, 0, 0x0000ff7f, 0x00000000 },
  4219. { 0x680c, 0, 0xffffffff, 0x00000000 },
  4220. { 0x6810, 0, 0xffffffff, 0x00000000 },
  4221. { 0x6814, 0, 0xffffffff, 0x00000000 },
  4222. { 0x6818, 0, 0xffffffff, 0x00000000 },
  4223. { 0x681c, 0, 0xffffffff, 0x00000000 },
  4224. { 0x6820, 0, 0x00ff00ff, 0x00000000 },
  4225. { 0x6824, 0, 0x00ff00ff, 0x00000000 },
  4226. { 0x6828, 0, 0x00ff00ff, 0x00000000 },
  4227. { 0x682c, 0, 0x03ff03ff, 0x00000000 },
  4228. { 0x6830, 0, 0x03ff03ff, 0x00000000 },
  4229. { 0x6834, 0, 0x03ff03ff, 0x00000000 },
  4230. { 0x6838, 0, 0x03ff03ff, 0x00000000 },
  4231. { 0x683c, 0, 0x0000ffff, 0x00000000 },
  4232. { 0x6840, 0, 0x00000ff0, 0x00000000 },
  4233. { 0x6844, 0, 0x00ffff00, 0x00000000 },
  4234. { 0x684c, 0, 0xffffffff, 0x00000000 },
  4235. { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
  4236. { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
  4237. { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
  4238. { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
  4239. { 0x6908, 0, 0x00000000, 0x0001ff0f },
  4240. { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
  4241. { 0xffff, 0, 0x00000000, 0x00000000 },
  4242. };
  4243. ret = 0;
  4244. is_5709 = 0;
  4245. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  4246. is_5709 = 1;
  4247. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  4248. u32 offset, rw_mask, ro_mask, save_val, val;
  4249. u16 flags = reg_tbl[i].flags;
  4250. if (is_5709 && (flags & BNX2_FL_NOT_5709))
  4251. continue;
  4252. offset = (u32) reg_tbl[i].offset;
  4253. rw_mask = reg_tbl[i].rw_mask;
  4254. ro_mask = reg_tbl[i].ro_mask;
  4255. save_val = readl(bp->regview + offset);
  4256. writel(0, bp->regview + offset);
  4257. val = readl(bp->regview + offset);
  4258. if ((val & rw_mask) != 0) {
  4259. goto reg_test_err;
  4260. }
  4261. if ((val & ro_mask) != (save_val & ro_mask)) {
  4262. goto reg_test_err;
  4263. }
  4264. writel(0xffffffff, bp->regview + offset);
  4265. val = readl(bp->regview + offset);
  4266. if ((val & rw_mask) != rw_mask) {
  4267. goto reg_test_err;
  4268. }
  4269. if ((val & ro_mask) != (save_val & ro_mask)) {
  4270. goto reg_test_err;
  4271. }
  4272. writel(save_val, bp->regview + offset);
  4273. continue;
  4274. reg_test_err:
  4275. writel(save_val, bp->regview + offset);
  4276. ret = -ENODEV;
  4277. break;
  4278. }
  4279. return ret;
  4280. }
  4281. static int
  4282. bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
  4283. {
  4284. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
  4285. 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
  4286. int i;
  4287. for (i = 0; i < sizeof(test_pattern) / 4; i++) {
  4288. u32 offset;
  4289. for (offset = 0; offset < size; offset += 4) {
  4290. bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
  4291. if (bnx2_reg_rd_ind(bp, start + offset) !=
  4292. test_pattern[i]) {
  4293. return -ENODEV;
  4294. }
  4295. }
  4296. }
  4297. return 0;
  4298. }
  4299. static int
  4300. bnx2_test_memory(struct bnx2 *bp)
  4301. {
  4302. int ret = 0;
  4303. int i;
  4304. static struct mem_entry {
  4305. u32 offset;
  4306. u32 len;
  4307. } mem_tbl_5706[] = {
  4308. { 0x60000, 0x4000 },
  4309. { 0xa0000, 0x3000 },
  4310. { 0xe0000, 0x4000 },
  4311. { 0x120000, 0x4000 },
  4312. { 0x1a0000, 0x4000 },
  4313. { 0x160000, 0x4000 },
  4314. { 0xffffffff, 0 },
  4315. },
  4316. mem_tbl_5709[] = {
  4317. { 0x60000, 0x4000 },
  4318. { 0xa0000, 0x3000 },
  4319. { 0xe0000, 0x4000 },
  4320. { 0x120000, 0x4000 },
  4321. { 0x1a0000, 0x4000 },
  4322. { 0xffffffff, 0 },
  4323. };
  4324. struct mem_entry *mem_tbl;
  4325. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  4326. mem_tbl = mem_tbl_5709;
  4327. else
  4328. mem_tbl = mem_tbl_5706;
  4329. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  4330. if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
  4331. mem_tbl[i].len)) != 0) {
  4332. return ret;
  4333. }
  4334. }
  4335. return ret;
  4336. }
  4337. #define BNX2_MAC_LOOPBACK 0
  4338. #define BNX2_PHY_LOOPBACK 1
  4339. static int
  4340. bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
  4341. {
  4342. unsigned int pkt_size, num_pkts, i;
  4343. struct sk_buff *skb, *rx_skb;
  4344. unsigned char *packet;
  4345. u16 rx_start_idx, rx_idx;
  4346. dma_addr_t map;
  4347. struct tx_bd *txbd;
  4348. struct sw_bd *rx_buf;
  4349. struct l2_fhdr *rx_hdr;
  4350. int ret = -ENODEV;
  4351. struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
  4352. struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
  4353. struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
  4354. tx_napi = bnapi;
  4355. txr = &tx_napi->tx_ring;
  4356. rxr = &bnapi->rx_ring;
  4357. if (loopback_mode == BNX2_MAC_LOOPBACK) {
  4358. bp->loopback = MAC_LOOPBACK;
  4359. bnx2_set_mac_loopback(bp);
  4360. }
  4361. else if (loopback_mode == BNX2_PHY_LOOPBACK) {
  4362. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4363. return 0;
  4364. bp->loopback = PHY_LOOPBACK;
  4365. bnx2_set_phy_loopback(bp);
  4366. }
  4367. else
  4368. return -EINVAL;
  4369. pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
  4370. skb = netdev_alloc_skb(bp->dev, pkt_size);
  4371. if (!skb)
  4372. return -ENOMEM;
  4373. packet = skb_put(skb, pkt_size);
  4374. memcpy(packet, bp->dev->dev_addr, 6);
  4375. memset(packet + 6, 0x0, 8);
  4376. for (i = 14; i < pkt_size; i++)
  4377. packet[i] = (unsigned char) (i & 0xff);
  4378. map = pci_map_single(bp->pdev, skb->data, pkt_size,
  4379. PCI_DMA_TODEVICE);
  4380. REG_WR(bp, BNX2_HC_COMMAND,
  4381. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  4382. REG_RD(bp, BNX2_HC_COMMAND);
  4383. udelay(5);
  4384. rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
  4385. num_pkts = 0;
  4386. txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
  4387. txbd->tx_bd_haddr_hi = (u64) map >> 32;
  4388. txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
  4389. txbd->tx_bd_mss_nbytes = pkt_size;
  4390. txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
  4391. num_pkts++;
  4392. txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
  4393. txr->tx_prod_bseq += pkt_size;
  4394. REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
  4395. REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
  4396. udelay(100);
  4397. REG_WR(bp, BNX2_HC_COMMAND,
  4398. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  4399. REG_RD(bp, BNX2_HC_COMMAND);
  4400. udelay(5);
  4401. pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
  4402. dev_kfree_skb(skb);
  4403. if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
  4404. goto loopback_test_done;
  4405. rx_idx = bnx2_get_hw_rx_cons(bnapi);
  4406. if (rx_idx != rx_start_idx + num_pkts) {
  4407. goto loopback_test_done;
  4408. }
  4409. rx_buf = &rxr->rx_buf_ring[rx_start_idx];
  4410. rx_skb = rx_buf->skb;
  4411. rx_hdr = (struct l2_fhdr *) rx_skb->data;
  4412. skb_reserve(rx_skb, BNX2_RX_OFFSET);
  4413. pci_dma_sync_single_for_cpu(bp->pdev,
  4414. pci_unmap_addr(rx_buf, mapping),
  4415. bp->rx_buf_size, PCI_DMA_FROMDEVICE);
  4416. if (rx_hdr->l2_fhdr_status &
  4417. (L2_FHDR_ERRORS_BAD_CRC |
  4418. L2_FHDR_ERRORS_PHY_DECODE |
  4419. L2_FHDR_ERRORS_ALIGNMENT |
  4420. L2_FHDR_ERRORS_TOO_SHORT |
  4421. L2_FHDR_ERRORS_GIANT_FRAME)) {
  4422. goto loopback_test_done;
  4423. }
  4424. if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
  4425. goto loopback_test_done;
  4426. }
  4427. for (i = 14; i < pkt_size; i++) {
  4428. if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
  4429. goto loopback_test_done;
  4430. }
  4431. }
  4432. ret = 0;
  4433. loopback_test_done:
  4434. bp->loopback = 0;
  4435. return ret;
  4436. }
  4437. #define BNX2_MAC_LOOPBACK_FAILED 1
  4438. #define BNX2_PHY_LOOPBACK_FAILED 2
  4439. #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
  4440. BNX2_PHY_LOOPBACK_FAILED)
  4441. static int
  4442. bnx2_test_loopback(struct bnx2 *bp)
  4443. {
  4444. int rc = 0;
  4445. if (!netif_running(bp->dev))
  4446. return BNX2_LOOPBACK_FAILED;
  4447. bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
  4448. spin_lock_bh(&bp->phy_lock);
  4449. bnx2_init_phy(bp, 1);
  4450. spin_unlock_bh(&bp->phy_lock);
  4451. if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
  4452. rc |= BNX2_MAC_LOOPBACK_FAILED;
  4453. if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
  4454. rc |= BNX2_PHY_LOOPBACK_FAILED;
  4455. return rc;
  4456. }
  4457. #define NVRAM_SIZE 0x200
  4458. #define CRC32_RESIDUAL 0xdebb20e3
  4459. static int
  4460. bnx2_test_nvram(struct bnx2 *bp)
  4461. {
  4462. __be32 buf[NVRAM_SIZE / 4];
  4463. u8 *data = (u8 *) buf;
  4464. int rc = 0;
  4465. u32 magic, csum;
  4466. if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
  4467. goto test_nvram_done;
  4468. magic = be32_to_cpu(buf[0]);
  4469. if (magic != 0x669955aa) {
  4470. rc = -ENODEV;
  4471. goto test_nvram_done;
  4472. }
  4473. if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
  4474. goto test_nvram_done;
  4475. csum = ether_crc_le(0x100, data);
  4476. if (csum != CRC32_RESIDUAL) {
  4477. rc = -ENODEV;
  4478. goto test_nvram_done;
  4479. }
  4480. csum = ether_crc_le(0x100, data + 0x100);
  4481. if (csum != CRC32_RESIDUAL) {
  4482. rc = -ENODEV;
  4483. }
  4484. test_nvram_done:
  4485. return rc;
  4486. }
  4487. static int
  4488. bnx2_test_link(struct bnx2 *bp)
  4489. {
  4490. u32 bmsr;
  4491. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  4492. if (bp->link_up)
  4493. return 0;
  4494. return -ENODEV;
  4495. }
  4496. spin_lock_bh(&bp->phy_lock);
  4497. bnx2_enable_bmsr1(bp);
  4498. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  4499. bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
  4500. bnx2_disable_bmsr1(bp);
  4501. spin_unlock_bh(&bp->phy_lock);
  4502. if (bmsr & BMSR_LSTATUS) {
  4503. return 0;
  4504. }
  4505. return -ENODEV;
  4506. }
  4507. static int
  4508. bnx2_test_intr(struct bnx2 *bp)
  4509. {
  4510. int i;
  4511. u16 status_idx;
  4512. if (!netif_running(bp->dev))
  4513. return -ENODEV;
  4514. status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
  4515. /* This register is not touched during run-time. */
  4516. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  4517. REG_RD(bp, BNX2_HC_COMMAND);
  4518. for (i = 0; i < 10; i++) {
  4519. if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
  4520. status_idx) {
  4521. break;
  4522. }
  4523. msleep_interruptible(10);
  4524. }
  4525. if (i < 10)
  4526. return 0;
  4527. return -ENODEV;
  4528. }
  4529. /* Determining link for parallel detection. */
  4530. static int
  4531. bnx2_5706_serdes_has_link(struct bnx2 *bp)
  4532. {
  4533. u32 mode_ctl, an_dbg, exp;
  4534. if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
  4535. return 0;
  4536. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
  4537. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
  4538. if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
  4539. return 0;
  4540. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  4541. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  4542. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
  4543. if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
  4544. return 0;
  4545. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
  4546. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
  4547. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
  4548. if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
  4549. return 0;
  4550. return 1;
  4551. }
  4552. static void
  4553. bnx2_5706_serdes_timer(struct bnx2 *bp)
  4554. {
  4555. int check_link = 1;
  4556. spin_lock(&bp->phy_lock);
  4557. if (bp->serdes_an_pending) {
  4558. bp->serdes_an_pending--;
  4559. check_link = 0;
  4560. } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  4561. u32 bmcr;
  4562. bp->current_interval = bp->timer_interval;
  4563. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  4564. if (bmcr & BMCR_ANENABLE) {
  4565. if (bnx2_5706_serdes_has_link(bp)) {
  4566. bmcr &= ~BMCR_ANENABLE;
  4567. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  4568. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  4569. bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
  4570. }
  4571. }
  4572. }
  4573. else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
  4574. (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
  4575. u32 phy2;
  4576. bnx2_write_phy(bp, 0x17, 0x0f01);
  4577. bnx2_read_phy(bp, 0x15, &phy2);
  4578. if (phy2 & 0x20) {
  4579. u32 bmcr;
  4580. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  4581. bmcr |= BMCR_ANENABLE;
  4582. bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
  4583. bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
  4584. }
  4585. } else
  4586. bp->current_interval = bp->timer_interval;
  4587. if (check_link) {
  4588. u32 val;
  4589. bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
  4590. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
  4591. bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
  4592. if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
  4593. if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
  4594. bnx2_5706s_force_link_dn(bp, 1);
  4595. bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
  4596. } else
  4597. bnx2_set_link(bp);
  4598. } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
  4599. bnx2_set_link(bp);
  4600. }
  4601. spin_unlock(&bp->phy_lock);
  4602. }
  4603. static void
  4604. bnx2_5708_serdes_timer(struct bnx2 *bp)
  4605. {
  4606. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  4607. return;
  4608. if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
  4609. bp->serdes_an_pending = 0;
  4610. return;
  4611. }
  4612. spin_lock(&bp->phy_lock);
  4613. if (bp->serdes_an_pending)
  4614. bp->serdes_an_pending--;
  4615. else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  4616. u32 bmcr;
  4617. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  4618. if (bmcr & BMCR_ANENABLE) {
  4619. bnx2_enable_forced_2g5(bp);
  4620. bp->current_interval = SERDES_FORCED_TIMEOUT;
  4621. } else {
  4622. bnx2_disable_forced_2g5(bp);
  4623. bp->serdes_an_pending = 2;
  4624. bp->current_interval = bp->timer_interval;
  4625. }
  4626. } else
  4627. bp->current_interval = bp->timer_interval;
  4628. spin_unlock(&bp->phy_lock);
  4629. }
  4630. static void
  4631. bnx2_timer(unsigned long data)
  4632. {
  4633. struct bnx2 *bp = (struct bnx2 *) data;
  4634. if (!netif_running(bp->dev))
  4635. return;
  4636. if (atomic_read(&bp->intr_sem) != 0)
  4637. goto bnx2_restart_timer;
  4638. bnx2_send_heart_beat(bp);
  4639. bp->stats_blk->stat_FwRxDrop =
  4640. bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
  4641. /* workaround occasional corrupted counters */
  4642. if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
  4643. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
  4644. BNX2_HC_COMMAND_STATS_NOW);
  4645. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  4646. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  4647. bnx2_5706_serdes_timer(bp);
  4648. else
  4649. bnx2_5708_serdes_timer(bp);
  4650. }
  4651. bnx2_restart_timer:
  4652. mod_timer(&bp->timer, jiffies + bp->current_interval);
  4653. }
  4654. static int
  4655. bnx2_request_irq(struct bnx2 *bp)
  4656. {
  4657. unsigned long flags;
  4658. struct bnx2_irq *irq;
  4659. int rc = 0, i;
  4660. if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
  4661. flags = 0;
  4662. else
  4663. flags = IRQF_SHARED;
  4664. for (i = 0; i < bp->irq_nvecs; i++) {
  4665. irq = &bp->irq_tbl[i];
  4666. rc = request_irq(irq->vector, irq->handler, flags, irq->name,
  4667. &bp->bnx2_napi[i]);
  4668. if (rc)
  4669. break;
  4670. irq->requested = 1;
  4671. }
  4672. return rc;
  4673. }
  4674. static void
  4675. bnx2_free_irq(struct bnx2 *bp)
  4676. {
  4677. struct bnx2_irq *irq;
  4678. int i;
  4679. for (i = 0; i < bp->irq_nvecs; i++) {
  4680. irq = &bp->irq_tbl[i];
  4681. if (irq->requested)
  4682. free_irq(irq->vector, &bp->bnx2_napi[i]);
  4683. irq->requested = 0;
  4684. }
  4685. if (bp->flags & BNX2_FLAG_USING_MSI)
  4686. pci_disable_msi(bp->pdev);
  4687. else if (bp->flags & BNX2_FLAG_USING_MSIX)
  4688. pci_disable_msix(bp->pdev);
  4689. bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
  4690. }
  4691. static void
  4692. bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
  4693. {
  4694. int i, rc;
  4695. struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
  4696. bnx2_setup_msix_tbl(bp);
  4697. REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
  4698. REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
  4699. REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
  4700. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
  4701. msix_ent[i].entry = i;
  4702. msix_ent[i].vector = 0;
  4703. strcpy(bp->irq_tbl[i].name, bp->dev->name);
  4704. bp->irq_tbl[i].handler = bnx2_msi_1shot;
  4705. }
  4706. rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
  4707. if (rc != 0)
  4708. return;
  4709. bp->irq_nvecs = msix_vecs;
  4710. bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
  4711. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
  4712. bp->irq_tbl[i].vector = msix_ent[i].vector;
  4713. }
  4714. static void
  4715. bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
  4716. {
  4717. int cpus = num_online_cpus();
  4718. int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
  4719. bp->irq_tbl[0].handler = bnx2_interrupt;
  4720. strcpy(bp->irq_tbl[0].name, bp->dev->name);
  4721. bp->irq_nvecs = 1;
  4722. bp->irq_tbl[0].vector = bp->pdev->irq;
  4723. if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
  4724. bnx2_enable_msix(bp, msix_vecs);
  4725. if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
  4726. !(bp->flags & BNX2_FLAG_USING_MSIX)) {
  4727. if (pci_enable_msi(bp->pdev) == 0) {
  4728. bp->flags |= BNX2_FLAG_USING_MSI;
  4729. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  4730. bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
  4731. bp->irq_tbl[0].handler = bnx2_msi_1shot;
  4732. } else
  4733. bp->irq_tbl[0].handler = bnx2_msi;
  4734. bp->irq_tbl[0].vector = bp->pdev->irq;
  4735. }
  4736. }
  4737. bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
  4738. bp->dev->real_num_tx_queues = bp->num_tx_rings;
  4739. bp->num_rx_rings = bp->irq_nvecs;
  4740. }
  4741. /* Called with rtnl_lock */
  4742. static int
  4743. bnx2_open(struct net_device *dev)
  4744. {
  4745. struct bnx2 *bp = netdev_priv(dev);
  4746. int rc;
  4747. netif_carrier_off(dev);
  4748. bnx2_set_power_state(bp, PCI_D0);
  4749. bnx2_disable_int(bp);
  4750. bnx2_setup_int_mode(bp, disable_msi);
  4751. bnx2_napi_enable(bp);
  4752. rc = bnx2_alloc_mem(bp);
  4753. if (rc)
  4754. goto open_err;
  4755. rc = bnx2_request_irq(bp);
  4756. if (rc)
  4757. goto open_err;
  4758. rc = bnx2_init_nic(bp, 1);
  4759. if (rc)
  4760. goto open_err;
  4761. mod_timer(&bp->timer, jiffies + bp->current_interval);
  4762. atomic_set(&bp->intr_sem, 0);
  4763. bnx2_enable_int(bp);
  4764. if (bp->flags & BNX2_FLAG_USING_MSI) {
  4765. /* Test MSI to make sure it is working
  4766. * If MSI test fails, go back to INTx mode
  4767. */
  4768. if (bnx2_test_intr(bp) != 0) {
  4769. printk(KERN_WARNING PFX "%s: No interrupt was generated"
  4770. " using MSI, switching to INTx mode. Please"
  4771. " report this failure to the PCI maintainer"
  4772. " and include system chipset information.\n",
  4773. bp->dev->name);
  4774. bnx2_disable_int(bp);
  4775. bnx2_free_irq(bp);
  4776. bnx2_setup_int_mode(bp, 1);
  4777. rc = bnx2_init_nic(bp, 0);
  4778. if (!rc)
  4779. rc = bnx2_request_irq(bp);
  4780. if (rc) {
  4781. del_timer_sync(&bp->timer);
  4782. goto open_err;
  4783. }
  4784. bnx2_enable_int(bp);
  4785. }
  4786. }
  4787. if (bp->flags & BNX2_FLAG_USING_MSI)
  4788. printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
  4789. else if (bp->flags & BNX2_FLAG_USING_MSIX)
  4790. printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
  4791. netif_tx_start_all_queues(dev);
  4792. return 0;
  4793. open_err:
  4794. bnx2_napi_disable(bp);
  4795. bnx2_free_skbs(bp);
  4796. bnx2_free_irq(bp);
  4797. bnx2_free_mem(bp);
  4798. return rc;
  4799. }
  4800. static void
  4801. bnx2_reset_task(struct work_struct *work)
  4802. {
  4803. struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
  4804. if (!netif_running(bp->dev))
  4805. return;
  4806. bnx2_netif_stop(bp);
  4807. bnx2_init_nic(bp, 1);
  4808. atomic_set(&bp->intr_sem, 1);
  4809. bnx2_netif_start(bp);
  4810. }
  4811. static void
  4812. bnx2_tx_timeout(struct net_device *dev)
  4813. {
  4814. struct bnx2 *bp = netdev_priv(dev);
  4815. /* This allows the netif to be shutdown gracefully before resetting */
  4816. schedule_work(&bp->reset_task);
  4817. }
  4818. #ifdef BCM_VLAN
  4819. /* Called with rtnl_lock */
  4820. static void
  4821. bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
  4822. {
  4823. struct bnx2 *bp = netdev_priv(dev);
  4824. bnx2_netif_stop(bp);
  4825. bp->vlgrp = vlgrp;
  4826. bnx2_set_rx_mode(dev);
  4827. if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
  4828. bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
  4829. bnx2_netif_start(bp);
  4830. }
  4831. #endif
  4832. /* Called with netif_tx_lock.
  4833. * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
  4834. * netif_wake_queue().
  4835. */
  4836. static int
  4837. bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
  4838. {
  4839. struct bnx2 *bp = netdev_priv(dev);
  4840. dma_addr_t mapping;
  4841. struct tx_bd *txbd;
  4842. struct sw_bd *tx_buf;
  4843. u32 len, vlan_tag_flags, last_frag, mss;
  4844. u16 prod, ring_prod;
  4845. int i;
  4846. struct bnx2_napi *bnapi;
  4847. struct bnx2_tx_ring_info *txr;
  4848. struct netdev_queue *txq;
  4849. /* Determine which tx ring we will be placed on */
  4850. i = skb_get_queue_mapping(skb);
  4851. bnapi = &bp->bnx2_napi[i];
  4852. txr = &bnapi->tx_ring;
  4853. txq = netdev_get_tx_queue(dev, i);
  4854. if (unlikely(bnx2_tx_avail(bp, txr) <
  4855. (skb_shinfo(skb)->nr_frags + 1))) {
  4856. netif_tx_stop_queue(txq);
  4857. printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
  4858. dev->name);
  4859. return NETDEV_TX_BUSY;
  4860. }
  4861. len = skb_headlen(skb);
  4862. prod = txr->tx_prod;
  4863. ring_prod = TX_RING_IDX(prod);
  4864. vlan_tag_flags = 0;
  4865. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  4866. vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
  4867. }
  4868. #ifdef BCM_VLAN
  4869. if (bp->vlgrp && vlan_tx_tag_present(skb)) {
  4870. vlan_tag_flags |=
  4871. (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
  4872. }
  4873. #endif
  4874. if ((mss = skb_shinfo(skb)->gso_size)) {
  4875. u32 tcp_opt_len, ip_tcp_len;
  4876. struct iphdr *iph;
  4877. vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
  4878. tcp_opt_len = tcp_optlen(skb);
  4879. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
  4880. u32 tcp_off = skb_transport_offset(skb) -
  4881. sizeof(struct ipv6hdr) - ETH_HLEN;
  4882. vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
  4883. TX_BD_FLAGS_SW_FLAGS;
  4884. if (likely(tcp_off == 0))
  4885. vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
  4886. else {
  4887. tcp_off >>= 3;
  4888. vlan_tag_flags |= ((tcp_off & 0x3) <<
  4889. TX_BD_FLAGS_TCP6_OFF0_SHL) |
  4890. ((tcp_off & 0x10) <<
  4891. TX_BD_FLAGS_TCP6_OFF4_SHL);
  4892. mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
  4893. }
  4894. } else {
  4895. if (skb_header_cloned(skb) &&
  4896. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  4897. dev_kfree_skb(skb);
  4898. return NETDEV_TX_OK;
  4899. }
  4900. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  4901. iph = ip_hdr(skb);
  4902. iph->check = 0;
  4903. iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  4904. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  4905. iph->daddr, 0,
  4906. IPPROTO_TCP,
  4907. 0);
  4908. if (tcp_opt_len || (iph->ihl > 5)) {
  4909. vlan_tag_flags |= ((iph->ihl - 5) +
  4910. (tcp_opt_len >> 2)) << 8;
  4911. }
  4912. }
  4913. } else
  4914. mss = 0;
  4915. mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  4916. tx_buf = &txr->tx_buf_ring[ring_prod];
  4917. tx_buf->skb = skb;
  4918. pci_unmap_addr_set(tx_buf, mapping, mapping);
  4919. txbd = &txr->tx_desc_ring[ring_prod];
  4920. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  4921. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  4922. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  4923. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
  4924. last_frag = skb_shinfo(skb)->nr_frags;
  4925. for (i = 0; i < last_frag; i++) {
  4926. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4927. prod = NEXT_TX_BD(prod);
  4928. ring_prod = TX_RING_IDX(prod);
  4929. txbd = &txr->tx_desc_ring[ring_prod];
  4930. len = frag->size;
  4931. mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
  4932. len, PCI_DMA_TODEVICE);
  4933. pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
  4934. mapping, mapping);
  4935. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  4936. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  4937. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  4938. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
  4939. }
  4940. txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
  4941. prod = NEXT_TX_BD(prod);
  4942. txr->tx_prod_bseq += skb->len;
  4943. REG_WR16(bp, txr->tx_bidx_addr, prod);
  4944. REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
  4945. mmiowb();
  4946. txr->tx_prod = prod;
  4947. dev->trans_start = jiffies;
  4948. if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
  4949. netif_tx_stop_queue(txq);
  4950. if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
  4951. netif_tx_wake_queue(txq);
  4952. }
  4953. return NETDEV_TX_OK;
  4954. }
  4955. /* Called with rtnl_lock */
  4956. static int
  4957. bnx2_close(struct net_device *dev)
  4958. {
  4959. struct bnx2 *bp = netdev_priv(dev);
  4960. u32 reset_code;
  4961. cancel_work_sync(&bp->reset_task);
  4962. bnx2_disable_int_sync(bp);
  4963. bnx2_napi_disable(bp);
  4964. del_timer_sync(&bp->timer);
  4965. if (bp->flags & BNX2_FLAG_NO_WOL)
  4966. reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
  4967. else if (bp->wol)
  4968. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  4969. else
  4970. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  4971. bnx2_reset_chip(bp, reset_code);
  4972. bnx2_free_irq(bp);
  4973. bnx2_free_skbs(bp);
  4974. bnx2_free_mem(bp);
  4975. bp->link_up = 0;
  4976. netif_carrier_off(bp->dev);
  4977. bnx2_set_power_state(bp, PCI_D3hot);
  4978. return 0;
  4979. }
  4980. #define GET_NET_STATS64(ctr) \
  4981. (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
  4982. (unsigned long) (ctr##_lo)
  4983. #define GET_NET_STATS32(ctr) \
  4984. (ctr##_lo)
  4985. #if (BITS_PER_LONG == 64)
  4986. #define GET_NET_STATS GET_NET_STATS64
  4987. #else
  4988. #define GET_NET_STATS GET_NET_STATS32
  4989. #endif
  4990. static struct net_device_stats *
  4991. bnx2_get_stats(struct net_device *dev)
  4992. {
  4993. struct bnx2 *bp = netdev_priv(dev);
  4994. struct statistics_block *stats_blk = bp->stats_blk;
  4995. struct net_device_stats *net_stats = &bp->net_stats;
  4996. if (bp->stats_blk == NULL) {
  4997. return net_stats;
  4998. }
  4999. net_stats->rx_packets =
  5000. GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
  5001. GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
  5002. GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
  5003. net_stats->tx_packets =
  5004. GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
  5005. GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
  5006. GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
  5007. net_stats->rx_bytes =
  5008. GET_NET_STATS(stats_blk->stat_IfHCInOctets);
  5009. net_stats->tx_bytes =
  5010. GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
  5011. net_stats->multicast =
  5012. GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
  5013. net_stats->collisions =
  5014. (unsigned long) stats_blk->stat_EtherStatsCollisions;
  5015. net_stats->rx_length_errors =
  5016. (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
  5017. stats_blk->stat_EtherStatsOverrsizePkts);
  5018. net_stats->rx_over_errors =
  5019. (unsigned long) stats_blk->stat_IfInMBUFDiscards;
  5020. net_stats->rx_frame_errors =
  5021. (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
  5022. net_stats->rx_crc_errors =
  5023. (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
  5024. net_stats->rx_errors = net_stats->rx_length_errors +
  5025. net_stats->rx_over_errors + net_stats->rx_frame_errors +
  5026. net_stats->rx_crc_errors;
  5027. net_stats->tx_aborted_errors =
  5028. (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
  5029. stats_blk->stat_Dot3StatsLateCollisions);
  5030. if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
  5031. (CHIP_ID(bp) == CHIP_ID_5708_A0))
  5032. net_stats->tx_carrier_errors = 0;
  5033. else {
  5034. net_stats->tx_carrier_errors =
  5035. (unsigned long)
  5036. stats_blk->stat_Dot3StatsCarrierSenseErrors;
  5037. }
  5038. net_stats->tx_errors =
  5039. (unsigned long)
  5040. stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
  5041. +
  5042. net_stats->tx_aborted_errors +
  5043. net_stats->tx_carrier_errors;
  5044. net_stats->rx_missed_errors =
  5045. (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
  5046. stats_blk->stat_FwRxDrop);
  5047. return net_stats;
  5048. }
  5049. /* All ethtool functions called with rtnl_lock */
  5050. static int
  5051. bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5052. {
  5053. struct bnx2 *bp = netdev_priv(dev);
  5054. int support_serdes = 0, support_copper = 0;
  5055. cmd->supported = SUPPORTED_Autoneg;
  5056. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  5057. support_serdes = 1;
  5058. support_copper = 1;
  5059. } else if (bp->phy_port == PORT_FIBRE)
  5060. support_serdes = 1;
  5061. else
  5062. support_copper = 1;
  5063. if (support_serdes) {
  5064. cmd->supported |= SUPPORTED_1000baseT_Full |
  5065. SUPPORTED_FIBRE;
  5066. if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
  5067. cmd->supported |= SUPPORTED_2500baseX_Full;
  5068. }
  5069. if (support_copper) {
  5070. cmd->supported |= SUPPORTED_10baseT_Half |
  5071. SUPPORTED_10baseT_Full |
  5072. SUPPORTED_100baseT_Half |
  5073. SUPPORTED_100baseT_Full |
  5074. SUPPORTED_1000baseT_Full |
  5075. SUPPORTED_TP;
  5076. }
  5077. spin_lock_bh(&bp->phy_lock);
  5078. cmd->port = bp->phy_port;
  5079. cmd->advertising = bp->advertising;
  5080. if (bp->autoneg & AUTONEG_SPEED) {
  5081. cmd->autoneg = AUTONEG_ENABLE;
  5082. }
  5083. else {
  5084. cmd->autoneg = AUTONEG_DISABLE;
  5085. }
  5086. if (netif_carrier_ok(dev)) {
  5087. cmd->speed = bp->line_speed;
  5088. cmd->duplex = bp->duplex;
  5089. }
  5090. else {
  5091. cmd->speed = -1;
  5092. cmd->duplex = -1;
  5093. }
  5094. spin_unlock_bh(&bp->phy_lock);
  5095. cmd->transceiver = XCVR_INTERNAL;
  5096. cmd->phy_address = bp->phy_addr;
  5097. return 0;
  5098. }
  5099. static int
  5100. bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  5101. {
  5102. struct bnx2 *bp = netdev_priv(dev);
  5103. u8 autoneg = bp->autoneg;
  5104. u8 req_duplex = bp->req_duplex;
  5105. u16 req_line_speed = bp->req_line_speed;
  5106. u32 advertising = bp->advertising;
  5107. int err = -EINVAL;
  5108. spin_lock_bh(&bp->phy_lock);
  5109. if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
  5110. goto err_out_unlock;
  5111. if (cmd->port != bp->phy_port &&
  5112. !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
  5113. goto err_out_unlock;
  5114. /* If device is down, we can store the settings only if the user
  5115. * is setting the currently active port.
  5116. */
  5117. if (!netif_running(dev) && cmd->port != bp->phy_port)
  5118. goto err_out_unlock;
  5119. if (cmd->autoneg == AUTONEG_ENABLE) {
  5120. autoneg |= AUTONEG_SPEED;
  5121. cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
  5122. /* allow advertising 1 speed */
  5123. if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
  5124. (cmd->advertising == ADVERTISED_10baseT_Full) ||
  5125. (cmd->advertising == ADVERTISED_100baseT_Half) ||
  5126. (cmd->advertising == ADVERTISED_100baseT_Full)) {
  5127. if (cmd->port == PORT_FIBRE)
  5128. goto err_out_unlock;
  5129. advertising = cmd->advertising;
  5130. } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
  5131. if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
  5132. (cmd->port == PORT_TP))
  5133. goto err_out_unlock;
  5134. } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
  5135. advertising = cmd->advertising;
  5136. else if (cmd->advertising == ADVERTISED_1000baseT_Half)
  5137. goto err_out_unlock;
  5138. else {
  5139. if (cmd->port == PORT_FIBRE)
  5140. advertising = ETHTOOL_ALL_FIBRE_SPEED;
  5141. else
  5142. advertising = ETHTOOL_ALL_COPPER_SPEED;
  5143. }
  5144. advertising |= ADVERTISED_Autoneg;
  5145. }
  5146. else {
  5147. if (cmd->port == PORT_FIBRE) {
  5148. if ((cmd->speed != SPEED_1000 &&
  5149. cmd->speed != SPEED_2500) ||
  5150. (cmd->duplex != DUPLEX_FULL))
  5151. goto err_out_unlock;
  5152. if (cmd->speed == SPEED_2500 &&
  5153. !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
  5154. goto err_out_unlock;
  5155. }
  5156. else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
  5157. goto err_out_unlock;
  5158. autoneg &= ~AUTONEG_SPEED;
  5159. req_line_speed = cmd->speed;
  5160. req_duplex = cmd->duplex;
  5161. advertising = 0;
  5162. }
  5163. bp->autoneg = autoneg;
  5164. bp->advertising = advertising;
  5165. bp->req_line_speed = req_line_speed;
  5166. bp->req_duplex = req_duplex;
  5167. err = 0;
  5168. /* If device is down, the new settings will be picked up when it is
  5169. * brought up.
  5170. */
  5171. if (netif_running(dev))
  5172. err = bnx2_setup_phy(bp, cmd->port);
  5173. err_out_unlock:
  5174. spin_unlock_bh(&bp->phy_lock);
  5175. return err;
  5176. }
  5177. static void
  5178. bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  5179. {
  5180. struct bnx2 *bp = netdev_priv(dev);
  5181. strcpy(info->driver, DRV_MODULE_NAME);
  5182. strcpy(info->version, DRV_MODULE_VERSION);
  5183. strcpy(info->bus_info, pci_name(bp->pdev));
  5184. strcpy(info->fw_version, bp->fw_version);
  5185. }
  5186. #define BNX2_REGDUMP_LEN (32 * 1024)
  5187. static int
  5188. bnx2_get_regs_len(struct net_device *dev)
  5189. {
  5190. return BNX2_REGDUMP_LEN;
  5191. }
  5192. static void
  5193. bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
  5194. {
  5195. u32 *p = _p, i, offset;
  5196. u8 *orig_p = _p;
  5197. struct bnx2 *bp = netdev_priv(dev);
  5198. u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
  5199. 0x0800, 0x0880, 0x0c00, 0x0c10,
  5200. 0x0c30, 0x0d08, 0x1000, 0x101c,
  5201. 0x1040, 0x1048, 0x1080, 0x10a4,
  5202. 0x1400, 0x1490, 0x1498, 0x14f0,
  5203. 0x1500, 0x155c, 0x1580, 0x15dc,
  5204. 0x1600, 0x1658, 0x1680, 0x16d8,
  5205. 0x1800, 0x1820, 0x1840, 0x1854,
  5206. 0x1880, 0x1894, 0x1900, 0x1984,
  5207. 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
  5208. 0x1c80, 0x1c94, 0x1d00, 0x1d84,
  5209. 0x2000, 0x2030, 0x23c0, 0x2400,
  5210. 0x2800, 0x2820, 0x2830, 0x2850,
  5211. 0x2b40, 0x2c10, 0x2fc0, 0x3058,
  5212. 0x3c00, 0x3c94, 0x4000, 0x4010,
  5213. 0x4080, 0x4090, 0x43c0, 0x4458,
  5214. 0x4c00, 0x4c18, 0x4c40, 0x4c54,
  5215. 0x4fc0, 0x5010, 0x53c0, 0x5444,
  5216. 0x5c00, 0x5c18, 0x5c80, 0x5c90,
  5217. 0x5fc0, 0x6000, 0x6400, 0x6428,
  5218. 0x6800, 0x6848, 0x684c, 0x6860,
  5219. 0x6888, 0x6910, 0x8000 };
  5220. regs->version = 0;
  5221. memset(p, 0, BNX2_REGDUMP_LEN);
  5222. if (!netif_running(bp->dev))
  5223. return;
  5224. i = 0;
  5225. offset = reg_boundaries[0];
  5226. p += offset;
  5227. while (offset < BNX2_REGDUMP_LEN) {
  5228. *p++ = REG_RD(bp, offset);
  5229. offset += 4;
  5230. if (offset == reg_boundaries[i + 1]) {
  5231. offset = reg_boundaries[i + 2];
  5232. p = (u32 *) (orig_p + offset);
  5233. i += 2;
  5234. }
  5235. }
  5236. }
  5237. static void
  5238. bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  5239. {
  5240. struct bnx2 *bp = netdev_priv(dev);
  5241. if (bp->flags & BNX2_FLAG_NO_WOL) {
  5242. wol->supported = 0;
  5243. wol->wolopts = 0;
  5244. }
  5245. else {
  5246. wol->supported = WAKE_MAGIC;
  5247. if (bp->wol)
  5248. wol->wolopts = WAKE_MAGIC;
  5249. else
  5250. wol->wolopts = 0;
  5251. }
  5252. memset(&wol->sopass, 0, sizeof(wol->sopass));
  5253. }
  5254. static int
  5255. bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  5256. {
  5257. struct bnx2 *bp = netdev_priv(dev);
  5258. if (wol->wolopts & ~WAKE_MAGIC)
  5259. return -EINVAL;
  5260. if (wol->wolopts & WAKE_MAGIC) {
  5261. if (bp->flags & BNX2_FLAG_NO_WOL)
  5262. return -EINVAL;
  5263. bp->wol = 1;
  5264. }
  5265. else {
  5266. bp->wol = 0;
  5267. }
  5268. return 0;
  5269. }
  5270. static int
  5271. bnx2_nway_reset(struct net_device *dev)
  5272. {
  5273. struct bnx2 *bp = netdev_priv(dev);
  5274. u32 bmcr;
  5275. if (!(bp->autoneg & AUTONEG_SPEED)) {
  5276. return -EINVAL;
  5277. }
  5278. spin_lock_bh(&bp->phy_lock);
  5279. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
  5280. int rc;
  5281. rc = bnx2_setup_remote_phy(bp, bp->phy_port);
  5282. spin_unlock_bh(&bp->phy_lock);
  5283. return rc;
  5284. }
  5285. /* Force a link down visible on the other side */
  5286. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  5287. bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
  5288. spin_unlock_bh(&bp->phy_lock);
  5289. msleep(20);
  5290. spin_lock_bh(&bp->phy_lock);
  5291. bp->current_interval = SERDES_AN_TIMEOUT;
  5292. bp->serdes_an_pending = 1;
  5293. mod_timer(&bp->timer, jiffies + bp->current_interval);
  5294. }
  5295. bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
  5296. bmcr &= ~BMCR_LOOPBACK;
  5297. bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
  5298. spin_unlock_bh(&bp->phy_lock);
  5299. return 0;
  5300. }
  5301. static int
  5302. bnx2_get_eeprom_len(struct net_device *dev)
  5303. {
  5304. struct bnx2 *bp = netdev_priv(dev);
  5305. if (bp->flash_info == NULL)
  5306. return 0;
  5307. return (int) bp->flash_size;
  5308. }
  5309. static int
  5310. bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  5311. u8 *eebuf)
  5312. {
  5313. struct bnx2 *bp = netdev_priv(dev);
  5314. int rc;
  5315. /* parameters already validated in ethtool_get_eeprom */
  5316. rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
  5317. return rc;
  5318. }
  5319. static int
  5320. bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  5321. u8 *eebuf)
  5322. {
  5323. struct bnx2 *bp = netdev_priv(dev);
  5324. int rc;
  5325. /* parameters already validated in ethtool_set_eeprom */
  5326. rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
  5327. return rc;
  5328. }
  5329. static int
  5330. bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  5331. {
  5332. struct bnx2 *bp = netdev_priv(dev);
  5333. memset(coal, 0, sizeof(struct ethtool_coalesce));
  5334. coal->rx_coalesce_usecs = bp->rx_ticks;
  5335. coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
  5336. coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
  5337. coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
  5338. coal->tx_coalesce_usecs = bp->tx_ticks;
  5339. coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
  5340. coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
  5341. coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
  5342. coal->stats_block_coalesce_usecs = bp->stats_ticks;
  5343. return 0;
  5344. }
  5345. static int
  5346. bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  5347. {
  5348. struct bnx2 *bp = netdev_priv(dev);
  5349. bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
  5350. if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
  5351. bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
  5352. if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
  5353. bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
  5354. if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
  5355. bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
  5356. if (bp->rx_quick_cons_trip_int > 0xff)
  5357. bp->rx_quick_cons_trip_int = 0xff;
  5358. bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
  5359. if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
  5360. bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
  5361. if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
  5362. bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
  5363. if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
  5364. bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
  5365. if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
  5366. 0xff;
  5367. bp->stats_ticks = coal->stats_block_coalesce_usecs;
  5368. if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  5369. if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
  5370. bp->stats_ticks = USEC_PER_SEC;
  5371. }
  5372. if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
  5373. bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  5374. bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  5375. if (netif_running(bp->dev)) {
  5376. bnx2_netif_stop(bp);
  5377. bnx2_init_nic(bp, 0);
  5378. bnx2_netif_start(bp);
  5379. }
  5380. return 0;
  5381. }
  5382. static void
  5383. bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  5384. {
  5385. struct bnx2 *bp = netdev_priv(dev);
  5386. ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
  5387. ering->rx_mini_max_pending = 0;
  5388. ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
  5389. ering->rx_pending = bp->rx_ring_size;
  5390. ering->rx_mini_pending = 0;
  5391. ering->rx_jumbo_pending = bp->rx_pg_ring_size;
  5392. ering->tx_max_pending = MAX_TX_DESC_CNT;
  5393. ering->tx_pending = bp->tx_ring_size;
  5394. }
  5395. static int
  5396. bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
  5397. {
  5398. if (netif_running(bp->dev)) {
  5399. bnx2_netif_stop(bp);
  5400. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
  5401. bnx2_free_skbs(bp);
  5402. bnx2_free_mem(bp);
  5403. }
  5404. bnx2_set_rx_ring_size(bp, rx);
  5405. bp->tx_ring_size = tx;
  5406. if (netif_running(bp->dev)) {
  5407. int rc;
  5408. rc = bnx2_alloc_mem(bp);
  5409. if (rc)
  5410. return rc;
  5411. bnx2_init_nic(bp, 0);
  5412. bnx2_netif_start(bp);
  5413. }
  5414. return 0;
  5415. }
  5416. static int
  5417. bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  5418. {
  5419. struct bnx2 *bp = netdev_priv(dev);
  5420. int rc;
  5421. if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
  5422. (ering->tx_pending > MAX_TX_DESC_CNT) ||
  5423. (ering->tx_pending <= MAX_SKB_FRAGS)) {
  5424. return -EINVAL;
  5425. }
  5426. rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
  5427. return rc;
  5428. }
  5429. static void
  5430. bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  5431. {
  5432. struct bnx2 *bp = netdev_priv(dev);
  5433. epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
  5434. epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
  5435. epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
  5436. }
  5437. static int
  5438. bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  5439. {
  5440. struct bnx2 *bp = netdev_priv(dev);
  5441. bp->req_flow_ctrl = 0;
  5442. if (epause->rx_pause)
  5443. bp->req_flow_ctrl |= FLOW_CTRL_RX;
  5444. if (epause->tx_pause)
  5445. bp->req_flow_ctrl |= FLOW_CTRL_TX;
  5446. if (epause->autoneg) {
  5447. bp->autoneg |= AUTONEG_FLOW_CTRL;
  5448. }
  5449. else {
  5450. bp->autoneg &= ~AUTONEG_FLOW_CTRL;
  5451. }
  5452. spin_lock_bh(&bp->phy_lock);
  5453. bnx2_setup_phy(bp, bp->phy_port);
  5454. spin_unlock_bh(&bp->phy_lock);
  5455. return 0;
  5456. }
  5457. static u32
  5458. bnx2_get_rx_csum(struct net_device *dev)
  5459. {
  5460. struct bnx2 *bp = netdev_priv(dev);
  5461. return bp->rx_csum;
  5462. }
  5463. static int
  5464. bnx2_set_rx_csum(struct net_device *dev, u32 data)
  5465. {
  5466. struct bnx2 *bp = netdev_priv(dev);
  5467. bp->rx_csum = data;
  5468. return 0;
  5469. }
  5470. static int
  5471. bnx2_set_tso(struct net_device *dev, u32 data)
  5472. {
  5473. struct bnx2 *bp = netdev_priv(dev);
  5474. if (data) {
  5475. dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
  5476. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  5477. dev->features |= NETIF_F_TSO6;
  5478. } else
  5479. dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
  5480. NETIF_F_TSO_ECN);
  5481. return 0;
  5482. }
  5483. #define BNX2_NUM_STATS 46
  5484. static struct {
  5485. char string[ETH_GSTRING_LEN];
  5486. } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
  5487. { "rx_bytes" },
  5488. { "rx_error_bytes" },
  5489. { "tx_bytes" },
  5490. { "tx_error_bytes" },
  5491. { "rx_ucast_packets" },
  5492. { "rx_mcast_packets" },
  5493. { "rx_bcast_packets" },
  5494. { "tx_ucast_packets" },
  5495. { "tx_mcast_packets" },
  5496. { "tx_bcast_packets" },
  5497. { "tx_mac_errors" },
  5498. { "tx_carrier_errors" },
  5499. { "rx_crc_errors" },
  5500. { "rx_align_errors" },
  5501. { "tx_single_collisions" },
  5502. { "tx_multi_collisions" },
  5503. { "tx_deferred" },
  5504. { "tx_excess_collisions" },
  5505. { "tx_late_collisions" },
  5506. { "tx_total_collisions" },
  5507. { "rx_fragments" },
  5508. { "rx_jabbers" },
  5509. { "rx_undersize_packets" },
  5510. { "rx_oversize_packets" },
  5511. { "rx_64_byte_packets" },
  5512. { "rx_65_to_127_byte_packets" },
  5513. { "rx_128_to_255_byte_packets" },
  5514. { "rx_256_to_511_byte_packets" },
  5515. { "rx_512_to_1023_byte_packets" },
  5516. { "rx_1024_to_1522_byte_packets" },
  5517. { "rx_1523_to_9022_byte_packets" },
  5518. { "tx_64_byte_packets" },
  5519. { "tx_65_to_127_byte_packets" },
  5520. { "tx_128_to_255_byte_packets" },
  5521. { "tx_256_to_511_byte_packets" },
  5522. { "tx_512_to_1023_byte_packets" },
  5523. { "tx_1024_to_1522_byte_packets" },
  5524. { "tx_1523_to_9022_byte_packets" },
  5525. { "rx_xon_frames" },
  5526. { "rx_xoff_frames" },
  5527. { "tx_xon_frames" },
  5528. { "tx_xoff_frames" },
  5529. { "rx_mac_ctrl_frames" },
  5530. { "rx_filtered_packets" },
  5531. { "rx_discards" },
  5532. { "rx_fw_discards" },
  5533. };
  5534. #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
  5535. static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
  5536. STATS_OFFSET32(stat_IfHCInOctets_hi),
  5537. STATS_OFFSET32(stat_IfHCInBadOctets_hi),
  5538. STATS_OFFSET32(stat_IfHCOutOctets_hi),
  5539. STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
  5540. STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
  5541. STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
  5542. STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
  5543. STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
  5544. STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
  5545. STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
  5546. STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
  5547. STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
  5548. STATS_OFFSET32(stat_Dot3StatsFCSErrors),
  5549. STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
  5550. STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
  5551. STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
  5552. STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
  5553. STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
  5554. STATS_OFFSET32(stat_Dot3StatsLateCollisions),
  5555. STATS_OFFSET32(stat_EtherStatsCollisions),
  5556. STATS_OFFSET32(stat_EtherStatsFragments),
  5557. STATS_OFFSET32(stat_EtherStatsJabbers),
  5558. STATS_OFFSET32(stat_EtherStatsUndersizePkts),
  5559. STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
  5560. STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
  5561. STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
  5562. STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
  5563. STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
  5564. STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
  5565. STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
  5566. STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
  5567. STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
  5568. STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
  5569. STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
  5570. STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
  5571. STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
  5572. STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
  5573. STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
  5574. STATS_OFFSET32(stat_XonPauseFramesReceived),
  5575. STATS_OFFSET32(stat_XoffPauseFramesReceived),
  5576. STATS_OFFSET32(stat_OutXonSent),
  5577. STATS_OFFSET32(stat_OutXoffSent),
  5578. STATS_OFFSET32(stat_MacControlFramesReceived),
  5579. STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
  5580. STATS_OFFSET32(stat_IfInMBUFDiscards),
  5581. STATS_OFFSET32(stat_FwRxDrop),
  5582. };
  5583. /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
  5584. * skipped because of errata.
  5585. */
  5586. static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
  5587. 8,0,8,8,8,8,8,8,8,8,
  5588. 4,0,4,4,4,4,4,4,4,4,
  5589. 4,4,4,4,4,4,4,4,4,4,
  5590. 4,4,4,4,4,4,4,4,4,4,
  5591. 4,4,4,4,4,4,
  5592. };
  5593. static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
  5594. 8,0,8,8,8,8,8,8,8,8,
  5595. 4,4,4,4,4,4,4,4,4,4,
  5596. 4,4,4,4,4,4,4,4,4,4,
  5597. 4,4,4,4,4,4,4,4,4,4,
  5598. 4,4,4,4,4,4,
  5599. };
  5600. #define BNX2_NUM_TESTS 6
  5601. static struct {
  5602. char string[ETH_GSTRING_LEN];
  5603. } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
  5604. { "register_test (offline)" },
  5605. { "memory_test (offline)" },
  5606. { "loopback_test (offline)" },
  5607. { "nvram_test (online)" },
  5608. { "interrupt_test (online)" },
  5609. { "link_test (online)" },
  5610. };
  5611. static int
  5612. bnx2_get_sset_count(struct net_device *dev, int sset)
  5613. {
  5614. switch (sset) {
  5615. case ETH_SS_TEST:
  5616. return BNX2_NUM_TESTS;
  5617. case ETH_SS_STATS:
  5618. return BNX2_NUM_STATS;
  5619. default:
  5620. return -EOPNOTSUPP;
  5621. }
  5622. }
  5623. static void
  5624. bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
  5625. {
  5626. struct bnx2 *bp = netdev_priv(dev);
  5627. memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
  5628. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  5629. int i;
  5630. bnx2_netif_stop(bp);
  5631. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
  5632. bnx2_free_skbs(bp);
  5633. if (bnx2_test_registers(bp) != 0) {
  5634. buf[0] = 1;
  5635. etest->flags |= ETH_TEST_FL_FAILED;
  5636. }
  5637. if (bnx2_test_memory(bp) != 0) {
  5638. buf[1] = 1;
  5639. etest->flags |= ETH_TEST_FL_FAILED;
  5640. }
  5641. if ((buf[2] = bnx2_test_loopback(bp)) != 0)
  5642. etest->flags |= ETH_TEST_FL_FAILED;
  5643. if (!netif_running(bp->dev)) {
  5644. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
  5645. }
  5646. else {
  5647. bnx2_init_nic(bp, 1);
  5648. bnx2_netif_start(bp);
  5649. }
  5650. /* wait for link up */
  5651. for (i = 0; i < 7; i++) {
  5652. if (bp->link_up)
  5653. break;
  5654. msleep_interruptible(1000);
  5655. }
  5656. }
  5657. if (bnx2_test_nvram(bp) != 0) {
  5658. buf[3] = 1;
  5659. etest->flags |= ETH_TEST_FL_FAILED;
  5660. }
  5661. if (bnx2_test_intr(bp) != 0) {
  5662. buf[4] = 1;
  5663. etest->flags |= ETH_TEST_FL_FAILED;
  5664. }
  5665. if (bnx2_test_link(bp) != 0) {
  5666. buf[5] = 1;
  5667. etest->flags |= ETH_TEST_FL_FAILED;
  5668. }
  5669. }
  5670. static void
  5671. bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  5672. {
  5673. switch (stringset) {
  5674. case ETH_SS_STATS:
  5675. memcpy(buf, bnx2_stats_str_arr,
  5676. sizeof(bnx2_stats_str_arr));
  5677. break;
  5678. case ETH_SS_TEST:
  5679. memcpy(buf, bnx2_tests_str_arr,
  5680. sizeof(bnx2_tests_str_arr));
  5681. break;
  5682. }
  5683. }
  5684. static void
  5685. bnx2_get_ethtool_stats(struct net_device *dev,
  5686. struct ethtool_stats *stats, u64 *buf)
  5687. {
  5688. struct bnx2 *bp = netdev_priv(dev);
  5689. int i;
  5690. u32 *hw_stats = (u32 *) bp->stats_blk;
  5691. u8 *stats_len_arr = NULL;
  5692. if (hw_stats == NULL) {
  5693. memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
  5694. return;
  5695. }
  5696. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  5697. (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
  5698. (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
  5699. (CHIP_ID(bp) == CHIP_ID_5708_A0))
  5700. stats_len_arr = bnx2_5706_stats_len_arr;
  5701. else
  5702. stats_len_arr = bnx2_5708_stats_len_arr;
  5703. for (i = 0; i < BNX2_NUM_STATS; i++) {
  5704. if (stats_len_arr[i] == 0) {
  5705. /* skip this counter */
  5706. buf[i] = 0;
  5707. continue;
  5708. }
  5709. if (stats_len_arr[i] == 4) {
  5710. /* 4-byte counter */
  5711. buf[i] = (u64)
  5712. *(hw_stats + bnx2_stats_offset_arr[i]);
  5713. continue;
  5714. }
  5715. /* 8-byte counter */
  5716. buf[i] = (((u64) *(hw_stats +
  5717. bnx2_stats_offset_arr[i])) << 32) +
  5718. *(hw_stats + bnx2_stats_offset_arr[i] + 1);
  5719. }
  5720. }
  5721. static int
  5722. bnx2_phys_id(struct net_device *dev, u32 data)
  5723. {
  5724. struct bnx2 *bp = netdev_priv(dev);
  5725. int i;
  5726. u32 save;
  5727. if (data == 0)
  5728. data = 2;
  5729. save = REG_RD(bp, BNX2_MISC_CFG);
  5730. REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
  5731. for (i = 0; i < (data * 2); i++) {
  5732. if ((i % 2) == 0) {
  5733. REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
  5734. }
  5735. else {
  5736. REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
  5737. BNX2_EMAC_LED_1000MB_OVERRIDE |
  5738. BNX2_EMAC_LED_100MB_OVERRIDE |
  5739. BNX2_EMAC_LED_10MB_OVERRIDE |
  5740. BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
  5741. BNX2_EMAC_LED_TRAFFIC);
  5742. }
  5743. msleep_interruptible(500);
  5744. if (signal_pending(current))
  5745. break;
  5746. }
  5747. REG_WR(bp, BNX2_EMAC_LED, 0);
  5748. REG_WR(bp, BNX2_MISC_CFG, save);
  5749. return 0;
  5750. }
  5751. static int
  5752. bnx2_set_tx_csum(struct net_device *dev, u32 data)
  5753. {
  5754. struct bnx2 *bp = netdev_priv(dev);
  5755. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  5756. return (ethtool_op_set_tx_ipv6_csum(dev, data));
  5757. else
  5758. return (ethtool_op_set_tx_csum(dev, data));
  5759. }
  5760. static const struct ethtool_ops bnx2_ethtool_ops = {
  5761. .get_settings = bnx2_get_settings,
  5762. .set_settings = bnx2_set_settings,
  5763. .get_drvinfo = bnx2_get_drvinfo,
  5764. .get_regs_len = bnx2_get_regs_len,
  5765. .get_regs = bnx2_get_regs,
  5766. .get_wol = bnx2_get_wol,
  5767. .set_wol = bnx2_set_wol,
  5768. .nway_reset = bnx2_nway_reset,
  5769. .get_link = ethtool_op_get_link,
  5770. .get_eeprom_len = bnx2_get_eeprom_len,
  5771. .get_eeprom = bnx2_get_eeprom,
  5772. .set_eeprom = bnx2_set_eeprom,
  5773. .get_coalesce = bnx2_get_coalesce,
  5774. .set_coalesce = bnx2_set_coalesce,
  5775. .get_ringparam = bnx2_get_ringparam,
  5776. .set_ringparam = bnx2_set_ringparam,
  5777. .get_pauseparam = bnx2_get_pauseparam,
  5778. .set_pauseparam = bnx2_set_pauseparam,
  5779. .get_rx_csum = bnx2_get_rx_csum,
  5780. .set_rx_csum = bnx2_set_rx_csum,
  5781. .set_tx_csum = bnx2_set_tx_csum,
  5782. .set_sg = ethtool_op_set_sg,
  5783. .set_tso = bnx2_set_tso,
  5784. .self_test = bnx2_self_test,
  5785. .get_strings = bnx2_get_strings,
  5786. .phys_id = bnx2_phys_id,
  5787. .get_ethtool_stats = bnx2_get_ethtool_stats,
  5788. .get_sset_count = bnx2_get_sset_count,
  5789. };
  5790. /* Called with rtnl_lock */
  5791. static int
  5792. bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  5793. {
  5794. struct mii_ioctl_data *data = if_mii(ifr);
  5795. struct bnx2 *bp = netdev_priv(dev);
  5796. int err;
  5797. switch(cmd) {
  5798. case SIOCGMIIPHY:
  5799. data->phy_id = bp->phy_addr;
  5800. /* fallthru */
  5801. case SIOCGMIIREG: {
  5802. u32 mii_regval;
  5803. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  5804. return -EOPNOTSUPP;
  5805. if (!netif_running(dev))
  5806. return -EAGAIN;
  5807. spin_lock_bh(&bp->phy_lock);
  5808. err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
  5809. spin_unlock_bh(&bp->phy_lock);
  5810. data->val_out = mii_regval;
  5811. return err;
  5812. }
  5813. case SIOCSMIIREG:
  5814. if (!capable(CAP_NET_ADMIN))
  5815. return -EPERM;
  5816. if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
  5817. return -EOPNOTSUPP;
  5818. if (!netif_running(dev))
  5819. return -EAGAIN;
  5820. spin_lock_bh(&bp->phy_lock);
  5821. err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
  5822. spin_unlock_bh(&bp->phy_lock);
  5823. return err;
  5824. default:
  5825. /* do nothing */
  5826. break;
  5827. }
  5828. return -EOPNOTSUPP;
  5829. }
  5830. /* Called with rtnl_lock */
  5831. static int
  5832. bnx2_change_mac_addr(struct net_device *dev, void *p)
  5833. {
  5834. struct sockaddr *addr = p;
  5835. struct bnx2 *bp = netdev_priv(dev);
  5836. if (!is_valid_ether_addr(addr->sa_data))
  5837. return -EINVAL;
  5838. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  5839. if (netif_running(dev))
  5840. bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
  5841. return 0;
  5842. }
  5843. /* Called with rtnl_lock */
  5844. static int
  5845. bnx2_change_mtu(struct net_device *dev, int new_mtu)
  5846. {
  5847. struct bnx2 *bp = netdev_priv(dev);
  5848. if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
  5849. ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
  5850. return -EINVAL;
  5851. dev->mtu = new_mtu;
  5852. return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
  5853. }
  5854. #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
  5855. static void
  5856. poll_bnx2(struct net_device *dev)
  5857. {
  5858. struct bnx2 *bp = netdev_priv(dev);
  5859. disable_irq(bp->pdev->irq);
  5860. bnx2_interrupt(bp->pdev->irq, dev);
  5861. enable_irq(bp->pdev->irq);
  5862. }
  5863. #endif
  5864. static void __devinit
  5865. bnx2_get_5709_media(struct bnx2 *bp)
  5866. {
  5867. u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
  5868. u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
  5869. u32 strap;
  5870. if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
  5871. return;
  5872. else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
  5873. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  5874. return;
  5875. }
  5876. if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
  5877. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
  5878. else
  5879. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
  5880. if (PCI_FUNC(bp->pdev->devfn) == 0) {
  5881. switch (strap) {
  5882. case 0x4:
  5883. case 0x5:
  5884. case 0x6:
  5885. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  5886. return;
  5887. }
  5888. } else {
  5889. switch (strap) {
  5890. case 0x1:
  5891. case 0x2:
  5892. case 0x4:
  5893. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  5894. return;
  5895. }
  5896. }
  5897. }
  5898. static void __devinit
  5899. bnx2_get_pci_speed(struct bnx2 *bp)
  5900. {
  5901. u32 reg;
  5902. reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
  5903. if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
  5904. u32 clkreg;
  5905. bp->flags |= BNX2_FLAG_PCIX;
  5906. clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
  5907. clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
  5908. switch (clkreg) {
  5909. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
  5910. bp->bus_speed_mhz = 133;
  5911. break;
  5912. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
  5913. bp->bus_speed_mhz = 100;
  5914. break;
  5915. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
  5916. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
  5917. bp->bus_speed_mhz = 66;
  5918. break;
  5919. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
  5920. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
  5921. bp->bus_speed_mhz = 50;
  5922. break;
  5923. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
  5924. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
  5925. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
  5926. bp->bus_speed_mhz = 33;
  5927. break;
  5928. }
  5929. }
  5930. else {
  5931. if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
  5932. bp->bus_speed_mhz = 66;
  5933. else
  5934. bp->bus_speed_mhz = 33;
  5935. }
  5936. if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
  5937. bp->flags |= BNX2_FLAG_PCI_32BIT;
  5938. }
  5939. static int __devinit
  5940. bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
  5941. {
  5942. struct bnx2 *bp;
  5943. unsigned long mem_len;
  5944. int rc, i, j;
  5945. u32 reg;
  5946. u64 dma_mask, persist_dma_mask;
  5947. SET_NETDEV_DEV(dev, &pdev->dev);
  5948. bp = netdev_priv(dev);
  5949. bp->flags = 0;
  5950. bp->phy_flags = 0;
  5951. /* enable device (incl. PCI PM wakeup), and bus-mastering */
  5952. rc = pci_enable_device(pdev);
  5953. if (rc) {
  5954. dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
  5955. goto err_out;
  5956. }
  5957. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  5958. dev_err(&pdev->dev,
  5959. "Cannot find PCI device base address, aborting.\n");
  5960. rc = -ENODEV;
  5961. goto err_out_disable;
  5962. }
  5963. rc = pci_request_regions(pdev, DRV_MODULE_NAME);
  5964. if (rc) {
  5965. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
  5966. goto err_out_disable;
  5967. }
  5968. pci_set_master(pdev);
  5969. pci_save_state(pdev);
  5970. bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  5971. if (bp->pm_cap == 0) {
  5972. dev_err(&pdev->dev,
  5973. "Cannot find power management capability, aborting.\n");
  5974. rc = -EIO;
  5975. goto err_out_release;
  5976. }
  5977. bp->dev = dev;
  5978. bp->pdev = pdev;
  5979. spin_lock_init(&bp->phy_lock);
  5980. spin_lock_init(&bp->indirect_lock);
  5981. INIT_WORK(&bp->reset_task, bnx2_reset_task);
  5982. dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
  5983. mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
  5984. dev->mem_end = dev->mem_start + mem_len;
  5985. dev->irq = pdev->irq;
  5986. bp->regview = ioremap_nocache(dev->base_addr, mem_len);
  5987. if (!bp->regview) {
  5988. dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
  5989. rc = -ENOMEM;
  5990. goto err_out_release;
  5991. }
  5992. /* Configure byte swap and enable write to the reg_window registers.
  5993. * Rely on CPU to do target byte swapping on big endian systems
  5994. * The chip's target access swapping will not swap all accesses
  5995. */
  5996. pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
  5997. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  5998. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
  5999. bnx2_set_power_state(bp, PCI_D0);
  6000. bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
  6001. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  6002. if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
  6003. dev_err(&pdev->dev,
  6004. "Cannot find PCIE capability, aborting.\n");
  6005. rc = -EIO;
  6006. goto err_out_unmap;
  6007. }
  6008. bp->flags |= BNX2_FLAG_PCIE;
  6009. if (CHIP_REV(bp) == CHIP_REV_Ax)
  6010. bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
  6011. } else {
  6012. bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
  6013. if (bp->pcix_cap == 0) {
  6014. dev_err(&pdev->dev,
  6015. "Cannot find PCIX capability, aborting.\n");
  6016. rc = -EIO;
  6017. goto err_out_unmap;
  6018. }
  6019. }
  6020. if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
  6021. if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
  6022. bp->flags |= BNX2_FLAG_MSIX_CAP;
  6023. }
  6024. if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
  6025. if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
  6026. bp->flags |= BNX2_FLAG_MSI_CAP;
  6027. }
  6028. /* 5708 cannot support DMA addresses > 40-bit. */
  6029. if (CHIP_NUM(bp) == CHIP_NUM_5708)
  6030. persist_dma_mask = dma_mask = DMA_40BIT_MASK;
  6031. else
  6032. persist_dma_mask = dma_mask = DMA_64BIT_MASK;
  6033. /* Configure DMA attributes. */
  6034. if (pci_set_dma_mask(pdev, dma_mask) == 0) {
  6035. dev->features |= NETIF_F_HIGHDMA;
  6036. rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
  6037. if (rc) {
  6038. dev_err(&pdev->dev,
  6039. "pci_set_consistent_dma_mask failed, aborting.\n");
  6040. goto err_out_unmap;
  6041. }
  6042. } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
  6043. dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
  6044. goto err_out_unmap;
  6045. }
  6046. if (!(bp->flags & BNX2_FLAG_PCIE))
  6047. bnx2_get_pci_speed(bp);
  6048. /* 5706A0 may falsely detect SERR and PERR. */
  6049. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  6050. reg = REG_RD(bp, PCI_COMMAND);
  6051. reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  6052. REG_WR(bp, PCI_COMMAND, reg);
  6053. }
  6054. else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
  6055. !(bp->flags & BNX2_FLAG_PCIX)) {
  6056. dev_err(&pdev->dev,
  6057. "5706 A1 can only be used in a PCIX bus, aborting.\n");
  6058. goto err_out_unmap;
  6059. }
  6060. bnx2_init_nvram(bp);
  6061. reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
  6062. if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
  6063. BNX2_SHM_HDR_SIGNATURE_SIG) {
  6064. u32 off = PCI_FUNC(pdev->devfn) << 2;
  6065. bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
  6066. } else
  6067. bp->shmem_base = HOST_VIEW_SHMEM_BASE;
  6068. /* Get the permanent MAC address. First we need to make sure the
  6069. * firmware is actually running.
  6070. */
  6071. reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
  6072. if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
  6073. BNX2_DEV_INFO_SIGNATURE_MAGIC) {
  6074. dev_err(&pdev->dev, "Firmware not running, aborting.\n");
  6075. rc = -ENODEV;
  6076. goto err_out_unmap;
  6077. }
  6078. reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
  6079. for (i = 0, j = 0; i < 3; i++) {
  6080. u8 num, k, skip0;
  6081. num = (u8) (reg >> (24 - (i * 8)));
  6082. for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
  6083. if (num >= k || !skip0 || k == 1) {
  6084. bp->fw_version[j++] = (num / k) + '0';
  6085. skip0 = 0;
  6086. }
  6087. }
  6088. if (i != 2)
  6089. bp->fw_version[j++] = '.';
  6090. }
  6091. reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
  6092. if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
  6093. bp->wol = 1;
  6094. if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
  6095. bp->flags |= BNX2_FLAG_ASF_ENABLE;
  6096. for (i = 0; i < 30; i++) {
  6097. reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
  6098. if (reg & BNX2_CONDITION_MFW_RUN_MASK)
  6099. break;
  6100. msleep(10);
  6101. }
  6102. }
  6103. reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
  6104. reg &= BNX2_CONDITION_MFW_RUN_MASK;
  6105. if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
  6106. reg != BNX2_CONDITION_MFW_RUN_NONE) {
  6107. u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
  6108. bp->fw_version[j++] = ' ';
  6109. for (i = 0; i < 3; i++) {
  6110. reg = bnx2_reg_rd_ind(bp, addr + i * 4);
  6111. reg = swab32(reg);
  6112. memcpy(&bp->fw_version[j], &reg, 4);
  6113. j += 4;
  6114. }
  6115. }
  6116. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
  6117. bp->mac_addr[0] = (u8) (reg >> 8);
  6118. bp->mac_addr[1] = (u8) reg;
  6119. reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
  6120. bp->mac_addr[2] = (u8) (reg >> 24);
  6121. bp->mac_addr[3] = (u8) (reg >> 16);
  6122. bp->mac_addr[4] = (u8) (reg >> 8);
  6123. bp->mac_addr[5] = (u8) reg;
  6124. bp->tx_ring_size = MAX_TX_DESC_CNT;
  6125. bnx2_set_rx_ring_size(bp, 255);
  6126. bp->rx_csum = 1;
  6127. bp->tx_quick_cons_trip_int = 20;
  6128. bp->tx_quick_cons_trip = 20;
  6129. bp->tx_ticks_int = 80;
  6130. bp->tx_ticks = 80;
  6131. bp->rx_quick_cons_trip_int = 6;
  6132. bp->rx_quick_cons_trip = 6;
  6133. bp->rx_ticks_int = 18;
  6134. bp->rx_ticks = 18;
  6135. bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
  6136. bp->timer_interval = HZ;
  6137. bp->current_interval = HZ;
  6138. bp->phy_addr = 1;
  6139. /* Disable WOL support if we are running on a SERDES chip. */
  6140. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  6141. bnx2_get_5709_media(bp);
  6142. else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
  6143. bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
  6144. bp->phy_port = PORT_TP;
  6145. if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
  6146. bp->phy_port = PORT_FIBRE;
  6147. reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
  6148. if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
  6149. bp->flags |= BNX2_FLAG_NO_WOL;
  6150. bp->wol = 0;
  6151. }
  6152. if (CHIP_NUM(bp) == CHIP_NUM_5706) {
  6153. /* Don't do parallel detect on this board because of
  6154. * some board problems. The link will not go down
  6155. * if we do parallel detect.
  6156. */
  6157. if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  6158. pdev->subsystem_device == 0x310c)
  6159. bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
  6160. } else {
  6161. bp->phy_addr = 2;
  6162. if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
  6163. bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
  6164. }
  6165. } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
  6166. CHIP_NUM(bp) == CHIP_NUM_5708)
  6167. bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
  6168. else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
  6169. (CHIP_REV(bp) == CHIP_REV_Ax ||
  6170. CHIP_REV(bp) == CHIP_REV_Bx))
  6171. bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
  6172. bnx2_init_fw_cap(bp);
  6173. if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
  6174. (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
  6175. (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
  6176. bp->flags |= BNX2_FLAG_NO_WOL;
  6177. bp->wol = 0;
  6178. }
  6179. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  6180. bp->tx_quick_cons_trip_int =
  6181. bp->tx_quick_cons_trip;
  6182. bp->tx_ticks_int = bp->tx_ticks;
  6183. bp->rx_quick_cons_trip_int =
  6184. bp->rx_quick_cons_trip;
  6185. bp->rx_ticks_int = bp->rx_ticks;
  6186. bp->comp_prod_trip_int = bp->comp_prod_trip;
  6187. bp->com_ticks_int = bp->com_ticks;
  6188. bp->cmd_ticks_int = bp->cmd_ticks;
  6189. }
  6190. /* Disable MSI on 5706 if AMD 8132 bridge is found.
  6191. *
  6192. * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
  6193. * with byte enables disabled on the unused 32-bit word. This is legal
  6194. * but causes problems on the AMD 8132 which will eventually stop
  6195. * responding after a while.
  6196. *
  6197. * AMD believes this incompatibility is unique to the 5706, and
  6198. * prefers to locally disable MSI rather than globally disabling it.
  6199. */
  6200. if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
  6201. struct pci_dev *amd_8132 = NULL;
  6202. while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
  6203. PCI_DEVICE_ID_AMD_8132_BRIDGE,
  6204. amd_8132))) {
  6205. if (amd_8132->revision >= 0x10 &&
  6206. amd_8132->revision <= 0x13) {
  6207. disable_msi = 1;
  6208. pci_dev_put(amd_8132);
  6209. break;
  6210. }
  6211. }
  6212. }
  6213. bnx2_set_default_link(bp);
  6214. bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
  6215. init_timer(&bp->timer);
  6216. bp->timer.expires = RUN_AT(bp->timer_interval);
  6217. bp->timer.data = (unsigned long) bp;
  6218. bp->timer.function = bnx2_timer;
  6219. return 0;
  6220. err_out_unmap:
  6221. if (bp->regview) {
  6222. iounmap(bp->regview);
  6223. bp->regview = NULL;
  6224. }
  6225. err_out_release:
  6226. pci_release_regions(pdev);
  6227. err_out_disable:
  6228. pci_disable_device(pdev);
  6229. pci_set_drvdata(pdev, NULL);
  6230. err_out:
  6231. return rc;
  6232. }
  6233. static char * __devinit
  6234. bnx2_bus_string(struct bnx2 *bp, char *str)
  6235. {
  6236. char *s = str;
  6237. if (bp->flags & BNX2_FLAG_PCIE) {
  6238. s += sprintf(s, "PCI Express");
  6239. } else {
  6240. s += sprintf(s, "PCI");
  6241. if (bp->flags & BNX2_FLAG_PCIX)
  6242. s += sprintf(s, "-X");
  6243. if (bp->flags & BNX2_FLAG_PCI_32BIT)
  6244. s += sprintf(s, " 32-bit");
  6245. else
  6246. s += sprintf(s, " 64-bit");
  6247. s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
  6248. }
  6249. return str;
  6250. }
  6251. static void __devinit
  6252. bnx2_init_napi(struct bnx2 *bp)
  6253. {
  6254. int i;
  6255. for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
  6256. struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
  6257. int (*poll)(struct napi_struct *, int);
  6258. if (i == 0)
  6259. poll = bnx2_poll;
  6260. else
  6261. poll = bnx2_poll_msix;
  6262. netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
  6263. bnapi->bp = bp;
  6264. }
  6265. }
  6266. static int __devinit
  6267. bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  6268. {
  6269. static int version_printed = 0;
  6270. struct net_device *dev = NULL;
  6271. struct bnx2 *bp;
  6272. int rc;
  6273. char str[40];
  6274. DECLARE_MAC_BUF(mac);
  6275. if (version_printed++ == 0)
  6276. printk(KERN_INFO "%s", version);
  6277. /* dev zeroed in init_etherdev */
  6278. dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
  6279. if (!dev)
  6280. return -ENOMEM;
  6281. rc = bnx2_init_board(pdev, dev);
  6282. if (rc < 0) {
  6283. free_netdev(dev);
  6284. return rc;
  6285. }
  6286. dev->open = bnx2_open;
  6287. dev->hard_start_xmit = bnx2_start_xmit;
  6288. dev->stop = bnx2_close;
  6289. dev->get_stats = bnx2_get_stats;
  6290. dev->set_rx_mode = bnx2_set_rx_mode;
  6291. dev->do_ioctl = bnx2_ioctl;
  6292. dev->set_mac_address = bnx2_change_mac_addr;
  6293. dev->change_mtu = bnx2_change_mtu;
  6294. dev->tx_timeout = bnx2_tx_timeout;
  6295. dev->watchdog_timeo = TX_TIMEOUT;
  6296. #ifdef BCM_VLAN
  6297. dev->vlan_rx_register = bnx2_vlan_rx_register;
  6298. #endif
  6299. dev->ethtool_ops = &bnx2_ethtool_ops;
  6300. bp = netdev_priv(dev);
  6301. bnx2_init_napi(bp);
  6302. #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
  6303. dev->poll_controller = poll_bnx2;
  6304. #endif
  6305. pci_set_drvdata(pdev, dev);
  6306. memcpy(dev->dev_addr, bp->mac_addr, 6);
  6307. memcpy(dev->perm_addr, bp->mac_addr, 6);
  6308. bp->name = board_info[ent->driver_data].name;
  6309. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  6310. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  6311. dev->features |= NETIF_F_IPV6_CSUM;
  6312. #ifdef BCM_VLAN
  6313. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  6314. #endif
  6315. dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
  6316. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  6317. dev->features |= NETIF_F_TSO6;
  6318. if ((rc = register_netdev(dev))) {
  6319. dev_err(&pdev->dev, "Cannot register net device\n");
  6320. if (bp->regview)
  6321. iounmap(bp->regview);
  6322. pci_release_regions(pdev);
  6323. pci_disable_device(pdev);
  6324. pci_set_drvdata(pdev, NULL);
  6325. free_netdev(dev);
  6326. return rc;
  6327. }
  6328. printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
  6329. "IRQ %d, node addr %s\n",
  6330. dev->name,
  6331. bp->name,
  6332. ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
  6333. ((CHIP_ID(bp) & 0x0ff0) >> 4),
  6334. bnx2_bus_string(bp, str),
  6335. dev->base_addr,
  6336. bp->pdev->irq, print_mac(mac, dev->dev_addr));
  6337. return 0;
  6338. }
  6339. static void __devexit
  6340. bnx2_remove_one(struct pci_dev *pdev)
  6341. {
  6342. struct net_device *dev = pci_get_drvdata(pdev);
  6343. struct bnx2 *bp = netdev_priv(dev);
  6344. flush_scheduled_work();
  6345. unregister_netdev(dev);
  6346. if (bp->regview)
  6347. iounmap(bp->regview);
  6348. free_netdev(dev);
  6349. pci_release_regions(pdev);
  6350. pci_disable_device(pdev);
  6351. pci_set_drvdata(pdev, NULL);
  6352. }
  6353. static int
  6354. bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
  6355. {
  6356. struct net_device *dev = pci_get_drvdata(pdev);
  6357. struct bnx2 *bp = netdev_priv(dev);
  6358. u32 reset_code;
  6359. /* PCI register 4 needs to be saved whether netif_running() or not.
  6360. * MSI address and data need to be saved if using MSI and
  6361. * netif_running().
  6362. */
  6363. pci_save_state(pdev);
  6364. if (!netif_running(dev))
  6365. return 0;
  6366. flush_scheduled_work();
  6367. bnx2_netif_stop(bp);
  6368. netif_device_detach(dev);
  6369. del_timer_sync(&bp->timer);
  6370. if (bp->flags & BNX2_FLAG_NO_WOL)
  6371. reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
  6372. else if (bp->wol)
  6373. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  6374. else
  6375. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  6376. bnx2_reset_chip(bp, reset_code);
  6377. bnx2_free_skbs(bp);
  6378. bnx2_set_power_state(bp, pci_choose_state(pdev, state));
  6379. return 0;
  6380. }
  6381. static int
  6382. bnx2_resume(struct pci_dev *pdev)
  6383. {
  6384. struct net_device *dev = pci_get_drvdata(pdev);
  6385. struct bnx2 *bp = netdev_priv(dev);
  6386. pci_restore_state(pdev);
  6387. if (!netif_running(dev))
  6388. return 0;
  6389. bnx2_set_power_state(bp, PCI_D0);
  6390. netif_device_attach(dev);
  6391. bnx2_init_nic(bp, 1);
  6392. bnx2_netif_start(bp);
  6393. return 0;
  6394. }
  6395. /**
  6396. * bnx2_io_error_detected - called when PCI error is detected
  6397. * @pdev: Pointer to PCI device
  6398. * @state: The current pci connection state
  6399. *
  6400. * This function is called after a PCI bus error affecting
  6401. * this device has been detected.
  6402. */
  6403. static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
  6404. pci_channel_state_t state)
  6405. {
  6406. struct net_device *dev = pci_get_drvdata(pdev);
  6407. struct bnx2 *bp = netdev_priv(dev);
  6408. rtnl_lock();
  6409. netif_device_detach(dev);
  6410. if (netif_running(dev)) {
  6411. bnx2_netif_stop(bp);
  6412. del_timer_sync(&bp->timer);
  6413. bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
  6414. }
  6415. pci_disable_device(pdev);
  6416. rtnl_unlock();
  6417. /* Request a slot slot reset. */
  6418. return PCI_ERS_RESULT_NEED_RESET;
  6419. }
  6420. /**
  6421. * bnx2_io_slot_reset - called after the pci bus has been reset.
  6422. * @pdev: Pointer to PCI device
  6423. *
  6424. * Restart the card from scratch, as if from a cold-boot.
  6425. */
  6426. static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
  6427. {
  6428. struct net_device *dev = pci_get_drvdata(pdev);
  6429. struct bnx2 *bp = netdev_priv(dev);
  6430. rtnl_lock();
  6431. if (pci_enable_device(pdev)) {
  6432. dev_err(&pdev->dev,
  6433. "Cannot re-enable PCI device after reset.\n");
  6434. rtnl_unlock();
  6435. return PCI_ERS_RESULT_DISCONNECT;
  6436. }
  6437. pci_set_master(pdev);
  6438. pci_restore_state(pdev);
  6439. if (netif_running(dev)) {
  6440. bnx2_set_power_state(bp, PCI_D0);
  6441. bnx2_init_nic(bp, 1);
  6442. }
  6443. rtnl_unlock();
  6444. return PCI_ERS_RESULT_RECOVERED;
  6445. }
  6446. /**
  6447. * bnx2_io_resume - called when traffic can start flowing again.
  6448. * @pdev: Pointer to PCI device
  6449. *
  6450. * This callback is called when the error recovery driver tells us that
  6451. * its OK to resume normal operation.
  6452. */
  6453. static void bnx2_io_resume(struct pci_dev *pdev)
  6454. {
  6455. struct net_device *dev = pci_get_drvdata(pdev);
  6456. struct bnx2 *bp = netdev_priv(dev);
  6457. rtnl_lock();
  6458. if (netif_running(dev))
  6459. bnx2_netif_start(bp);
  6460. netif_device_attach(dev);
  6461. rtnl_unlock();
  6462. }
  6463. static struct pci_error_handlers bnx2_err_handler = {
  6464. .error_detected = bnx2_io_error_detected,
  6465. .slot_reset = bnx2_io_slot_reset,
  6466. .resume = bnx2_io_resume,
  6467. };
  6468. static struct pci_driver bnx2_pci_driver = {
  6469. .name = DRV_MODULE_NAME,
  6470. .id_table = bnx2_pci_tbl,
  6471. .probe = bnx2_init_one,
  6472. .remove = __devexit_p(bnx2_remove_one),
  6473. .suspend = bnx2_suspend,
  6474. .resume = bnx2_resume,
  6475. .err_handler = &bnx2_err_handler,
  6476. };
  6477. static int __init bnx2_init(void)
  6478. {
  6479. return pci_register_driver(&bnx2_pci_driver);
  6480. }
  6481. static void __exit bnx2_cleanup(void)
  6482. {
  6483. pci_unregister_driver(&bnx2_pci_driver);
  6484. }
  6485. module_init(bnx2_init);
  6486. module_exit(bnx2_cleanup);