main.c 36 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #define ATH_PCI_VERSION "0.1"
  20. #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
  21. #define IEEE80211_ACTION_CAT_HT 7
  22. #define IEEE80211_ACTION_HT_TXCHWIDTH 0
  23. static char *dev_info = "ath9k";
  24. MODULE_AUTHOR("Atheros Communications");
  25. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27. MODULE_LICENSE("Dual BSD/GPL");
  28. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  29. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  31. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  32. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  33. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  34. { 0 }
  35. };
  36. static int ath_get_channel(struct ath_softc *sc,
  37. struct ieee80211_channel *chan)
  38. {
  39. int i;
  40. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  41. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  42. return i;
  43. }
  44. return -1;
  45. }
  46. static u32 ath_get_extchanmode(struct ath_softc *sc,
  47. struct ieee80211_channel *chan)
  48. {
  49. u32 chanmode = 0;
  50. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  51. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  52. switch (chan->band) {
  53. case IEEE80211_BAND_2GHZ:
  54. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  55. (tx_chan_width == ATH9K_HT_MACMODE_20))
  56. chanmode = CHANNEL_G_HT20;
  57. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  58. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  59. chanmode = CHANNEL_G_HT40PLUS;
  60. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  61. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  62. chanmode = CHANNEL_G_HT40MINUS;
  63. break;
  64. case IEEE80211_BAND_5GHZ:
  65. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  66. (tx_chan_width == ATH9K_HT_MACMODE_20))
  67. chanmode = CHANNEL_A_HT20;
  68. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  69. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  70. chanmode = CHANNEL_A_HT40PLUS;
  71. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  72. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  73. chanmode = CHANNEL_A_HT40MINUS;
  74. break;
  75. default:
  76. break;
  77. }
  78. return chanmode;
  79. }
  80. static int ath_setkey_tkip(struct ath_softc *sc,
  81. struct ieee80211_key_conf *key,
  82. struct ath9k_keyval *hk,
  83. const u8 *addr)
  84. {
  85. u8 *key_rxmic = NULL;
  86. u8 *key_txmic = NULL;
  87. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  88. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  89. if (addr == NULL) {
  90. /* Group key installation */
  91. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  92. return ath_keyset(sc, key->keyidx, hk, addr);
  93. }
  94. if (!sc->sc_splitmic) {
  95. /*
  96. * data key goes at first index,
  97. * the hal handles the MIC keys at index+64.
  98. */
  99. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  100. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  101. return ath_keyset(sc, key->keyidx, hk, addr);
  102. }
  103. /*
  104. * TX key goes at first index, RX key at +32.
  105. * The hal handles the MIC keys at index+64.
  106. */
  107. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  108. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  109. /* Txmic entry failed. No need to proceed further */
  110. DPRINTF(sc, ATH_DBG_KEYCACHE,
  111. "%s Setting TX MIC Key Failed\n", __func__);
  112. return 0;
  113. }
  114. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  115. /* XXX delete tx key on failure? */
  116. return ath_keyset(sc, key->keyidx+32, hk, addr);
  117. }
  118. static int ath_key_config(struct ath_softc *sc,
  119. const u8 *addr,
  120. struct ieee80211_key_conf *key)
  121. {
  122. struct ieee80211_vif *vif;
  123. struct ath9k_keyval hk;
  124. const u8 *mac = NULL;
  125. int ret = 0;
  126. enum ieee80211_if_types opmode;
  127. memset(&hk, 0, sizeof(hk));
  128. switch (key->alg) {
  129. case ALG_WEP:
  130. hk.kv_type = ATH9K_CIPHER_WEP;
  131. break;
  132. case ALG_TKIP:
  133. hk.kv_type = ATH9K_CIPHER_TKIP;
  134. break;
  135. case ALG_CCMP:
  136. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  137. break;
  138. default:
  139. return -EINVAL;
  140. }
  141. hk.kv_len = key->keylen;
  142. memcpy(hk.kv_val, key->key, key->keylen);
  143. if (!sc->sc_vaps[0])
  144. return -EIO;
  145. vif = sc->sc_vaps[0]->av_if_data;
  146. opmode = vif->type;
  147. /*
  148. * Strategy:
  149. * For _M_STA mc tx, we will not setup a key at all since we never
  150. * tx mc.
  151. * _M_STA mc rx, we will use the keyID.
  152. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  153. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  154. * peer node. BUT we will plumb a cleartext key so that we can do
  155. * perSta default key table lookup in software.
  156. */
  157. if (is_broadcast_ether_addr(addr)) {
  158. switch (opmode) {
  159. case IEEE80211_IF_TYPE_STA:
  160. /* default key: could be group WPA key
  161. * or could be static WEP key */
  162. mac = NULL;
  163. break;
  164. case IEEE80211_IF_TYPE_IBSS:
  165. break;
  166. case IEEE80211_IF_TYPE_AP:
  167. break;
  168. default:
  169. ASSERT(0);
  170. break;
  171. }
  172. } else {
  173. mac = addr;
  174. }
  175. if (key->alg == ALG_TKIP)
  176. ret = ath_setkey_tkip(sc, key, &hk, mac);
  177. else
  178. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  179. if (!ret)
  180. return -EIO;
  181. return 0;
  182. }
  183. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  184. {
  185. #define ATH_MAX_NUM_KEYS 4
  186. int freeslot;
  187. freeslot = (key->keyidx >= ATH_MAX_NUM_KEYS) ? 1 : 0;
  188. ath_key_reset(sc, key->keyidx, freeslot);
  189. #undef ATH_MAX_NUM_KEYS
  190. }
  191. static void setup_ht_cap(struct ieee80211_ht_info *ht_info)
  192. {
  193. /* Until mac80211 includes these fields */
  194. #define IEEE80211_HT_CAP_DSSSCCK40 0x1000
  195. #define IEEE80211_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  196. #define IEEE80211_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  197. ht_info->ht_supported = 1;
  198. ht_info->cap = (u16)IEEE80211_HT_CAP_SUP_WIDTH
  199. |(u16)IEEE80211_HT_CAP_MIMO_PS
  200. |(u16)IEEE80211_HT_CAP_SGI_40
  201. |(u16)IEEE80211_HT_CAP_DSSSCCK40;
  202. ht_info->ampdu_factor = IEEE80211_HT_CAP_MAXRXAMPDU_65536;
  203. ht_info->ampdu_density = IEEE80211_HT_CAP_MPDUDENSITY_8;
  204. /* setup supported mcs set */
  205. memset(ht_info->supp_mcs_set, 0, 16);
  206. ht_info->supp_mcs_set[0] = 0xff;
  207. ht_info->supp_mcs_set[1] = 0xff;
  208. ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
  209. }
  210. static int ath_rate2idx(struct ath_softc *sc, int rate)
  211. {
  212. int i = 0, cur_band, n_rates;
  213. struct ieee80211_hw *hw = sc->hw;
  214. cur_band = hw->conf.channel->band;
  215. n_rates = sc->sbands[cur_band].n_bitrates;
  216. for (i = 0; i < n_rates; i++) {
  217. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  218. break;
  219. }
  220. /*
  221. * NB:mac80211 validates rx rate index against the supported legacy rate
  222. * index only (should be done against ht rates also), return the highest
  223. * legacy rate index for rx rate which does not match any one of the
  224. * supported basic and extended rates to make mac80211 happy.
  225. * The following hack will be cleaned up once the issue with
  226. * the rx rate index validation in mac80211 is fixed.
  227. */
  228. if (i == n_rates)
  229. return n_rates - 1;
  230. return i;
  231. }
  232. static void ath9k_rx_prepare(struct ath_softc *sc,
  233. struct sk_buff *skb,
  234. struct ath_recv_status *status,
  235. struct ieee80211_rx_status *rx_status)
  236. {
  237. struct ieee80211_hw *hw = sc->hw;
  238. struct ieee80211_channel *curchan = hw->conf.channel;
  239. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  240. rx_status->mactime = status->tsf;
  241. rx_status->band = curchan->band;
  242. rx_status->freq = curchan->center_freq;
  243. rx_status->noise = ATH_DEFAULT_NOISE_FLOOR;
  244. rx_status->signal = rx_status->noise + status->rssi;
  245. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  246. rx_status->antenna = status->antenna;
  247. rx_status->qual = status->rssi * 100 / 64;
  248. if (status->flags & ATH_RX_MIC_ERROR)
  249. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  250. if (status->flags & ATH_RX_FCS_ERROR)
  251. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  252. rx_status->flag |= RX_FLAG_TSFT;
  253. }
  254. static u8 parse_mpdudensity(u8 mpdudensity)
  255. {
  256. /*
  257. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  258. * 0 for no restriction
  259. * 1 for 1/4 us
  260. * 2 for 1/2 us
  261. * 3 for 1 us
  262. * 4 for 2 us
  263. * 5 for 4 us
  264. * 6 for 8 us
  265. * 7 for 16 us
  266. */
  267. switch (mpdudensity) {
  268. case 0:
  269. return 0;
  270. case 1:
  271. case 2:
  272. case 3:
  273. /* Our lower layer calculations limit our precision to
  274. 1 microsecond */
  275. return 1;
  276. case 4:
  277. return 2;
  278. case 5:
  279. return 4;
  280. case 6:
  281. return 8;
  282. case 7:
  283. return 16;
  284. default:
  285. return 0;
  286. }
  287. }
  288. static int ath9k_start(struct ieee80211_hw *hw)
  289. {
  290. struct ath_softc *sc = hw->priv;
  291. struct ieee80211_channel *curchan = hw->conf.channel;
  292. int error = 0, pos;
  293. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  294. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  295. /* setup initial channel */
  296. pos = ath_get_channel(sc, curchan);
  297. if (pos == -1) {
  298. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  299. return -EINVAL;
  300. }
  301. sc->sc_ah->ah_channels[pos].chanmode =
  302. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  303. /* open ath_dev */
  304. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  305. if (error) {
  306. DPRINTF(sc, ATH_DBG_FATAL,
  307. "%s: Unable to complete ath_open\n", __func__);
  308. return error;
  309. }
  310. ieee80211_wake_queues(hw);
  311. return 0;
  312. }
  313. static int ath9k_tx(struct ieee80211_hw *hw,
  314. struct sk_buff *skb)
  315. {
  316. struct ath_softc *sc = hw->priv;
  317. int hdrlen, padsize;
  318. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  319. /*
  320. * As a temporary workaround, assign seq# here; this will likely need
  321. * to be cleaned up to work better with Beacon transmission and virtual
  322. * BSSes.
  323. */
  324. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  325. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  326. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  327. sc->seq_no += 0x10;
  328. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  329. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  330. }
  331. /* Add the padding after the header if this is not already done */
  332. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  333. if (hdrlen & 3) {
  334. padsize = hdrlen % 4;
  335. if (skb_headroom(skb) < padsize)
  336. return -1;
  337. skb_push(skb, padsize);
  338. memmove(skb->data, skb->data + padsize, hdrlen);
  339. }
  340. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  341. __func__,
  342. skb);
  343. if (ath_tx_start(sc, skb) != 0) {
  344. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  345. dev_kfree_skb_any(skb);
  346. /* FIXME: Check for proper return value from ATH_DEV */
  347. return 0;
  348. }
  349. return 0;
  350. }
  351. static void ath9k_stop(struct ieee80211_hw *hw)
  352. {
  353. struct ath_softc *sc = hw->priv;
  354. int error;
  355. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  356. error = ath_suspend(sc);
  357. if (error)
  358. DPRINTF(sc, ATH_DBG_CONFIG,
  359. "%s: Device is no longer present\n", __func__);
  360. ieee80211_stop_queues(hw);
  361. }
  362. static int ath9k_add_interface(struct ieee80211_hw *hw,
  363. struct ieee80211_if_init_conf *conf)
  364. {
  365. struct ath_softc *sc = hw->priv;
  366. int error, ic_opmode = 0;
  367. /* Support only vap for now */
  368. if (sc->sc_nvaps)
  369. return -ENOBUFS;
  370. switch (conf->type) {
  371. case IEEE80211_IF_TYPE_STA:
  372. ic_opmode = ATH9K_M_STA;
  373. break;
  374. case IEEE80211_IF_TYPE_IBSS:
  375. ic_opmode = ATH9K_M_IBSS;
  376. break;
  377. default:
  378. DPRINTF(sc, ATH_DBG_FATAL,
  379. "%s: Only STA and IBSS are supported currently\n",
  380. __func__);
  381. return -EOPNOTSUPP;
  382. }
  383. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  384. __func__,
  385. ic_opmode);
  386. error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
  387. if (error) {
  388. DPRINTF(sc, ATH_DBG_FATAL,
  389. "%s: Unable to attach vap, error: %d\n",
  390. __func__, error);
  391. return error;
  392. }
  393. return 0;
  394. }
  395. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  396. struct ieee80211_if_init_conf *conf)
  397. {
  398. struct ath_softc *sc = hw->priv;
  399. struct ath_vap *avp;
  400. int error;
  401. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  402. avp = sc->sc_vaps[0];
  403. if (avp == NULL) {
  404. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  405. __func__);
  406. return;
  407. }
  408. #ifdef CONFIG_SLOW_ANT_DIV
  409. ath_slow_ant_div_stop(&sc->sc_antdiv);
  410. #endif
  411. /* Update ratectrl */
  412. ath_rate_newstate(sc, avp);
  413. /* Reclaim beacon resources */
  414. if (sc->sc_opmode == ATH9K_M_HOSTAP || sc->sc_opmode == ATH9K_M_IBSS) {
  415. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  416. ath_beacon_return(sc, avp);
  417. }
  418. /* Set interrupt mask */
  419. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  420. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
  421. sc->sc_beacons = 0;
  422. error = ath_vap_detach(sc, 0);
  423. if (error)
  424. DPRINTF(sc, ATH_DBG_FATAL,
  425. "%s: Unable to detach vap, error: %d\n",
  426. __func__, error);
  427. }
  428. static int ath9k_config(struct ieee80211_hw *hw,
  429. struct ieee80211_conf *conf)
  430. {
  431. struct ath_softc *sc = hw->priv;
  432. struct ieee80211_channel *curchan = hw->conf.channel;
  433. int pos;
  434. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  435. __func__,
  436. curchan->center_freq);
  437. pos = ath_get_channel(sc, curchan);
  438. if (pos == -1) {
  439. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  440. return -EINVAL;
  441. }
  442. sc->sc_ah->ah_channels[pos].chanmode =
  443. (curchan->band == IEEE80211_BAND_2GHZ) ?
  444. CHANNEL_G : CHANNEL_A;
  445. if (sc->sc_curaid && hw->conf.ht_conf.ht_supported)
  446. sc->sc_ah->ah_channels[pos].chanmode =
  447. ath_get_extchanmode(sc, curchan);
  448. sc->sc_config.txpowlimit = 2 * conf->power_level;
  449. /* set h/w channel */
  450. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  451. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  452. __func__);
  453. return 0;
  454. }
  455. static int ath9k_config_interface(struct ieee80211_hw *hw,
  456. struct ieee80211_vif *vif,
  457. struct ieee80211_if_conf *conf)
  458. {
  459. struct ath_softc *sc = hw->priv;
  460. struct ath_vap *avp;
  461. u32 rfilt = 0;
  462. int error, i;
  463. DECLARE_MAC_BUF(mac);
  464. avp = sc->sc_vaps[0];
  465. if (avp == NULL) {
  466. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  467. __func__);
  468. return -EINVAL;
  469. }
  470. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  471. !is_zero_ether_addr(conf->bssid)) {
  472. switch (vif->type) {
  473. case IEEE80211_IF_TYPE_STA:
  474. case IEEE80211_IF_TYPE_IBSS:
  475. /* Update ratectrl about the new state */
  476. ath_rate_newstate(sc, avp);
  477. /* Set rx filter */
  478. rfilt = ath_calcrxfilter(sc);
  479. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  480. /* Set BSSID */
  481. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  482. sc->sc_curaid = 0;
  483. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  484. sc->sc_curaid);
  485. /* Set aggregation protection mode parameters */
  486. sc->sc_config.ath_aggr_prot = 0;
  487. /*
  488. * Reset our TSF so that its value is lower than the
  489. * beacon that we are trying to catch.
  490. * Only then hw will update its TSF register with the
  491. * new beacon. Reset the TSF before setting the BSSID
  492. * to avoid allowing in any frames that would update
  493. * our TSF only to have us clear it
  494. * immediately thereafter.
  495. */
  496. ath9k_hw_reset_tsf(sc->sc_ah);
  497. /* Disable BMISS interrupt when we're not associated */
  498. ath9k_hw_set_interrupts(sc->sc_ah,
  499. sc->sc_imask &
  500. ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  501. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  502. DPRINTF(sc, ATH_DBG_CONFIG,
  503. "%s: RX filter 0x%x bssid %s aid 0x%x\n",
  504. __func__, rfilt,
  505. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  506. /* need to reconfigure the beacon */
  507. sc->sc_beacons = 0;
  508. break;
  509. default:
  510. break;
  511. }
  512. }
  513. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  514. (vif->type == IEEE80211_IF_TYPE_IBSS)) {
  515. /*
  516. * Allocate and setup the beacon frame.
  517. *
  518. * Stop any previous beacon DMA. This may be
  519. * necessary, for example, when an ibss merge
  520. * causes reconfiguration; we may be called
  521. * with beacon transmission active.
  522. */
  523. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  524. error = ath_beacon_alloc(sc, 0);
  525. if (error != 0)
  526. return error;
  527. ath_beacon_sync(sc, 0);
  528. }
  529. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  530. if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
  531. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  532. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  533. ath9k_hw_keysetmac(sc->sc_ah,
  534. (u16)i,
  535. sc->sc_curbssid);
  536. }
  537. /* Only legacy IBSS for now */
  538. if (vif->type == IEEE80211_IF_TYPE_IBSS)
  539. ath_update_chainmask(sc, 0);
  540. return 0;
  541. }
  542. #define SUPPORTED_FILTERS \
  543. (FIF_PROMISC_IN_BSS | \
  544. FIF_ALLMULTI | \
  545. FIF_CONTROL | \
  546. FIF_OTHER_BSS | \
  547. FIF_BCN_PRBRESP_PROMISC | \
  548. FIF_FCSFAIL)
  549. /* Accept unicast, bcast and mcast frames */
  550. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  551. unsigned int changed_flags,
  552. unsigned int *total_flags,
  553. int mc_count,
  554. struct dev_mc_list *mclist)
  555. {
  556. struct ath_softc *sc = hw->priv;
  557. changed_flags &= SUPPORTED_FILTERS;
  558. *total_flags &= SUPPORTED_FILTERS;
  559. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  560. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  561. ath_scan_start(sc);
  562. else
  563. ath_scan_end(sc);
  564. }
  565. }
  566. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  567. struct ieee80211_vif *vif,
  568. enum sta_notify_cmd cmd,
  569. const u8 *addr)
  570. {
  571. struct ath_softc *sc = hw->priv;
  572. struct ath_node *an;
  573. unsigned long flags;
  574. DECLARE_MAC_BUF(mac);
  575. spin_lock_irqsave(&sc->node_lock, flags);
  576. an = ath_node_find(sc, (u8 *) addr);
  577. spin_unlock_irqrestore(&sc->node_lock, flags);
  578. switch (cmd) {
  579. case STA_NOTIFY_ADD:
  580. spin_lock_irqsave(&sc->node_lock, flags);
  581. if (!an) {
  582. ath_node_attach(sc, (u8 *)addr, 0);
  583. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %s\n",
  584. __func__,
  585. print_mac(mac, addr));
  586. } else {
  587. ath_node_get(sc, (u8 *)addr);
  588. }
  589. spin_unlock_irqrestore(&sc->node_lock, flags);
  590. break;
  591. case STA_NOTIFY_REMOVE:
  592. if (!an)
  593. DPRINTF(sc, ATH_DBG_FATAL,
  594. "%s: Removal of a non-existent node\n",
  595. __func__);
  596. else {
  597. ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
  598. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %s\n",
  599. __func__,
  600. print_mac(mac, addr));
  601. }
  602. break;
  603. default:
  604. break;
  605. }
  606. }
  607. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  608. u16 queue,
  609. const struct ieee80211_tx_queue_params *params)
  610. {
  611. struct ath_softc *sc = hw->priv;
  612. struct ath9k_tx_queue_info qi;
  613. int ret = 0, qnum;
  614. if (queue >= WME_NUM_AC)
  615. return 0;
  616. qi.tqi_aifs = params->aifs;
  617. qi.tqi_cwmin = params->cw_min;
  618. qi.tqi_cwmax = params->cw_max;
  619. qi.tqi_burstTime = params->txop;
  620. qnum = ath_get_hal_qnum(queue, sc);
  621. DPRINTF(sc, ATH_DBG_CONFIG,
  622. "%s: Configure tx [queue/halq] [%d/%d], "
  623. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  624. __func__,
  625. queue,
  626. qnum,
  627. params->aifs,
  628. params->cw_min,
  629. params->cw_max,
  630. params->txop);
  631. ret = ath_txq_update(sc, qnum, &qi);
  632. if (ret)
  633. DPRINTF(sc, ATH_DBG_FATAL,
  634. "%s: TXQ Update failed\n", __func__);
  635. return ret;
  636. }
  637. static int ath9k_set_key(struct ieee80211_hw *hw,
  638. enum set_key_cmd cmd,
  639. const u8 *local_addr,
  640. const u8 *addr,
  641. struct ieee80211_key_conf *key)
  642. {
  643. struct ath_softc *sc = hw->priv;
  644. int ret = 0;
  645. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  646. switch (cmd) {
  647. case SET_KEY:
  648. ret = ath_key_config(sc, addr, key);
  649. if (!ret) {
  650. set_bit(key->keyidx, sc->sc_keymap);
  651. key->hw_key_idx = key->keyidx;
  652. /* push IV and Michael MIC generation to stack */
  653. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  654. if (key->alg == ALG_TKIP)
  655. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  656. }
  657. break;
  658. case DISABLE_KEY:
  659. ath_key_delete(sc, key);
  660. clear_bit(key->keyidx, sc->sc_keymap);
  661. break;
  662. default:
  663. ret = -EINVAL;
  664. }
  665. return ret;
  666. }
  667. static void ath9k_ht_conf(struct ath_softc *sc,
  668. struct ieee80211_bss_conf *bss_conf)
  669. {
  670. #define IEEE80211_HT_CAP_40MHZ_INTOLERANT BIT(14)
  671. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  672. if (bss_conf->assoc_ht) {
  673. ht_info->ext_chan_offset =
  674. bss_conf->ht_bss_conf->bss_cap &
  675. IEEE80211_HT_IE_CHA_SEC_OFFSET;
  676. if (!(bss_conf->ht_conf->cap &
  677. IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
  678. (bss_conf->ht_bss_conf->bss_cap &
  679. IEEE80211_HT_IE_CHA_WIDTH))
  680. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  681. else
  682. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  683. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  684. ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
  685. bss_conf->ht_conf->ampdu_factor);
  686. ht_info->mpdudensity =
  687. parse_mpdudensity(bss_conf->ht_conf->ampdu_density);
  688. }
  689. #undef IEEE80211_HT_CAP_40MHZ_INTOLERANT
  690. }
  691. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  692. struct ieee80211_bss_conf *bss_conf)
  693. {
  694. struct ieee80211_hw *hw = sc->hw;
  695. struct ieee80211_channel *curchan = hw->conf.channel;
  696. struct ath_vap *avp;
  697. int pos;
  698. DECLARE_MAC_BUF(mac);
  699. if (bss_conf->assoc) {
  700. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  701. __func__,
  702. bss_conf->aid);
  703. avp = sc->sc_vaps[0];
  704. if (avp == NULL) {
  705. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  706. __func__);
  707. return;
  708. }
  709. /* New association, store aid */
  710. if (avp->av_opmode == ATH9K_M_STA) {
  711. sc->sc_curaid = bss_conf->aid;
  712. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  713. sc->sc_curaid);
  714. }
  715. /* Configure the beacon */
  716. ath_beacon_config(sc, 0);
  717. sc->sc_beacons = 1;
  718. /* Reset rssi stats */
  719. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  720. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  721. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  722. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  723. /* Update chainmask */
  724. ath_update_chainmask(sc, bss_conf->assoc_ht);
  725. DPRINTF(sc, ATH_DBG_CONFIG,
  726. "%s: bssid %s aid 0x%x\n",
  727. __func__,
  728. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  729. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  730. __func__,
  731. curchan->center_freq);
  732. pos = ath_get_channel(sc, curchan);
  733. if (pos == -1) {
  734. DPRINTF(sc, ATH_DBG_FATAL,
  735. "%s: Invalid channel\n", __func__);
  736. return;
  737. }
  738. if (hw->conf.ht_conf.ht_supported)
  739. sc->sc_ah->ah_channels[pos].chanmode =
  740. ath_get_extchanmode(sc, curchan);
  741. else
  742. sc->sc_ah->ah_channels[pos].chanmode =
  743. (curchan->band == IEEE80211_BAND_2GHZ) ?
  744. CHANNEL_G : CHANNEL_A;
  745. /* set h/w channel */
  746. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  747. DPRINTF(sc, ATH_DBG_FATAL,
  748. "%s: Unable to set channel\n",
  749. __func__);
  750. ath_rate_newstate(sc, avp);
  751. /* Update ratectrl about the new state */
  752. ath_rc_node_update(hw, avp->rc_node);
  753. } else {
  754. DPRINTF(sc, ATH_DBG_CONFIG,
  755. "%s: Bss Info DISSOC\n", __func__);
  756. sc->sc_curaid = 0;
  757. }
  758. }
  759. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  760. struct ieee80211_vif *vif,
  761. struct ieee80211_bss_conf *bss_conf,
  762. u32 changed)
  763. {
  764. struct ath_softc *sc = hw->priv;
  765. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  766. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  767. __func__,
  768. bss_conf->use_short_preamble);
  769. if (bss_conf->use_short_preamble)
  770. sc->sc_flags |= ATH_PREAMBLE_SHORT;
  771. else
  772. sc->sc_flags &= ~ATH_PREAMBLE_SHORT;
  773. }
  774. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  775. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  776. __func__,
  777. bss_conf->use_cts_prot);
  778. if (bss_conf->use_cts_prot &&
  779. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  780. sc->sc_flags |= ATH_PROTECT_ENABLE;
  781. else
  782. sc->sc_flags &= ~ATH_PROTECT_ENABLE;
  783. }
  784. if (changed & BSS_CHANGED_HT) {
  785. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
  786. __func__,
  787. bss_conf->assoc_ht);
  788. ath9k_ht_conf(sc, bss_conf);
  789. }
  790. if (changed & BSS_CHANGED_ASSOC) {
  791. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  792. __func__,
  793. bss_conf->assoc);
  794. ath9k_bss_assoc_info(sc, bss_conf);
  795. }
  796. }
  797. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  798. {
  799. u64 tsf;
  800. struct ath_softc *sc = hw->priv;
  801. struct ath_hal *ah = sc->sc_ah;
  802. tsf = ath9k_hw_gettsf64(ah);
  803. return tsf;
  804. }
  805. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  806. {
  807. struct ath_softc *sc = hw->priv;
  808. struct ath_hal *ah = sc->sc_ah;
  809. ath9k_hw_reset_tsf(ah);
  810. }
  811. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  812. enum ieee80211_ampdu_mlme_action action,
  813. const u8 *addr,
  814. u16 tid,
  815. u16 *ssn)
  816. {
  817. struct ath_softc *sc = hw->priv;
  818. int ret = 0;
  819. switch (action) {
  820. case IEEE80211_AMPDU_RX_START:
  821. ret = ath_rx_aggr_start(sc, addr, tid, ssn);
  822. if (ret < 0)
  823. DPRINTF(sc, ATH_DBG_FATAL,
  824. "%s: Unable to start RX aggregation\n",
  825. __func__);
  826. break;
  827. case IEEE80211_AMPDU_RX_STOP:
  828. ret = ath_rx_aggr_stop(sc, addr, tid);
  829. if (ret < 0)
  830. DPRINTF(sc, ATH_DBG_FATAL,
  831. "%s: Unable to stop RX aggregation\n",
  832. __func__);
  833. break;
  834. case IEEE80211_AMPDU_TX_START:
  835. ret = ath_tx_aggr_start(sc, addr, tid, ssn);
  836. if (ret < 0)
  837. DPRINTF(sc, ATH_DBG_FATAL,
  838. "%s: Unable to start TX aggregation\n",
  839. __func__);
  840. else
  841. ieee80211_start_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
  842. break;
  843. case IEEE80211_AMPDU_TX_STOP:
  844. ret = ath_tx_aggr_stop(sc, addr, tid);
  845. if (ret < 0)
  846. DPRINTF(sc, ATH_DBG_FATAL,
  847. "%s: Unable to stop TX aggregation\n",
  848. __func__);
  849. ieee80211_stop_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
  850. break;
  851. default:
  852. DPRINTF(sc, ATH_DBG_FATAL,
  853. "%s: Unknown AMPDU action\n", __func__);
  854. }
  855. return ret;
  856. }
  857. static struct ieee80211_ops ath9k_ops = {
  858. .tx = ath9k_tx,
  859. .start = ath9k_start,
  860. .stop = ath9k_stop,
  861. .add_interface = ath9k_add_interface,
  862. .remove_interface = ath9k_remove_interface,
  863. .config = ath9k_config,
  864. .config_interface = ath9k_config_interface,
  865. .configure_filter = ath9k_configure_filter,
  866. .get_stats = NULL,
  867. .sta_notify = ath9k_sta_notify,
  868. .conf_tx = ath9k_conf_tx,
  869. .get_tx_stats = NULL,
  870. .bss_info_changed = ath9k_bss_info_changed,
  871. .set_tim = NULL,
  872. .set_key = ath9k_set_key,
  873. .hw_scan = NULL,
  874. .get_tkip_seq = NULL,
  875. .set_rts_threshold = NULL,
  876. .set_frag_threshold = NULL,
  877. .set_retry_limit = NULL,
  878. .get_tsf = ath9k_get_tsf,
  879. .reset_tsf = ath9k_reset_tsf,
  880. .tx_last_beacon = NULL,
  881. .ampdu_action = ath9k_ampdu_action
  882. };
  883. void ath_get_beaconconfig(struct ath_softc *sc,
  884. int if_id,
  885. struct ath_beacon_config *conf)
  886. {
  887. struct ieee80211_hw *hw = sc->hw;
  888. /* fill in beacon config data */
  889. conf->beacon_interval = hw->conf.beacon_int;
  890. conf->listen_interval = 100;
  891. conf->dtim_count = 1;
  892. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  893. }
  894. int ath_update_beacon(struct ath_softc *sc,
  895. int if_id,
  896. struct ath_beacon_offset *bo,
  897. struct sk_buff *skb,
  898. int mcast)
  899. {
  900. return 0;
  901. }
  902. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  903. struct ath_xmit_status *tx_status, struct ath_node *an)
  904. {
  905. struct ieee80211_hw *hw = sc->hw;
  906. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  907. DPRINTF(sc, ATH_DBG_XMIT,
  908. "%s: TX complete: skb: %p\n", __func__, skb);
  909. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  910. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  911. /* free driver's private data area of tx_info */
  912. if (tx_info->driver_data[0] != NULL)
  913. kfree(tx_info->driver_data[0]);
  914. tx_info->driver_data[0] = NULL;
  915. }
  916. if (tx_status->flags & ATH_TX_BAR) {
  917. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  918. tx_status->flags &= ~ATH_TX_BAR;
  919. }
  920. if (tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY)) {
  921. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  922. /* Frame was not ACKed, but an ACK was expected */
  923. tx_info->status.excessive_retries = 1;
  924. }
  925. } else {
  926. /* Frame was ACKed */
  927. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  928. }
  929. tx_info->status.retry_count = tx_status->retries;
  930. ieee80211_tx_status(hw, skb);
  931. if (an)
  932. ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
  933. }
  934. int ath__rx_indicate(struct ath_softc *sc,
  935. struct sk_buff *skb,
  936. struct ath_recv_status *status,
  937. u16 keyix)
  938. {
  939. struct ieee80211_hw *hw = sc->hw;
  940. struct ath_node *an = NULL;
  941. struct ieee80211_rx_status rx_status;
  942. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  943. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  944. int padsize;
  945. enum ATH_RX_TYPE st;
  946. /* see if any padding is done by the hw and remove it */
  947. if (hdrlen & 3) {
  948. padsize = hdrlen % 4;
  949. memmove(skb->data + padsize, skb->data, hdrlen);
  950. skb_pull(skb, padsize);
  951. }
  952. /* remove FCS before passing up to protocol stack */
  953. skb_trim(skb, (skb->len - FCS_LEN));
  954. /* Prepare rx status */
  955. ath9k_rx_prepare(sc, skb, status, &rx_status);
  956. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  957. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  958. rx_status.flag |= RX_FLAG_DECRYPTED;
  959. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  960. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  961. && skb->len >= hdrlen + 4) {
  962. keyix = skb->data[hdrlen + 3] >> 6;
  963. if (test_bit(keyix, sc->sc_keymap))
  964. rx_status.flag |= RX_FLAG_DECRYPTED;
  965. }
  966. spin_lock_bh(&sc->node_lock);
  967. an = ath_node_find(sc, hdr->addr2);
  968. spin_unlock_bh(&sc->node_lock);
  969. if (an) {
  970. ath_rx_input(sc, an,
  971. hw->conf.ht_conf.ht_supported,
  972. skb, status, &st);
  973. }
  974. if (!an || (st != ATH_RX_CONSUMED))
  975. __ieee80211_rx(hw, skb, &rx_status);
  976. return 0;
  977. }
  978. int ath_rx_subframe(struct ath_node *an,
  979. struct sk_buff *skb,
  980. struct ath_recv_status *status)
  981. {
  982. struct ath_softc *sc = an->an_sc;
  983. struct ieee80211_hw *hw = sc->hw;
  984. struct ieee80211_rx_status rx_status;
  985. /* Prepare rx status */
  986. ath9k_rx_prepare(sc, skb, status, &rx_status);
  987. if (!(status->flags & ATH_RX_DECRYPT_ERROR))
  988. rx_status.flag |= RX_FLAG_DECRYPTED;
  989. __ieee80211_rx(hw, skb, &rx_status);
  990. return 0;
  991. }
  992. enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
  993. {
  994. return sc->sc_ht_info.tx_chan_width;
  995. }
  996. static int ath_detach(struct ath_softc *sc)
  997. {
  998. struct ieee80211_hw *hw = sc->hw;
  999. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  1000. /* Unregister hw */
  1001. ieee80211_unregister_hw(hw);
  1002. /* unregister Rate control */
  1003. ath_rate_control_unregister();
  1004. /* tx/rx cleanup */
  1005. ath_rx_cleanup(sc);
  1006. ath_tx_cleanup(sc);
  1007. /* Deinit */
  1008. ath_deinit(sc);
  1009. return 0;
  1010. }
  1011. static int ath_attach(u16 devid,
  1012. struct ath_softc *sc)
  1013. {
  1014. struct ieee80211_hw *hw = sc->hw;
  1015. int error = 0;
  1016. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  1017. error = ath_init(devid, sc);
  1018. if (error != 0)
  1019. return error;
  1020. /* Init nodes */
  1021. INIT_LIST_HEAD(&sc->node_list);
  1022. spin_lock_init(&sc->node_lock);
  1023. /* get mac address from hardware and set in mac80211 */
  1024. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  1025. /* setup channels and rates */
  1026. sc->sbands[IEEE80211_BAND_2GHZ].channels =
  1027. sc->channels[IEEE80211_BAND_2GHZ];
  1028. sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
  1029. sc->rates[IEEE80211_BAND_2GHZ];
  1030. sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  1031. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  1032. /* Setup HT capabilities for 2.4Ghz*/
  1033. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
  1034. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1035. &sc->sbands[IEEE80211_BAND_2GHZ];
  1036. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
  1037. sc->sbands[IEEE80211_BAND_5GHZ].channels =
  1038. sc->channels[IEEE80211_BAND_5GHZ];
  1039. sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
  1040. sc->rates[IEEE80211_BAND_5GHZ];
  1041. sc->sbands[IEEE80211_BAND_5GHZ].band =
  1042. IEEE80211_BAND_5GHZ;
  1043. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  1044. /* Setup HT capabilities for 5Ghz*/
  1045. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
  1046. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1047. &sc->sbands[IEEE80211_BAND_5GHZ];
  1048. }
  1049. /* FIXME: Have to figure out proper hw init values later */
  1050. hw->queues = 4;
  1051. hw->ampdu_queues = 1;
  1052. /* Register rate control */
  1053. hw->rate_control_algorithm = "ath9k_rate_control";
  1054. error = ath_rate_control_register();
  1055. if (error != 0) {
  1056. DPRINTF(sc, ATH_DBG_FATAL,
  1057. "%s: Unable to register rate control "
  1058. "algorithm:%d\n", __func__, error);
  1059. ath_rate_control_unregister();
  1060. goto bad;
  1061. }
  1062. error = ieee80211_register_hw(hw);
  1063. if (error != 0) {
  1064. ath_rate_control_unregister();
  1065. goto bad;
  1066. }
  1067. /* initialize tx/rx engine */
  1068. error = ath_tx_init(sc, ATH_TXBUF);
  1069. if (error != 0)
  1070. goto bad1;
  1071. error = ath_rx_init(sc, ATH_RXBUF);
  1072. if (error != 0)
  1073. goto bad1;
  1074. return 0;
  1075. bad1:
  1076. ath_detach(sc);
  1077. bad:
  1078. return error;
  1079. }
  1080. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1081. {
  1082. void __iomem *mem;
  1083. struct ath_softc *sc;
  1084. struct ieee80211_hw *hw;
  1085. const char *athname;
  1086. u8 csz;
  1087. u32 val;
  1088. int ret = 0;
  1089. if (pci_enable_device(pdev))
  1090. return -EIO;
  1091. /* XXX 32-bit addressing only */
  1092. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1093. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1094. ret = -ENODEV;
  1095. goto bad;
  1096. }
  1097. /*
  1098. * Cache line size is used to size and align various
  1099. * structures used to communicate with the hardware.
  1100. */
  1101. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1102. if (csz == 0) {
  1103. /*
  1104. * Linux 2.4.18 (at least) writes the cache line size
  1105. * register as a 16-bit wide register which is wrong.
  1106. * We must have this setup properly for rx buffer
  1107. * DMA to work so force a reasonable value here if it
  1108. * comes up zero.
  1109. */
  1110. csz = L1_CACHE_BYTES / sizeof(u32);
  1111. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1112. }
  1113. /*
  1114. * The default setting of latency timer yields poor results,
  1115. * set it to the value used by other systems. It may be worth
  1116. * tweaking this setting more.
  1117. */
  1118. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1119. pci_set_master(pdev);
  1120. /*
  1121. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1122. * PCI Tx retries from interfering with C3 CPU state.
  1123. */
  1124. pci_read_config_dword(pdev, 0x40, &val);
  1125. if ((val & 0x0000ff00) != 0)
  1126. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1127. ret = pci_request_region(pdev, 0, "ath9k");
  1128. if (ret) {
  1129. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1130. ret = -ENODEV;
  1131. goto bad;
  1132. }
  1133. mem = pci_iomap(pdev, 0, 0);
  1134. if (!mem) {
  1135. printk(KERN_ERR "PCI memory map error\n") ;
  1136. ret = -EIO;
  1137. goto bad1;
  1138. }
  1139. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1140. if (hw == NULL) {
  1141. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1142. goto bad2;
  1143. }
  1144. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1145. IEEE80211_HW_NOISE_DBM;
  1146. SET_IEEE80211_DEV(hw, &pdev->dev);
  1147. pci_set_drvdata(pdev, hw);
  1148. sc = hw->priv;
  1149. sc->hw = hw;
  1150. sc->pdev = pdev;
  1151. sc->mem = mem;
  1152. if (ath_attach(id->device, sc) != 0) {
  1153. ret = -ENODEV;
  1154. goto bad3;
  1155. }
  1156. /* setup interrupt service routine */
  1157. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1158. printk(KERN_ERR "%s: request_irq failed\n",
  1159. wiphy_name(hw->wiphy));
  1160. ret = -EIO;
  1161. goto bad4;
  1162. }
  1163. athname = ath9k_hw_probe(id->vendor, id->device);
  1164. printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
  1165. wiphy_name(hw->wiphy),
  1166. athname ? athname : "Atheros ???",
  1167. (unsigned long)mem, pdev->irq);
  1168. return 0;
  1169. bad4:
  1170. ath_detach(sc);
  1171. bad3:
  1172. ieee80211_free_hw(hw);
  1173. bad2:
  1174. pci_iounmap(pdev, mem);
  1175. bad1:
  1176. pci_release_region(pdev, 0);
  1177. bad:
  1178. pci_disable_device(pdev);
  1179. return ret;
  1180. }
  1181. static void ath_pci_remove(struct pci_dev *pdev)
  1182. {
  1183. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1184. struct ath_softc *sc = hw->priv;
  1185. if (pdev->irq)
  1186. free_irq(pdev->irq, sc);
  1187. ath_detach(sc);
  1188. pci_iounmap(pdev, sc->mem);
  1189. pci_release_region(pdev, 0);
  1190. pci_disable_device(pdev);
  1191. ieee80211_free_hw(hw);
  1192. }
  1193. #ifdef CONFIG_PM
  1194. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1195. {
  1196. pci_save_state(pdev);
  1197. pci_disable_device(pdev);
  1198. pci_set_power_state(pdev, 3);
  1199. return 0;
  1200. }
  1201. static int ath_pci_resume(struct pci_dev *pdev)
  1202. {
  1203. u32 val;
  1204. int err;
  1205. err = pci_enable_device(pdev);
  1206. if (err)
  1207. return err;
  1208. pci_restore_state(pdev);
  1209. /*
  1210. * Suspend/Resume resets the PCI configuration space, so we have to
  1211. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1212. * PCI Tx retries from interfering with C3 CPU state
  1213. */
  1214. pci_read_config_dword(pdev, 0x40, &val);
  1215. if ((val & 0x0000ff00) != 0)
  1216. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1217. return 0;
  1218. }
  1219. #endif /* CONFIG_PM */
  1220. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1221. static struct pci_driver ath_pci_driver = {
  1222. .name = "ath9k",
  1223. .id_table = ath_pci_id_table,
  1224. .probe = ath_pci_probe,
  1225. .remove = ath_pci_remove,
  1226. #ifdef CONFIG_PM
  1227. .suspend = ath_pci_suspend,
  1228. .resume = ath_pci_resume,
  1229. #endif /* CONFIG_PM */
  1230. };
  1231. static int __init init_ath_pci(void)
  1232. {
  1233. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1234. if (pci_register_driver(&ath_pci_driver) < 0) {
  1235. printk(KERN_ERR
  1236. "ath_pci: No devices found, driver not installed.\n");
  1237. pci_unregister_driver(&ath_pci_driver);
  1238. return -ENODEV;
  1239. }
  1240. return 0;
  1241. }
  1242. module_init(init_ath_pci);
  1243. static void __exit exit_ath_pci(void)
  1244. {
  1245. pci_unregister_driver(&ath_pci_driver);
  1246. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1247. }
  1248. module_exit(exit_ath_pci);