cx23885-dvb.c 23 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "tda10048.h"
  39. #include "tuner-xc2028.h"
  40. #include "tuner-simple.h"
  41. #include "dib7000p.h"
  42. #include "dibx000_common.h"
  43. #include "zl10353.h"
  44. #include "stv0900.h"
  45. #include "stv6110.h"
  46. #include "lnbh24.h"
  47. #include "cx24116.h"
  48. #include "cimax2.h"
  49. #include "netup-eeprom.h"
  50. #include "netup-init.h"
  51. #include "lgdt3305.h"
  52. static unsigned int debug;
  53. #define dprintk(level, fmt, arg...)\
  54. do { if (debug >= level)\
  55. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  56. } while (0)
  57. /* ------------------------------------------------------------------ */
  58. static unsigned int alt_tuner;
  59. module_param(alt_tuner, int, 0644);
  60. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  61. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  62. /* ------------------------------------------------------------------ */
  63. static int dvb_buf_setup(struct videobuf_queue *q,
  64. unsigned int *count, unsigned int *size)
  65. {
  66. struct cx23885_tsport *port = q->priv_data;
  67. port->ts_packet_size = 188 * 4;
  68. port->ts_packet_count = 32;
  69. *size = port->ts_packet_size * port->ts_packet_count;
  70. *count = 32;
  71. return 0;
  72. }
  73. static int dvb_buf_prepare(struct videobuf_queue *q,
  74. struct videobuf_buffer *vb, enum v4l2_field field)
  75. {
  76. struct cx23885_tsport *port = q->priv_data;
  77. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  78. }
  79. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  80. {
  81. struct cx23885_tsport *port = q->priv_data;
  82. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  83. }
  84. static void dvb_buf_release(struct videobuf_queue *q,
  85. struct videobuf_buffer *vb)
  86. {
  87. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  88. }
  89. static struct videobuf_queue_ops dvb_qops = {
  90. .buf_setup = dvb_buf_setup,
  91. .buf_prepare = dvb_buf_prepare,
  92. .buf_queue = dvb_buf_queue,
  93. .buf_release = dvb_buf_release,
  94. };
  95. static struct s5h1409_config hauppauge_generic_config = {
  96. .demod_address = 0x32 >> 1,
  97. .output_mode = S5H1409_SERIAL_OUTPUT,
  98. .gpio = S5H1409_GPIO_ON,
  99. .qam_if = 44000,
  100. .inversion = S5H1409_INVERSION_OFF,
  101. .status_mode = S5H1409_DEMODLOCKING,
  102. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  103. };
  104. static struct tda10048_config hauppauge_hvr1200_config = {
  105. .demod_address = 0x10 >> 1,
  106. .output_mode = TDA10048_SERIAL_OUTPUT,
  107. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  108. .inversion = TDA10048_INVERSION_ON,
  109. .if_freq_khz = TDA10048_IF_4300,
  110. .clk_freq_khz = TDA10048_CLK_16000,
  111. };
  112. static struct s5h1409_config hauppauge_ezqam_config = {
  113. .demod_address = 0x32 >> 1,
  114. .output_mode = S5H1409_SERIAL_OUTPUT,
  115. .gpio = S5H1409_GPIO_OFF,
  116. .qam_if = 4000,
  117. .inversion = S5H1409_INVERSION_ON,
  118. .status_mode = S5H1409_DEMODLOCKING,
  119. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  120. };
  121. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  122. .demod_address = 0x32 >> 1,
  123. .output_mode = S5H1409_SERIAL_OUTPUT,
  124. .gpio = S5H1409_GPIO_OFF,
  125. .qam_if = 44000,
  126. .inversion = S5H1409_INVERSION_OFF,
  127. .status_mode = S5H1409_DEMODLOCKING,
  128. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  129. };
  130. static struct s5h1409_config hauppauge_hvr1500_config = {
  131. .demod_address = 0x32 >> 1,
  132. .output_mode = S5H1409_SERIAL_OUTPUT,
  133. .gpio = S5H1409_GPIO_OFF,
  134. .inversion = S5H1409_INVERSION_OFF,
  135. .status_mode = S5H1409_DEMODLOCKING,
  136. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  137. };
  138. static struct mt2131_config hauppauge_generic_tunerconfig = {
  139. 0x61
  140. };
  141. static struct lgdt330x_config fusionhdtv_5_express = {
  142. .demod_address = 0x0e,
  143. .demod_chip = LGDT3303,
  144. .serial_mpeg = 0x40,
  145. };
  146. static struct s5h1409_config hauppauge_hvr1500q_config = {
  147. .demod_address = 0x32 >> 1,
  148. .output_mode = S5H1409_SERIAL_OUTPUT,
  149. .gpio = S5H1409_GPIO_ON,
  150. .qam_if = 44000,
  151. .inversion = S5H1409_INVERSION_OFF,
  152. .status_mode = S5H1409_DEMODLOCKING,
  153. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  154. };
  155. static struct s5h1409_config dvico_s5h1409_config = {
  156. .demod_address = 0x32 >> 1,
  157. .output_mode = S5H1409_SERIAL_OUTPUT,
  158. .gpio = S5H1409_GPIO_ON,
  159. .qam_if = 44000,
  160. .inversion = S5H1409_INVERSION_OFF,
  161. .status_mode = S5H1409_DEMODLOCKING,
  162. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  163. };
  164. static struct s5h1411_config dvico_s5h1411_config = {
  165. .output_mode = S5H1411_SERIAL_OUTPUT,
  166. .gpio = S5H1411_GPIO_ON,
  167. .qam_if = S5H1411_IF_44000,
  168. .vsb_if = S5H1411_IF_44000,
  169. .inversion = S5H1411_INVERSION_OFF,
  170. .status_mode = S5H1411_DEMODLOCKING,
  171. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  172. };
  173. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  174. .i2c_address = 0x61,
  175. .if_khz = 5380,
  176. };
  177. static struct xc5000_config dvico_xc5000_tunerconfig = {
  178. .i2c_address = 0x64,
  179. .if_khz = 5380,
  180. };
  181. static struct tda829x_config tda829x_no_probe = {
  182. .probe_tuner = TDA829X_DONT_PROBE,
  183. };
  184. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  185. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  186. .if_lvl = 6, .rfagc_top = 0x37 },
  187. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  188. .if_lvl = 6, .rfagc_top = 0x37 },
  189. };
  190. static struct tda18271_config hauppauge_tda18271_config = {
  191. .std_map = &hauppauge_tda18271_std_map,
  192. .gate = TDA18271_GATE_ANALOG,
  193. };
  194. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  195. .gate = TDA18271_GATE_ANALOG,
  196. };
  197. static struct tda18271_std_map hcw_lgdt3305_tda18271_std_map = {
  198. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  199. .if_lvl = 1, .rfagc_top = 0x58 },
  200. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  201. .if_lvl = 1, .rfagc_top = 0x58 },
  202. };
  203. static struct tda18271_config hcw_lgdt3305_tda18271_config = {
  204. .std_map = &hcw_lgdt3305_tda18271_std_map,
  205. };
  206. static struct lgdt3305_config hcw_lgdt3305_config = {
  207. .i2c_addr = 0x0e,
  208. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  209. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  210. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  211. .deny_i2c_rptr = 1,
  212. .spectral_inversion = 1,
  213. .qam_if_khz = 4000,
  214. .vsb_if_khz = 3250,
  215. };
  216. static struct dibx000_agc_config xc3028_agc_config = {
  217. BAND_VHF | BAND_UHF, /* band_caps */
  218. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  219. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  220. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  221. * P_agc_nb_est=2, P_agc_write=0
  222. */
  223. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  224. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  225. 712, /* inv_gain */
  226. 21, /* time_stabiliz */
  227. 0, /* alpha_level */
  228. 118, /* thlock */
  229. 0, /* wbd_inv */
  230. 2867, /* wbd_ref */
  231. 0, /* wbd_sel */
  232. 2, /* wbd_alpha */
  233. 0, /* agc1_max */
  234. 0, /* agc1_min */
  235. 39718, /* agc2_max */
  236. 9930, /* agc2_min */
  237. 0, /* agc1_pt1 */
  238. 0, /* agc1_pt2 */
  239. 0, /* agc1_pt3 */
  240. 0, /* agc1_slope1 */
  241. 0, /* agc1_slope2 */
  242. 0, /* agc2_pt1 */
  243. 128, /* agc2_pt2 */
  244. 29, /* agc2_slope1 */
  245. 29, /* agc2_slope2 */
  246. 17, /* alpha_mant */
  247. 27, /* alpha_exp */
  248. 23, /* beta_mant */
  249. 51, /* beta_exp */
  250. 1, /* perform_agc_softsplit */
  251. };
  252. /* PLL Configuration for COFDM BW_MHz = 8.000000
  253. * With external clock = 30.000000 */
  254. static struct dibx000_bandwidth_config xc3028_bw_config = {
  255. 60000, /* internal */
  256. 30000, /* sampling */
  257. 1, /* pll_cfg: prediv */
  258. 8, /* pll_cfg: ratio */
  259. 3, /* pll_cfg: range */
  260. 1, /* pll_cfg: reset */
  261. 0, /* pll_cfg: bypass */
  262. 0, /* misc: refdiv */
  263. 0, /* misc: bypclk_div */
  264. 1, /* misc: IO_CLK_en_core */
  265. 1, /* misc: ADClkSrc */
  266. 0, /* misc: modulo */
  267. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  268. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  269. 20452225, /* timf */
  270. 30000000 /* xtal_hz */
  271. };
  272. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  273. .output_mpeg2_in_188_bytes = 1,
  274. .hostbus_diversity = 1,
  275. .tuner_is_baseband = 0,
  276. .update_lna = NULL,
  277. .agc_config_count = 1,
  278. .agc = &xc3028_agc_config,
  279. .bw = &xc3028_bw_config,
  280. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  281. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  282. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  283. .pwm_freq_div = 0,
  284. .agc_control = NULL,
  285. .spur_protect = 0,
  286. .output_mode = OUTMODE_MPEG2_SERIAL,
  287. };
  288. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  289. .demod_address = 0x0f,
  290. .if2 = 45600,
  291. .no_tuner = 1,
  292. .disable_i2c_gate_ctrl = 1,
  293. };
  294. static struct stv0900_config netup_stv0900_config = {
  295. .demod_address = 0x68,
  296. .xtal = 27000000,
  297. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  298. .diseqc_mode = 2,/* 2/3 PWM */
  299. .path1_mode = 2,/*Serial continues clock */
  300. .path2_mode = 2,/*Serial continues clock */
  301. .tun1_maddress = 0,/* 0x60 */
  302. .tun2_maddress = 3,/* 0x63 */
  303. .tun1_adc = 1,/* 1 Vpp */
  304. .tun2_adc = 1,/* 1 Vpp */
  305. };
  306. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  307. .i2c_address = 0x60,
  308. .mclk = 27000000,
  309. .iq_wiring = 0,
  310. };
  311. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  312. .i2c_address = 0x63,
  313. .mclk = 27000000,
  314. .iq_wiring = 1,
  315. };
  316. static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  317. {
  318. struct cx23885_tsport *port = fe->dvb->priv;
  319. struct cx23885_dev *dev = port->dev;
  320. if (voltage == SEC_VOLTAGE_18)
  321. cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
  322. else if (voltage == SEC_VOLTAGE_13)
  323. cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
  324. else
  325. cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
  326. return 0;
  327. }
  328. static struct cx24116_config tbs_cx24116_config = {
  329. .demod_address = 0x05,
  330. };
  331. static struct cx24116_config tevii_cx24116_config = {
  332. .demod_address = 0x55,
  333. };
  334. static struct cx24116_config dvbworld_cx24116_config = {
  335. .demod_address = 0x05,
  336. };
  337. static int dvb_register(struct cx23885_tsport *port)
  338. {
  339. struct cx23885_dev *dev = port->dev;
  340. struct cx23885_i2c *i2c_bus = NULL;
  341. struct videobuf_dvb_frontend *fe0;
  342. int ret;
  343. /* Get the first frontend */
  344. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  345. if (!fe0)
  346. return -EINVAL;
  347. /* init struct videobuf_dvb */
  348. fe0->dvb.name = dev->name;
  349. /* init frontend */
  350. switch (dev->board) {
  351. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  352. i2c_bus = &dev->i2c_bus[0];
  353. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  354. &hauppauge_generic_config,
  355. &i2c_bus->i2c_adap);
  356. if (fe0->dvb.frontend != NULL) {
  357. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  358. &i2c_bus->i2c_adap,
  359. &hauppauge_generic_tunerconfig, 0);
  360. }
  361. break;
  362. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  363. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  364. i2c_bus = &dev->i2c_bus[0];
  365. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  366. &hcw_lgdt3305_config,
  367. &i2c_bus->i2c_adap);
  368. if (fe0->dvb.frontend != NULL) {
  369. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  370. 0x60, &dev->i2c_bus[1].i2c_adap,
  371. &hcw_lgdt3305_tda18271_config);
  372. }
  373. break;
  374. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  375. i2c_bus = &dev->i2c_bus[0];
  376. switch (alt_tuner) {
  377. case 1:
  378. fe0->dvb.frontend =
  379. dvb_attach(s5h1409_attach,
  380. &hauppauge_ezqam_config,
  381. &i2c_bus->i2c_adap);
  382. if (fe0->dvb.frontend != NULL) {
  383. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  384. &dev->i2c_bus[1].i2c_adap, 0x42,
  385. &tda829x_no_probe);
  386. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  387. 0x60, &dev->i2c_bus[1].i2c_adap,
  388. &hauppauge_tda18271_config);
  389. }
  390. break;
  391. case 0:
  392. default:
  393. fe0->dvb.frontend =
  394. dvb_attach(s5h1409_attach,
  395. &hauppauge_generic_config,
  396. &i2c_bus->i2c_adap);
  397. if (fe0->dvb.frontend != NULL)
  398. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  399. &i2c_bus->i2c_adap,
  400. &hauppauge_generic_tunerconfig, 0);
  401. break;
  402. }
  403. break;
  404. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  405. i2c_bus = &dev->i2c_bus[0];
  406. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  407. &hauppauge_hvr1800lp_config,
  408. &i2c_bus->i2c_adap);
  409. if (fe0->dvb.frontend != NULL) {
  410. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  411. &i2c_bus->i2c_adap,
  412. &hauppauge_generic_tunerconfig, 0);
  413. }
  414. break;
  415. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  416. i2c_bus = &dev->i2c_bus[0];
  417. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  418. &fusionhdtv_5_express,
  419. &i2c_bus->i2c_adap);
  420. if (fe0->dvb.frontend != NULL) {
  421. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  422. &i2c_bus->i2c_adap, 0x61,
  423. TUNER_LG_TDVS_H06XF);
  424. }
  425. break;
  426. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  427. i2c_bus = &dev->i2c_bus[1];
  428. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  429. &hauppauge_hvr1500q_config,
  430. &dev->i2c_bus[0].i2c_adap);
  431. if (fe0->dvb.frontend != NULL)
  432. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  433. &i2c_bus->i2c_adap,
  434. &hauppauge_hvr1500q_tunerconfig);
  435. break;
  436. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  437. i2c_bus = &dev->i2c_bus[1];
  438. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  439. &hauppauge_hvr1500_config,
  440. &dev->i2c_bus[0].i2c_adap);
  441. if (fe0->dvb.frontend != NULL) {
  442. struct dvb_frontend *fe;
  443. struct xc2028_config cfg = {
  444. .i2c_adap = &i2c_bus->i2c_adap,
  445. .i2c_addr = 0x61,
  446. };
  447. static struct xc2028_ctrl ctl = {
  448. .fname = XC2028_DEFAULT_FIRMWARE,
  449. .max_len = 64,
  450. .demod = XC3028_FE_OREN538,
  451. };
  452. fe = dvb_attach(xc2028_attach,
  453. fe0->dvb.frontend, &cfg);
  454. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  455. fe->ops.tuner_ops.set_config(fe, &ctl);
  456. }
  457. break;
  458. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  459. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  460. i2c_bus = &dev->i2c_bus[0];
  461. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  462. &hauppauge_hvr1200_config,
  463. &i2c_bus->i2c_adap);
  464. if (fe0->dvb.frontend != NULL) {
  465. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  466. &dev->i2c_bus[1].i2c_adap, 0x42,
  467. &tda829x_no_probe);
  468. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  469. 0x60, &dev->i2c_bus[1].i2c_adap,
  470. &hauppauge_hvr1200_tuner_config);
  471. }
  472. break;
  473. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  474. i2c_bus = &dev->i2c_bus[0];
  475. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  476. &i2c_bus->i2c_adap,
  477. 0x12, &hauppauge_hvr1400_dib7000_config);
  478. if (fe0->dvb.frontend != NULL) {
  479. struct dvb_frontend *fe;
  480. struct xc2028_config cfg = {
  481. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  482. .i2c_addr = 0x64,
  483. };
  484. static struct xc2028_ctrl ctl = {
  485. .fname = XC3028L_DEFAULT_FIRMWARE,
  486. .max_len = 64,
  487. .demod = 5000,
  488. /* This is true for all demods with
  489. v36 firmware? */
  490. .type = XC2028_D2633,
  491. };
  492. fe = dvb_attach(xc2028_attach,
  493. fe0->dvb.frontend, &cfg);
  494. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  495. fe->ops.tuner_ops.set_config(fe, &ctl);
  496. }
  497. break;
  498. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  499. i2c_bus = &dev->i2c_bus[port->nr - 1];
  500. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  501. &dvico_s5h1409_config,
  502. &i2c_bus->i2c_adap);
  503. if (fe0->dvb.frontend == NULL)
  504. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  505. &dvico_s5h1411_config,
  506. &i2c_bus->i2c_adap);
  507. if (fe0->dvb.frontend != NULL)
  508. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  509. &i2c_bus->i2c_adap,
  510. &dvico_xc5000_tunerconfig);
  511. break;
  512. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  513. i2c_bus = &dev->i2c_bus[port->nr - 1];
  514. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  515. &dvico_fusionhdtv_xc3028,
  516. &i2c_bus->i2c_adap);
  517. if (fe0->dvb.frontend != NULL) {
  518. struct dvb_frontend *fe;
  519. struct xc2028_config cfg = {
  520. .i2c_adap = &i2c_bus->i2c_adap,
  521. .i2c_addr = 0x61,
  522. };
  523. static struct xc2028_ctrl ctl = {
  524. .fname = XC2028_DEFAULT_FIRMWARE,
  525. .max_len = 64,
  526. .demod = XC3028_FE_ZARLINK456,
  527. };
  528. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  529. &cfg);
  530. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  531. fe->ops.tuner_ops.set_config(fe, &ctl);
  532. }
  533. break;
  534. }
  535. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  536. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  537. i2c_bus = &dev->i2c_bus[0];
  538. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  539. &dvico_fusionhdtv_xc3028,
  540. &i2c_bus->i2c_adap);
  541. if (fe0->dvb.frontend != NULL) {
  542. struct dvb_frontend *fe;
  543. struct xc2028_config cfg = {
  544. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  545. .i2c_addr = 0x61,
  546. };
  547. static struct xc2028_ctrl ctl = {
  548. .fname = XC2028_DEFAULT_FIRMWARE,
  549. .max_len = 64,
  550. .demod = XC3028_FE_ZARLINK456,
  551. };
  552. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  553. &cfg);
  554. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  555. fe->ops.tuner_ops.set_config(fe, &ctl);
  556. }
  557. break;
  558. case CX23885_BOARD_TBS_6920:
  559. i2c_bus = &dev->i2c_bus[0];
  560. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  561. &tbs_cx24116_config,
  562. &i2c_bus->i2c_adap);
  563. if (fe0->dvb.frontend != NULL)
  564. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  565. break;
  566. case CX23885_BOARD_TEVII_S470:
  567. i2c_bus = &dev->i2c_bus[1];
  568. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  569. &tevii_cx24116_config,
  570. &i2c_bus->i2c_adap);
  571. if (fe0->dvb.frontend != NULL)
  572. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  573. break;
  574. case CX23885_BOARD_DVBWORLD_2005:
  575. i2c_bus = &dev->i2c_bus[1];
  576. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  577. &dvbworld_cx24116_config,
  578. &i2c_bus->i2c_adap);
  579. break;
  580. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  581. i2c_bus = &dev->i2c_bus[0];
  582. switch (port->nr) {
  583. /* port B */
  584. case 1:
  585. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  586. &netup_stv0900_config,
  587. &i2c_bus->i2c_adap, 0);
  588. if (fe0->dvb.frontend != NULL) {
  589. if (dvb_attach(stv6110_attach,
  590. fe0->dvb.frontend,
  591. &netup_stv6110_tunerconfig_a,
  592. &i2c_bus->i2c_adap)) {
  593. if (!dvb_attach(lnbh24_attach,
  594. fe0->dvb.frontend,
  595. &i2c_bus->i2c_adap,
  596. LNBH24_PCL, 0, 0x09))
  597. printk(KERN_ERR
  598. "No LNBH24 found!\n");
  599. }
  600. }
  601. break;
  602. /* port C */
  603. case 2:
  604. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  605. &netup_stv0900_config,
  606. &i2c_bus->i2c_adap, 1);
  607. if (fe0->dvb.frontend != NULL) {
  608. if (dvb_attach(stv6110_attach,
  609. fe0->dvb.frontend,
  610. &netup_stv6110_tunerconfig_b,
  611. &i2c_bus->i2c_adap)) {
  612. if (!dvb_attach(lnbh24_attach,
  613. fe0->dvb.frontend,
  614. &i2c_bus->i2c_adap,
  615. LNBH24_PCL, 0, 0x0a))
  616. printk(KERN_ERR
  617. "No LNBH24 found!\n");
  618. }
  619. }
  620. break;
  621. }
  622. break;
  623. default:
  624. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  625. " isn't supported yet\n",
  626. dev->name);
  627. break;
  628. }
  629. if (NULL == fe0->dvb.frontend) {
  630. printk(KERN_ERR "%s: frontend initialization failed\n",
  631. dev->name);
  632. return -1;
  633. }
  634. /* define general-purpose callback pointer */
  635. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  636. /* Put the analog decoder in standby to keep it quiet */
  637. call_all(dev, tuner, s_standby);
  638. if (fe0->dvb.frontend->ops.analog_ops.standby)
  639. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  640. /* register everything */
  641. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  642. &dev->pci->dev, adapter_nr, 0);
  643. /* init CI & MAC */
  644. switch (dev->board) {
  645. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  646. static struct netup_card_info cinfo;
  647. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  648. memcpy(port->frontends.adapter.proposed_mac,
  649. cinfo.port[port->nr - 1].mac, 6);
  650. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  651. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  652. port->nr,
  653. port->frontends.adapter.proposed_mac[0],
  654. port->frontends.adapter.proposed_mac[1],
  655. port->frontends.adapter.proposed_mac[2],
  656. port->frontends.adapter.proposed_mac[3],
  657. port->frontends.adapter.proposed_mac[4],
  658. port->frontends.adapter.proposed_mac[5]);
  659. netup_ci_init(port);
  660. break;
  661. }
  662. }
  663. return ret;
  664. }
  665. int cx23885_dvb_register(struct cx23885_tsport *port)
  666. {
  667. struct videobuf_dvb_frontend *fe0;
  668. struct cx23885_dev *dev = port->dev;
  669. int err, i;
  670. /* Here we need to allocate the correct number of frontends,
  671. * as reflected in the cards struct. The reality is that currrently
  672. * no cx23885 boards support this - yet. But, if we don't modify this
  673. * code then the second frontend would never be allocated (later)
  674. * and fail with error before the attach in dvb_register().
  675. * Without these changes we risk an OOPS later. The changes here
  676. * are for safety, and should provide a good foundation for the
  677. * future addition of any multi-frontend cx23885 based boards.
  678. */
  679. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  680. port->num_frontends);
  681. for (i = 1; i <= port->num_frontends; i++) {
  682. if (videobuf_dvb_alloc_frontend(
  683. &port->frontends, i) == NULL) {
  684. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  685. return -ENOMEM;
  686. }
  687. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  688. if (!fe0)
  689. err = -EINVAL;
  690. dprintk(1, "%s\n", __func__);
  691. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  692. dev->board,
  693. dev->name,
  694. dev->pci_bus,
  695. dev->pci_slot);
  696. err = -ENODEV;
  697. /* dvb stuff */
  698. /* We have to init the queue for each frontend on a port. */
  699. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  700. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  701. &dev->pci->dev, &port->slock,
  702. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  703. sizeof(struct cx23885_buffer), port);
  704. }
  705. err = dvb_register(port);
  706. if (err != 0)
  707. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  708. __func__, err);
  709. return err;
  710. }
  711. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  712. {
  713. struct videobuf_dvb_frontend *fe0;
  714. /* FIXME: in an error condition where the we have
  715. * an expected number of frontends (attach problem)
  716. * then this might not clean up correctly, if 1
  717. * is invalid.
  718. * This comment only applies to future boards IF they
  719. * implement MFE support.
  720. */
  721. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  722. if (fe0->dvb.frontend)
  723. videobuf_dvb_unregister_bus(&port->frontends);
  724. switch (port->dev->board) {
  725. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  726. netup_ci_exit(port);
  727. break;
  728. }
  729. return 0;
  730. }