solos-pci.c 27 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define DATA_RAM_SIZE 32768
  55. #define BUF_SIZE 4096
  56. #define FPGA_PAGE 528 /* FPGA flash page size*/
  57. #define SOLOS_PAGE 512 /* Solos flash page size*/
  58. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  59. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  60. #define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
  61. #define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
  62. static int debug = 0;
  63. static int atmdebug = 0;
  64. static int firmware_upgrade = 0;
  65. static int fpga_upgrade = 0;
  66. struct pkt_hdr {
  67. __le16 size;
  68. __le16 vpi;
  69. __le16 vci;
  70. __le16 type;
  71. };
  72. #define PKT_DATA 0
  73. #define PKT_COMMAND 1
  74. #define PKT_POPEN 3
  75. #define PKT_PCLOSE 4
  76. struct solos_card {
  77. void __iomem *config_regs;
  78. void __iomem *buffers;
  79. int nr_ports;
  80. struct pci_dev *dev;
  81. struct atm_dev *atmdev[4];
  82. struct tasklet_struct tlet;
  83. spinlock_t tx_lock;
  84. spinlock_t tx_queue_lock;
  85. spinlock_t cli_queue_lock;
  86. spinlock_t param_queue_lock;
  87. struct list_head param_queue;
  88. struct sk_buff_head tx_queue[4];
  89. struct sk_buff_head cli_queue[4];
  90. wait_queue_head_t param_wq;
  91. wait_queue_head_t fw_wq;
  92. };
  93. struct solos_param {
  94. struct list_head list;
  95. pid_t pid;
  96. int port;
  97. struct sk_buff *response;
  98. wait_queue_head_t wq;
  99. };
  100. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  101. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  102. MODULE_DESCRIPTION("Solos PCI driver");
  103. MODULE_VERSION(VERSION);
  104. MODULE_LICENSE("GPL");
  105. MODULE_PARM_DESC(debug, "Enable Loopback");
  106. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  107. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  108. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  109. module_param(debug, int, 0444);
  110. module_param(atmdebug, int, 0644);
  111. module_param(firmware_upgrade, int, 0444);
  112. module_param(fpga_upgrade, int, 0444);
  113. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  114. struct atm_vcc *vcc);
  115. static int fpga_tx(struct solos_card *);
  116. static irqreturn_t solos_irq(int irq, void *dev_id);
  117. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  118. static int list_vccs(int vci);
  119. static int atm_init(struct solos_card *);
  120. static void atm_remove(struct solos_card *);
  121. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  122. static void solos_bh(unsigned long);
  123. static int print_buffer(struct sk_buff *buf);
  124. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  125. {
  126. if (vcc->pop)
  127. vcc->pop(vcc, skb);
  128. else
  129. dev_kfree_skb_any(skb);
  130. }
  131. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  132. char *buf)
  133. {
  134. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  135. struct solos_card *card = atmdev->dev_data;
  136. struct solos_param prm;
  137. struct sk_buff *skb;
  138. struct pkt_hdr *header;
  139. int buflen;
  140. buflen = strlen(attr->attr.name) + 10;
  141. skb = alloc_skb(buflen, GFP_KERNEL);
  142. if (!skb) {
  143. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  144. return -ENOMEM;
  145. }
  146. header = (void *)skb_put(skb, sizeof(*header));
  147. buflen = snprintf((void *)&header[1], buflen - 1,
  148. "L%05d\n%s\n", current->pid, attr->attr.name);
  149. skb_put(skb, buflen);
  150. header->size = cpu_to_le16(buflen);
  151. header->vpi = cpu_to_le16(0);
  152. header->vci = cpu_to_le16(0);
  153. header->type = cpu_to_le16(PKT_COMMAND);
  154. prm.pid = current->pid;
  155. prm.response = NULL;
  156. prm.port = SOLOS_CHAN(atmdev);
  157. spin_lock_irq(&card->param_queue_lock);
  158. list_add(&prm.list, &card->param_queue);
  159. spin_unlock_irq(&card->param_queue_lock);
  160. fpga_queue(card, prm.port, skb, NULL);
  161. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  162. spin_lock_irq(&card->param_queue_lock);
  163. list_del(&prm.list);
  164. spin_unlock_irq(&card->param_queue_lock);
  165. if (!prm.response)
  166. return -EIO;
  167. buflen = prm.response->len;
  168. memcpy(buf, prm.response->data, buflen);
  169. kfree_skb(prm.response);
  170. return buflen;
  171. }
  172. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  173. const char *buf, size_t count)
  174. {
  175. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  176. struct solos_card *card = atmdev->dev_data;
  177. struct solos_param prm;
  178. struct sk_buff *skb;
  179. struct pkt_hdr *header;
  180. int buflen;
  181. ssize_t ret;
  182. buflen = strlen(attr->attr.name) + 11 + count;
  183. skb = alloc_skb(buflen, GFP_KERNEL);
  184. if (!skb) {
  185. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  186. return -ENOMEM;
  187. }
  188. header = (void *)skb_put(skb, sizeof(*header));
  189. buflen = snprintf((void *)&header[1], buflen - 1,
  190. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  191. skb_put(skb, buflen);
  192. header->size = cpu_to_le16(buflen);
  193. header->vpi = cpu_to_le16(0);
  194. header->vci = cpu_to_le16(0);
  195. header->type = cpu_to_le16(PKT_COMMAND);
  196. prm.pid = current->pid;
  197. prm.response = NULL;
  198. prm.port = SOLOS_CHAN(atmdev);
  199. spin_lock_irq(&card->param_queue_lock);
  200. list_add(&prm.list, &card->param_queue);
  201. spin_unlock_irq(&card->param_queue_lock);
  202. fpga_queue(card, prm.port, skb, NULL);
  203. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  204. spin_lock_irq(&card->param_queue_lock);
  205. list_del(&prm.list);
  206. spin_unlock_irq(&card->param_queue_lock);
  207. skb = prm.response;
  208. if (!skb)
  209. return -EIO;
  210. buflen = skb->len;
  211. /* Sometimes it has a newline, sometimes it doesn't. */
  212. if (skb->data[buflen - 1] == '\n')
  213. buflen--;
  214. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  215. ret = count;
  216. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  217. ret = -EIO;
  218. else {
  219. /* We know we have enough space allocated for this; we allocated
  220. it ourselves */
  221. skb->data[buflen] = 0;
  222. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  223. skb->data);
  224. ret = -EIO;
  225. }
  226. kfree_skb(skb);
  227. return ret;
  228. }
  229. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  230. {
  231. struct solos_param *prm;
  232. unsigned long flags;
  233. int cmdpid;
  234. int found = 0;
  235. if (skb->len < 7)
  236. return 0;
  237. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  238. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  239. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  240. skb->data[6] != '\n')
  241. return 0;
  242. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  243. spin_lock_irqsave(&card->param_queue_lock, flags);
  244. list_for_each_entry(prm, &card->param_queue, list) {
  245. if (prm->port == port && prm->pid == cmdpid) {
  246. prm->response = skb;
  247. skb_pull(skb, 7);
  248. wake_up(&card->param_wq);
  249. found = 1;
  250. break;
  251. }
  252. }
  253. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  254. return found;
  255. }
  256. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  257. char *buf)
  258. {
  259. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  260. struct solos_card *card = atmdev->dev_data;
  261. struct sk_buff *skb;
  262. spin_lock(&card->cli_queue_lock);
  263. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  264. spin_unlock(&card->cli_queue_lock);
  265. if(skb == NULL)
  266. return sprintf(buf, "No data.\n");
  267. memcpy(buf, skb->data, skb->len);
  268. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  269. kfree_skb(skb);
  270. return skb->len;
  271. }
  272. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  273. {
  274. struct sk_buff *skb;
  275. struct pkt_hdr *header;
  276. // dev_dbg(&card->dev->dev, "size: %d\n", size);
  277. if (size > (BUF_SIZE - sizeof(*header))) {
  278. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  279. return 0;
  280. }
  281. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  282. if (!skb) {
  283. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  284. return 0;
  285. }
  286. header = (void *)skb_put(skb, sizeof(*header));
  287. header->size = cpu_to_le16(size);
  288. header->vpi = cpu_to_le16(0);
  289. header->vci = cpu_to_le16(0);
  290. header->type = cpu_to_le16(PKT_COMMAND);
  291. memcpy(skb_put(skb, size), buf, size);
  292. fpga_queue(card, dev, skb, NULL);
  293. return 0;
  294. }
  295. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  296. const char *buf, size_t count)
  297. {
  298. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  299. struct solos_card *card = atmdev->dev_data;
  300. int err;
  301. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  302. return err?:count;
  303. }
  304. static DEVICE_ATTR(console, 0644, console_show, console_store);
  305. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  306. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  307. #include "solos-attrlist.c"
  308. #undef SOLOS_ATTR_RO
  309. #undef SOLOS_ATTR_RW
  310. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  311. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  312. static struct attribute *solos_attrs[] = {
  313. #include "solos-attrlist.c"
  314. NULL
  315. };
  316. static struct attribute_group solos_attr_group = {
  317. .attrs = solos_attrs,
  318. .name = "parameters",
  319. };
  320. static int flash_upgrade(struct solos_card *card, int chip)
  321. {
  322. const struct firmware *fw;
  323. const char *fw_name;
  324. uint32_t data32 = 0;
  325. int blocksize = 0;
  326. int numblocks = 0;
  327. int offset;
  328. if (chip == 0) {
  329. fw_name = "solos-FPGA.bin";
  330. blocksize = FPGA_BLOCK;
  331. } else {
  332. fw_name = "solos-Firmware.bin";
  333. blocksize = SOLOS_BLOCK;
  334. }
  335. if (request_firmware(&fw, fw_name, &card->dev->dev))
  336. return -ENOENT;
  337. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  338. numblocks = fw->size / blocksize;
  339. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  340. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  341. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  342. iowrite32(1, card->config_regs + FPGA_MODE);
  343. data32 = ioread32(card->config_regs + FPGA_MODE);
  344. /* Set mode to Chip Erase */
  345. dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
  346. chip?"Solos":"FPGA");
  347. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  348. iowrite32(1, card->config_regs + WRITE_FLASH);
  349. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  350. for (offset = 0; offset < fw->size; offset += blocksize) {
  351. int i;
  352. /* Clear write flag */
  353. iowrite32(0, card->config_regs + WRITE_FLASH);
  354. /* Set mode to Block Write */
  355. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  356. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  357. /* Copy block to buffer, swapping each 16 bits */
  358. for(i = 0; i < blocksize; i += 4) {
  359. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  360. iowrite32(word, RX_BUF(card, 3) + i);
  361. }
  362. /* Specify block number and then trigger flash write */
  363. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  364. iowrite32(1, card->config_regs + WRITE_FLASH);
  365. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  366. }
  367. release_firmware(fw);
  368. iowrite32(0, card->config_regs + WRITE_FLASH);
  369. iowrite32(0, card->config_regs + FPGA_MODE);
  370. iowrite32(0, card->config_regs + FLASH_MODE);
  371. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  372. return 0;
  373. }
  374. static irqreturn_t solos_irq(int irq, void *dev_id)
  375. {
  376. struct solos_card *card = dev_id;
  377. int handled = 1;
  378. //ACK IRQ
  379. iowrite32(0, card->config_regs + IRQ_CLEAR);
  380. //Disable IRQs from FPGA
  381. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  382. if (card->atmdev[0])
  383. tasklet_schedule(&card->tlet);
  384. else
  385. wake_up(&card->fw_wq);
  386. //Enable IRQs from FPGA
  387. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  388. return IRQ_RETVAL(handled);
  389. }
  390. void solos_bh(unsigned long card_arg)
  391. {
  392. struct solos_card *card = (void *)card_arg;
  393. int port;
  394. uint32_t card_flags;
  395. uint32_t tx_mask;
  396. uint32_t rx_done = 0;
  397. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  398. /* The TX bits are set if the channel is busy; clear if not. We want to
  399. invoke fpga_tx() unless _all_ the bits for active channels are set */
  400. tx_mask = (1 << card->nr_ports) - 1;
  401. if ((card_flags & tx_mask) != tx_mask)
  402. fpga_tx(card);
  403. for (port = 0; port < card->nr_ports; port++) {
  404. if (card_flags & (0x10 << port)) {
  405. struct pkt_hdr header;
  406. struct sk_buff *skb;
  407. struct atm_vcc *vcc;
  408. int size;
  409. rx_done |= 0x10 << port;
  410. memcpy_fromio(&header, RX_BUF(card, port), sizeof(header));
  411. size = le16_to_cpu(header.size);
  412. skb = alloc_skb(size, GFP_ATOMIC);
  413. if (!skb) {
  414. if (net_ratelimit())
  415. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  416. continue;
  417. }
  418. memcpy_fromio(skb_put(skb, size),
  419. RX_BUF(card, port) + sizeof(header),
  420. size);
  421. if (atmdebug) {
  422. dev_info(&card->dev->dev, "Received: device %d\n", port);
  423. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  424. size, le16_to_cpu(header.vpi),
  425. le16_to_cpu(header.vci));
  426. print_buffer(skb);
  427. }
  428. switch (le16_to_cpu(header.type)) {
  429. case PKT_DATA:
  430. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header.vpi),
  431. le16_to_cpu(header.vci));
  432. if (!vcc) {
  433. if (net_ratelimit())
  434. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  435. le16_to_cpu(header.vci), le16_to_cpu(header.vpi),
  436. port);
  437. continue;
  438. }
  439. atm_charge(vcc, skb->truesize);
  440. vcc->push(vcc, skb);
  441. atomic_inc(&vcc->stats->rx);
  442. break;
  443. case PKT_COMMAND:
  444. default: /* FIXME: Not really, surely? */
  445. if (process_command(card, port, skb))
  446. break;
  447. spin_lock(&card->cli_queue_lock);
  448. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  449. if (net_ratelimit())
  450. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  451. port);
  452. } else
  453. skb_queue_tail(&card->cli_queue[port], skb);
  454. spin_unlock(&card->cli_queue_lock);
  455. break;
  456. }
  457. }
  458. }
  459. if (rx_done)
  460. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  461. return;
  462. }
  463. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  464. {
  465. struct hlist_head *head;
  466. struct atm_vcc *vcc = NULL;
  467. struct hlist_node *node;
  468. struct sock *s;
  469. read_lock(&vcc_sklist_lock);
  470. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  471. sk_for_each(s, node, head) {
  472. vcc = atm_sk(s);
  473. if (vcc->dev == dev && vcc->vci == vci &&
  474. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  475. goto out;
  476. }
  477. vcc = NULL;
  478. out:
  479. read_unlock(&vcc_sklist_lock);
  480. return vcc;
  481. }
  482. static int list_vccs(int vci)
  483. {
  484. struct hlist_head *head;
  485. struct atm_vcc *vcc;
  486. struct hlist_node *node;
  487. struct sock *s;
  488. int num_found = 0;
  489. int i;
  490. read_lock(&vcc_sklist_lock);
  491. if (vci != 0){
  492. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  493. sk_for_each(s, node, head) {
  494. num_found ++;
  495. vcc = atm_sk(s);
  496. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  497. vcc->dev->number,
  498. vcc->vpi,
  499. vcc->vci);
  500. }
  501. } else {
  502. for(i=0; i<32; i++){
  503. head = &vcc_hash[i];
  504. sk_for_each(s, node, head) {
  505. num_found ++;
  506. vcc = atm_sk(s);
  507. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  508. vcc->dev->number,
  509. vcc->vpi,
  510. vcc->vci);
  511. }
  512. }
  513. }
  514. read_unlock(&vcc_sklist_lock);
  515. return num_found;
  516. }
  517. static int popen(struct atm_vcc *vcc)
  518. {
  519. struct solos_card *card = vcc->dev->dev_data;
  520. struct sk_buff *skb;
  521. struct pkt_hdr *header;
  522. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  523. if (!skb && net_ratelimit()) {
  524. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  525. return -ENOMEM;
  526. }
  527. header = (void *)skb_put(skb, sizeof(*header));
  528. header->size = cpu_to_le16(0);
  529. header->vpi = cpu_to_le16(vcc->vpi);
  530. header->vci = cpu_to_le16(vcc->vci);
  531. header->type = cpu_to_le16(PKT_POPEN);
  532. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  533. // dev_dbg(&card->dev->dev, "Open for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  534. set_bit(ATM_VF_ADDR, &vcc->flags); // accept the vpi / vci
  535. set_bit(ATM_VF_READY, &vcc->flags);
  536. list_vccs(0);
  537. return 0;
  538. }
  539. static void pclose(struct atm_vcc *vcc)
  540. {
  541. struct solos_card *card = vcc->dev->dev_data;
  542. struct sk_buff *skb;
  543. struct pkt_hdr *header;
  544. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  545. if (!skb) {
  546. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  547. return;
  548. }
  549. header = (void *)skb_put(skb, sizeof(*header));
  550. header->size = cpu_to_le16(0);
  551. header->vpi = cpu_to_le16(vcc->vpi);
  552. header->vci = cpu_to_le16(vcc->vci);
  553. header->type = cpu_to_le16(PKT_PCLOSE);
  554. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  555. // dev_dbg(&card->dev->dev, "Close for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  556. clear_bit(ATM_VF_ADDR, &vcc->flags);
  557. clear_bit(ATM_VF_READY, &vcc->flags);
  558. return;
  559. }
  560. static int print_buffer(struct sk_buff *buf)
  561. {
  562. int len,i;
  563. char msg[500];
  564. char item[10];
  565. len = buf->len;
  566. for (i = 0; i < len; i++){
  567. if(i % 8 == 0)
  568. sprintf(msg, "%02X: ", i);
  569. sprintf(item,"%02X ",*(buf->data + i));
  570. strcat(msg, item);
  571. if(i % 8 == 7) {
  572. sprintf(item, "\n");
  573. strcat(msg, item);
  574. printk(KERN_DEBUG "%s", msg);
  575. }
  576. }
  577. if (i % 8 != 0) {
  578. sprintf(item, "\n");
  579. strcat(msg, item);
  580. printk(KERN_DEBUG "%s", msg);
  581. }
  582. printk(KERN_DEBUG "\n");
  583. return 0;
  584. }
  585. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  586. struct atm_vcc *vcc)
  587. {
  588. int old_len;
  589. *(void **)skb->cb = vcc;
  590. spin_lock(&card->tx_queue_lock);
  591. old_len = skb_queue_len(&card->tx_queue[port]);
  592. skb_queue_tail(&card->tx_queue[port], skb);
  593. spin_unlock(&card->tx_queue_lock);
  594. /* If TX might need to be started, do so */
  595. if (!old_len)
  596. fpga_tx(card);
  597. }
  598. static int fpga_tx(struct solos_card *card)
  599. {
  600. uint32_t tx_pending;
  601. uint32_t tx_started = 0;
  602. struct sk_buff *skb;
  603. struct atm_vcc *vcc;
  604. unsigned char port;
  605. unsigned long flags;
  606. spin_lock_irqsave(&card->tx_lock, flags);
  607. tx_pending = ioread32(card->config_regs + FLAGS_ADDR);
  608. dev_vdbg(&card->dev->dev, "TX Flags are %X\n", tx_pending);
  609. for (port = 0; port < card->nr_ports; port++) {
  610. if (!(tx_pending & (1 << port))) {
  611. spin_lock(&card->tx_queue_lock);
  612. skb = skb_dequeue(&card->tx_queue[port]);
  613. spin_unlock(&card->tx_queue_lock);
  614. if (!skb)
  615. continue;
  616. if (atmdebug) {
  617. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  618. port);
  619. print_buffer(skb);
  620. }
  621. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  622. vcc = *(void **)skb->cb;
  623. if (vcc) {
  624. atomic_inc(&vcc->stats->tx);
  625. solos_pop(vcc, skb);
  626. } else
  627. dev_kfree_skb_irq(skb);
  628. tx_started |= 1 << port; //Set TX full flag
  629. }
  630. }
  631. if (tx_started)
  632. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  633. spin_unlock_irqrestore(&card->tx_lock, flags);
  634. return 0;
  635. }
  636. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  637. {
  638. struct solos_card *card = vcc->dev->dev_data;
  639. struct sk_buff *skb2 = NULL;
  640. struct pkt_hdr *header;
  641. int pktlen;
  642. //dev_dbg(&card->dev->dev, "psend called.\n");
  643. //dev_dbg(&card->dev->dev, "dev,vpi,vci = %d,%d,%d\n",SOLOS_CHAN(vcc->dev),vcc->vpi,vcc->vci);
  644. if (debug) {
  645. skb2 = atm_alloc_charge(vcc, skb->len, GFP_ATOMIC);
  646. if (skb2) {
  647. memcpy(skb2->data, skb->data, skb->len);
  648. skb_put(skb2, skb->len);
  649. vcc->push(vcc, skb2);
  650. atomic_inc(&vcc->stats->rx);
  651. }
  652. atomic_inc(&vcc->stats->tx);
  653. solos_pop(vcc, skb);
  654. return 0;
  655. }
  656. pktlen = skb->len;
  657. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  658. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  659. solos_pop(vcc, skb);
  660. return 0;
  661. }
  662. if (!skb_clone_writable(skb, sizeof(*header))) {
  663. int expand_by = 0;
  664. int ret;
  665. if (skb_headroom(skb) < sizeof(*header))
  666. expand_by = sizeof(*header) - skb_headroom(skb);
  667. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  668. if (ret) {
  669. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  670. solos_pop(vcc, skb);
  671. return ret;
  672. }
  673. }
  674. header = (void *)skb_push(skb, sizeof(*header));
  675. /* This does _not_ include the size of the header */
  676. header->size = cpu_to_le16(pktlen);
  677. header->vpi = cpu_to_le16(vcc->vpi);
  678. header->vci = cpu_to_le16(vcc->vci);
  679. header->type = cpu_to_le16(PKT_DATA);
  680. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  681. return 0;
  682. }
  683. static struct atmdev_ops fpga_ops = {
  684. .open = popen,
  685. .close = pclose,
  686. .ioctl = NULL,
  687. .getsockopt = NULL,
  688. .setsockopt = NULL,
  689. .send = psend,
  690. .send_oam = NULL,
  691. .phy_put = NULL,
  692. .phy_get = NULL,
  693. .change_qos = NULL,
  694. .proc_read = NULL,
  695. .owner = THIS_MODULE
  696. };
  697. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  698. {
  699. int err, i;
  700. uint16_t fpga_ver;
  701. uint8_t major_ver, minor_ver;
  702. uint32_t data32;
  703. struct solos_card *card;
  704. if (debug)
  705. return 0;
  706. card = kzalloc(sizeof(*card), GFP_KERNEL);
  707. if (!card)
  708. return -ENOMEM;
  709. card->dev = dev;
  710. init_waitqueue_head(&card->fw_wq);
  711. init_waitqueue_head(&card->param_wq);
  712. err = pci_enable_device(dev);
  713. if (err) {
  714. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  715. goto out;
  716. }
  717. err = pci_request_regions(dev, "solos");
  718. if (err) {
  719. dev_warn(&dev->dev, "Failed to request regions\n");
  720. goto out;
  721. }
  722. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  723. if (!card->config_regs) {
  724. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  725. goto out_release_regions;
  726. }
  727. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  728. if (!card->buffers) {
  729. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  730. goto out_unmap_config;
  731. }
  732. // for(i=0;i<64 ;i+=4){
  733. // data32=ioread32(card->buffers + i);
  734. // dev_dbg(&card->dev->dev, "%08lX\n",(unsigned long)data32);
  735. // }
  736. //Fill Config Mem with zeros
  737. for(i = 0; i < 128; i += 4)
  738. iowrite32(0, card->config_regs + i);
  739. //Set RX empty flags
  740. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  741. data32 = ioread32(card->config_regs + FPGA_VER);
  742. fpga_ver = (data32 & 0x0000FFFF);
  743. major_ver = ((data32 & 0xFF000000) >> 24);
  744. minor_ver = ((data32 & 0x00FF0000) >> 16);
  745. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  746. major_ver, minor_ver, fpga_ver);
  747. card->nr_ports = 2; /* FIXME: Detect daughterboard */
  748. pci_set_drvdata(dev, card);
  749. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  750. spin_lock_init(&card->tx_lock);
  751. spin_lock_init(&card->tx_queue_lock);
  752. spin_lock_init(&card->cli_queue_lock);
  753. spin_lock_init(&card->param_queue_lock);
  754. INIT_LIST_HEAD(&card->param_queue);
  755. /*
  756. // Set Loopback mode
  757. data32 = 0x00010000;
  758. iowrite32(data32,card->config_regs + FLAGS_ADDR);
  759. */
  760. /*
  761. // Fill Buffers with zeros
  762. for (i = 0; i < BUF_SIZE * 8; i += 4)
  763. iowrite32(0, card->buffers + i);
  764. */
  765. /*
  766. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  767. iowrite32(0x12345678, card->buffers + i + (0*BUF_SIZE));
  768. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  769. iowrite32(0xabcdef98, card->buffers + i + (1*BUF_SIZE));
  770. // Read Config Memory
  771. printk(KERN_DEBUG "Reading Config MEM\n");
  772. i = 0;
  773. for(i = 0; i < 16; i++) {
  774. data32=ioread32(card->buffers + i*(BUF_SIZE/2));
  775. printk(KERN_ALERT "Addr: %lX Data: %08lX\n",
  776. (unsigned long)(addr_start + i*(BUF_SIZE/2)),
  777. (unsigned long)data32);
  778. }
  779. */
  780. //dev_dbg(&card->dev->dev, "Requesting IRQ: %d\n",dev->irq);
  781. err = request_irq(dev->irq, solos_irq, IRQF_DISABLED|IRQF_SHARED,
  782. "solos-pci", card);
  783. if (err) {
  784. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  785. goto out_unmap_both;
  786. }
  787. // Enable IRQs
  788. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  789. if (fpga_upgrade)
  790. flash_upgrade(card, 0);
  791. if (firmware_upgrade)
  792. flash_upgrade(card, 1);
  793. err = atm_init(card);
  794. if (err)
  795. goto out_free_irq;
  796. return 0;
  797. out_free_irq:
  798. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  799. free_irq(dev->irq, card);
  800. tasklet_kill(&card->tlet);
  801. out_unmap_both:
  802. pci_set_drvdata(dev, NULL);
  803. pci_iounmap(dev, card->config_regs);
  804. out_unmap_config:
  805. pci_iounmap(dev, card->buffers);
  806. out_release_regions:
  807. pci_release_regions(dev);
  808. out:
  809. return err;
  810. }
  811. static int atm_init(struct solos_card *card)
  812. {
  813. int i;
  814. for (i = 0; i < card->nr_ports; i++) {
  815. skb_queue_head_init(&card->tx_queue[i]);
  816. skb_queue_head_init(&card->cli_queue[i]);
  817. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  818. if (!card->atmdev[i]) {
  819. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  820. atm_remove(card);
  821. return -ENODEV;
  822. }
  823. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  824. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  825. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  826. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  827. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  828. card->atmdev[i]->ci_range.vpi_bits = 8;
  829. card->atmdev[i]->ci_range.vci_bits = 16;
  830. card->atmdev[i]->dev_data = card;
  831. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  832. }
  833. return 0;
  834. }
  835. static void atm_remove(struct solos_card *card)
  836. {
  837. int i;
  838. for (i = 0; i < card->nr_ports; i++) {
  839. if (card->atmdev[i]) {
  840. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  841. atm_dev_deregister(card->atmdev[i]);
  842. }
  843. }
  844. }
  845. static void fpga_remove(struct pci_dev *dev)
  846. {
  847. struct solos_card *card = pci_get_drvdata(dev);
  848. if (debug)
  849. return;
  850. atm_remove(card);
  851. dev_vdbg(&dev->dev, "Freeing IRQ\n");
  852. // Disable IRQs from FPGA
  853. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  854. free_irq(dev->irq, card);
  855. tasklet_kill(&card->tlet);
  856. // iowrite32(0x01,pciregs);
  857. dev_vdbg(&dev->dev, "Unmapping PCI resource\n");
  858. pci_iounmap(dev, card->buffers);
  859. pci_iounmap(dev, card->config_regs);
  860. dev_vdbg(&dev->dev, "Releasing PCI Region\n");
  861. pci_release_regions(dev);
  862. pci_disable_device(dev);
  863. pci_set_drvdata(dev, NULL);
  864. kfree(card);
  865. // dev_dbg(&card->dev->dev, "fpga_remove\n");
  866. return;
  867. }
  868. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  869. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  870. { 0, }
  871. };
  872. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  873. static struct pci_driver fpga_driver = {
  874. .name = "solos",
  875. .id_table = fpga_pci_tbl,
  876. .probe = fpga_probe,
  877. .remove = fpga_remove,
  878. };
  879. static int __init solos_pci_init(void)
  880. {
  881. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  882. return pci_register_driver(&fpga_driver);
  883. }
  884. static void __exit solos_pci_exit(void)
  885. {
  886. pci_unregister_driver(&fpga_driver);
  887. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  888. }
  889. module_init(solos_pci_init);
  890. module_exit(solos_pci_exit);