be.h 15 KB

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  1. /*
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@emulex.com
  12. *
  13. * Emulex
  14. * 3333 Susan Street
  15. * Costa Mesa, CA 92626
  16. */
  17. #ifndef BE_H
  18. #define BE_H
  19. #include <linux/pci.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/delay.h>
  22. #include <net/tcp.h>
  23. #include <net/ip.h>
  24. #include <net/ipv6.h>
  25. #include <linux/if_vlan.h>
  26. #include <linux/workqueue.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/firmware.h>
  29. #include <linux/slab.h>
  30. #include <linux/u64_stats_sync.h>
  31. #include "be_hw.h"
  32. #define DRV_VER "4.2.220u"
  33. #define DRV_NAME "be2net"
  34. #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
  35. #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
  36. #define OC_NAME "Emulex OneConnect 10Gbps NIC"
  37. #define OC_NAME_BE OC_NAME "(be3)"
  38. #define OC_NAME_LANCER OC_NAME "(Lancer)"
  39. #define OC_NAME_SH OC_NAME "(Skyhawk)"
  40. #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
  41. #define BE_VENDOR_ID 0x19a2
  42. #define EMULEX_VENDOR_ID 0x10df
  43. #define BE_DEVICE_ID1 0x211
  44. #define BE_DEVICE_ID2 0x221
  45. #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
  46. #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
  47. #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
  48. #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
  49. #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
  50. #define OC_SUBSYS_DEVICE_ID1 0xE602
  51. #define OC_SUBSYS_DEVICE_ID2 0xE642
  52. #define OC_SUBSYS_DEVICE_ID3 0xE612
  53. #define OC_SUBSYS_DEVICE_ID4 0xE652
  54. static inline char *nic_name(struct pci_dev *pdev)
  55. {
  56. switch (pdev->device) {
  57. case OC_DEVICE_ID1:
  58. return OC_NAME;
  59. case OC_DEVICE_ID2:
  60. return OC_NAME_BE;
  61. case OC_DEVICE_ID3:
  62. case OC_DEVICE_ID4:
  63. return OC_NAME_LANCER;
  64. case BE_DEVICE_ID2:
  65. return BE3_NAME;
  66. case OC_DEVICE_ID5:
  67. return OC_NAME_SH;
  68. default:
  69. return BE_NAME;
  70. }
  71. }
  72. /* Number of bytes of an RX frame that are copied to skb->data */
  73. #define BE_HDR_LEN ((u16) 64)
  74. /* allocate extra space to allow tunneling decapsulation without head reallocation */
  75. #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
  76. #define BE_MAX_JUMBO_FRAME_SIZE 9018
  77. #define BE_MIN_MTU 256
  78. #define BE_NUM_VLANS_SUPPORTED 64
  79. #define BE_MAX_EQD 96u
  80. #define BE_MAX_TX_FRAG_COUNT 30
  81. #define EVNT_Q_LEN 1024
  82. #define TX_Q_LEN 2048
  83. #define TX_CQ_LEN 1024
  84. #define RX_Q_LEN 1024 /* Does not support any other value */
  85. #define RX_CQ_LEN 1024
  86. #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
  87. #define MCC_CQ_LEN 256
  88. #define BE3_MAX_RSS_QS 8
  89. #define BE2_MAX_RSS_QS 4
  90. #define MAX_RSS_QS BE3_MAX_RSS_QS
  91. #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
  92. #define MAX_TX_QS 8
  93. #define MAX_MSIX_VECTORS MAX_RSS_QS
  94. #define BE_TX_BUDGET 256
  95. #define BE_NAPI_WEIGHT 64
  96. #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
  97. #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
  98. #define FW_VER_LEN 32
  99. struct be_dma_mem {
  100. void *va;
  101. dma_addr_t dma;
  102. u32 size;
  103. };
  104. struct be_queue_info {
  105. struct be_dma_mem dma_mem;
  106. u16 len;
  107. u16 entry_size; /* Size of an element in the queue */
  108. u16 id;
  109. u16 tail, head;
  110. bool created;
  111. atomic_t used; /* Number of valid elements in the queue */
  112. };
  113. static inline u32 MODULO(u16 val, u16 limit)
  114. {
  115. BUG_ON(limit & (limit - 1));
  116. return val & (limit - 1);
  117. }
  118. static inline void index_adv(u16 *index, u16 val, u16 limit)
  119. {
  120. *index = MODULO((*index + val), limit);
  121. }
  122. static inline void index_inc(u16 *index, u16 limit)
  123. {
  124. *index = MODULO((*index + 1), limit);
  125. }
  126. static inline void *queue_head_node(struct be_queue_info *q)
  127. {
  128. return q->dma_mem.va + q->head * q->entry_size;
  129. }
  130. static inline void *queue_tail_node(struct be_queue_info *q)
  131. {
  132. return q->dma_mem.va + q->tail * q->entry_size;
  133. }
  134. static inline void *queue_index_node(struct be_queue_info *q, u16 index)
  135. {
  136. return q->dma_mem.va + index * q->entry_size;
  137. }
  138. static inline void queue_head_inc(struct be_queue_info *q)
  139. {
  140. index_inc(&q->head, q->len);
  141. }
  142. static inline void index_dec(u16 *index, u16 limit)
  143. {
  144. *index = MODULO((*index - 1), limit);
  145. }
  146. static inline void queue_tail_inc(struct be_queue_info *q)
  147. {
  148. index_inc(&q->tail, q->len);
  149. }
  150. struct be_eq_obj {
  151. struct be_queue_info q;
  152. char desc[32];
  153. /* Adaptive interrupt coalescing (AIC) info */
  154. bool enable_aic;
  155. u32 min_eqd; /* in usecs */
  156. u32 max_eqd; /* in usecs */
  157. u32 eqd; /* configured val when aic is off */
  158. u32 cur_eqd; /* in usecs */
  159. u8 idx; /* array index */
  160. u16 tx_budget;
  161. struct napi_struct napi;
  162. struct be_adapter *adapter;
  163. } ____cacheline_aligned_in_smp;
  164. struct be_mcc_obj {
  165. struct be_queue_info q;
  166. struct be_queue_info cq;
  167. bool rearm_cq;
  168. };
  169. struct be_tx_stats {
  170. u64 tx_bytes;
  171. u64 tx_pkts;
  172. u64 tx_reqs;
  173. u64 tx_wrbs;
  174. u64 tx_compl;
  175. ulong tx_jiffies;
  176. u32 tx_stops;
  177. struct u64_stats_sync sync;
  178. struct u64_stats_sync sync_compl;
  179. };
  180. struct be_tx_obj {
  181. struct be_queue_info q;
  182. struct be_queue_info cq;
  183. /* Remember the skbs that were transmitted */
  184. struct sk_buff *sent_skb_list[TX_Q_LEN];
  185. struct be_tx_stats stats;
  186. } ____cacheline_aligned_in_smp;
  187. /* Struct to remember the pages posted for rx frags */
  188. struct be_rx_page_info {
  189. struct page *page;
  190. DEFINE_DMA_UNMAP_ADDR(bus);
  191. u16 page_offset;
  192. bool last_page_user;
  193. };
  194. struct be_rx_stats {
  195. u64 rx_bytes;
  196. u64 rx_pkts;
  197. u64 rx_pkts_prev;
  198. ulong rx_jiffies;
  199. u32 rx_drops_no_skbs; /* skb allocation errors */
  200. u32 rx_drops_no_frags; /* HW has no fetched frags */
  201. u32 rx_post_fail; /* page post alloc failures */
  202. u32 rx_compl;
  203. u32 rx_mcast_pkts;
  204. u32 rx_compl_err; /* completions with err set */
  205. u32 rx_pps; /* pkts per second */
  206. struct u64_stats_sync sync;
  207. };
  208. struct be_rx_compl_info {
  209. u32 rss_hash;
  210. u16 vlan_tag;
  211. u16 pkt_size;
  212. u16 rxq_idx;
  213. u16 port;
  214. u8 vlanf;
  215. u8 num_rcvd;
  216. u8 err;
  217. u8 ipf;
  218. u8 tcpf;
  219. u8 udpf;
  220. u8 ip_csum;
  221. u8 l4_csum;
  222. u8 ipv6;
  223. u8 vtm;
  224. u8 pkt_type;
  225. };
  226. struct be_rx_obj {
  227. struct be_adapter *adapter;
  228. struct be_queue_info q;
  229. struct be_queue_info cq;
  230. struct be_rx_compl_info rxcp;
  231. struct be_rx_page_info page_info_tbl[RX_Q_LEN];
  232. struct be_rx_stats stats;
  233. u8 rss_id;
  234. bool rx_post_starved; /* Zero rx frags have been posted to BE */
  235. } ____cacheline_aligned_in_smp;
  236. struct be_drv_stats {
  237. u32 be_on_die_temperature;
  238. u32 eth_red_drops;
  239. u32 rx_drops_no_pbuf;
  240. u32 rx_drops_no_txpb;
  241. u32 rx_drops_no_erx_descr;
  242. u32 rx_drops_no_tpre_descr;
  243. u32 rx_drops_too_many_frags;
  244. u32 forwarded_packets;
  245. u32 rx_drops_mtu;
  246. u32 rx_crc_errors;
  247. u32 rx_alignment_symbol_errors;
  248. u32 rx_pause_frames;
  249. u32 rx_priority_pause_frames;
  250. u32 rx_control_frames;
  251. u32 rx_in_range_errors;
  252. u32 rx_out_range_errors;
  253. u32 rx_frame_too_long;
  254. u32 rx_address_mismatch_drops;
  255. u32 rx_dropped_too_small;
  256. u32 rx_dropped_too_short;
  257. u32 rx_dropped_header_too_small;
  258. u32 rx_dropped_tcp_length;
  259. u32 rx_dropped_runt;
  260. u32 rx_ip_checksum_errs;
  261. u32 rx_tcp_checksum_errs;
  262. u32 rx_udp_checksum_errs;
  263. u32 tx_pauseframes;
  264. u32 tx_priority_pauseframes;
  265. u32 tx_controlframes;
  266. u32 rxpp_fifo_overflow_drop;
  267. u32 rx_input_fifo_overflow_drop;
  268. u32 pmem_fifo_overflow_drop;
  269. u32 jabber_events;
  270. };
  271. struct be_vf_cfg {
  272. unsigned char mac_addr[ETH_ALEN];
  273. int if_handle;
  274. int pmac_id;
  275. u16 def_vid;
  276. u16 vlan_tag;
  277. u32 tx_rate;
  278. };
  279. enum vf_state {
  280. ENABLED = 0,
  281. ASSIGNED = 1
  282. };
  283. #define BE_FLAGS_LINK_STATUS_INIT 1
  284. #define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
  285. #define BE_UC_PMAC_COUNT 30
  286. #define BE_VF_UC_PMAC_COUNT 2
  287. struct phy_info {
  288. u8 transceiver;
  289. u8 autoneg;
  290. u8 fc_autoneg;
  291. u8 port_type;
  292. u16 phy_type;
  293. u16 interface_type;
  294. u32 misc_params;
  295. u16 auto_speeds_supported;
  296. u16 fixed_speeds_supported;
  297. int link_speed;
  298. int forced_port_speed;
  299. u32 dac_cable_len;
  300. u32 advertising;
  301. u32 supported;
  302. };
  303. struct be_adapter {
  304. struct pci_dev *pdev;
  305. struct net_device *netdev;
  306. u8 __iomem *csr;
  307. u8 __iomem *db; /* Door Bell */
  308. struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
  309. struct be_dma_mem mbox_mem;
  310. /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
  311. * is stored for freeing purpose */
  312. struct be_dma_mem mbox_mem_alloced;
  313. struct be_mcc_obj mcc_obj;
  314. spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
  315. spinlock_t mcc_cq_lock;
  316. u32 num_msix_vec;
  317. u32 num_evt_qs;
  318. struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
  319. struct msix_entry msix_entries[MAX_MSIX_VECTORS];
  320. bool isr_registered;
  321. /* TX Rings */
  322. u32 num_tx_qs;
  323. struct be_tx_obj tx_obj[MAX_TX_QS];
  324. /* Rx rings */
  325. u32 num_rx_qs;
  326. struct be_rx_obj rx_obj[MAX_RX_QS];
  327. u32 big_page_size; /* Compounded page size shared by rx wrbs */
  328. u8 eq_next_idx;
  329. struct be_drv_stats drv_stats;
  330. u16 vlans_added;
  331. u16 max_vlans; /* Number of vlans supported */
  332. u8 vlan_tag[VLAN_N_VID];
  333. u8 vlan_prio_bmap; /* Available Priority BitMap */
  334. u16 recommended_prio; /* Recommended Priority */
  335. struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
  336. struct be_dma_mem stats_cmd;
  337. /* Work queue used to perform periodic tasks like getting statistics */
  338. struct delayed_work work;
  339. u16 work_counter;
  340. u32 flags;
  341. /* Ethtool knobs and info */
  342. char fw_ver[FW_VER_LEN];
  343. int if_handle; /* Used to configure filtering */
  344. u32 *pmac_id; /* MAC addr handle used by BE card */
  345. u32 beacon_state; /* for set_phys_id */
  346. bool eeh_err;
  347. bool ue_detected;
  348. bool fw_timeout;
  349. u32 port_num;
  350. bool promiscuous;
  351. u32 function_mode;
  352. u32 function_caps;
  353. u32 rx_fc; /* Rx flow control */
  354. u32 tx_fc; /* Tx flow control */
  355. bool stats_cmd_sent;
  356. u8 generation; /* BladeEngine ASIC generation */
  357. u32 flash_status;
  358. struct completion flash_compl;
  359. u32 num_vfs; /* Number of VFs provisioned by PF driver */
  360. u32 dev_num_vfs; /* Number of VFs supported by HW */
  361. u8 virtfn;
  362. struct be_vf_cfg *vf_cfg;
  363. bool be3_native;
  364. u32 sli_family;
  365. u8 hba_port_num;
  366. u16 pvid;
  367. struct phy_info phy;
  368. u8 wol_cap;
  369. bool wol;
  370. u32 max_pmac_cnt; /* Max secondary UC MACs programmable */
  371. u32 uc_macs; /* Count of secondary UC MAC programmed */
  372. };
  373. #define be_physfn(adapter) (!adapter->virtfn)
  374. #define sriov_enabled(adapter) (adapter->num_vfs > 0)
  375. #define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
  376. be_physfn(adapter))
  377. #define for_all_vfs(adapter, vf_cfg, i) \
  378. for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
  379. i++, vf_cfg++)
  380. /* BladeEngine Generation numbers */
  381. #define BE_GEN2 2
  382. #define BE_GEN3 3
  383. #define ON 1
  384. #define OFF 0
  385. #define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \
  386. (adapter->pdev->device == OC_DEVICE_ID4))
  387. extern const struct ethtool_ops be_ethtool_ops;
  388. #define msix_enabled(adapter) (adapter->num_msix_vec > 0)
  389. #define num_irqs(adapter) (msix_enabled(adapter) ? \
  390. adapter->num_msix_vec : 1)
  391. #define tx_stats(txo) (&(txo)->stats)
  392. #define rx_stats(rxo) (&(rxo)->stats)
  393. /* The default RXQ is the last RXQ */
  394. #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
  395. #define for_all_rx_queues(adapter, rxo, i) \
  396. for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
  397. i++, rxo++)
  398. /* Skip the default non-rss queue (last one)*/
  399. #define for_all_rss_queues(adapter, rxo, i) \
  400. for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
  401. i++, rxo++)
  402. #define for_all_tx_queues(adapter, txo, i) \
  403. for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
  404. i++, txo++)
  405. #define for_all_evt_queues(adapter, eqo, i) \
  406. for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
  407. i++, eqo++)
  408. #define is_mcc_eqo(eqo) (eqo->idx == 0)
  409. #define mcc_eqo(adapter) (&adapter->eq_obj[0])
  410. #define PAGE_SHIFT_4K 12
  411. #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
  412. /* Returns number of pages spanned by the data starting at the given addr */
  413. #define PAGES_4K_SPANNED(_address, size) \
  414. ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
  415. (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
  416. /* Returns bit offset within a DWORD of a bitfield */
  417. #define AMAP_BIT_OFFSET(_struct, field) \
  418. (((size_t)&(((_struct *)0)->field))%32)
  419. /* Returns the bit mask of the field that is NOT shifted into location. */
  420. static inline u32 amap_mask(u32 bitsize)
  421. {
  422. return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
  423. }
  424. static inline void
  425. amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
  426. {
  427. u32 *dw = (u32 *) ptr + dw_offset;
  428. *dw &= ~(mask << offset);
  429. *dw |= (mask & value) << offset;
  430. }
  431. #define AMAP_SET_BITS(_struct, field, ptr, val) \
  432. amap_set(ptr, \
  433. offsetof(_struct, field)/32, \
  434. amap_mask(sizeof(((_struct *)0)->field)), \
  435. AMAP_BIT_OFFSET(_struct, field), \
  436. val)
  437. static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
  438. {
  439. u32 *dw = (u32 *) ptr;
  440. return mask & (*(dw + dw_offset) >> offset);
  441. }
  442. #define AMAP_GET_BITS(_struct, field, ptr) \
  443. amap_get(ptr, \
  444. offsetof(_struct, field)/32, \
  445. amap_mask(sizeof(((_struct *)0)->field)), \
  446. AMAP_BIT_OFFSET(_struct, field))
  447. #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
  448. #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
  449. static inline void swap_dws(void *wrb, int len)
  450. {
  451. #ifdef __BIG_ENDIAN
  452. u32 *dw = wrb;
  453. BUG_ON(len % 4);
  454. do {
  455. *dw = cpu_to_le32(*dw);
  456. dw++;
  457. len -= 4;
  458. } while (len);
  459. #endif /* __BIG_ENDIAN */
  460. }
  461. static inline u8 is_tcp_pkt(struct sk_buff *skb)
  462. {
  463. u8 val = 0;
  464. if (ip_hdr(skb)->version == 4)
  465. val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
  466. else if (ip_hdr(skb)->version == 6)
  467. val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
  468. return val;
  469. }
  470. static inline u8 is_udp_pkt(struct sk_buff *skb)
  471. {
  472. u8 val = 0;
  473. if (ip_hdr(skb)->version == 4)
  474. val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
  475. else if (ip_hdr(skb)->version == 6)
  476. val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
  477. return val;
  478. }
  479. static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
  480. {
  481. u32 addr;
  482. addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
  483. mac[5] = (u8)(addr & 0xFF);
  484. mac[4] = (u8)((addr >> 8) & 0xFF);
  485. mac[3] = (u8)((addr >> 16) & 0xFF);
  486. /* Use the OUI from the current MAC address */
  487. memcpy(mac, adapter->netdev->dev_addr, 3);
  488. }
  489. static inline bool be_multi_rxq(const struct be_adapter *adapter)
  490. {
  491. return adapter->num_rx_qs > 1;
  492. }
  493. static inline bool be_error(struct be_adapter *adapter)
  494. {
  495. return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout;
  496. }
  497. static inline bool be_is_wol_excluded(struct be_adapter *adapter)
  498. {
  499. struct pci_dev *pdev = adapter->pdev;
  500. if (!be_physfn(adapter))
  501. return true;
  502. switch (pdev->subsystem_device) {
  503. case OC_SUBSYS_DEVICE_ID1:
  504. case OC_SUBSYS_DEVICE_ID2:
  505. case OC_SUBSYS_DEVICE_ID3:
  506. case OC_SUBSYS_DEVICE_ID4:
  507. return true;
  508. default:
  509. return false;
  510. }
  511. }
  512. extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
  513. u16 num_popped);
  514. extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
  515. extern void be_parse_stats(struct be_adapter *adapter);
  516. extern int be_load_fw(struct be_adapter *adapter, u8 *func);
  517. extern bool be_is_wol_supported(struct be_adapter *adapter);
  518. extern bool be_pause_supported(struct be_adapter *adapter);
  519. #endif /* BE_H */