Kconfig 22 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_OPROFILE
  22. config ZONE_DMA
  23. bool
  24. default y
  25. config SEMAPHORE_SLEEPERS
  26. bool
  27. default y
  28. config GENERIC_FIND_NEXT_BIT
  29. bool
  30. default y
  31. config GENERIC_HWEIGHT
  32. bool
  33. default y
  34. config GENERIC_HARDIRQS
  35. bool
  36. default y
  37. config GENERIC_IRQ_PROBE
  38. bool
  39. default y
  40. config GENERIC_TIME
  41. bool
  42. default n
  43. config GENERIC_GPIO
  44. bool
  45. default y
  46. config FORCE_MAX_ZONEORDER
  47. int
  48. default "14"
  49. config GENERIC_CALIBRATE_DELAY
  50. bool
  51. default y
  52. config HARDWARE_PM
  53. def_bool y
  54. depends on OPROFILE
  55. source "init/Kconfig"
  56. source "kernel/Kconfig.preempt"
  57. menu "Blackfin Processor Options"
  58. comment "Processor and Board Settings"
  59. choice
  60. prompt "CPU"
  61. default BF533
  62. config BF522
  63. bool "BF522"
  64. help
  65. BF522 Processor Support.
  66. config BF523
  67. bool "BF523"
  68. help
  69. BF523 Processor Support.
  70. config BF524
  71. bool "BF524"
  72. help
  73. BF524 Processor Support.
  74. config BF525
  75. bool "BF525"
  76. help
  77. BF525 Processor Support.
  78. config BF526
  79. bool "BF526"
  80. help
  81. BF526 Processor Support.
  82. config BF527
  83. bool "BF527"
  84. help
  85. BF527 Processor Support.
  86. config BF531
  87. bool "BF531"
  88. help
  89. BF531 Processor Support.
  90. config BF532
  91. bool "BF532"
  92. help
  93. BF532 Processor Support.
  94. config BF533
  95. bool "BF533"
  96. help
  97. BF533 Processor Support.
  98. config BF534
  99. bool "BF534"
  100. help
  101. BF534 Processor Support.
  102. config BF536
  103. bool "BF536"
  104. help
  105. BF536 Processor Support.
  106. config BF537
  107. bool "BF537"
  108. help
  109. BF537 Processor Support.
  110. config BF542
  111. bool "BF542"
  112. help
  113. BF542 Processor Support.
  114. config BF544
  115. bool "BF544"
  116. help
  117. BF544 Processor Support.
  118. config BF547
  119. bool "BF547"
  120. help
  121. BF547 Processor Support.
  122. config BF548
  123. bool "BF548"
  124. help
  125. BF548 Processor Support.
  126. config BF549
  127. bool "BF549"
  128. help
  129. BF549 Processor Support.
  130. config BF561
  131. bool "BF561"
  132. help
  133. Not Supported Yet - Work in progress - BF561 Processor Support.
  134. endchoice
  135. choice
  136. prompt "Silicon Rev"
  137. default BF_REV_0_1 if BF527
  138. default BF_REV_0_2 if BF537
  139. default BF_REV_0_3 if BF533
  140. default BF_REV_0_0 if BF549
  141. config BF_REV_0_0
  142. bool "0.0"
  143. depends on (BF52x || BF54x)
  144. config BF_REV_0_1
  145. bool "0.1"
  146. depends on (BF52x || BF54x)
  147. config BF_REV_0_2
  148. bool "0.2"
  149. depends on (BF537 || BF536 || BF534)
  150. config BF_REV_0_3
  151. bool "0.3"
  152. depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  153. config BF_REV_0_4
  154. bool "0.4"
  155. depends on (BF561 || BF533 || BF532 || BF531)
  156. config BF_REV_0_5
  157. bool "0.5"
  158. depends on (BF561 || BF533 || BF532 || BF531)
  159. config BF_REV_ANY
  160. bool "any"
  161. config BF_REV_NONE
  162. bool "none"
  163. endchoice
  164. config BF52x
  165. bool
  166. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  167. default y
  168. config BF53x
  169. bool
  170. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  171. default y
  172. config BF54x
  173. bool
  174. depends on (BF542 || BF544 || BF547 || BF548 || BF549)
  175. default y
  176. config BFIN_DUAL_CORE
  177. bool
  178. depends on (BF561)
  179. default y
  180. config BFIN_SINGLE_CORE
  181. bool
  182. depends on !BFIN_DUAL_CORE
  183. default y
  184. config MEM_GENERIC_BOARD
  185. bool
  186. depends on GENERIC_BOARD
  187. default y
  188. config MEM_MT48LC64M4A2FB_7E
  189. bool
  190. depends on (BFIN533_STAMP)
  191. default y
  192. config MEM_MT48LC16M16A2TG_75
  193. bool
  194. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  195. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  196. || H8606_HVSISTEMAS)
  197. default y
  198. config MEM_MT48LC32M8A2_75
  199. bool
  200. depends on (BFIN537_STAMP || PNAV10)
  201. default y
  202. config MEM_MT48LC8M32B2B5_7
  203. bool
  204. depends on (BFIN561_BLUETECHNIX_CM)
  205. default y
  206. config MEM_MT48LC32M16A2TG_75
  207. bool
  208. depends on (BFIN527_EZKIT)
  209. default y
  210. source "arch/blackfin/mach-bf527/Kconfig"
  211. source "arch/blackfin/mach-bf533/Kconfig"
  212. source "arch/blackfin/mach-bf561/Kconfig"
  213. source "arch/blackfin/mach-bf537/Kconfig"
  214. source "arch/blackfin/mach-bf548/Kconfig"
  215. menu "Board customizations"
  216. config CMDLINE_BOOL
  217. bool "Default bootloader kernel arguments"
  218. config CMDLINE
  219. string "Initial kernel command string"
  220. depends on CMDLINE_BOOL
  221. default "console=ttyBF0,57600"
  222. help
  223. If you don't have a boot loader capable of passing a command line string
  224. to the kernel, you may specify one here. As a minimum, you should specify
  225. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  226. comment "Clock/PLL Setup"
  227. config CLKIN_HZ
  228. int "Crystal Frequency in Hz"
  229. default "11059200" if BFIN533_STAMP
  230. default "27000000" if BFIN533_EZKIT
  231. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
  232. default "30000000" if BFIN561_EZKIT
  233. default "24576000" if PNAV10
  234. help
  235. The frequency of CLKIN crystal oscillator on the board in Hz.
  236. config BFIN_KERNEL_CLOCK
  237. bool "Re-program Clocks while Kernel boots?"
  238. default n
  239. help
  240. This option decides if kernel clocks are re-programed from the
  241. bootloader settings. If the clocks are not set, the SDRAM settings
  242. are also not changed, and the Bootloader does 100% of the hardware
  243. configuration.
  244. config PLL_BYPASS
  245. bool "Bypass PLL"
  246. depends on BFIN_KERNEL_CLOCK
  247. default n
  248. config CLKIN_HALF
  249. bool "Half Clock In"
  250. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  251. default n
  252. help
  253. If this is set the clock will be divided by 2, before it goes to the PLL.
  254. config VCO_MULT
  255. int "VCO Multiplier"
  256. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  257. range 1 64
  258. default "22" if BFIN533_EZKIT
  259. default "45" if BFIN533_STAMP
  260. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
  261. default "22" if BFIN533_BLUETECHNIX_CM
  262. default "20" if BFIN537_BLUETECHNIX_CM
  263. default "20" if BFIN561_BLUETECHNIX_CM
  264. default "20" if BFIN561_EZKIT
  265. default "16" if H8606_HVSISTEMAS
  266. help
  267. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  268. PLL Frequency = (Crystal Frequency) * (this setting)
  269. choice
  270. prompt "Core Clock Divider"
  271. depends on BFIN_KERNEL_CLOCK
  272. default CCLK_DIV_1
  273. help
  274. This sets the frequency of the core. It can be 1, 2, 4 or 8
  275. Core Frequency = (PLL frequency) / (this setting)
  276. config CCLK_DIV_1
  277. bool "1"
  278. config CCLK_DIV_2
  279. bool "2"
  280. config CCLK_DIV_4
  281. bool "4"
  282. config CCLK_DIV_8
  283. bool "8"
  284. endchoice
  285. config SCLK_DIV
  286. int "System Clock Divider"
  287. depends on BFIN_KERNEL_CLOCK
  288. range 1 15
  289. default 5 if BFIN533_EZKIT
  290. default 5 if BFIN533_STAMP
  291. default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
  292. default 5 if BFIN533_BLUETECHNIX_CM
  293. default 4 if BFIN537_BLUETECHNIX_CM
  294. default 4 if BFIN561_BLUETECHNIX_CM
  295. default 5 if BFIN561_EZKIT
  296. default 3 if H8606_HVSISTEMAS
  297. help
  298. This sets the frequency of the system clock (including SDRAM or DDR).
  299. This can be between 1 and 15
  300. System Clock = (PLL frequency) / (this setting)
  301. #
  302. # Max & Min Speeds for various Chips
  303. #
  304. config MAX_VCO_HZ
  305. int
  306. default 600000000 if BF522
  307. default 400000000 if BF523
  308. default 400000000 if BF524
  309. default 600000000 if BF525
  310. default 400000000 if BF526
  311. default 600000000 if BF527
  312. default 400000000 if BF531
  313. default 400000000 if BF532
  314. default 750000000 if BF533
  315. default 500000000 if BF534
  316. default 400000000 if BF536
  317. default 600000000 if BF537
  318. default 533333333 if BF538
  319. default 533333333 if BF539
  320. default 600000000 if BF542
  321. default 533333333 if BF544
  322. default 600000000 if BF547
  323. default 600000000 if BF548
  324. default 533333333 if BF549
  325. default 600000000 if BF561
  326. config MIN_VCO_HZ
  327. int
  328. default 50000000
  329. config MAX_SCLK_HZ
  330. int
  331. default 133333333
  332. config MIN_SCLK_HZ
  333. int
  334. default 27000000
  335. comment "Kernel Timer/Scheduler"
  336. source kernel/Kconfig.hz
  337. comment "Memory Setup"
  338. config MEM_SIZE
  339. int "SDRAM Memory Size in MBytes"
  340. default 32 if BFIN533_EZKIT
  341. default 64 if BFIN527_EZKIT
  342. default 64 if BFIN537_STAMP
  343. default 64 if BFIN548_EZKIT
  344. default 64 if BFIN561_EZKIT
  345. default 128 if BFIN533_STAMP
  346. default 64 if PNAV10
  347. default 32 if H8606_HVSISTEMAS
  348. config MEM_ADD_WIDTH
  349. int "SDRAM Memory Address Width"
  350. depends on (!BF54x)
  351. default 9 if BFIN533_EZKIT
  352. default 9 if BFIN561_EZKIT
  353. default 9 if H8606_HVSISTEMAS
  354. default 10 if BFIN527_EZKIT
  355. default 10 if BFIN537_STAMP
  356. default 11 if BFIN533_STAMP
  357. default 10 if PNAV10
  358. choice
  359. prompt "DDR SDRAM Chip Type"
  360. depends on BFIN548_EZKIT
  361. default MEM_MT46V32M16_5B
  362. config MEM_MT46V32M16_6T
  363. bool "MT46V32M16_6T"
  364. config MEM_MT46V32M16_5B
  365. bool "MT46V32M16_5B"
  366. endchoice
  367. config ENET_FLASH_PIN
  368. int "PF port/pin used for flash and ethernet sharing"
  369. depends on (BFIN533_STAMP)
  370. default 0
  371. help
  372. PF port/pin used for flash and ethernet sharing to allow other PF
  373. pins to be used on other platforms without having to touch common
  374. code.
  375. For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
  376. config BOOT_LOAD
  377. hex "Kernel load address for booting"
  378. default "0x1000"
  379. range 0x1000 0x20000000
  380. help
  381. This option allows you to set the load address of the kernel.
  382. This can be useful if you are on a board which has a small amount
  383. of memory or you wish to reserve some memory at the beginning of
  384. the address space.
  385. Note that you need to keep this value above 4k (0x1000) as this
  386. memory region is used to capture NULL pointer references as well
  387. as some core kernel functions.
  388. choice
  389. prompt "Blackfin Exception Scratch Register"
  390. default BFIN_SCRATCH_REG_RETN
  391. help
  392. Select the resource to reserve for the Exception handler:
  393. - RETN: Non-Maskable Interrupt (NMI)
  394. - RETE: Exception Return (JTAG/ICE)
  395. - CYCLES: Performance counter
  396. If you are unsure, please select "RETN".
  397. config BFIN_SCRATCH_REG_RETN
  398. bool "RETN"
  399. help
  400. Use the RETN register in the Blackfin exception handler
  401. as a stack scratch register. This means you cannot
  402. safely use NMI on the Blackfin while running Linux, but
  403. you can debug the system with a JTAG ICE and use the
  404. CYCLES performance registers.
  405. If you are unsure, please select "RETN".
  406. config BFIN_SCRATCH_REG_RETE
  407. bool "RETE"
  408. help
  409. Use the RETE register in the Blackfin exception handler
  410. as a stack scratch register. This means you cannot
  411. safely use a JTAG ICE while debugging a Blackfin board,
  412. but you can safely use the CYCLES performance registers
  413. and the NMI.
  414. If you are unsure, please select "RETN".
  415. config BFIN_SCRATCH_REG_CYCLES
  416. bool "CYCLES"
  417. help
  418. Use the CYCLES register in the Blackfin exception handler
  419. as a stack scratch register. This means you cannot
  420. safely use the CYCLES performance registers on a Blackfin
  421. board at anytime, but you can debug the system with a JTAG
  422. ICE and use the NMI.
  423. If you are unsure, please select "RETN".
  424. endchoice
  425. endmenu
  426. menu "Blackfin Kernel Optimizations"
  427. comment "Memory Optimizations"
  428. config I_ENTRY_L1
  429. bool "Locate interrupt entry code in L1 Memory"
  430. default y
  431. help
  432. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  433. into L1 instruction memory. (less latency)
  434. config EXCPT_IRQ_SYSC_L1
  435. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  436. default y
  437. help
  438. If enabled, the entire ASM lowlevel exception and interrupt entry code
  439. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  440. (less latency)
  441. config DO_IRQ_L1
  442. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  443. default y
  444. help
  445. If enabled, the frequently called do_irq dispatcher function is linked
  446. into L1 instruction memory. (less latency)
  447. config CORE_TIMER_IRQ_L1
  448. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  449. default y
  450. help
  451. If enabled, the frequently called timer_interrupt() function is linked
  452. into L1 instruction memory. (less latency)
  453. config IDLE_L1
  454. bool "Locate frequently idle function in L1 Memory"
  455. default y
  456. help
  457. If enabled, the frequently called idle function is linked
  458. into L1 instruction memory. (less latency)
  459. config SCHEDULE_L1
  460. bool "Locate kernel schedule function in L1 Memory"
  461. default y
  462. help
  463. If enabled, the frequently called kernel schedule is linked
  464. into L1 instruction memory. (less latency)
  465. config ARITHMETIC_OPS_L1
  466. bool "Locate kernel owned arithmetic functions in L1 Memory"
  467. default y
  468. help
  469. If enabled, arithmetic functions are linked
  470. into L1 instruction memory. (less latency)
  471. config ACCESS_OK_L1
  472. bool "Locate access_ok function in L1 Memory"
  473. default y
  474. help
  475. If enabled, the access_ok function is linked
  476. into L1 instruction memory. (less latency)
  477. config MEMSET_L1
  478. bool "Locate memset function in L1 Memory"
  479. default y
  480. help
  481. If enabled, the memset function is linked
  482. into L1 instruction memory. (less latency)
  483. config MEMCPY_L1
  484. bool "Locate memcpy function in L1 Memory"
  485. default y
  486. help
  487. If enabled, the memcpy function is linked
  488. into L1 instruction memory. (less latency)
  489. config SYS_BFIN_SPINLOCK_L1
  490. bool "Locate sys_bfin_spinlock function in L1 Memory"
  491. default y
  492. help
  493. If enabled, sys_bfin_spinlock function is linked
  494. into L1 instruction memory. (less latency)
  495. config IP_CHECKSUM_L1
  496. bool "Locate IP Checksum function in L1 Memory"
  497. default n
  498. help
  499. If enabled, the IP Checksum function is linked
  500. into L1 instruction memory. (less latency)
  501. config CACHELINE_ALIGNED_L1
  502. bool "Locate cacheline_aligned data to L1 Data Memory"
  503. default y if !BF54x
  504. default n if BF54x
  505. depends on !BF531
  506. help
  507. If enabled, cacheline_anligned data is linked
  508. into L1 data memory. (less latency)
  509. config SYSCALL_TAB_L1
  510. bool "Locate Syscall Table L1 Data Memory"
  511. default n
  512. depends on !BF531
  513. help
  514. If enabled, the Syscall LUT is linked
  515. into L1 data memory. (less latency)
  516. config CPLB_SWITCH_TAB_L1
  517. bool "Locate CPLB Switch Tables L1 Data Memory"
  518. default n
  519. depends on !BF531
  520. help
  521. If enabled, the CPLB Switch Tables are linked
  522. into L1 data memory. (less latency)
  523. endmenu
  524. choice
  525. prompt "Kernel executes from"
  526. help
  527. Choose the memory type that the kernel will be running in.
  528. config RAMKERNEL
  529. bool "RAM"
  530. help
  531. The kernel will be resident in RAM when running.
  532. config ROMKERNEL
  533. bool "ROM"
  534. help
  535. The kernel will be resident in FLASH/ROM when running.
  536. endchoice
  537. source "mm/Kconfig"
  538. config LARGE_ALLOCS
  539. bool "Allow allocating large blocks (> 1MB) of memory"
  540. help
  541. Allow the slab memory allocator to keep chains for very large
  542. memory sizes - upto 32MB. You may need this if your system has
  543. a lot of RAM, and you need to able to allocate very large
  544. contiguous chunks. If unsure, say N.
  545. config BFIN_GPTIMERS
  546. tristate "Enable Blackfin General Purpose Timers API"
  547. default n
  548. help
  549. Enable support for the General Purpose Timers API. If you
  550. are unsure, say N.
  551. To compile this driver as a module, choose M here: the module
  552. will be called gptimers.ko.
  553. config BFIN_DMA_5XX
  554. bool "Enable DMA Support"
  555. depends on (BF52x || BF53x || BF561 || BF54x)
  556. default y
  557. help
  558. DMA driver for BF5xx.
  559. choice
  560. prompt "Uncached SDRAM region"
  561. default DMA_UNCACHED_1M
  562. depends on BFIN_DMA_5XX
  563. config DMA_UNCACHED_2M
  564. bool "Enable 2M DMA region"
  565. config DMA_UNCACHED_1M
  566. bool "Enable 1M DMA region"
  567. config DMA_UNCACHED_NONE
  568. bool "Disable DMA region"
  569. endchoice
  570. comment "Cache Support"
  571. config BFIN_ICACHE
  572. bool "Enable ICACHE"
  573. config BFIN_DCACHE
  574. bool "Enable DCACHE"
  575. config BFIN_DCACHE_BANKA
  576. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  577. depends on BFIN_DCACHE && !BF531
  578. default n
  579. config BFIN_ICACHE_LOCK
  580. bool "Enable Instruction Cache Locking"
  581. choice
  582. prompt "Policy"
  583. depends on BFIN_DCACHE
  584. default BFIN_WB
  585. config BFIN_WB
  586. bool "Write back"
  587. help
  588. Write Back Policy:
  589. Cached data will be written back to SDRAM only when needed.
  590. This can give a nice increase in performance, but beware of
  591. broken drivers that do not properly invalidate/flush their
  592. cache.
  593. Write Through Policy:
  594. Cached data will always be written back to SDRAM when the
  595. cache is updated. This is a completely safe setting, but
  596. performance is worse than Write Back.
  597. If you are unsure of the options and you want to be safe,
  598. then go with Write Through.
  599. config BFIN_WT
  600. bool "Write through"
  601. help
  602. Write Back Policy:
  603. Cached data will be written back to SDRAM only when needed.
  604. This can give a nice increase in performance, but beware of
  605. broken drivers that do not properly invalidate/flush their
  606. cache.
  607. Write Through Policy:
  608. Cached data will always be written back to SDRAM when the
  609. cache is updated. This is a completely safe setting, but
  610. performance is worse than Write Back.
  611. If you are unsure of the options and you want to be safe,
  612. then go with Write Through.
  613. endchoice
  614. config L1_MAX_PIECE
  615. int "Set the max L1 SRAM pieces"
  616. default 16
  617. help
  618. Set the max memory pieces for the L1 SRAM allocation algorithm.
  619. Min value is 16. Max value is 1024.
  620. config MPU
  621. bool "Enable the memory protection unit (EXPERIMENTAL)"
  622. default n
  623. help
  624. Use the processor's MPU to protect applications from accessing
  625. memory they do not own. This comes at a performance penalty
  626. and is recommended only for debugging.
  627. comment "Asynchonous Memory Configuration"
  628. menu "EBIU_AMGCTL Global Control"
  629. config C_AMCKEN
  630. bool "Enable CLKOUT"
  631. default y
  632. config C_CDPRIO
  633. bool "DMA has priority over core for ext. accesses"
  634. default n
  635. config C_B0PEN
  636. depends on BF561
  637. bool "Bank 0 16 bit packing enable"
  638. default y
  639. config C_B1PEN
  640. depends on BF561
  641. bool "Bank 1 16 bit packing enable"
  642. default y
  643. config C_B2PEN
  644. depends on BF561
  645. bool "Bank 2 16 bit packing enable"
  646. default y
  647. config C_B3PEN
  648. depends on BF561
  649. bool "Bank 3 16 bit packing enable"
  650. default n
  651. choice
  652. prompt"Enable Asynchonous Memory Banks"
  653. default C_AMBEN_ALL
  654. config C_AMBEN
  655. bool "Disable All Banks"
  656. config C_AMBEN_B0
  657. bool "Enable Bank 0"
  658. config C_AMBEN_B0_B1
  659. bool "Enable Bank 0 & 1"
  660. config C_AMBEN_B0_B1_B2
  661. bool "Enable Bank 0 & 1 & 2"
  662. config C_AMBEN_ALL
  663. bool "Enable All Banks"
  664. endchoice
  665. endmenu
  666. menu "EBIU_AMBCTL Control"
  667. config BANK_0
  668. hex "Bank 0"
  669. default 0x7BB0
  670. config BANK_1
  671. hex "Bank 1"
  672. default 0x7BB0
  673. config BANK_2
  674. hex "Bank 2"
  675. default 0x7BB0
  676. config BANK_3
  677. hex "Bank 3"
  678. default 0x99B3
  679. endmenu
  680. config EBIU_MBSCTLVAL
  681. hex "EBIU Bank Select Control Register"
  682. depends on BF54x
  683. default 0
  684. config EBIU_MODEVAL
  685. hex "Flash Memory Mode Control Register"
  686. depends on BF54x
  687. default 1
  688. config EBIU_FCTLVAL
  689. hex "Flash Memory Bank Control Register"
  690. depends on BF54x
  691. default 6
  692. endmenu
  693. #############################################################################
  694. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  695. config PCI
  696. bool "PCI support"
  697. help
  698. Support for PCI bus.
  699. source "drivers/pci/Kconfig"
  700. config HOTPLUG
  701. bool "Support for hot-pluggable device"
  702. help
  703. Say Y here if you want to plug devices into your computer while
  704. the system is running, and be able to use them quickly. In many
  705. cases, the devices can likewise be unplugged at any time too.
  706. One well known example of this is PCMCIA- or PC-cards, credit-card
  707. size devices such as network cards, modems or hard drives which are
  708. plugged into slots found on all modern laptop computers. Another
  709. example, used on modern desktops as well as laptops, is USB.
  710. Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
  711. software (at <http://linux-hotplug.sourceforge.net/>) and install it.
  712. Then your kernel will automatically call out to a user mode "policy
  713. agent" (/sbin/hotplug) to load modules and set up software needed
  714. to use devices as you hotplug them.
  715. source "drivers/pcmcia/Kconfig"
  716. source "drivers/pci/hotplug/Kconfig"
  717. endmenu
  718. menu "Executable file formats"
  719. source "fs/Kconfig.binfmt"
  720. endmenu
  721. menu "Power management options"
  722. source "kernel/power/Kconfig"
  723. config ARCH_SUSPEND_POSSIBLE
  724. def_bool y
  725. depends on !SMP
  726. choice
  727. prompt "Default Power Saving Mode"
  728. depends on PM
  729. default PM_BFIN_SLEEP_DEEPER
  730. config PM_BFIN_SLEEP_DEEPER
  731. bool "Sleep Deeper"
  732. help
  733. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  734. power dissipation by disabling the clock to the processor core (CCLK).
  735. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  736. to 0.85 V to provide the greatest power savings, while preserving the
  737. processor state.
  738. The PLL and system clock (SCLK) continue to operate at a very low
  739. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  740. the SDRAM is put into Self Refresh Mode. Typically an external event
  741. such as GPIO interrupt or RTC activity wakes up the processor.
  742. Various Peripherals such as UART, SPORT, PPI may not function as
  743. normal during Sleep Deeper, due to the reduced SCLK frequency.
  744. When in the sleep mode, system DMA access to L1 memory is not supported.
  745. config PM_BFIN_SLEEP
  746. bool "Sleep"
  747. help
  748. Sleep Mode (High Power Savings) - The sleep mode reduces power
  749. dissipation by disabling the clock to the processor core (CCLK).
  750. The PLL and system clock (SCLK), however, continue to operate in
  751. this mode. Typically an external event or RTC activity will wake
  752. up the processor. When in the sleep mode,
  753. system DMA access to L1 memory is not supported.
  754. endchoice
  755. config PM_WAKEUP_BY_GPIO
  756. bool "Cause Wakeup Event by GPIO"
  757. config PM_WAKEUP_GPIO_NUMBER
  758. int "Wakeup GPIO number"
  759. range 0 47
  760. depends on PM_WAKEUP_BY_GPIO
  761. default 2 if BFIN537_STAMP
  762. choice
  763. prompt "GPIO Polarity"
  764. depends on PM_WAKEUP_BY_GPIO
  765. default PM_WAKEUP_GPIO_POLAR_H
  766. config PM_WAKEUP_GPIO_POLAR_H
  767. bool "Active High"
  768. config PM_WAKEUP_GPIO_POLAR_L
  769. bool "Active Low"
  770. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  771. bool "Falling EDGE"
  772. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  773. bool "Rising EDGE"
  774. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  775. bool "Both EDGE"
  776. endchoice
  777. endmenu
  778. if (BF537 || BF533 || BF54x)
  779. menu "CPU Frequency scaling"
  780. source "drivers/cpufreq/Kconfig"
  781. config CPU_FREQ
  782. bool
  783. default n
  784. help
  785. If you want to enable this option, you should select the
  786. DPMC driver from Character Devices.
  787. endmenu
  788. endif
  789. source "net/Kconfig"
  790. source "drivers/Kconfig"
  791. source "fs/Kconfig"
  792. source "arch/blackfin/Kconfig.debug"
  793. source "security/Kconfig"
  794. source "crypto/Kconfig"
  795. source "lib/Kconfig"