iwl-agn.c 124 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/slab.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/sched.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/wireless.h>
  40. #include <linux/firmware.h>
  41. #include <linux/etherdevice.h>
  42. #include <linux/if_arp.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwlagn"
  46. #include "iwl-eeprom.h"
  47. #include "iwl-dev.h"
  48. #include "iwl-core.h"
  49. #include "iwl-io.h"
  50. #include "iwl-helpers.h"
  51. #include "iwl-sta.h"
  52. #include "iwl-calib.h"
  53. #include "iwl-agn.h"
  54. /******************************************************************************
  55. *
  56. * module boiler plate
  57. *
  58. ******************************************************************************/
  59. /*
  60. * module name, copyright, version, etc.
  61. */
  62. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  63. #ifdef CONFIG_IWLWIFI_DEBUG
  64. #define VD "d"
  65. #else
  66. #define VD
  67. #endif
  68. #define DRV_VERSION IWLWIFI_VERSION VD
  69. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  70. MODULE_VERSION(DRV_VERSION);
  71. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  72. MODULE_LICENSE("GPL");
  73. MODULE_ALIAS("iwl4965");
  74. /**
  75. * iwl_commit_rxon - commit staging_rxon to hardware
  76. *
  77. * The RXON command in staging_rxon is committed to the hardware and
  78. * the active_rxon structure is updated with the new data. This
  79. * function correctly transitions out of the RXON_ASSOC_MSK state if
  80. * a HW tune is required based on the RXON structure changes.
  81. */
  82. int iwl_commit_rxon(struct iwl_priv *priv)
  83. {
  84. /* cast away the const for active_rxon in this function */
  85. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  86. int ret;
  87. bool new_assoc =
  88. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  89. if (!iwl_is_alive(priv))
  90. return -EBUSY;
  91. /* always get timestamp with Rx frame */
  92. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  93. ret = iwl_check_rxon_cmd(priv);
  94. if (ret) {
  95. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  96. return -EINVAL;
  97. }
  98. /*
  99. * receive commit_rxon request
  100. * abort any previous channel switch if still in process
  101. */
  102. if (priv->switch_rxon.switch_in_progress &&
  103. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  104. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  105. le16_to_cpu(priv->switch_rxon.channel));
  106. iwl_chswitch_done(priv, false);
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. iwl_print_rx_config_cmd(priv);
  119. return 0;
  120. }
  121. /* If we are currently associated and the new config requires
  122. * an RXON_ASSOC and the new config wants the associated mask enabled,
  123. * we must clear the associated from the active configuration
  124. * before we apply the new config */
  125. if (iwl_is_associated(priv) && new_assoc) {
  126. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  127. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  128. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  129. sizeof(struct iwl_rxon_cmd),
  130. &priv->active_rxon);
  131. /* If the mask clearing failed then we set
  132. * active_rxon back to what it was previously */
  133. if (ret) {
  134. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  135. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  136. return ret;
  137. }
  138. iwl_clear_ucode_stations(priv);
  139. iwl_restore_stations(priv);
  140. ret = iwl_restore_default_wep_keys(priv);
  141. if (ret) {
  142. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  143. return ret;
  144. }
  145. }
  146. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  147. "* with%s RXON_FILTER_ASSOC_MSK\n"
  148. "* channel = %d\n"
  149. "* bssid = %pM\n",
  150. (new_assoc ? "" : "out"),
  151. le16_to_cpu(priv->staging_rxon.channel),
  152. priv->staging_rxon.bssid_addr);
  153. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  154. /* Apply the new configuration
  155. * RXON unassoc clears the station table in uCode so restoration of
  156. * stations is needed after it (the RXON command) completes
  157. */
  158. if (!new_assoc) {
  159. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  160. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  161. if (ret) {
  162. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  163. return ret;
  164. }
  165. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
  166. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  167. iwl_clear_ucode_stations(priv);
  168. iwl_restore_stations(priv);
  169. ret = iwl_restore_default_wep_keys(priv);
  170. if (ret) {
  171. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  172. return ret;
  173. }
  174. }
  175. priv->start_calib = 0;
  176. if (new_assoc) {
  177. /*
  178. * allow CTS-to-self if possible for new association.
  179. * this is relevant only for 5000 series and up,
  180. * but will not damage 4965
  181. */
  182. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  183. /* Apply the new configuration
  184. * RXON assoc doesn't clear the station table in uCode,
  185. */
  186. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  187. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  188. if (ret) {
  189. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  190. return ret;
  191. }
  192. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  193. }
  194. iwl_print_rx_config_cmd(priv);
  195. iwl_init_sensitivity(priv);
  196. /* If we issue a new RXON command which required a tune then we must
  197. * send a new TXPOWER command or we won't be able to Tx any frames */
  198. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  199. if (ret) {
  200. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  201. return ret;
  202. }
  203. return 0;
  204. }
  205. void iwl_update_chain_flags(struct iwl_priv *priv)
  206. {
  207. if (priv->cfg->ops->hcmd->set_rxon_chain)
  208. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  209. iwlcore_commit_rxon(priv);
  210. }
  211. static void iwl_clear_free_frames(struct iwl_priv *priv)
  212. {
  213. struct list_head *element;
  214. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  215. priv->frames_count);
  216. while (!list_empty(&priv->free_frames)) {
  217. element = priv->free_frames.next;
  218. list_del(element);
  219. kfree(list_entry(element, struct iwl_frame, list));
  220. priv->frames_count--;
  221. }
  222. if (priv->frames_count) {
  223. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  224. priv->frames_count);
  225. priv->frames_count = 0;
  226. }
  227. }
  228. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  229. {
  230. struct iwl_frame *frame;
  231. struct list_head *element;
  232. if (list_empty(&priv->free_frames)) {
  233. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  234. if (!frame) {
  235. IWL_ERR(priv, "Could not allocate frame!\n");
  236. return NULL;
  237. }
  238. priv->frames_count++;
  239. return frame;
  240. }
  241. element = priv->free_frames.next;
  242. list_del(element);
  243. return list_entry(element, struct iwl_frame, list);
  244. }
  245. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  246. {
  247. memset(frame, 0, sizeof(*frame));
  248. list_add(&frame->list, &priv->free_frames);
  249. }
  250. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  251. struct ieee80211_hdr *hdr,
  252. int left)
  253. {
  254. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  255. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  256. (priv->iw_mode != NL80211_IFTYPE_AP)))
  257. return 0;
  258. if (priv->ibss_beacon->len > left)
  259. return 0;
  260. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  261. return priv->ibss_beacon->len;
  262. }
  263. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  264. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  265. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  266. u8 *beacon, u32 frame_size)
  267. {
  268. u16 tim_idx;
  269. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  270. /*
  271. * The index is relative to frame start but we start looking at the
  272. * variable-length part of the beacon.
  273. */
  274. tim_idx = mgmt->u.beacon.variable - beacon;
  275. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  276. while ((tim_idx < (frame_size - 2)) &&
  277. (beacon[tim_idx] != WLAN_EID_TIM))
  278. tim_idx += beacon[tim_idx+1] + 2;
  279. /* If TIM field was found, set variables */
  280. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  281. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  282. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  283. } else
  284. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  285. }
  286. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  287. struct iwl_frame *frame)
  288. {
  289. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  290. u32 frame_size;
  291. u32 rate_flags;
  292. u32 rate;
  293. /*
  294. * We have to set up the TX command, the TX Beacon command, and the
  295. * beacon contents.
  296. */
  297. /* Initialize memory */
  298. tx_beacon_cmd = &frame->u.beacon;
  299. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  300. /* Set up TX beacon contents */
  301. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  302. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  303. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  304. return 0;
  305. /* Set up TX command fields */
  306. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  307. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  308. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  309. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  310. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  311. /* Set up TX beacon command fields */
  312. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  313. frame_size);
  314. /* Set up packet rate and flags */
  315. rate = iwl_rate_get_lowest_plcp(priv);
  316. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  317. priv->hw_params.valid_tx_ant);
  318. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  319. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  320. rate_flags |= RATE_MCS_CCK_MSK;
  321. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  322. rate_flags);
  323. return sizeof(*tx_beacon_cmd) + frame_size;
  324. }
  325. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  326. {
  327. struct iwl_frame *frame;
  328. unsigned int frame_size;
  329. int rc;
  330. frame = iwl_get_free_frame(priv);
  331. if (!frame) {
  332. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  333. "command.\n");
  334. return -ENOMEM;
  335. }
  336. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  337. if (!frame_size) {
  338. IWL_ERR(priv, "Error configuring the beacon command\n");
  339. iwl_free_frame(priv, frame);
  340. return -EINVAL;
  341. }
  342. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  343. &frame->u.cmd[0]);
  344. iwl_free_frame(priv, frame);
  345. return rc;
  346. }
  347. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  348. {
  349. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  350. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  351. if (sizeof(dma_addr_t) > sizeof(u32))
  352. addr |=
  353. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  354. return addr;
  355. }
  356. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  357. {
  358. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  359. return le16_to_cpu(tb->hi_n_len) >> 4;
  360. }
  361. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  362. dma_addr_t addr, u16 len)
  363. {
  364. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  365. u16 hi_n_len = len << 4;
  366. put_unaligned_le32(addr, &tb->lo);
  367. if (sizeof(dma_addr_t) > sizeof(u32))
  368. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  369. tb->hi_n_len = cpu_to_le16(hi_n_len);
  370. tfd->num_tbs = idx + 1;
  371. }
  372. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  373. {
  374. return tfd->num_tbs & 0x1f;
  375. }
  376. /**
  377. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  378. * @priv - driver private data
  379. * @txq - tx queue
  380. *
  381. * Does NOT advance any TFD circular buffer read/write indexes
  382. * Does NOT free the TFD itself (which is within circular buffer)
  383. */
  384. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  385. {
  386. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  387. struct iwl_tfd *tfd;
  388. struct pci_dev *dev = priv->pci_dev;
  389. int index = txq->q.read_ptr;
  390. int i;
  391. int num_tbs;
  392. tfd = &tfd_tmp[index];
  393. /* Sanity check on number of chunks */
  394. num_tbs = iwl_tfd_get_num_tbs(tfd);
  395. if (num_tbs >= IWL_NUM_OF_TBS) {
  396. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  397. /* @todo issue fatal error, it is quite serious situation */
  398. return;
  399. }
  400. /* Unmap tx_cmd */
  401. if (num_tbs)
  402. pci_unmap_single(dev,
  403. dma_unmap_addr(&txq->meta[index], mapping),
  404. dma_unmap_len(&txq->meta[index], len),
  405. PCI_DMA_BIDIRECTIONAL);
  406. /* Unmap chunks, if any. */
  407. for (i = 1; i < num_tbs; i++)
  408. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  409. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  410. /* free SKB */
  411. if (txq->txb) {
  412. struct sk_buff *skb;
  413. skb = txq->txb[txq->q.read_ptr].skb;
  414. /* can be called from irqs-disabled context */
  415. if (skb) {
  416. dev_kfree_skb_any(skb);
  417. txq->txb[txq->q.read_ptr].skb = NULL;
  418. }
  419. }
  420. }
  421. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  422. struct iwl_tx_queue *txq,
  423. dma_addr_t addr, u16 len,
  424. u8 reset, u8 pad)
  425. {
  426. struct iwl_queue *q;
  427. struct iwl_tfd *tfd, *tfd_tmp;
  428. u32 num_tbs;
  429. q = &txq->q;
  430. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  431. tfd = &tfd_tmp[q->write_ptr];
  432. if (reset)
  433. memset(tfd, 0, sizeof(*tfd));
  434. num_tbs = iwl_tfd_get_num_tbs(tfd);
  435. /* Each TFD can point to a maximum 20 Tx buffers */
  436. if (num_tbs >= IWL_NUM_OF_TBS) {
  437. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  438. IWL_NUM_OF_TBS);
  439. return -EINVAL;
  440. }
  441. BUG_ON(addr & ~DMA_BIT_MASK(36));
  442. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  443. IWL_ERR(priv, "Unaligned address = %llx\n",
  444. (unsigned long long)addr);
  445. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  446. return 0;
  447. }
  448. /*
  449. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  450. * given Tx queue, and enable the DMA channel used for that queue.
  451. *
  452. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  453. * channels supported in hardware.
  454. */
  455. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  456. struct iwl_tx_queue *txq)
  457. {
  458. int txq_id = txq->q.id;
  459. /* Circular buffer (TFD queue in DRAM) physical base address */
  460. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  461. txq->q.dma_addr >> 8);
  462. return 0;
  463. }
  464. /******************************************************************************
  465. *
  466. * Generic RX handler implementations
  467. *
  468. ******************************************************************************/
  469. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  470. struct iwl_rx_mem_buffer *rxb)
  471. {
  472. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  473. struct iwl_alive_resp *palive;
  474. struct delayed_work *pwork;
  475. palive = &pkt->u.alive_frame;
  476. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  477. "0x%01X 0x%01X\n",
  478. palive->is_valid, palive->ver_type,
  479. palive->ver_subtype);
  480. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  481. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  482. memcpy(&priv->card_alive_init,
  483. &pkt->u.alive_frame,
  484. sizeof(struct iwl_init_alive_resp));
  485. pwork = &priv->init_alive_start;
  486. } else {
  487. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  488. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  489. sizeof(struct iwl_alive_resp));
  490. pwork = &priv->alive_start;
  491. }
  492. /* We delay the ALIVE response by 5ms to
  493. * give the HW RF Kill time to activate... */
  494. if (palive->is_valid == UCODE_VALID_OK)
  495. queue_delayed_work(priv->workqueue, pwork,
  496. msecs_to_jiffies(5));
  497. else
  498. IWL_WARN(priv, "uCode did not respond OK.\n");
  499. }
  500. static void iwl_bg_beacon_update(struct work_struct *work)
  501. {
  502. struct iwl_priv *priv =
  503. container_of(work, struct iwl_priv, beacon_update);
  504. struct sk_buff *beacon;
  505. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  506. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  507. if (!beacon) {
  508. IWL_ERR(priv, "update beacon failed\n");
  509. return;
  510. }
  511. mutex_lock(&priv->mutex);
  512. /* new beacon skb is allocated every time; dispose previous.*/
  513. if (priv->ibss_beacon)
  514. dev_kfree_skb(priv->ibss_beacon);
  515. priv->ibss_beacon = beacon;
  516. mutex_unlock(&priv->mutex);
  517. iwl_send_beacon_cmd(priv);
  518. }
  519. /**
  520. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  521. *
  522. * This callback is provided in order to send a statistics request.
  523. *
  524. * This timer function is continually reset to execute within
  525. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  526. * was received. We need to ensure we receive the statistics in order
  527. * to update the temperature used for calibrating the TXPOWER.
  528. */
  529. static void iwl_bg_statistics_periodic(unsigned long data)
  530. {
  531. struct iwl_priv *priv = (struct iwl_priv *)data;
  532. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  533. return;
  534. /* dont send host command if rf-kill is on */
  535. if (!iwl_is_ready_rf(priv))
  536. return;
  537. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  538. }
  539. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  540. u32 start_idx, u32 num_events,
  541. u32 mode)
  542. {
  543. u32 i;
  544. u32 ptr; /* SRAM byte address of log data */
  545. u32 ev, time, data; /* event log data */
  546. unsigned long reg_flags;
  547. if (mode == 0)
  548. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  549. else
  550. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  551. /* Make sure device is powered up for SRAM reads */
  552. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  553. if (iwl_grab_nic_access(priv)) {
  554. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  555. return;
  556. }
  557. /* Set starting address; reads will auto-increment */
  558. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  559. rmb();
  560. /*
  561. * "time" is actually "data" for mode 0 (no timestamp).
  562. * place event id # at far right for easier visual parsing.
  563. */
  564. for (i = 0; i < num_events; i++) {
  565. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  566. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  567. if (mode == 0) {
  568. trace_iwlwifi_dev_ucode_cont_event(priv,
  569. 0, time, ev);
  570. } else {
  571. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  572. trace_iwlwifi_dev_ucode_cont_event(priv,
  573. time, data, ev);
  574. }
  575. }
  576. /* Allow device to power down */
  577. iwl_release_nic_access(priv);
  578. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  579. }
  580. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  581. {
  582. u32 capacity; /* event log capacity in # entries */
  583. u32 base; /* SRAM byte address of event log header */
  584. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  585. u32 num_wraps; /* # times uCode wrapped to top of log */
  586. u32 next_entry; /* index of next entry to be written by uCode */
  587. if (priv->ucode_type == UCODE_INIT)
  588. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  589. else
  590. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  591. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  592. capacity = iwl_read_targ_mem(priv, base);
  593. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  594. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  595. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  596. } else
  597. return;
  598. if (num_wraps == priv->event_log.num_wraps) {
  599. iwl_print_cont_event_trace(priv,
  600. base, priv->event_log.next_entry,
  601. next_entry - priv->event_log.next_entry,
  602. mode);
  603. priv->event_log.non_wraps_count++;
  604. } else {
  605. if ((num_wraps - priv->event_log.num_wraps) > 1)
  606. priv->event_log.wraps_more_count++;
  607. else
  608. priv->event_log.wraps_once_count++;
  609. trace_iwlwifi_dev_ucode_wrap_event(priv,
  610. num_wraps - priv->event_log.num_wraps,
  611. next_entry, priv->event_log.next_entry);
  612. if (next_entry < priv->event_log.next_entry) {
  613. iwl_print_cont_event_trace(priv, base,
  614. priv->event_log.next_entry,
  615. capacity - priv->event_log.next_entry,
  616. mode);
  617. iwl_print_cont_event_trace(priv, base, 0,
  618. next_entry, mode);
  619. } else {
  620. iwl_print_cont_event_trace(priv, base,
  621. next_entry, capacity - next_entry,
  622. mode);
  623. iwl_print_cont_event_trace(priv, base, 0,
  624. next_entry, mode);
  625. }
  626. }
  627. priv->event_log.num_wraps = num_wraps;
  628. priv->event_log.next_entry = next_entry;
  629. }
  630. /**
  631. * iwl_bg_ucode_trace - Timer callback to log ucode event
  632. *
  633. * The timer is continually set to execute every
  634. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  635. * this function is to perform continuous uCode event logging operation
  636. * if enabled
  637. */
  638. static void iwl_bg_ucode_trace(unsigned long data)
  639. {
  640. struct iwl_priv *priv = (struct iwl_priv *)data;
  641. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  642. return;
  643. if (priv->event_log.ucode_trace) {
  644. iwl_continuous_event_trace(priv);
  645. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  646. mod_timer(&priv->ucode_trace,
  647. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  648. }
  649. }
  650. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  651. struct iwl_rx_mem_buffer *rxb)
  652. {
  653. #ifdef CONFIG_IWLWIFI_DEBUG
  654. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  655. struct iwl4965_beacon_notif *beacon =
  656. (struct iwl4965_beacon_notif *)pkt->u.raw;
  657. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  658. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  659. "tsf %d %d rate %d\n",
  660. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  661. beacon->beacon_notify_hdr.failure_frame,
  662. le32_to_cpu(beacon->ibss_mgr_status),
  663. le32_to_cpu(beacon->high_tsf),
  664. le32_to_cpu(beacon->low_tsf), rate);
  665. #endif
  666. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  667. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  668. queue_work(priv->workqueue, &priv->beacon_update);
  669. }
  670. /* Handle notification from uCode that card's power state is changing
  671. * due to software, hardware, or critical temperature RFKILL */
  672. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  673. struct iwl_rx_mem_buffer *rxb)
  674. {
  675. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  676. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  677. unsigned long status = priv->status;
  678. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  679. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  680. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  681. (flags & CT_CARD_DISABLED) ?
  682. "Reached" : "Not reached");
  683. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  684. CT_CARD_DISABLED)) {
  685. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  686. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  687. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  688. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  689. if (!(flags & RXON_CARD_DISABLED)) {
  690. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  691. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  692. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  693. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  694. }
  695. if (flags & CT_CARD_DISABLED)
  696. iwl_tt_enter_ct_kill(priv);
  697. }
  698. if (!(flags & CT_CARD_DISABLED))
  699. iwl_tt_exit_ct_kill(priv);
  700. if (flags & HW_CARD_DISABLED)
  701. set_bit(STATUS_RF_KILL_HW, &priv->status);
  702. else
  703. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  704. if (!(flags & RXON_CARD_DISABLED))
  705. iwl_scan_cancel(priv);
  706. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  707. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  708. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  709. test_bit(STATUS_RF_KILL_HW, &priv->status));
  710. else
  711. wake_up_interruptible(&priv->wait_command_queue);
  712. }
  713. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  714. {
  715. if (src == IWL_PWR_SRC_VAUX) {
  716. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  717. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  718. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  719. ~APMG_PS_CTRL_MSK_PWR_SRC);
  720. } else {
  721. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  722. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  723. ~APMG_PS_CTRL_MSK_PWR_SRC);
  724. }
  725. return 0;
  726. }
  727. /**
  728. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  729. *
  730. * Setup the RX handlers for each of the reply types sent from the uCode
  731. * to the host.
  732. *
  733. * This function chains into the hardware specific files for them to setup
  734. * any hardware specific handlers as well.
  735. */
  736. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  737. {
  738. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  739. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  740. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  741. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  742. iwl_rx_spectrum_measure_notif;
  743. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  744. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  745. iwl_rx_pm_debug_statistics_notif;
  746. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  747. /*
  748. * The same handler is used for both the REPLY to a discrete
  749. * statistics request from the host as well as for the periodic
  750. * statistics notifications (after received beacons) from the uCode.
  751. */
  752. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  753. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  754. iwl_setup_rx_scan_handlers(priv);
  755. /* status change handler */
  756. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  757. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  758. iwl_rx_missed_beacon_notif;
  759. /* Rx handlers */
  760. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
  761. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
  762. /* block ack */
  763. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  764. /* Set up hardware specific Rx handlers */
  765. priv->cfg->ops->lib->rx_handler_setup(priv);
  766. }
  767. /**
  768. * iwl_rx_handle - Main entry function for receiving responses from uCode
  769. *
  770. * Uses the priv->rx_handlers callback function array to invoke
  771. * the appropriate handlers, including command responses,
  772. * frame-received notifications, and other notifications.
  773. */
  774. void iwl_rx_handle(struct iwl_priv *priv)
  775. {
  776. struct iwl_rx_mem_buffer *rxb;
  777. struct iwl_rx_packet *pkt;
  778. struct iwl_rx_queue *rxq = &priv->rxq;
  779. u32 r, i;
  780. int reclaim;
  781. unsigned long flags;
  782. u8 fill_rx = 0;
  783. u32 count = 8;
  784. int total_empty;
  785. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  786. * buffer that the driver may process (last buffer filled by ucode). */
  787. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  788. i = rxq->read;
  789. /* Rx interrupt, but nothing sent from uCode */
  790. if (i == r)
  791. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  792. /* calculate total frames need to be restock after handling RX */
  793. total_empty = r - rxq->write_actual;
  794. if (total_empty < 0)
  795. total_empty += RX_QUEUE_SIZE;
  796. if (total_empty > (RX_QUEUE_SIZE / 2))
  797. fill_rx = 1;
  798. while (i != r) {
  799. int len;
  800. rxb = rxq->queue[i];
  801. /* If an RXB doesn't have a Rx queue slot associated with it,
  802. * then a bug has been introduced in the queue refilling
  803. * routines -- catch it here */
  804. BUG_ON(rxb == NULL);
  805. rxq->queue[i] = NULL;
  806. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  807. PAGE_SIZE << priv->hw_params.rx_page_order,
  808. PCI_DMA_FROMDEVICE);
  809. pkt = rxb_addr(rxb);
  810. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  811. len += sizeof(u32); /* account for status word */
  812. trace_iwlwifi_dev_rx(priv, pkt, len);
  813. /* Reclaim a command buffer only if this packet is a response
  814. * to a (driver-originated) command.
  815. * If the packet (e.g. Rx frame) originated from uCode,
  816. * there is no command buffer to reclaim.
  817. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  818. * but apparently a few don't get set; catch them here. */
  819. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  820. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  821. (pkt->hdr.cmd != REPLY_RX) &&
  822. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  823. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  824. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  825. (pkt->hdr.cmd != REPLY_TX);
  826. /* Based on type of command response or notification,
  827. * handle those that need handling via function in
  828. * rx_handlers table. See iwl_setup_rx_handlers() */
  829. if (priv->rx_handlers[pkt->hdr.cmd]) {
  830. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  831. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  832. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  833. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  834. } else {
  835. /* No handling needed */
  836. IWL_DEBUG_RX(priv,
  837. "r %d i %d No handler needed for %s, 0x%02x\n",
  838. r, i, get_cmd_string(pkt->hdr.cmd),
  839. pkt->hdr.cmd);
  840. }
  841. /*
  842. * XXX: After here, we should always check rxb->page
  843. * against NULL before touching it or its virtual
  844. * memory (pkt). Because some rx_handler might have
  845. * already taken or freed the pages.
  846. */
  847. if (reclaim) {
  848. /* Invoke any callbacks, transfer the buffer to caller,
  849. * and fire off the (possibly) blocking iwl_send_cmd()
  850. * as we reclaim the driver command queue */
  851. if (rxb->page)
  852. iwl_tx_cmd_complete(priv, rxb);
  853. else
  854. IWL_WARN(priv, "Claim null rxb?\n");
  855. }
  856. /* Reuse the page if possible. For notification packets and
  857. * SKBs that fail to Rx correctly, add them back into the
  858. * rx_free list for reuse later. */
  859. spin_lock_irqsave(&rxq->lock, flags);
  860. if (rxb->page != NULL) {
  861. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  862. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  863. PCI_DMA_FROMDEVICE);
  864. list_add_tail(&rxb->list, &rxq->rx_free);
  865. rxq->free_count++;
  866. } else
  867. list_add_tail(&rxb->list, &rxq->rx_used);
  868. spin_unlock_irqrestore(&rxq->lock, flags);
  869. i = (i + 1) & RX_QUEUE_MASK;
  870. /* If there are a lot of unused frames,
  871. * restock the Rx queue so ucode wont assert. */
  872. if (fill_rx) {
  873. count++;
  874. if (count >= 8) {
  875. rxq->read = i;
  876. iwlagn_rx_replenish_now(priv);
  877. count = 0;
  878. }
  879. }
  880. }
  881. /* Backtrack one entry */
  882. rxq->read = i;
  883. if (fill_rx)
  884. iwlagn_rx_replenish_now(priv);
  885. else
  886. iwlagn_rx_queue_restock(priv);
  887. }
  888. /* call this function to flush any scheduled tasklet */
  889. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  890. {
  891. /* wait to make sure we flush pending tasklet*/
  892. synchronize_irq(priv->pci_dev->irq);
  893. tasklet_kill(&priv->irq_tasklet);
  894. }
  895. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  896. {
  897. u32 inta, handled = 0;
  898. u32 inta_fh;
  899. unsigned long flags;
  900. u32 i;
  901. #ifdef CONFIG_IWLWIFI_DEBUG
  902. u32 inta_mask;
  903. #endif
  904. spin_lock_irqsave(&priv->lock, flags);
  905. /* Ack/clear/reset pending uCode interrupts.
  906. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  907. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  908. inta = iwl_read32(priv, CSR_INT);
  909. iwl_write32(priv, CSR_INT, inta);
  910. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  911. * Any new interrupts that happen after this, either while we're
  912. * in this tasklet, or later, will show up in next ISR/tasklet. */
  913. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  914. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  915. #ifdef CONFIG_IWLWIFI_DEBUG
  916. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  917. /* just for debug */
  918. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  919. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  920. inta, inta_mask, inta_fh);
  921. }
  922. #endif
  923. spin_unlock_irqrestore(&priv->lock, flags);
  924. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  925. * atomic, make sure that inta covers all the interrupts that
  926. * we've discovered, even if FH interrupt came in just after
  927. * reading CSR_INT. */
  928. if (inta_fh & CSR49_FH_INT_RX_MASK)
  929. inta |= CSR_INT_BIT_FH_RX;
  930. if (inta_fh & CSR49_FH_INT_TX_MASK)
  931. inta |= CSR_INT_BIT_FH_TX;
  932. /* Now service all interrupt bits discovered above. */
  933. if (inta & CSR_INT_BIT_HW_ERR) {
  934. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  935. /* Tell the device to stop sending interrupts */
  936. iwl_disable_interrupts(priv);
  937. priv->isr_stats.hw++;
  938. iwl_irq_handle_error(priv);
  939. handled |= CSR_INT_BIT_HW_ERR;
  940. return;
  941. }
  942. #ifdef CONFIG_IWLWIFI_DEBUG
  943. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  944. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  945. if (inta & CSR_INT_BIT_SCD) {
  946. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  947. "the frame/frames.\n");
  948. priv->isr_stats.sch++;
  949. }
  950. /* Alive notification via Rx interrupt will do the real work */
  951. if (inta & CSR_INT_BIT_ALIVE) {
  952. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  953. priv->isr_stats.alive++;
  954. }
  955. }
  956. #endif
  957. /* Safely ignore these bits for debug checks below */
  958. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  959. /* HW RF KILL switch toggled */
  960. if (inta & CSR_INT_BIT_RF_KILL) {
  961. int hw_rf_kill = 0;
  962. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  963. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  964. hw_rf_kill = 1;
  965. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  966. hw_rf_kill ? "disable radio" : "enable radio");
  967. priv->isr_stats.rfkill++;
  968. /* driver only loads ucode once setting the interface up.
  969. * the driver allows loading the ucode even if the radio
  970. * is killed. Hence update the killswitch state here. The
  971. * rfkill handler will care about restarting if needed.
  972. */
  973. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  974. if (hw_rf_kill)
  975. set_bit(STATUS_RF_KILL_HW, &priv->status);
  976. else
  977. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  978. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  979. }
  980. handled |= CSR_INT_BIT_RF_KILL;
  981. }
  982. /* Chip got too hot and stopped itself */
  983. if (inta & CSR_INT_BIT_CT_KILL) {
  984. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  985. priv->isr_stats.ctkill++;
  986. handled |= CSR_INT_BIT_CT_KILL;
  987. }
  988. /* Error detected by uCode */
  989. if (inta & CSR_INT_BIT_SW_ERR) {
  990. IWL_ERR(priv, "Microcode SW error detected. "
  991. " Restarting 0x%X.\n", inta);
  992. priv->isr_stats.sw++;
  993. priv->isr_stats.sw_err = inta;
  994. iwl_irq_handle_error(priv);
  995. handled |= CSR_INT_BIT_SW_ERR;
  996. }
  997. /*
  998. * uCode wakes up after power-down sleep.
  999. * Tell device about any new tx or host commands enqueued,
  1000. * and about any Rx buffers made available while asleep.
  1001. */
  1002. if (inta & CSR_INT_BIT_WAKEUP) {
  1003. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1004. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1005. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1006. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1007. priv->isr_stats.wakeup++;
  1008. handled |= CSR_INT_BIT_WAKEUP;
  1009. }
  1010. /* All uCode command responses, including Tx command responses,
  1011. * Rx "responses" (frame-received notification), and other
  1012. * notifications from uCode come through here*/
  1013. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1014. iwl_rx_handle(priv);
  1015. priv->isr_stats.rx++;
  1016. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1017. }
  1018. /* This "Tx" DMA channel is used only for loading uCode */
  1019. if (inta & CSR_INT_BIT_FH_TX) {
  1020. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1021. priv->isr_stats.tx++;
  1022. handled |= CSR_INT_BIT_FH_TX;
  1023. /* Wake up uCode load routine, now that load is complete */
  1024. priv->ucode_write_complete = 1;
  1025. wake_up_interruptible(&priv->wait_command_queue);
  1026. }
  1027. if (inta & ~handled) {
  1028. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1029. priv->isr_stats.unhandled++;
  1030. }
  1031. if (inta & ~(priv->inta_mask)) {
  1032. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1033. inta & ~priv->inta_mask);
  1034. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1035. }
  1036. /* Re-enable all interrupts */
  1037. /* only Re-enable if diabled by irq */
  1038. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1039. iwl_enable_interrupts(priv);
  1040. #ifdef CONFIG_IWLWIFI_DEBUG
  1041. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1042. inta = iwl_read32(priv, CSR_INT);
  1043. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1044. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1045. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1046. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1047. }
  1048. #endif
  1049. }
  1050. /* tasklet for iwlagn interrupt */
  1051. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1052. {
  1053. u32 inta = 0;
  1054. u32 handled = 0;
  1055. unsigned long flags;
  1056. u32 i;
  1057. #ifdef CONFIG_IWLWIFI_DEBUG
  1058. u32 inta_mask;
  1059. #endif
  1060. spin_lock_irqsave(&priv->lock, flags);
  1061. /* Ack/clear/reset pending uCode interrupts.
  1062. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1063. */
  1064. /* There is a hardware bug in the interrupt mask function that some
  1065. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  1066. * they are disabled in the CSR_INT_MASK register. Furthermore the
  1067. * ICT interrupt handling mechanism has another bug that might cause
  1068. * these unmasked interrupts fail to be detected. We workaround the
  1069. * hardware bugs here by ACKing all the possible interrupts so that
  1070. * interrupt coalescing can still be achieved.
  1071. */
  1072. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  1073. inta = priv->_agn.inta;
  1074. #ifdef CONFIG_IWLWIFI_DEBUG
  1075. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1076. /* just for debug */
  1077. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1078. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1079. inta, inta_mask);
  1080. }
  1081. #endif
  1082. spin_unlock_irqrestore(&priv->lock, flags);
  1083. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1084. priv->_agn.inta = 0;
  1085. /* Now service all interrupt bits discovered above. */
  1086. if (inta & CSR_INT_BIT_HW_ERR) {
  1087. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1088. /* Tell the device to stop sending interrupts */
  1089. iwl_disable_interrupts(priv);
  1090. priv->isr_stats.hw++;
  1091. iwl_irq_handle_error(priv);
  1092. handled |= CSR_INT_BIT_HW_ERR;
  1093. return;
  1094. }
  1095. #ifdef CONFIG_IWLWIFI_DEBUG
  1096. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1097. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1098. if (inta & CSR_INT_BIT_SCD) {
  1099. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1100. "the frame/frames.\n");
  1101. priv->isr_stats.sch++;
  1102. }
  1103. /* Alive notification via Rx interrupt will do the real work */
  1104. if (inta & CSR_INT_BIT_ALIVE) {
  1105. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1106. priv->isr_stats.alive++;
  1107. }
  1108. }
  1109. #endif
  1110. /* Safely ignore these bits for debug checks below */
  1111. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1112. /* HW RF KILL switch toggled */
  1113. if (inta & CSR_INT_BIT_RF_KILL) {
  1114. int hw_rf_kill = 0;
  1115. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1116. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1117. hw_rf_kill = 1;
  1118. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1119. hw_rf_kill ? "disable radio" : "enable radio");
  1120. priv->isr_stats.rfkill++;
  1121. /* driver only loads ucode once setting the interface up.
  1122. * the driver allows loading the ucode even if the radio
  1123. * is killed. Hence update the killswitch state here. The
  1124. * rfkill handler will care about restarting if needed.
  1125. */
  1126. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1127. if (hw_rf_kill)
  1128. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1129. else
  1130. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1131. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1132. }
  1133. handled |= CSR_INT_BIT_RF_KILL;
  1134. }
  1135. /* Chip got too hot and stopped itself */
  1136. if (inta & CSR_INT_BIT_CT_KILL) {
  1137. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1138. priv->isr_stats.ctkill++;
  1139. handled |= CSR_INT_BIT_CT_KILL;
  1140. }
  1141. /* Error detected by uCode */
  1142. if (inta & CSR_INT_BIT_SW_ERR) {
  1143. IWL_ERR(priv, "Microcode SW error detected. "
  1144. " Restarting 0x%X.\n", inta);
  1145. priv->isr_stats.sw++;
  1146. priv->isr_stats.sw_err = inta;
  1147. iwl_irq_handle_error(priv);
  1148. handled |= CSR_INT_BIT_SW_ERR;
  1149. }
  1150. /* uCode wakes up after power-down sleep */
  1151. if (inta & CSR_INT_BIT_WAKEUP) {
  1152. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1153. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1154. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1155. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1156. priv->isr_stats.wakeup++;
  1157. handled |= CSR_INT_BIT_WAKEUP;
  1158. }
  1159. /* All uCode command responses, including Tx command responses,
  1160. * Rx "responses" (frame-received notification), and other
  1161. * notifications from uCode come through here*/
  1162. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1163. CSR_INT_BIT_RX_PERIODIC)) {
  1164. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1165. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1166. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1167. iwl_write32(priv, CSR_FH_INT_STATUS,
  1168. CSR49_FH_INT_RX_MASK);
  1169. }
  1170. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1171. handled |= CSR_INT_BIT_RX_PERIODIC;
  1172. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1173. }
  1174. /* Sending RX interrupt require many steps to be done in the
  1175. * the device:
  1176. * 1- write interrupt to current index in ICT table.
  1177. * 2- dma RX frame.
  1178. * 3- update RX shared data to indicate last write index.
  1179. * 4- send interrupt.
  1180. * This could lead to RX race, driver could receive RX interrupt
  1181. * but the shared data changes does not reflect this;
  1182. * periodic interrupt will detect any dangling Rx activity.
  1183. */
  1184. /* Disable periodic interrupt; we use it as just a one-shot. */
  1185. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1186. CSR_INT_PERIODIC_DIS);
  1187. iwl_rx_handle(priv);
  1188. /*
  1189. * Enable periodic interrupt in 8 msec only if we received
  1190. * real RX interrupt (instead of just periodic int), to catch
  1191. * any dangling Rx interrupt. If it was just the periodic
  1192. * interrupt, there was no dangling Rx activity, and no need
  1193. * to extend the periodic interrupt; one-shot is enough.
  1194. */
  1195. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1196. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1197. CSR_INT_PERIODIC_ENA);
  1198. priv->isr_stats.rx++;
  1199. }
  1200. /* This "Tx" DMA channel is used only for loading uCode */
  1201. if (inta & CSR_INT_BIT_FH_TX) {
  1202. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1203. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1204. priv->isr_stats.tx++;
  1205. handled |= CSR_INT_BIT_FH_TX;
  1206. /* Wake up uCode load routine, now that load is complete */
  1207. priv->ucode_write_complete = 1;
  1208. wake_up_interruptible(&priv->wait_command_queue);
  1209. }
  1210. if (inta & ~handled) {
  1211. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1212. priv->isr_stats.unhandled++;
  1213. }
  1214. if (inta & ~(priv->inta_mask)) {
  1215. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1216. inta & ~priv->inta_mask);
  1217. }
  1218. /* Re-enable all interrupts */
  1219. /* only Re-enable if diabled by irq */
  1220. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1221. iwl_enable_interrupts(priv);
  1222. }
  1223. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1224. #define ACK_CNT_RATIO (50)
  1225. #define BA_TIMEOUT_CNT (5)
  1226. #define BA_TIMEOUT_MAX (16)
  1227. /**
  1228. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1229. *
  1230. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1231. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1232. * operation state.
  1233. */
  1234. bool iwl_good_ack_health(struct iwl_priv *priv,
  1235. struct iwl_rx_packet *pkt)
  1236. {
  1237. bool rc = true;
  1238. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1239. int ba_timeout_delta;
  1240. actual_ack_cnt_delta =
  1241. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1242. le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
  1243. expected_ack_cnt_delta =
  1244. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1245. le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
  1246. ba_timeout_delta =
  1247. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1248. le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
  1249. if ((priv->_agn.agg_tids_count > 0) &&
  1250. (expected_ack_cnt_delta > 0) &&
  1251. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1252. < ACK_CNT_RATIO) &&
  1253. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1254. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1255. " expected_ack_cnt = %d\n",
  1256. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1257. #ifdef CONFIG_IWLWIFI_DEBUGFS
  1258. /*
  1259. * This is ifdef'ed on DEBUGFS because otherwise the
  1260. * statistics aren't available. If DEBUGFS is set but
  1261. * DEBUG is not, these will just compile out.
  1262. */
  1263. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1264. priv->_agn.delta_statistics.tx.rx_detected_cnt);
  1265. IWL_DEBUG_RADIO(priv,
  1266. "ack_or_ba_timeout_collision delta = %d\n",
  1267. priv->_agn.delta_statistics.tx.
  1268. ack_or_ba_timeout_collision);
  1269. #endif
  1270. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1271. ba_timeout_delta);
  1272. if (!actual_ack_cnt_delta &&
  1273. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1274. rc = false;
  1275. }
  1276. return rc;
  1277. }
  1278. /*****************************************************************************
  1279. *
  1280. * sysfs attributes
  1281. *
  1282. *****************************************************************************/
  1283. #ifdef CONFIG_IWLWIFI_DEBUG
  1284. /*
  1285. * The following adds a new attribute to the sysfs representation
  1286. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1287. * used for controlling the debug level.
  1288. *
  1289. * See the level definitions in iwl for details.
  1290. *
  1291. * The debug_level being managed using sysfs below is a per device debug
  1292. * level that is used instead of the global debug level if it (the per
  1293. * device debug level) is set.
  1294. */
  1295. static ssize_t show_debug_level(struct device *d,
  1296. struct device_attribute *attr, char *buf)
  1297. {
  1298. struct iwl_priv *priv = dev_get_drvdata(d);
  1299. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  1300. }
  1301. static ssize_t store_debug_level(struct device *d,
  1302. struct device_attribute *attr,
  1303. const char *buf, size_t count)
  1304. {
  1305. struct iwl_priv *priv = dev_get_drvdata(d);
  1306. unsigned long val;
  1307. int ret;
  1308. ret = strict_strtoul(buf, 0, &val);
  1309. if (ret)
  1310. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1311. else {
  1312. priv->debug_level = val;
  1313. if (iwl_alloc_traffic_mem(priv))
  1314. IWL_ERR(priv,
  1315. "Not enough memory to generate traffic log\n");
  1316. }
  1317. return strnlen(buf, count);
  1318. }
  1319. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1320. show_debug_level, store_debug_level);
  1321. #endif /* CONFIG_IWLWIFI_DEBUG */
  1322. static ssize_t show_temperature(struct device *d,
  1323. struct device_attribute *attr, char *buf)
  1324. {
  1325. struct iwl_priv *priv = dev_get_drvdata(d);
  1326. if (!iwl_is_alive(priv))
  1327. return -EAGAIN;
  1328. return sprintf(buf, "%d\n", priv->temperature);
  1329. }
  1330. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  1331. static ssize_t show_tx_power(struct device *d,
  1332. struct device_attribute *attr, char *buf)
  1333. {
  1334. struct iwl_priv *priv = dev_get_drvdata(d);
  1335. if (!iwl_is_ready_rf(priv))
  1336. return sprintf(buf, "off\n");
  1337. else
  1338. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  1339. }
  1340. static ssize_t store_tx_power(struct device *d,
  1341. struct device_attribute *attr,
  1342. const char *buf, size_t count)
  1343. {
  1344. struct iwl_priv *priv = dev_get_drvdata(d);
  1345. unsigned long val;
  1346. int ret;
  1347. ret = strict_strtoul(buf, 10, &val);
  1348. if (ret)
  1349. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  1350. else {
  1351. ret = iwl_set_tx_power(priv, val, false);
  1352. if (ret)
  1353. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  1354. ret);
  1355. else
  1356. ret = count;
  1357. }
  1358. return ret;
  1359. }
  1360. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  1361. static ssize_t show_rts_ht_protection(struct device *d,
  1362. struct device_attribute *attr, char *buf)
  1363. {
  1364. struct iwl_priv *priv = dev_get_drvdata(d);
  1365. return sprintf(buf, "%s\n",
  1366. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  1367. }
  1368. static ssize_t store_rts_ht_protection(struct device *d,
  1369. struct device_attribute *attr,
  1370. const char *buf, size_t count)
  1371. {
  1372. struct iwl_priv *priv = dev_get_drvdata(d);
  1373. unsigned long val;
  1374. int ret;
  1375. ret = strict_strtoul(buf, 10, &val);
  1376. if (ret)
  1377. IWL_INFO(priv, "Input is not in decimal form.\n");
  1378. else {
  1379. if (!iwl_is_associated(priv))
  1380. priv->cfg->use_rts_for_ht = val ? true : false;
  1381. else
  1382. IWL_ERR(priv, "Sta associated with AP - "
  1383. "Change protection mechanism is not allowed\n");
  1384. ret = count;
  1385. }
  1386. return ret;
  1387. }
  1388. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  1389. show_rts_ht_protection, store_rts_ht_protection);
  1390. static struct attribute *iwl_sysfs_entries[] = {
  1391. &dev_attr_temperature.attr,
  1392. &dev_attr_tx_power.attr,
  1393. &dev_attr_rts_ht_protection.attr,
  1394. #ifdef CONFIG_IWLWIFI_DEBUG
  1395. &dev_attr_debug_level.attr,
  1396. #endif
  1397. NULL
  1398. };
  1399. static struct attribute_group iwl_attribute_group = {
  1400. .name = NULL, /* put in device directory */
  1401. .attrs = iwl_sysfs_entries,
  1402. };
  1403. /******************************************************************************
  1404. *
  1405. * uCode download functions
  1406. *
  1407. ******************************************************************************/
  1408. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1409. {
  1410. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1411. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1412. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1413. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1414. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1415. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1416. }
  1417. static void iwl_nic_start(struct iwl_priv *priv)
  1418. {
  1419. /* Remove all resets to allow NIC to operate */
  1420. iwl_write32(priv, CSR_RESET, 0);
  1421. }
  1422. struct iwlagn_ucode_capabilities {
  1423. u32 max_probe_length;
  1424. };
  1425. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1426. static int iwl_mac_setup_register(struct iwl_priv *priv,
  1427. struct iwlagn_ucode_capabilities *capa);
  1428. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1429. {
  1430. const char *name_pre = priv->cfg->fw_name_pre;
  1431. if (first)
  1432. priv->fw_index = priv->cfg->ucode_api_max;
  1433. else
  1434. priv->fw_index--;
  1435. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1436. IWL_ERR(priv, "no suitable firmware found!\n");
  1437. return -ENOENT;
  1438. }
  1439. sprintf(priv->firmware_name, "%s%d%s",
  1440. name_pre, priv->fw_index, ".ucode");
  1441. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1442. priv->firmware_name);
  1443. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1444. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1445. iwl_ucode_callback);
  1446. }
  1447. struct iwlagn_firmware_pieces {
  1448. const void *inst, *data, *init, *init_data, *boot;
  1449. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  1450. u32 build;
  1451. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  1452. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  1453. };
  1454. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  1455. const struct firmware *ucode_raw,
  1456. struct iwlagn_firmware_pieces *pieces)
  1457. {
  1458. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  1459. u32 api_ver, hdr_size;
  1460. const u8 *src;
  1461. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1462. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1463. switch (api_ver) {
  1464. default:
  1465. /*
  1466. * 4965 doesn't revision the firmware file format
  1467. * along with the API version, it always uses v1
  1468. * file format.
  1469. */
  1470. if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
  1471. CSR_HW_REV_TYPE_4965) {
  1472. hdr_size = 28;
  1473. if (ucode_raw->size < hdr_size) {
  1474. IWL_ERR(priv, "File size too small!\n");
  1475. return -EINVAL;
  1476. }
  1477. pieces->build = le32_to_cpu(ucode->u.v2.build);
  1478. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  1479. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  1480. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  1481. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  1482. pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
  1483. src = ucode->u.v2.data;
  1484. break;
  1485. }
  1486. /* fall through for 4965 */
  1487. case 0:
  1488. case 1:
  1489. case 2:
  1490. hdr_size = 24;
  1491. if (ucode_raw->size < hdr_size) {
  1492. IWL_ERR(priv, "File size too small!\n");
  1493. return -EINVAL;
  1494. }
  1495. pieces->build = 0;
  1496. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  1497. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  1498. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  1499. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  1500. pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
  1501. src = ucode->u.v1.data;
  1502. break;
  1503. }
  1504. /* Verify size of file vs. image size info in file's header */
  1505. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1506. pieces->data_size + pieces->init_size +
  1507. pieces->init_data_size + pieces->boot_size) {
  1508. IWL_ERR(priv,
  1509. "uCode file size %d does not match expected size\n",
  1510. (int)ucode_raw->size);
  1511. return -EINVAL;
  1512. }
  1513. pieces->inst = src;
  1514. src += pieces->inst_size;
  1515. pieces->data = src;
  1516. src += pieces->data_size;
  1517. pieces->init = src;
  1518. src += pieces->init_size;
  1519. pieces->init_data = src;
  1520. src += pieces->init_data_size;
  1521. pieces->boot = src;
  1522. src += pieces->boot_size;
  1523. return 0;
  1524. }
  1525. static int iwlagn_wanted_ucode_alternative = 1;
  1526. static int iwlagn_load_firmware(struct iwl_priv *priv,
  1527. const struct firmware *ucode_raw,
  1528. struct iwlagn_firmware_pieces *pieces,
  1529. struct iwlagn_ucode_capabilities *capa)
  1530. {
  1531. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  1532. struct iwl_ucode_tlv *tlv;
  1533. size_t len = ucode_raw->size;
  1534. const u8 *data;
  1535. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  1536. u64 alternatives;
  1537. if (len < sizeof(*ucode))
  1538. return -EINVAL;
  1539. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC))
  1540. return -EINVAL;
  1541. /*
  1542. * Check which alternatives are present, and "downgrade"
  1543. * when the chosen alternative is not present, warning
  1544. * the user when that happens. Some files may not have
  1545. * any alternatives, so don't warn in that case.
  1546. */
  1547. alternatives = le64_to_cpu(ucode->alternatives);
  1548. tmp = wanted_alternative;
  1549. if (wanted_alternative > 63)
  1550. wanted_alternative = 63;
  1551. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  1552. wanted_alternative--;
  1553. if (wanted_alternative && wanted_alternative != tmp)
  1554. IWL_WARN(priv,
  1555. "uCode alternative %d not available, choosing %d\n",
  1556. tmp, wanted_alternative);
  1557. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1558. pieces->build = le32_to_cpu(ucode->build);
  1559. data = ucode->data;
  1560. len -= sizeof(*ucode);
  1561. while (len >= sizeof(*tlv)) {
  1562. u32 tlv_len;
  1563. enum iwl_ucode_tlv_type tlv_type;
  1564. u16 tlv_alt;
  1565. const u8 *tlv_data;
  1566. len -= sizeof(*tlv);
  1567. tlv = (void *)data;
  1568. tlv_len = le32_to_cpu(tlv->length);
  1569. tlv_type = le16_to_cpu(tlv->type);
  1570. tlv_alt = le16_to_cpu(tlv->alternative);
  1571. tlv_data = tlv->data;
  1572. if (len < tlv_len)
  1573. return -EINVAL;
  1574. len -= ALIGN(tlv_len, 4);
  1575. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  1576. /*
  1577. * Alternative 0 is always valid.
  1578. *
  1579. * Skip alternative TLVs that are not selected.
  1580. */
  1581. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  1582. continue;
  1583. switch (tlv_type) {
  1584. case IWL_UCODE_TLV_INST:
  1585. pieces->inst = tlv_data;
  1586. pieces->inst_size = tlv_len;
  1587. break;
  1588. case IWL_UCODE_TLV_DATA:
  1589. pieces->data = tlv_data;
  1590. pieces->data_size = tlv_len;
  1591. break;
  1592. case IWL_UCODE_TLV_INIT:
  1593. pieces->init = tlv_data;
  1594. pieces->init_size = tlv_len;
  1595. break;
  1596. case IWL_UCODE_TLV_INIT_DATA:
  1597. pieces->init_data = tlv_data;
  1598. pieces->init_data_size = tlv_len;
  1599. break;
  1600. case IWL_UCODE_TLV_BOOT:
  1601. pieces->boot = tlv_data;
  1602. pieces->boot_size = tlv_len;
  1603. break;
  1604. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1605. if (tlv_len != 4)
  1606. return -EINVAL;
  1607. capa->max_probe_length =
  1608. le32_to_cpup((__le32 *)tlv_data);
  1609. break;
  1610. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1611. if (tlv_len != 4)
  1612. return -EINVAL;
  1613. pieces->init_evtlog_ptr =
  1614. le32_to_cpup((__le32 *)tlv_data);
  1615. break;
  1616. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1617. if (tlv_len != 4)
  1618. return -EINVAL;
  1619. pieces->init_evtlog_size =
  1620. le32_to_cpup((__le32 *)tlv_data);
  1621. break;
  1622. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1623. if (tlv_len != 4)
  1624. return -EINVAL;
  1625. pieces->init_errlog_ptr =
  1626. le32_to_cpup((__le32 *)tlv_data);
  1627. break;
  1628. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1629. if (tlv_len != 4)
  1630. return -EINVAL;
  1631. pieces->inst_evtlog_ptr =
  1632. le32_to_cpup((__le32 *)tlv_data);
  1633. break;
  1634. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1635. if (tlv_len != 4)
  1636. return -EINVAL;
  1637. pieces->inst_evtlog_size =
  1638. le32_to_cpup((__le32 *)tlv_data);
  1639. break;
  1640. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1641. if (tlv_len != 4)
  1642. return -EINVAL;
  1643. pieces->inst_errlog_ptr =
  1644. le32_to_cpup((__le32 *)tlv_data);
  1645. break;
  1646. default:
  1647. break;
  1648. }
  1649. }
  1650. if (len)
  1651. return -EINVAL;
  1652. return 0;
  1653. }
  1654. /**
  1655. * iwl_ucode_callback - callback when firmware was loaded
  1656. *
  1657. * If loaded successfully, copies the firmware into buffers
  1658. * for the card to fetch (via DMA).
  1659. */
  1660. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1661. {
  1662. struct iwl_priv *priv = context;
  1663. struct iwl_ucode_header *ucode;
  1664. int err;
  1665. struct iwlagn_firmware_pieces pieces;
  1666. const unsigned int api_max = priv->cfg->ucode_api_max;
  1667. const unsigned int api_min = priv->cfg->ucode_api_min;
  1668. u32 api_ver;
  1669. char buildstr[25];
  1670. u32 build;
  1671. struct iwlagn_ucode_capabilities ucode_capa = {
  1672. .max_probe_length = 200,
  1673. };
  1674. memset(&pieces, 0, sizeof(pieces));
  1675. if (!ucode_raw) {
  1676. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1677. priv->firmware_name);
  1678. goto try_again;
  1679. }
  1680. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1681. priv->firmware_name, ucode_raw->size);
  1682. /* Make sure that we got at least the API version number */
  1683. if (ucode_raw->size < 4) {
  1684. IWL_ERR(priv, "File size way too small!\n");
  1685. goto try_again;
  1686. }
  1687. /* Data from ucode file: header followed by uCode images */
  1688. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1689. if (ucode->ver)
  1690. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1691. else
  1692. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1693. &ucode_capa);
  1694. if (err)
  1695. goto try_again;
  1696. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1697. build = pieces.build;
  1698. /*
  1699. * api_ver should match the api version forming part of the
  1700. * firmware filename ... but we don't check for that and only rely
  1701. * on the API version read from firmware header from here on forward
  1702. */
  1703. if (api_ver < api_min || api_ver > api_max) {
  1704. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1705. "Driver supports v%u, firmware is v%u.\n",
  1706. api_max, api_ver);
  1707. goto try_again;
  1708. }
  1709. if (api_ver != api_max)
  1710. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1711. "got v%u. New firmware can be obtained "
  1712. "from http://www.intellinuxwireless.org.\n",
  1713. api_max, api_ver);
  1714. if (build)
  1715. sprintf(buildstr, " build %u", build);
  1716. else
  1717. buildstr[0] = '\0';
  1718. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1719. IWL_UCODE_MAJOR(priv->ucode_ver),
  1720. IWL_UCODE_MINOR(priv->ucode_ver),
  1721. IWL_UCODE_API(priv->ucode_ver),
  1722. IWL_UCODE_SERIAL(priv->ucode_ver),
  1723. buildstr);
  1724. snprintf(priv->hw->wiphy->fw_version,
  1725. sizeof(priv->hw->wiphy->fw_version),
  1726. "%u.%u.%u.%u%s",
  1727. IWL_UCODE_MAJOR(priv->ucode_ver),
  1728. IWL_UCODE_MINOR(priv->ucode_ver),
  1729. IWL_UCODE_API(priv->ucode_ver),
  1730. IWL_UCODE_SERIAL(priv->ucode_ver),
  1731. buildstr);
  1732. /*
  1733. * For any of the failures below (before allocating pci memory)
  1734. * we will try to load a version with a smaller API -- maybe the
  1735. * user just got a corrupted version of the latest API.
  1736. */
  1737. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1738. priv->ucode_ver);
  1739. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1740. pieces.inst_size);
  1741. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1742. pieces.data_size);
  1743. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1744. pieces.init_size);
  1745. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1746. pieces.init_data_size);
  1747. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
  1748. pieces.boot_size);
  1749. /* Verify that uCode images will fit in card's SRAM */
  1750. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1751. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1752. pieces.inst_size);
  1753. goto try_again;
  1754. }
  1755. if (pieces.data_size > priv->hw_params.max_data_size) {
  1756. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1757. pieces.data_size);
  1758. goto try_again;
  1759. }
  1760. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1761. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1762. pieces.init_size);
  1763. goto try_again;
  1764. }
  1765. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1766. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1767. pieces.init_data_size);
  1768. goto try_again;
  1769. }
  1770. if (pieces.boot_size > priv->hw_params.max_bsm_size) {
  1771. IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
  1772. pieces.boot_size);
  1773. goto try_again;
  1774. }
  1775. /* Allocate ucode buffers for card's bus-master loading ... */
  1776. /* Runtime instructions and 2 copies of data:
  1777. * 1) unmodified from disk
  1778. * 2) backup cache for save/restore during power-downs */
  1779. priv->ucode_code.len = pieces.inst_size;
  1780. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1781. priv->ucode_data.len = pieces.data_size;
  1782. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1783. priv->ucode_data_backup.len = pieces.data_size;
  1784. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1785. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1786. !priv->ucode_data_backup.v_addr)
  1787. goto err_pci_alloc;
  1788. /* Initialization instructions and data */
  1789. if (pieces.init_size && pieces.init_data_size) {
  1790. priv->ucode_init.len = pieces.init_size;
  1791. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1792. priv->ucode_init_data.len = pieces.init_data_size;
  1793. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1794. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1795. goto err_pci_alloc;
  1796. }
  1797. /* Bootstrap (instructions only, no data) */
  1798. if (pieces.boot_size) {
  1799. priv->ucode_boot.len = pieces.boot_size;
  1800. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1801. if (!priv->ucode_boot.v_addr)
  1802. goto err_pci_alloc;
  1803. }
  1804. /* Now that we can no longer fail, copy information */
  1805. /*
  1806. * The (size - 16) / 12 formula is based on the information recorded
  1807. * for each event, which is of mode 1 (including timestamp) for all
  1808. * new microcodes that include this information.
  1809. */
  1810. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1811. if (pieces.init_evtlog_size)
  1812. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1813. else
  1814. priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
  1815. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1816. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1817. if (pieces.inst_evtlog_size)
  1818. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1819. else
  1820. priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
  1821. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1822. /* Copy images into buffers for card's bus-master reads ... */
  1823. /* Runtime instructions (first block of data in file) */
  1824. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1825. pieces.inst_size);
  1826. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1827. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1828. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1829. /*
  1830. * Runtime data
  1831. * NOTE: Copy into backup buffer will be done in iwl_up()
  1832. */
  1833. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1834. pieces.data_size);
  1835. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1836. memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1837. /* Initialization instructions */
  1838. if (pieces.init_size) {
  1839. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1840. pieces.init_size);
  1841. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1842. }
  1843. /* Initialization data */
  1844. if (pieces.init_data_size) {
  1845. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1846. pieces.init_data_size);
  1847. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1848. pieces.init_data_size);
  1849. }
  1850. /* Bootstrap instructions */
  1851. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
  1852. pieces.boot_size);
  1853. memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1854. /**************************************************
  1855. * This is still part of probe() in a sense...
  1856. *
  1857. * 9. Setup and register with mac80211 and debugfs
  1858. **************************************************/
  1859. err = iwl_mac_setup_register(priv, &ucode_capa);
  1860. if (err)
  1861. goto out_unbind;
  1862. err = iwl_dbgfs_register(priv, DRV_NAME);
  1863. if (err)
  1864. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1865. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1866. &iwl_attribute_group);
  1867. if (err) {
  1868. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1869. goto out_unbind;
  1870. }
  1871. /* We have our copies now, allow OS release its copies */
  1872. release_firmware(ucode_raw);
  1873. complete(&priv->_agn.firmware_loading_complete);
  1874. return;
  1875. try_again:
  1876. /* try next, if any */
  1877. if (iwl_request_firmware(priv, false))
  1878. goto out_unbind;
  1879. release_firmware(ucode_raw);
  1880. return;
  1881. err_pci_alloc:
  1882. IWL_ERR(priv, "failed to allocate pci memory\n");
  1883. iwl_dealloc_ucode_pci(priv);
  1884. out_unbind:
  1885. complete(&priv->_agn.firmware_loading_complete);
  1886. device_release_driver(&priv->pci_dev->dev);
  1887. release_firmware(ucode_raw);
  1888. }
  1889. static const char *desc_lookup_text[] = {
  1890. "OK",
  1891. "FAIL",
  1892. "BAD_PARAM",
  1893. "BAD_CHECKSUM",
  1894. "NMI_INTERRUPT_WDG",
  1895. "SYSASSERT",
  1896. "FATAL_ERROR",
  1897. "BAD_COMMAND",
  1898. "HW_ERROR_TUNE_LOCK",
  1899. "HW_ERROR_TEMPERATURE",
  1900. "ILLEGAL_CHAN_FREQ",
  1901. "VCC_NOT_STABLE",
  1902. "FH_ERROR",
  1903. "NMI_INTERRUPT_HOST",
  1904. "NMI_INTERRUPT_ACTION_PT",
  1905. "NMI_INTERRUPT_UNKNOWN",
  1906. "UCODE_VERSION_MISMATCH",
  1907. "HW_ERROR_ABS_LOCK",
  1908. "HW_ERROR_CAL_LOCK_FAIL",
  1909. "NMI_INTERRUPT_INST_ACTION_PT",
  1910. "NMI_INTERRUPT_DATA_ACTION_PT",
  1911. "NMI_TRM_HW_ER",
  1912. "NMI_INTERRUPT_TRM",
  1913. "NMI_INTERRUPT_BREAK_POINT"
  1914. "DEBUG_0",
  1915. "DEBUG_1",
  1916. "DEBUG_2",
  1917. "DEBUG_3",
  1918. "ADVANCED SYSASSERT"
  1919. };
  1920. static const char *desc_lookup(int i)
  1921. {
  1922. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1923. if (i < 0 || i > max)
  1924. i = max;
  1925. return desc_lookup_text[i];
  1926. }
  1927. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1928. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1929. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1930. {
  1931. u32 data2, line;
  1932. u32 desc, time, count, base, data1;
  1933. u32 blink1, blink2, ilink1, ilink2;
  1934. u32 pc, hcmd;
  1935. if (priv->ucode_type == UCODE_INIT) {
  1936. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1937. if (!base)
  1938. base = priv->_agn.init_errlog_ptr;
  1939. } else {
  1940. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1941. if (!base)
  1942. base = priv->_agn.inst_errlog_ptr;
  1943. }
  1944. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1945. IWL_ERR(priv,
  1946. "Not valid error log pointer 0x%08X for %s uCode\n",
  1947. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1948. return;
  1949. }
  1950. count = iwl_read_targ_mem(priv, base);
  1951. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1952. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1953. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1954. priv->status, count);
  1955. }
  1956. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1957. pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
  1958. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1959. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1960. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1961. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1962. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1963. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1964. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1965. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1966. hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
  1967. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1968. blink1, blink2, ilink1, ilink2);
  1969. IWL_ERR(priv, "Desc Time "
  1970. "data1 data2 line\n");
  1971. IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
  1972. desc_lookup(desc), desc, time, data1, data2, line);
  1973. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  1974. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  1975. pc, blink1, blink2, ilink1, ilink2, hcmd);
  1976. }
  1977. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1978. /**
  1979. * iwl_print_event_log - Dump error event log to syslog
  1980. *
  1981. */
  1982. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1983. u32 num_events, u32 mode,
  1984. int pos, char **buf, size_t bufsz)
  1985. {
  1986. u32 i;
  1987. u32 base; /* SRAM byte address of event log header */
  1988. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1989. u32 ptr; /* SRAM byte address of log data */
  1990. u32 ev, time, data; /* event log data */
  1991. unsigned long reg_flags;
  1992. if (num_events == 0)
  1993. return pos;
  1994. if (priv->ucode_type == UCODE_INIT) {
  1995. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1996. if (!base)
  1997. base = priv->_agn.init_evtlog_ptr;
  1998. } else {
  1999. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2000. if (!base)
  2001. base = priv->_agn.inst_evtlog_ptr;
  2002. }
  2003. if (mode == 0)
  2004. event_size = 2 * sizeof(u32);
  2005. else
  2006. event_size = 3 * sizeof(u32);
  2007. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  2008. /* Make sure device is powered up for SRAM reads */
  2009. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  2010. iwl_grab_nic_access(priv);
  2011. /* Set starting address; reads will auto-increment */
  2012. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  2013. rmb();
  2014. /* "time" is actually "data" for mode 0 (no timestamp).
  2015. * place event id # at far right for easier visual parsing. */
  2016. for (i = 0; i < num_events; i++) {
  2017. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2018. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2019. if (mode == 0) {
  2020. /* data, ev */
  2021. if (bufsz) {
  2022. pos += scnprintf(*buf + pos, bufsz - pos,
  2023. "EVT_LOG:0x%08x:%04u\n",
  2024. time, ev);
  2025. } else {
  2026. trace_iwlwifi_dev_ucode_event(priv, 0,
  2027. time, ev);
  2028. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  2029. time, ev);
  2030. }
  2031. } else {
  2032. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  2033. if (bufsz) {
  2034. pos += scnprintf(*buf + pos, bufsz - pos,
  2035. "EVT_LOGT:%010u:0x%08x:%04u\n",
  2036. time, data, ev);
  2037. } else {
  2038. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  2039. time, data, ev);
  2040. trace_iwlwifi_dev_ucode_event(priv, time,
  2041. data, ev);
  2042. }
  2043. }
  2044. }
  2045. /* Allow device to power down */
  2046. iwl_release_nic_access(priv);
  2047. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  2048. return pos;
  2049. }
  2050. /**
  2051. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  2052. */
  2053. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  2054. u32 num_wraps, u32 next_entry,
  2055. u32 size, u32 mode,
  2056. int pos, char **buf, size_t bufsz)
  2057. {
  2058. /*
  2059. * display the newest DEFAULT_LOG_ENTRIES entries
  2060. * i.e the entries just before the next ont that uCode would fill.
  2061. */
  2062. if (num_wraps) {
  2063. if (next_entry < size) {
  2064. pos = iwl_print_event_log(priv,
  2065. capacity - (size - next_entry),
  2066. size - next_entry, mode,
  2067. pos, buf, bufsz);
  2068. pos = iwl_print_event_log(priv, 0,
  2069. next_entry, mode,
  2070. pos, buf, bufsz);
  2071. } else
  2072. pos = iwl_print_event_log(priv, next_entry - size,
  2073. size, mode, pos, buf, bufsz);
  2074. } else {
  2075. if (next_entry < size) {
  2076. pos = iwl_print_event_log(priv, 0, next_entry,
  2077. mode, pos, buf, bufsz);
  2078. } else {
  2079. pos = iwl_print_event_log(priv, next_entry - size,
  2080. size, mode, pos, buf, bufsz);
  2081. }
  2082. }
  2083. return pos;
  2084. }
  2085. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  2086. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  2087. char **buf, bool display)
  2088. {
  2089. u32 base; /* SRAM byte address of event log header */
  2090. u32 capacity; /* event log capacity in # entries */
  2091. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  2092. u32 num_wraps; /* # times uCode wrapped to top of log */
  2093. u32 next_entry; /* index of next entry to be written by uCode */
  2094. u32 size; /* # entries that we'll print */
  2095. u32 logsize;
  2096. int pos = 0;
  2097. size_t bufsz = 0;
  2098. if (priv->ucode_type == UCODE_INIT) {
  2099. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  2100. logsize = priv->_agn.init_evtlog_size;
  2101. if (!base)
  2102. base = priv->_agn.init_evtlog_ptr;
  2103. } else {
  2104. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2105. logsize = priv->_agn.inst_evtlog_size;
  2106. if (!base)
  2107. base = priv->_agn.inst_evtlog_ptr;
  2108. }
  2109. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  2110. IWL_ERR(priv,
  2111. "Invalid event log pointer 0x%08X for %s uCode\n",
  2112. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  2113. return -EINVAL;
  2114. }
  2115. /* event log header */
  2116. capacity = iwl_read_targ_mem(priv, base);
  2117. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  2118. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  2119. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  2120. if (capacity > logsize) {
  2121. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  2122. capacity, logsize);
  2123. capacity = logsize;
  2124. }
  2125. if (next_entry > logsize) {
  2126. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  2127. next_entry, logsize);
  2128. next_entry = logsize;
  2129. }
  2130. size = num_wraps ? capacity : next_entry;
  2131. /* bail out if nothing in log */
  2132. if (size == 0) {
  2133. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  2134. return pos;
  2135. }
  2136. #ifdef CONFIG_IWLWIFI_DEBUG
  2137. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  2138. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2139. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2140. #else
  2141. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  2142. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  2143. #endif
  2144. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  2145. size);
  2146. #ifdef CONFIG_IWLWIFI_DEBUG
  2147. if (display) {
  2148. if (full_log)
  2149. bufsz = capacity * 48;
  2150. else
  2151. bufsz = size * 48;
  2152. *buf = kmalloc(bufsz, GFP_KERNEL);
  2153. if (!*buf)
  2154. return -ENOMEM;
  2155. }
  2156. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  2157. /*
  2158. * if uCode has wrapped back to top of log,
  2159. * start at the oldest entry,
  2160. * i.e the next one that uCode would fill.
  2161. */
  2162. if (num_wraps)
  2163. pos = iwl_print_event_log(priv, next_entry,
  2164. capacity - next_entry, mode,
  2165. pos, buf, bufsz);
  2166. /* (then/else) start at top of log */
  2167. pos = iwl_print_event_log(priv, 0,
  2168. next_entry, mode, pos, buf, bufsz);
  2169. } else
  2170. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2171. next_entry, size, mode,
  2172. pos, buf, bufsz);
  2173. #else
  2174. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  2175. next_entry, size, mode,
  2176. pos, buf, bufsz);
  2177. #endif
  2178. return pos;
  2179. }
  2180. /**
  2181. * iwl_alive_start - called after REPLY_ALIVE notification received
  2182. * from protocol/runtime uCode (initialization uCode's
  2183. * Alive gets handled by iwl_init_alive_start()).
  2184. */
  2185. static void iwl_alive_start(struct iwl_priv *priv)
  2186. {
  2187. int ret = 0;
  2188. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2189. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2190. /* We had an error bringing up the hardware, so take it
  2191. * all the way back down so we can try again */
  2192. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2193. goto restart;
  2194. }
  2195. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2196. * This is a paranoid check, because we would not have gotten the
  2197. * "runtime" alive if code weren't properly loaded. */
  2198. if (iwl_verify_ucode(priv)) {
  2199. /* Runtime instruction load was bad;
  2200. * take it all the way back down so we can try again */
  2201. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2202. goto restart;
  2203. }
  2204. ret = priv->cfg->ops->lib->alive_notify(priv);
  2205. if (ret) {
  2206. IWL_WARN(priv,
  2207. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  2208. goto restart;
  2209. }
  2210. /* After the ALIVE response, we can send host commands to the uCode */
  2211. set_bit(STATUS_ALIVE, &priv->status);
  2212. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2213. /* Enable timer to monitor the driver queues */
  2214. mod_timer(&priv->monitor_recover,
  2215. jiffies +
  2216. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  2217. }
  2218. if (iwl_is_rfkill(priv))
  2219. return;
  2220. ieee80211_wake_queues(priv->hw);
  2221. priv->active_rate = IWL_RATES_MASK;
  2222. /* Configure Tx antenna selection based on H/W config */
  2223. if (priv->cfg->ops->hcmd->set_tx_ant)
  2224. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  2225. if (iwl_is_associated(priv)) {
  2226. struct iwl_rxon_cmd *active_rxon =
  2227. (struct iwl_rxon_cmd *)&priv->active_rxon;
  2228. /* apply any changes in staging */
  2229. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2230. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2231. } else {
  2232. /* Initialize our rx_config data */
  2233. iwl_connection_init_rx_config(priv, NULL);
  2234. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2235. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2236. }
  2237. /* Configure Bluetooth device coexistence support */
  2238. priv->cfg->ops->hcmd->send_bt_config(priv);
  2239. iwl_reset_run_time_calib(priv);
  2240. /* Configure the adapter for unassociated operation */
  2241. iwlcore_commit_rxon(priv);
  2242. /* At this point, the NIC is initialized and operational */
  2243. iwl_rf_kill_ct_config(priv);
  2244. iwl_leds_init(priv);
  2245. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2246. set_bit(STATUS_READY, &priv->status);
  2247. wake_up_interruptible(&priv->wait_command_queue);
  2248. iwl_power_update_mode(priv, true);
  2249. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  2250. return;
  2251. restart:
  2252. queue_work(priv->workqueue, &priv->restart);
  2253. }
  2254. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  2255. static void __iwl_down(struct iwl_priv *priv)
  2256. {
  2257. unsigned long flags;
  2258. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2259. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2260. if (!exit_pending)
  2261. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2262. iwl_clear_ucode_stations(priv);
  2263. iwl_dealloc_bcast_station(priv);
  2264. iwl_clear_driver_stations(priv);
  2265. /* Unblock any waiting calls */
  2266. wake_up_interruptible_all(&priv->wait_command_queue);
  2267. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2268. * exiting the module */
  2269. if (!exit_pending)
  2270. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2271. /* stop and reset the on-board processor */
  2272. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2273. /* tell the device to stop sending interrupts */
  2274. spin_lock_irqsave(&priv->lock, flags);
  2275. iwl_disable_interrupts(priv);
  2276. spin_unlock_irqrestore(&priv->lock, flags);
  2277. iwl_synchronize_irq(priv);
  2278. if (priv->mac80211_registered)
  2279. ieee80211_stop_queues(priv->hw);
  2280. /* If we have not previously called iwl_init() then
  2281. * clear all bits but the RF Kill bit and return */
  2282. if (!iwl_is_init(priv)) {
  2283. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2284. STATUS_RF_KILL_HW |
  2285. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2286. STATUS_GEO_CONFIGURED |
  2287. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2288. STATUS_EXIT_PENDING;
  2289. goto exit;
  2290. }
  2291. /* ...otherwise clear out all the status bits but the RF Kill
  2292. * bit and continue taking the NIC down. */
  2293. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2294. STATUS_RF_KILL_HW |
  2295. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2296. STATUS_GEO_CONFIGURED |
  2297. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2298. STATUS_FW_ERROR |
  2299. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2300. STATUS_EXIT_PENDING;
  2301. /* device going down, Stop using ICT table */
  2302. iwl_disable_ict(priv);
  2303. iwlagn_txq_ctx_stop(priv);
  2304. iwlagn_rxq_stop(priv);
  2305. /* Power-down device's busmaster DMA clocks */
  2306. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2307. udelay(5);
  2308. /* Make sure (redundant) we've released our request to stay awake */
  2309. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2310. /* Stop the device, and put it in low power state */
  2311. priv->cfg->ops->lib->apm_ops.stop(priv);
  2312. exit:
  2313. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2314. if (priv->ibss_beacon)
  2315. dev_kfree_skb(priv->ibss_beacon);
  2316. priv->ibss_beacon = NULL;
  2317. /* clear out any free frames */
  2318. iwl_clear_free_frames(priv);
  2319. }
  2320. static void iwl_down(struct iwl_priv *priv)
  2321. {
  2322. mutex_lock(&priv->mutex);
  2323. __iwl_down(priv);
  2324. mutex_unlock(&priv->mutex);
  2325. iwl_cancel_deferred_work(priv);
  2326. }
  2327. #define HW_READY_TIMEOUT (50)
  2328. static int iwl_set_hw_ready(struct iwl_priv *priv)
  2329. {
  2330. int ret = 0;
  2331. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2332. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2333. /* See if we got it */
  2334. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2335. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2336. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2337. HW_READY_TIMEOUT);
  2338. if (ret != -ETIMEDOUT)
  2339. priv->hw_ready = true;
  2340. else
  2341. priv->hw_ready = false;
  2342. IWL_DEBUG_INFO(priv, "hardware %s\n",
  2343. (priv->hw_ready == 1) ? "ready" : "not ready");
  2344. return ret;
  2345. }
  2346. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  2347. {
  2348. int ret = 0;
  2349. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  2350. ret = iwl_set_hw_ready(priv);
  2351. if (priv->hw_ready)
  2352. return ret;
  2353. /* If HW is not ready, prepare the conditions to check again */
  2354. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2355. CSR_HW_IF_CONFIG_REG_PREPARE);
  2356. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2357. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2358. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2359. /* HW should be ready by now, check again. */
  2360. if (ret != -ETIMEDOUT)
  2361. iwl_set_hw_ready(priv);
  2362. return ret;
  2363. }
  2364. #define MAX_HW_RESTARTS 5
  2365. static int __iwl_up(struct iwl_priv *priv)
  2366. {
  2367. int i;
  2368. int ret;
  2369. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2370. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2371. return -EIO;
  2372. }
  2373. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2374. IWL_ERR(priv, "ucode not available for device bringup\n");
  2375. return -EIO;
  2376. }
  2377. ret = iwl_alloc_bcast_station(priv, true);
  2378. if (ret)
  2379. return ret;
  2380. iwl_prepare_card_hw(priv);
  2381. if (!priv->hw_ready) {
  2382. IWL_WARN(priv, "Exit HW not ready\n");
  2383. return -EIO;
  2384. }
  2385. /* If platform's RF_KILL switch is NOT set to KILL */
  2386. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2387. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2388. else
  2389. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2390. if (iwl_is_rfkill(priv)) {
  2391. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  2392. iwl_enable_interrupts(priv);
  2393. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2394. return 0;
  2395. }
  2396. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2397. ret = iwlagn_hw_nic_init(priv);
  2398. if (ret) {
  2399. IWL_ERR(priv, "Unable to init nic\n");
  2400. return ret;
  2401. }
  2402. /* make sure rfkill handshake bits are cleared */
  2403. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2404. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2405. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2406. /* clear (again), then enable host interrupts */
  2407. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2408. iwl_enable_interrupts(priv);
  2409. /* really make sure rfkill handshake bits are cleared */
  2410. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2411. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2412. /* Copy original ucode data image from disk into backup cache.
  2413. * This will be used to initialize the on-board processor's
  2414. * data SRAM for a clean start when the runtime program first loads. */
  2415. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2416. priv->ucode_data.len);
  2417. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2418. /* load bootstrap state machine,
  2419. * load bootstrap program into processor's memory,
  2420. * prepare to load the "initialize" uCode */
  2421. ret = priv->cfg->ops->lib->load_ucode(priv);
  2422. if (ret) {
  2423. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2424. ret);
  2425. continue;
  2426. }
  2427. /* start card; "initialize" will load runtime ucode */
  2428. iwl_nic_start(priv);
  2429. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2430. return 0;
  2431. }
  2432. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2433. __iwl_down(priv);
  2434. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2435. /* tried to restart and config the device for as long as our
  2436. * patience could withstand */
  2437. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2438. return -EIO;
  2439. }
  2440. /*****************************************************************************
  2441. *
  2442. * Workqueue callbacks
  2443. *
  2444. *****************************************************************************/
  2445. static void iwl_bg_init_alive_start(struct work_struct *data)
  2446. {
  2447. struct iwl_priv *priv =
  2448. container_of(data, struct iwl_priv, init_alive_start.work);
  2449. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2450. return;
  2451. mutex_lock(&priv->mutex);
  2452. priv->cfg->ops->lib->init_alive_start(priv);
  2453. mutex_unlock(&priv->mutex);
  2454. }
  2455. static void iwl_bg_alive_start(struct work_struct *data)
  2456. {
  2457. struct iwl_priv *priv =
  2458. container_of(data, struct iwl_priv, alive_start.work);
  2459. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2460. return;
  2461. /* enable dram interrupt */
  2462. iwl_reset_ict(priv);
  2463. mutex_lock(&priv->mutex);
  2464. iwl_alive_start(priv);
  2465. mutex_unlock(&priv->mutex);
  2466. }
  2467. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2468. {
  2469. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2470. run_time_calib_work);
  2471. mutex_lock(&priv->mutex);
  2472. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2473. test_bit(STATUS_SCANNING, &priv->status)) {
  2474. mutex_unlock(&priv->mutex);
  2475. return;
  2476. }
  2477. if (priv->start_calib) {
  2478. iwl_chain_noise_calibration(priv, &priv->_agn.statistics);
  2479. iwl_sensitivity_calibration(priv, &priv->_agn.statistics);
  2480. }
  2481. mutex_unlock(&priv->mutex);
  2482. }
  2483. static void iwl_bg_restart(struct work_struct *data)
  2484. {
  2485. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2486. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2487. return;
  2488. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2489. mutex_lock(&priv->mutex);
  2490. priv->vif = NULL;
  2491. priv->is_open = 0;
  2492. mutex_unlock(&priv->mutex);
  2493. iwl_down(priv);
  2494. ieee80211_restart_hw(priv->hw);
  2495. } else {
  2496. iwl_down(priv);
  2497. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2498. return;
  2499. mutex_lock(&priv->mutex);
  2500. __iwl_up(priv);
  2501. mutex_unlock(&priv->mutex);
  2502. }
  2503. }
  2504. static void iwl_bg_rx_replenish(struct work_struct *data)
  2505. {
  2506. struct iwl_priv *priv =
  2507. container_of(data, struct iwl_priv, rx_replenish);
  2508. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2509. return;
  2510. mutex_lock(&priv->mutex);
  2511. iwlagn_rx_replenish(priv);
  2512. mutex_unlock(&priv->mutex);
  2513. }
  2514. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2515. void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2516. {
  2517. struct ieee80211_conf *conf = NULL;
  2518. int ret = 0;
  2519. if (!vif || !priv->is_open)
  2520. return;
  2521. if (vif->type == NL80211_IFTYPE_AP) {
  2522. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2523. return;
  2524. }
  2525. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2526. return;
  2527. iwl_scan_cancel_timeout(priv, 200);
  2528. conf = ieee80211_get_hw_conf(priv->hw);
  2529. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2530. iwlcore_commit_rxon(priv);
  2531. iwl_setup_rxon_timing(priv, vif);
  2532. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2533. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2534. if (ret)
  2535. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2536. "Attempting to continue.\n");
  2537. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2538. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2539. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2540. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2541. priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2542. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2543. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2544. if (vif->bss_conf.use_short_preamble)
  2545. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2546. else
  2547. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2548. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2549. if (vif->bss_conf.use_short_slot)
  2550. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2551. else
  2552. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2553. }
  2554. iwlcore_commit_rxon(priv);
  2555. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2556. vif->bss_conf.aid, priv->active_rxon.bssid_addr);
  2557. switch (vif->type) {
  2558. case NL80211_IFTYPE_STATION:
  2559. break;
  2560. case NL80211_IFTYPE_ADHOC:
  2561. iwl_send_beacon_cmd(priv);
  2562. break;
  2563. default:
  2564. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2565. __func__, vif->type);
  2566. break;
  2567. }
  2568. /* the chain noise calibration will enabled PM upon completion
  2569. * If chain noise has already been run, then we need to enable
  2570. * power management here */
  2571. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2572. iwl_power_update_mode(priv, false);
  2573. /* Enable Rx differential gain and sensitivity calibrations */
  2574. iwl_chain_noise_reset(priv);
  2575. priv->start_calib = 1;
  2576. }
  2577. /*****************************************************************************
  2578. *
  2579. * mac80211 entry point functions
  2580. *
  2581. *****************************************************************************/
  2582. #define UCODE_READY_TIMEOUT (4 * HZ)
  2583. /*
  2584. * Not a mac80211 entry point function, but it fits in with all the
  2585. * other mac80211 functions grouped here.
  2586. */
  2587. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2588. struct iwlagn_ucode_capabilities *capa)
  2589. {
  2590. int ret;
  2591. struct ieee80211_hw *hw = priv->hw;
  2592. hw->rate_control_algorithm = "iwl-agn-rs";
  2593. /* Tell mac80211 our characteristics */
  2594. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2595. IEEE80211_HW_AMPDU_AGGREGATION |
  2596. IEEE80211_HW_SPECTRUM_MGMT;
  2597. if (!priv->cfg->broken_powersave)
  2598. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2599. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2600. if (priv->cfg->sku & IWL_SKU_N)
  2601. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2602. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2603. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2604. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2605. hw->wiphy->interface_modes =
  2606. BIT(NL80211_IFTYPE_STATION) |
  2607. BIT(NL80211_IFTYPE_ADHOC);
  2608. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2609. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2610. /*
  2611. * For now, disable PS by default because it affects
  2612. * RX performance significantly.
  2613. */
  2614. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2615. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2616. /* we create the 802.11 header and a zero-length SSID element */
  2617. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2618. /* Default value; 4 EDCA QOS priorities */
  2619. hw->queues = 4;
  2620. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2621. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2622. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2623. &priv->bands[IEEE80211_BAND_2GHZ];
  2624. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2625. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2626. &priv->bands[IEEE80211_BAND_5GHZ];
  2627. ret = ieee80211_register_hw(priv->hw);
  2628. if (ret) {
  2629. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2630. return ret;
  2631. }
  2632. priv->mac80211_registered = 1;
  2633. return 0;
  2634. }
  2635. static int iwl_mac_start(struct ieee80211_hw *hw)
  2636. {
  2637. struct iwl_priv *priv = hw->priv;
  2638. int ret;
  2639. IWL_DEBUG_MAC80211(priv, "enter\n");
  2640. /* we should be verifying the device is ready to be opened */
  2641. mutex_lock(&priv->mutex);
  2642. ret = __iwl_up(priv);
  2643. mutex_unlock(&priv->mutex);
  2644. if (ret)
  2645. return ret;
  2646. if (iwl_is_rfkill(priv))
  2647. goto out;
  2648. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2649. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2650. * mac80211 will not be run successfully. */
  2651. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2652. test_bit(STATUS_READY, &priv->status),
  2653. UCODE_READY_TIMEOUT);
  2654. if (!ret) {
  2655. if (!test_bit(STATUS_READY, &priv->status)) {
  2656. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2657. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2658. return -ETIMEDOUT;
  2659. }
  2660. }
  2661. iwl_led_start(priv);
  2662. out:
  2663. priv->is_open = 1;
  2664. IWL_DEBUG_MAC80211(priv, "leave\n");
  2665. return 0;
  2666. }
  2667. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2668. {
  2669. struct iwl_priv *priv = hw->priv;
  2670. IWL_DEBUG_MAC80211(priv, "enter\n");
  2671. if (!priv->is_open)
  2672. return;
  2673. priv->is_open = 0;
  2674. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2675. /* stop mac, cancel any scan request and clear
  2676. * RXON_FILTER_ASSOC_MSK BIT
  2677. */
  2678. mutex_lock(&priv->mutex);
  2679. iwl_scan_cancel_timeout(priv, 100);
  2680. mutex_unlock(&priv->mutex);
  2681. }
  2682. iwl_down(priv);
  2683. flush_workqueue(priv->workqueue);
  2684. /* enable interrupts again in order to receive rfkill changes */
  2685. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2686. iwl_enable_interrupts(priv);
  2687. IWL_DEBUG_MAC80211(priv, "leave\n");
  2688. }
  2689. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2690. {
  2691. struct iwl_priv *priv = hw->priv;
  2692. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2693. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2694. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2695. if (iwlagn_tx_skb(priv, skb))
  2696. dev_kfree_skb_any(skb);
  2697. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2698. return NETDEV_TX_OK;
  2699. }
  2700. void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2701. {
  2702. int ret = 0;
  2703. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2704. return;
  2705. /* The following should be done only at AP bring up */
  2706. if (!iwl_is_associated(priv)) {
  2707. /* RXON - unassoc (to set timing command) */
  2708. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2709. iwlcore_commit_rxon(priv);
  2710. /* RXON Timing */
  2711. iwl_setup_rxon_timing(priv, vif);
  2712. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2713. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2714. if (ret)
  2715. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2716. "Attempting to continue.\n");
  2717. /* AP has all antennas */
  2718. priv->chain_noise_data.active_chains =
  2719. priv->hw_params.valid_rx_ant;
  2720. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2721. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2722. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2723. priv->staging_rxon.assoc_id = 0;
  2724. if (vif->bss_conf.use_short_preamble)
  2725. priv->staging_rxon.flags |=
  2726. RXON_FLG_SHORT_PREAMBLE_MSK;
  2727. else
  2728. priv->staging_rxon.flags &=
  2729. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2730. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2731. if (vif->bss_conf.use_short_slot)
  2732. priv->staging_rxon.flags |=
  2733. RXON_FLG_SHORT_SLOT_MSK;
  2734. else
  2735. priv->staging_rxon.flags &=
  2736. ~RXON_FLG_SHORT_SLOT_MSK;
  2737. }
  2738. /* restore RXON assoc */
  2739. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2740. iwlcore_commit_rxon(priv);
  2741. }
  2742. iwl_send_beacon_cmd(priv);
  2743. /* FIXME - we need to add code here to detect a totally new
  2744. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2745. * clear sta table, add BCAST sta... */
  2746. }
  2747. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2748. struct ieee80211_vif *vif,
  2749. struct ieee80211_key_conf *keyconf,
  2750. struct ieee80211_sta *sta,
  2751. u32 iv32, u16 *phase1key)
  2752. {
  2753. struct iwl_priv *priv = hw->priv;
  2754. IWL_DEBUG_MAC80211(priv, "enter\n");
  2755. iwl_update_tkip_key(priv, keyconf, sta,
  2756. iv32, phase1key);
  2757. IWL_DEBUG_MAC80211(priv, "leave\n");
  2758. }
  2759. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2760. struct ieee80211_vif *vif,
  2761. struct ieee80211_sta *sta,
  2762. struct ieee80211_key_conf *key)
  2763. {
  2764. struct iwl_priv *priv = hw->priv;
  2765. int ret;
  2766. u8 sta_id;
  2767. bool is_default_wep_key = false;
  2768. IWL_DEBUG_MAC80211(priv, "enter\n");
  2769. if (priv->cfg->mod_params->sw_crypto) {
  2770. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2771. return -EOPNOTSUPP;
  2772. }
  2773. sta_id = iwl_sta_id_or_broadcast(priv, sta);
  2774. if (sta_id == IWL_INVALID_STATION)
  2775. return -EINVAL;
  2776. mutex_lock(&priv->mutex);
  2777. iwl_scan_cancel_timeout(priv, 100);
  2778. /*
  2779. * If we are getting WEP group key and we didn't receive any key mapping
  2780. * so far, we are in legacy wep mode (group key only), otherwise we are
  2781. * in 1X mode.
  2782. * In legacy wep mode, we use another host command to the uCode.
  2783. */
  2784. if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
  2785. if (cmd == SET_KEY)
  2786. is_default_wep_key = !priv->key_mapping_key;
  2787. else
  2788. is_default_wep_key =
  2789. (key->hw_key_idx == HW_KEY_DEFAULT);
  2790. }
  2791. switch (cmd) {
  2792. case SET_KEY:
  2793. if (is_default_wep_key)
  2794. ret = iwl_set_default_wep_key(priv, key);
  2795. else
  2796. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2797. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2798. break;
  2799. case DISABLE_KEY:
  2800. if (is_default_wep_key)
  2801. ret = iwl_remove_default_wep_key(priv, key);
  2802. else
  2803. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2804. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2805. break;
  2806. default:
  2807. ret = -EINVAL;
  2808. }
  2809. mutex_unlock(&priv->mutex);
  2810. IWL_DEBUG_MAC80211(priv, "leave\n");
  2811. return ret;
  2812. }
  2813. /*
  2814. * switch to RTS/CTS for TX
  2815. */
  2816. static void iwl_enable_rts_cts(struct iwl_priv *priv)
  2817. {
  2818. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2819. return;
  2820. priv->staging_rxon.flags &= ~RXON_FLG_SELF_CTS_EN;
  2821. if (!test_bit(STATUS_SCANNING, &priv->status)) {
  2822. IWL_DEBUG_INFO(priv, "use RTS/CTS protection\n");
  2823. iwlcore_commit_rxon(priv);
  2824. } else {
  2825. /* scanning, defer the request until scan completed */
  2826. IWL_DEBUG_INFO(priv, "defer setting RTS/CTS protection\n");
  2827. }
  2828. }
  2829. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2830. struct ieee80211_vif *vif,
  2831. enum ieee80211_ampdu_mlme_action action,
  2832. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2833. {
  2834. struct iwl_priv *priv = hw->priv;
  2835. int ret = -EINVAL;
  2836. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2837. sta->addr, tid);
  2838. if (!(priv->cfg->sku & IWL_SKU_N))
  2839. return -EACCES;
  2840. mutex_lock(&priv->mutex);
  2841. switch (action) {
  2842. case IEEE80211_AMPDU_RX_START:
  2843. IWL_DEBUG_HT(priv, "start Rx\n");
  2844. ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2845. break;
  2846. case IEEE80211_AMPDU_RX_STOP:
  2847. IWL_DEBUG_HT(priv, "stop Rx\n");
  2848. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2849. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2850. ret = 0;
  2851. break;
  2852. case IEEE80211_AMPDU_TX_START:
  2853. IWL_DEBUG_HT(priv, "start Tx\n");
  2854. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2855. if (ret == 0) {
  2856. priv->_agn.agg_tids_count++;
  2857. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2858. priv->_agn.agg_tids_count);
  2859. }
  2860. break;
  2861. case IEEE80211_AMPDU_TX_STOP:
  2862. IWL_DEBUG_HT(priv, "stop Tx\n");
  2863. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2864. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2865. priv->_agn.agg_tids_count--;
  2866. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2867. priv->_agn.agg_tids_count);
  2868. }
  2869. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2870. ret = 0;
  2871. break;
  2872. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2873. if (priv->cfg->use_rts_for_ht) {
  2874. /*
  2875. * switch to RTS/CTS if it is the prefer protection
  2876. * method for HT traffic
  2877. */
  2878. iwl_enable_rts_cts(priv);
  2879. }
  2880. ret = 0;
  2881. break;
  2882. }
  2883. mutex_unlock(&priv->mutex);
  2884. return ret;
  2885. }
  2886. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2887. struct ieee80211_vif *vif,
  2888. enum sta_notify_cmd cmd,
  2889. struct ieee80211_sta *sta)
  2890. {
  2891. struct iwl_priv *priv = hw->priv;
  2892. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2893. int sta_id;
  2894. switch (cmd) {
  2895. case STA_NOTIFY_SLEEP:
  2896. WARN_ON(!sta_priv->client);
  2897. sta_priv->asleep = true;
  2898. if (atomic_read(&sta_priv->pending_frames) > 0)
  2899. ieee80211_sta_block_awake(hw, sta, true);
  2900. break;
  2901. case STA_NOTIFY_AWAKE:
  2902. WARN_ON(!sta_priv->client);
  2903. if (!sta_priv->asleep)
  2904. break;
  2905. sta_priv->asleep = false;
  2906. sta_id = iwl_sta_id(sta);
  2907. if (sta_id != IWL_INVALID_STATION)
  2908. iwl_sta_modify_ps_wake(priv, sta_id);
  2909. break;
  2910. default:
  2911. break;
  2912. }
  2913. }
  2914. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2915. struct ieee80211_vif *vif,
  2916. struct ieee80211_sta *sta)
  2917. {
  2918. struct iwl_priv *priv = hw->priv;
  2919. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2920. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2921. int ret;
  2922. u8 sta_id;
  2923. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2924. sta->addr);
  2925. mutex_lock(&priv->mutex);
  2926. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2927. sta->addr);
  2928. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2929. atomic_set(&sta_priv->pending_frames, 0);
  2930. if (vif->type == NL80211_IFTYPE_AP)
  2931. sta_priv->client = true;
  2932. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  2933. &sta_id);
  2934. if (ret) {
  2935. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2936. sta->addr, ret);
  2937. /* Should we return success if return code is EEXIST ? */
  2938. mutex_unlock(&priv->mutex);
  2939. return ret;
  2940. }
  2941. sta_priv->common.sta_id = sta_id;
  2942. /* Initialize rate scaling */
  2943. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2944. sta->addr);
  2945. iwl_rs_rate_init(priv, sta, sta_id);
  2946. mutex_unlock(&priv->mutex);
  2947. return 0;
  2948. }
  2949. static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
  2950. struct ieee80211_channel_switch *ch_switch)
  2951. {
  2952. struct iwl_priv *priv = hw->priv;
  2953. const struct iwl_channel_info *ch_info;
  2954. struct ieee80211_conf *conf = &hw->conf;
  2955. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2956. u16 ch;
  2957. unsigned long flags = 0;
  2958. IWL_DEBUG_MAC80211(priv, "enter\n");
  2959. if (iwl_is_rfkill(priv))
  2960. goto out_exit;
  2961. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2962. test_bit(STATUS_SCANNING, &priv->status))
  2963. goto out_exit;
  2964. if (!iwl_is_associated(priv))
  2965. goto out_exit;
  2966. /* channel switch in progress */
  2967. if (priv->switch_rxon.switch_in_progress == true)
  2968. goto out_exit;
  2969. mutex_lock(&priv->mutex);
  2970. if (priv->cfg->ops->lib->set_channel_switch) {
  2971. ch = ieee80211_frequency_to_channel(
  2972. ch_switch->channel->center_freq);
  2973. if (le16_to_cpu(priv->active_rxon.channel) != ch) {
  2974. ch_info = iwl_get_channel_info(priv,
  2975. conf->channel->band,
  2976. ch);
  2977. if (!is_channel_valid(ch_info)) {
  2978. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  2979. goto out;
  2980. }
  2981. spin_lock_irqsave(&priv->lock, flags);
  2982. priv->current_ht_config.smps = conf->smps_mode;
  2983. /* Configure HT40 channels */
  2984. ht_conf->is_ht = conf_is_ht(conf);
  2985. if (ht_conf->is_ht) {
  2986. if (conf_is_ht40_minus(conf)) {
  2987. ht_conf->extension_chan_offset =
  2988. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2989. ht_conf->is_40mhz = true;
  2990. } else if (conf_is_ht40_plus(conf)) {
  2991. ht_conf->extension_chan_offset =
  2992. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2993. ht_conf->is_40mhz = true;
  2994. } else {
  2995. ht_conf->extension_chan_offset =
  2996. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2997. ht_conf->is_40mhz = false;
  2998. }
  2999. } else
  3000. ht_conf->is_40mhz = false;
  3001. /* if we are switching from ht to 2.4 clear flags
  3002. * from any ht related info since 2.4 does not
  3003. * support ht */
  3004. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  3005. priv->staging_rxon.flags = 0;
  3006. iwl_set_rxon_channel(priv, conf->channel);
  3007. iwl_set_rxon_ht(priv, ht_conf);
  3008. iwl_set_flags_for_band(priv, conf->channel->band,
  3009. priv->vif);
  3010. spin_unlock_irqrestore(&priv->lock, flags);
  3011. iwl_set_rate(priv);
  3012. /*
  3013. * at this point, staging_rxon has the
  3014. * configuration for channel switch
  3015. */
  3016. if (priv->cfg->ops->lib->set_channel_switch(priv,
  3017. ch_switch))
  3018. priv->switch_rxon.switch_in_progress = false;
  3019. }
  3020. }
  3021. out:
  3022. mutex_unlock(&priv->mutex);
  3023. out_exit:
  3024. if (!priv->switch_rxon.switch_in_progress)
  3025. ieee80211_chswitch_done(priv->vif, false);
  3026. IWL_DEBUG_MAC80211(priv, "leave\n");
  3027. }
  3028. /*****************************************************************************
  3029. *
  3030. * driver setup and teardown
  3031. *
  3032. *****************************************************************************/
  3033. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  3034. {
  3035. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3036. init_waitqueue_head(&priv->wait_command_queue);
  3037. INIT_WORK(&priv->restart, iwl_bg_restart);
  3038. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  3039. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  3040. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  3041. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  3042. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  3043. iwl_setup_scan_deferred_work(priv);
  3044. if (priv->cfg->ops->lib->setup_deferred_work)
  3045. priv->cfg->ops->lib->setup_deferred_work(priv);
  3046. init_timer(&priv->statistics_periodic);
  3047. priv->statistics_periodic.data = (unsigned long)priv;
  3048. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  3049. init_timer(&priv->ucode_trace);
  3050. priv->ucode_trace.data = (unsigned long)priv;
  3051. priv->ucode_trace.function = iwl_bg_ucode_trace;
  3052. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  3053. init_timer(&priv->monitor_recover);
  3054. priv->monitor_recover.data = (unsigned long)priv;
  3055. priv->monitor_recover.function =
  3056. priv->cfg->ops->lib->recover_from_tx_stall;
  3057. }
  3058. if (!priv->cfg->use_isr_legacy)
  3059. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3060. iwl_irq_tasklet, (unsigned long)priv);
  3061. else
  3062. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3063. iwl_irq_tasklet_legacy, (unsigned long)priv);
  3064. }
  3065. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  3066. {
  3067. if (priv->cfg->ops->lib->cancel_deferred_work)
  3068. priv->cfg->ops->lib->cancel_deferred_work(priv);
  3069. cancel_delayed_work_sync(&priv->init_alive_start);
  3070. cancel_delayed_work(&priv->scan_check);
  3071. cancel_work_sync(&priv->start_internal_scan);
  3072. cancel_delayed_work(&priv->alive_start);
  3073. cancel_work_sync(&priv->run_time_calib_work);
  3074. cancel_work_sync(&priv->beacon_update);
  3075. del_timer_sync(&priv->statistics_periodic);
  3076. del_timer_sync(&priv->ucode_trace);
  3077. if (priv->cfg->ops->lib->recover_from_tx_stall)
  3078. del_timer_sync(&priv->monitor_recover);
  3079. }
  3080. static void iwl_init_hw_rates(struct iwl_priv *priv,
  3081. struct ieee80211_rate *rates)
  3082. {
  3083. int i;
  3084. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  3085. rates[i].bitrate = iwl_rates[i].ieee * 5;
  3086. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3087. rates[i].hw_value_short = i;
  3088. rates[i].flags = 0;
  3089. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  3090. /*
  3091. * If CCK != 1M then set short preamble rate flag.
  3092. */
  3093. rates[i].flags |=
  3094. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  3095. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3096. }
  3097. }
  3098. }
  3099. static int iwl_init_drv(struct iwl_priv *priv)
  3100. {
  3101. int ret;
  3102. priv->ibss_beacon = NULL;
  3103. spin_lock_init(&priv->sta_lock);
  3104. spin_lock_init(&priv->hcmd_lock);
  3105. INIT_LIST_HEAD(&priv->free_frames);
  3106. mutex_init(&priv->mutex);
  3107. mutex_init(&priv->sync_cmd_mutex);
  3108. priv->ieee_channels = NULL;
  3109. priv->ieee_rates = NULL;
  3110. priv->band = IEEE80211_BAND_2GHZ;
  3111. priv->iw_mode = NL80211_IFTYPE_STATION;
  3112. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  3113. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3114. priv->_agn.agg_tids_count = 0;
  3115. /* initialize force reset */
  3116. priv->force_reset[IWL_RF_RESET].reset_duration =
  3117. IWL_DELAY_NEXT_FORCE_RF_RESET;
  3118. priv->force_reset[IWL_FW_RESET].reset_duration =
  3119. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  3120. /* Choose which receivers/antennas to use */
  3121. if (priv->cfg->ops->hcmd->set_rxon_chain)
  3122. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  3123. iwl_init_scan_params(priv);
  3124. /* Set the tx_power_user_lmt to the lowest power level
  3125. * this value will get overwritten by channel max power avg
  3126. * from eeprom */
  3127. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  3128. ret = iwl_init_channel_map(priv);
  3129. if (ret) {
  3130. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3131. goto err;
  3132. }
  3133. ret = iwlcore_init_geos(priv);
  3134. if (ret) {
  3135. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3136. goto err_free_channel_map;
  3137. }
  3138. iwl_init_hw_rates(priv, priv->ieee_rates);
  3139. return 0;
  3140. err_free_channel_map:
  3141. iwl_free_channel_map(priv);
  3142. err:
  3143. return ret;
  3144. }
  3145. static void iwl_uninit_drv(struct iwl_priv *priv)
  3146. {
  3147. iwl_calib_free_results(priv);
  3148. iwlcore_free_geos(priv);
  3149. iwl_free_channel_map(priv);
  3150. kfree(priv->scan_cmd);
  3151. }
  3152. static struct ieee80211_ops iwl_hw_ops = {
  3153. .tx = iwl_mac_tx,
  3154. .start = iwl_mac_start,
  3155. .stop = iwl_mac_stop,
  3156. .add_interface = iwl_mac_add_interface,
  3157. .remove_interface = iwl_mac_remove_interface,
  3158. .config = iwl_mac_config,
  3159. .configure_filter = iwl_configure_filter,
  3160. .set_key = iwl_mac_set_key,
  3161. .update_tkip_key = iwl_mac_update_tkip_key,
  3162. .conf_tx = iwl_mac_conf_tx,
  3163. .reset_tsf = iwl_mac_reset_tsf,
  3164. .bss_info_changed = iwl_bss_info_changed,
  3165. .ampdu_action = iwl_mac_ampdu_action,
  3166. .hw_scan = iwl_mac_hw_scan,
  3167. .sta_notify = iwl_mac_sta_notify,
  3168. .sta_add = iwlagn_mac_sta_add,
  3169. .sta_remove = iwl_mac_sta_remove,
  3170. .channel_switch = iwl_mac_channel_switch,
  3171. };
  3172. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3173. {
  3174. int err = 0;
  3175. struct iwl_priv *priv;
  3176. struct ieee80211_hw *hw;
  3177. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3178. unsigned long flags;
  3179. u16 pci_cmd;
  3180. u8 perm_addr[ETH_ALEN];
  3181. /************************
  3182. * 1. Allocating HW data
  3183. ************************/
  3184. /* Disabling hardware scan means that mac80211 will perform scans
  3185. * "the hard way", rather than using device's scan. */
  3186. if (cfg->mod_params->disable_hw_scan) {
  3187. if (iwl_debug_level & IWL_DL_INFO)
  3188. dev_printk(KERN_DEBUG, &(pdev->dev),
  3189. "Disabling hw_scan\n");
  3190. iwl_hw_ops.hw_scan = NULL;
  3191. }
  3192. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  3193. if (!hw) {
  3194. err = -ENOMEM;
  3195. goto out;
  3196. }
  3197. priv = hw->priv;
  3198. /* At this point both hw and priv are allocated. */
  3199. SET_IEEE80211_DEV(hw, &pdev->dev);
  3200. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3201. priv->cfg = cfg;
  3202. priv->pci_dev = pdev;
  3203. priv->inta_mask = CSR_INI_SET_MASK;
  3204. if (iwl_alloc_traffic_mem(priv))
  3205. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3206. /**************************
  3207. * 2. Initializing PCI bus
  3208. **************************/
  3209. if (pci_enable_device(pdev)) {
  3210. err = -ENODEV;
  3211. goto out_ieee80211_free_hw;
  3212. }
  3213. pci_set_master(pdev);
  3214. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  3215. if (!err)
  3216. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  3217. if (err) {
  3218. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3219. if (!err)
  3220. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3221. /* both attempts failed: */
  3222. if (err) {
  3223. IWL_WARN(priv, "No suitable DMA available.\n");
  3224. goto out_pci_disable_device;
  3225. }
  3226. }
  3227. err = pci_request_regions(pdev, DRV_NAME);
  3228. if (err)
  3229. goto out_pci_disable_device;
  3230. pci_set_drvdata(pdev, priv);
  3231. /***********************
  3232. * 3. Read REV register
  3233. ***********************/
  3234. priv->hw_base = pci_iomap(pdev, 0, 0);
  3235. if (!priv->hw_base) {
  3236. err = -ENODEV;
  3237. goto out_pci_release_regions;
  3238. }
  3239. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3240. (unsigned long long) pci_resource_len(pdev, 0));
  3241. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3242. /* these spin locks will be used in apm_ops.init and EEPROM access
  3243. * we should init now
  3244. */
  3245. spin_lock_init(&priv->reg_lock);
  3246. spin_lock_init(&priv->lock);
  3247. /*
  3248. * stop and reset the on-board processor just in case it is in a
  3249. * strange state ... like being left stranded by a primary kernel
  3250. * and this is now the kdump kernel trying to start up
  3251. */
  3252. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3253. iwl_hw_detect(priv);
  3254. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3255. priv->cfg->name, priv->hw_rev);
  3256. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3257. * PCI Tx retries from interfering with C3 CPU state */
  3258. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3259. iwl_prepare_card_hw(priv);
  3260. if (!priv->hw_ready) {
  3261. IWL_WARN(priv, "Failed, HW not ready\n");
  3262. goto out_iounmap;
  3263. }
  3264. /*****************
  3265. * 4. Read EEPROM
  3266. *****************/
  3267. /* Read the EEPROM */
  3268. err = iwl_eeprom_init(priv);
  3269. if (err) {
  3270. IWL_ERR(priv, "Unable to init EEPROM\n");
  3271. goto out_iounmap;
  3272. }
  3273. err = iwl_eeprom_check_version(priv);
  3274. if (err)
  3275. goto out_free_eeprom;
  3276. /* extract MAC Address */
  3277. iwl_eeprom_get_mac(priv, perm_addr);
  3278. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", perm_addr);
  3279. SET_IEEE80211_PERM_ADDR(priv->hw, perm_addr);
  3280. /************************
  3281. * 5. Setup HW constants
  3282. ************************/
  3283. if (iwl_set_hw_params(priv)) {
  3284. IWL_ERR(priv, "failed to set hw parameters\n");
  3285. goto out_free_eeprom;
  3286. }
  3287. /*******************
  3288. * 6. Setup priv
  3289. *******************/
  3290. err = iwl_init_drv(priv);
  3291. if (err)
  3292. goto out_free_eeprom;
  3293. /* At this point both hw and priv are initialized. */
  3294. /********************
  3295. * 7. Setup services
  3296. ********************/
  3297. spin_lock_irqsave(&priv->lock, flags);
  3298. iwl_disable_interrupts(priv);
  3299. spin_unlock_irqrestore(&priv->lock, flags);
  3300. pci_enable_msi(priv->pci_dev);
  3301. iwl_alloc_isr_ict(priv);
  3302. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3303. IRQF_SHARED, DRV_NAME, priv);
  3304. if (err) {
  3305. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3306. goto out_disable_msi;
  3307. }
  3308. iwl_setup_deferred_work(priv);
  3309. iwl_setup_rx_handlers(priv);
  3310. /*********************************************
  3311. * 8. Enable interrupts and read RFKILL state
  3312. *********************************************/
  3313. /* enable interrupts if needed: hw bug w/a */
  3314. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3315. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3316. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3317. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3318. }
  3319. iwl_enable_interrupts(priv);
  3320. /* If platform's RF_KILL switch is NOT set to KILL */
  3321. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3322. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3323. else
  3324. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3325. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3326. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3327. iwl_power_initialize(priv);
  3328. iwl_tt_initialize(priv);
  3329. init_completion(&priv->_agn.firmware_loading_complete);
  3330. err = iwl_request_firmware(priv, true);
  3331. if (err)
  3332. goto out_destroy_workqueue;
  3333. return 0;
  3334. out_destroy_workqueue:
  3335. destroy_workqueue(priv->workqueue);
  3336. priv->workqueue = NULL;
  3337. free_irq(priv->pci_dev->irq, priv);
  3338. iwl_free_isr_ict(priv);
  3339. out_disable_msi:
  3340. pci_disable_msi(priv->pci_dev);
  3341. iwl_uninit_drv(priv);
  3342. out_free_eeprom:
  3343. iwl_eeprom_free(priv);
  3344. out_iounmap:
  3345. pci_iounmap(pdev, priv->hw_base);
  3346. out_pci_release_regions:
  3347. pci_set_drvdata(pdev, NULL);
  3348. pci_release_regions(pdev);
  3349. out_pci_disable_device:
  3350. pci_disable_device(pdev);
  3351. out_ieee80211_free_hw:
  3352. iwl_free_traffic_mem(priv);
  3353. ieee80211_free_hw(priv->hw);
  3354. out:
  3355. return err;
  3356. }
  3357. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3358. {
  3359. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3360. unsigned long flags;
  3361. if (!priv)
  3362. return;
  3363. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3364. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3365. iwl_dbgfs_unregister(priv);
  3366. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3367. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3368. * to be called and iwl_down since we are removing the device
  3369. * we need to set STATUS_EXIT_PENDING bit.
  3370. */
  3371. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3372. if (priv->mac80211_registered) {
  3373. ieee80211_unregister_hw(priv->hw);
  3374. priv->mac80211_registered = 0;
  3375. } else {
  3376. iwl_down(priv);
  3377. }
  3378. /*
  3379. * Make sure device is reset to low power before unloading driver.
  3380. * This may be redundant with iwl_down(), but there are paths to
  3381. * run iwl_down() without calling apm_ops.stop(), and there are
  3382. * paths to avoid running iwl_down() at all before leaving driver.
  3383. * This (inexpensive) call *makes sure* device is reset.
  3384. */
  3385. priv->cfg->ops->lib->apm_ops.stop(priv);
  3386. iwl_tt_exit(priv);
  3387. /* make sure we flush any pending irq or
  3388. * tasklet for the driver
  3389. */
  3390. spin_lock_irqsave(&priv->lock, flags);
  3391. iwl_disable_interrupts(priv);
  3392. spin_unlock_irqrestore(&priv->lock, flags);
  3393. iwl_synchronize_irq(priv);
  3394. iwl_dealloc_ucode_pci(priv);
  3395. if (priv->rxq.bd)
  3396. iwlagn_rx_queue_free(priv, &priv->rxq);
  3397. iwlagn_hw_txq_ctx_free(priv);
  3398. iwl_eeprom_free(priv);
  3399. /*netif_stop_queue(dev); */
  3400. flush_workqueue(priv->workqueue);
  3401. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3402. * priv->workqueue... so we can't take down the workqueue
  3403. * until now... */
  3404. destroy_workqueue(priv->workqueue);
  3405. priv->workqueue = NULL;
  3406. iwl_free_traffic_mem(priv);
  3407. free_irq(priv->pci_dev->irq, priv);
  3408. pci_disable_msi(priv->pci_dev);
  3409. pci_iounmap(pdev, priv->hw_base);
  3410. pci_release_regions(pdev);
  3411. pci_disable_device(pdev);
  3412. pci_set_drvdata(pdev, NULL);
  3413. iwl_uninit_drv(priv);
  3414. iwl_free_isr_ict(priv);
  3415. if (priv->ibss_beacon)
  3416. dev_kfree_skb(priv->ibss_beacon);
  3417. ieee80211_free_hw(priv->hw);
  3418. }
  3419. /*****************************************************************************
  3420. *
  3421. * driver and module entry point
  3422. *
  3423. *****************************************************************************/
  3424. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3425. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3426. #ifdef CONFIG_IWL4965
  3427. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3428. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3429. #endif /* CONFIG_IWL4965 */
  3430. #ifdef CONFIG_IWL5000
  3431. /* 5100 Series WiFi */
  3432. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3433. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3434. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3435. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3436. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3437. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3438. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3439. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3440. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3441. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3442. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3443. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3444. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3445. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3446. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3447. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3448. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3449. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3450. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3451. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3452. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3453. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3454. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3455. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3456. /* 5300 Series WiFi */
  3457. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3458. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3459. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3460. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3461. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3462. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3463. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3464. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3465. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3466. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3467. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3468. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3469. /* 5350 Series WiFi/WiMax */
  3470. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3471. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3472. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3473. /* 5150 Series Wifi/WiMax */
  3474. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3475. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3476. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3477. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3478. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3479. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3480. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3481. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3482. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3483. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3484. /* 6x00 Series */
  3485. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3486. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3487. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3488. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3489. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3490. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3491. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3492. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3493. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3494. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3495. /* 6x00 Series Gen2a */
  3496. {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
  3497. {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
  3498. {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
  3499. {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
  3500. {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
  3501. {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
  3502. {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
  3503. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
  3504. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
  3505. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
  3506. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
  3507. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
  3508. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
  3509. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
  3510. /* 6x00 Series Gen2b */
  3511. {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
  3512. {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
  3513. {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
  3514. {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
  3515. {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
  3516. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3517. {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
  3518. {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
  3519. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3520. {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
  3521. {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
  3522. {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
  3523. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
  3524. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
  3525. {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
  3526. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
  3527. {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
  3528. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
  3529. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
  3530. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
  3531. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
  3532. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
  3533. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
  3534. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
  3535. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
  3536. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
  3537. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
  3538. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
  3539. /* 6x50 WiFi/WiMax Series */
  3540. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3541. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3542. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3543. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3544. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3545. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3546. /* 1000 Series WiFi */
  3547. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3548. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3549. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3550. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3551. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3552. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3553. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3554. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3555. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3556. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3557. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3558. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3559. #endif /* CONFIG_IWL5000 */
  3560. {0}
  3561. };
  3562. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3563. static struct pci_driver iwl_driver = {
  3564. .name = DRV_NAME,
  3565. .id_table = iwl_hw_card_ids,
  3566. .probe = iwl_pci_probe,
  3567. .remove = __devexit_p(iwl_pci_remove),
  3568. #ifdef CONFIG_PM
  3569. .suspend = iwl_pci_suspend,
  3570. .resume = iwl_pci_resume,
  3571. #endif
  3572. };
  3573. static int __init iwl_init(void)
  3574. {
  3575. int ret;
  3576. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3577. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3578. ret = iwlagn_rate_control_register();
  3579. if (ret) {
  3580. printk(KERN_ERR DRV_NAME
  3581. "Unable to register rate control algorithm: %d\n", ret);
  3582. return ret;
  3583. }
  3584. ret = pci_register_driver(&iwl_driver);
  3585. if (ret) {
  3586. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3587. goto error_register;
  3588. }
  3589. return ret;
  3590. error_register:
  3591. iwlagn_rate_control_unregister();
  3592. return ret;
  3593. }
  3594. static void __exit iwl_exit(void)
  3595. {
  3596. pci_unregister_driver(&iwl_driver);
  3597. iwlagn_rate_control_unregister();
  3598. }
  3599. module_exit(iwl_exit);
  3600. module_init(iwl_init);
  3601. #ifdef CONFIG_IWLWIFI_DEBUG
  3602. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3603. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3604. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3605. MODULE_PARM_DESC(debug, "debug output mask");
  3606. #endif
  3607. module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
  3608. MODULE_PARM_DESC(swcrypto50,
  3609. "using crypto in software (default 0 [hardware]) (deprecated)");
  3610. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3611. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3612. module_param_named(queues_num50,
  3613. iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3614. MODULE_PARM_DESC(queues_num50,
  3615. "number of hw queues in 50xx series (deprecated)");
  3616. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3617. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3618. module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3619. MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
  3620. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3621. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3622. module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
  3623. int, S_IRUGO);
  3624. MODULE_PARM_DESC(amsdu_size_8K50,
  3625. "enable 8K amsdu size in 50XX series (deprecated)");
  3626. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3627. int, S_IRUGO);
  3628. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3629. module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3630. MODULE_PARM_DESC(fw_restart50,
  3631. "restart firmware in case of error (deprecated)");
  3632. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3633. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3634. module_param_named(
  3635. disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
  3636. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3637. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3638. S_IRUGO);
  3639. MODULE_PARM_DESC(ucode_alternative,
  3640. "specify ucode alternative to use from ucode file");