davinci_spi.c 31 KB

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  1. /*
  2. * Copyright (C) 2009 Texas Instruments.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17. */
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio.h>
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/err.h>
  25. #include <linux/clk.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/spi/spi.h>
  28. #include <linux/spi/spi_bitbang.h>
  29. #include <linux/slab.h>
  30. #include <mach/spi.h>
  31. #include <mach/edma.h>
  32. #define SPI_NO_RESOURCE ((resource_size_t)-1)
  33. #define SPI_MAX_CHIPSELECT 2
  34. #define CS_DEFAULT 0xFF
  35. #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
  36. #define DAVINCI_DMA_DATA_TYPE_S8 0x01
  37. #define DAVINCI_DMA_DATA_TYPE_S16 0x02
  38. #define DAVINCI_DMA_DATA_TYPE_S32 0x04
  39. #define SPIFMT_PHASE_MASK BIT(16)
  40. #define SPIFMT_POLARITY_MASK BIT(17)
  41. #define SPIFMT_DISTIMER_MASK BIT(18)
  42. #define SPIFMT_SHIFTDIR_MASK BIT(20)
  43. #define SPIFMT_WAITENA_MASK BIT(21)
  44. #define SPIFMT_PARITYENA_MASK BIT(22)
  45. #define SPIFMT_ODD_PARITY_MASK BIT(23)
  46. #define SPIFMT_WDELAY_MASK 0x3f000000u
  47. #define SPIFMT_WDELAY_SHIFT 24
  48. #define SPIFMT_CHARLEN_MASK 0x0000001Fu
  49. /* SPIPC0 */
  50. #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
  51. #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
  52. #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
  53. #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
  54. #define SPIINT_MASKALL 0x0101035F
  55. #define SPI_INTLVL_1 0x000001FFu
  56. #define SPI_INTLVL_0 0x00000000u
  57. /* SPIDAT1 (upper 16 bit defines) */
  58. #define SPIDAT1_CSHOLD_MASK BIT(12)
  59. /* SPIGCR1 */
  60. #define SPIGCR1_CLKMOD_MASK BIT(1)
  61. #define SPIGCR1_MASTER_MASK BIT(0)
  62. #define SPIGCR1_LOOPBACK_MASK BIT(16)
  63. #define SPIGCR1_SPIENA_MASK BIT(24)
  64. /* SPIBUF */
  65. #define SPIBUF_TXFULL_MASK BIT(29)
  66. #define SPIBUF_RXEMPTY_MASK BIT(31)
  67. /* Error Masks */
  68. #define SPIFLG_DLEN_ERR_MASK BIT(0)
  69. #define SPIFLG_TIMEOUT_MASK BIT(1)
  70. #define SPIFLG_PARERR_MASK BIT(2)
  71. #define SPIFLG_DESYNC_MASK BIT(3)
  72. #define SPIFLG_BITERR_MASK BIT(4)
  73. #define SPIFLG_OVRRUN_MASK BIT(6)
  74. #define SPIFLG_RX_INTR_MASK BIT(8)
  75. #define SPIFLG_TX_INTR_MASK BIT(9)
  76. #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
  77. #define SPIINT_BITERR_INTR BIT(4)
  78. #define SPIINT_OVRRUN_INTR BIT(6)
  79. #define SPIINT_RX_INTR BIT(8)
  80. #define SPIINT_TX_INTR BIT(9)
  81. #define SPIINT_DMA_REQ_EN BIT(16)
  82. #define SPI_T2CDELAY_SHIFT 16
  83. #define SPI_C2TDELAY_SHIFT 24
  84. /* SPI Controller registers */
  85. #define SPIGCR0 0x00
  86. #define SPIGCR1 0x04
  87. #define SPIINT 0x08
  88. #define SPILVL 0x0c
  89. #define SPIFLG 0x10
  90. #define SPIPC0 0x14
  91. #define SPIDAT1 0x3c
  92. #define SPIBUF 0x40
  93. #define SPIDELAY 0x48
  94. #define SPIDEF 0x4c
  95. #define SPIFMT0 0x50
  96. struct davinci_spi_slave {
  97. u32 cmd_to_write;
  98. u32 clk_ctrl_to_write;
  99. u32 bytes_per_word;
  100. u8 active_cs;
  101. };
  102. /* We have 2 DMA channels per CS, one for RX and one for TX */
  103. struct davinci_spi_dma {
  104. int dma_tx_channel;
  105. int dma_rx_channel;
  106. int dma_tx_sync_dev;
  107. int dma_rx_sync_dev;
  108. enum dma_event_q eventq;
  109. struct completion dma_tx_completion;
  110. struct completion dma_rx_completion;
  111. };
  112. /* SPI Controller driver's private data. */
  113. struct davinci_spi {
  114. struct spi_bitbang bitbang;
  115. struct clk *clk;
  116. u8 version;
  117. resource_size_t pbase;
  118. void __iomem *base;
  119. size_t region_size;
  120. u32 irq;
  121. struct completion done;
  122. const void *tx;
  123. void *rx;
  124. u8 *tmp_buf;
  125. int count;
  126. struct davinci_spi_dma *dma_channels;
  127. struct davinci_spi_platform_data *pdata;
  128. void (*get_rx)(u32 rx_data, struct davinci_spi *);
  129. u32 (*get_tx)(struct davinci_spi *);
  130. struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
  131. };
  132. static unsigned use_dma;
  133. static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
  134. {
  135. u8 *rx = davinci_spi->rx;
  136. *rx++ = (u8)data;
  137. davinci_spi->rx = rx;
  138. }
  139. static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
  140. {
  141. u16 *rx = davinci_spi->rx;
  142. *rx++ = (u16)data;
  143. davinci_spi->rx = rx;
  144. }
  145. static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
  146. {
  147. u32 data;
  148. const u8 *tx = davinci_spi->tx;
  149. data = *tx++;
  150. davinci_spi->tx = tx;
  151. return data;
  152. }
  153. static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
  154. {
  155. u32 data;
  156. const u16 *tx = davinci_spi->tx;
  157. data = *tx++;
  158. davinci_spi->tx = tx;
  159. return data;
  160. }
  161. static inline void set_io_bits(void __iomem *addr, u32 bits)
  162. {
  163. u32 v = ioread32(addr);
  164. v |= bits;
  165. iowrite32(v, addr);
  166. }
  167. static inline void clear_io_bits(void __iomem *addr, u32 bits)
  168. {
  169. u32 v = ioread32(addr);
  170. v &= ~bits;
  171. iowrite32(v, addr);
  172. }
  173. static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
  174. {
  175. set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
  176. }
  177. static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
  178. {
  179. clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
  180. }
  181. static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
  182. {
  183. struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
  184. if (enable)
  185. set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
  186. else
  187. clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
  188. }
  189. /*
  190. * Interface to control the chip select signal
  191. */
  192. static void davinci_spi_chipselect(struct spi_device *spi, int value)
  193. {
  194. struct davinci_spi *davinci_spi;
  195. struct davinci_spi_platform_data *pdata;
  196. u8 chip_sel = spi->chip_select;
  197. u16 spidat1_cfg = CS_DEFAULT;
  198. davinci_spi = spi_master_get_devdata(spi->master);
  199. pdata = davinci_spi->pdata;
  200. /*
  201. * Board specific chip select logic decides the polarity and cs
  202. * line for the controller
  203. */
  204. if (value == BITBANG_CS_ACTIVE) {
  205. spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
  206. spidat1_cfg &= ~(0x1 << chip_sel);
  207. }
  208. iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
  209. }
  210. /**
  211. * davinci_spi_setup_transfer - This functions will determine transfer method
  212. * @spi: spi device on which data transfer to be done
  213. * @t: spi transfer in which transfer info is filled
  214. *
  215. * This function determines data transfer method (8/16/32 bit transfer).
  216. * It will also set the SPI Clock Control register according to
  217. * SPI slave device freq.
  218. */
  219. static int davinci_spi_setup_transfer(struct spi_device *spi,
  220. struct spi_transfer *t)
  221. {
  222. struct davinci_spi *davinci_spi;
  223. u8 bits_per_word = 0;
  224. u32 hz = 0, prescale = 0, clkspeed;
  225. davinci_spi = spi_master_get_devdata(spi->master);
  226. if (t) {
  227. bits_per_word = t->bits_per_word;
  228. hz = t->speed_hz;
  229. }
  230. /* if bits_per_word is not set then set it default */
  231. if (!bits_per_word)
  232. bits_per_word = spi->bits_per_word;
  233. /*
  234. * Assign function pointer to appropriate transfer method
  235. * 8bit, 16bit or 32bit transfer
  236. */
  237. if (bits_per_word <= 8 && bits_per_word >= 2) {
  238. davinci_spi->get_rx = davinci_spi_rx_buf_u8;
  239. davinci_spi->get_tx = davinci_spi_tx_buf_u8;
  240. davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
  241. } else if (bits_per_word <= 16 && bits_per_word >= 2) {
  242. davinci_spi->get_rx = davinci_spi_rx_buf_u16;
  243. davinci_spi->get_tx = davinci_spi_tx_buf_u16;
  244. davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
  245. } else
  246. return -EINVAL;
  247. if (!hz)
  248. hz = spi->max_speed_hz;
  249. clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
  250. spi->chip_select);
  251. set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
  252. spi->chip_select);
  253. clkspeed = clk_get_rate(davinci_spi->clk);
  254. if (hz > clkspeed / 2)
  255. prescale = 1 << 8;
  256. if (hz < clkspeed / 256)
  257. prescale = 255 << 8;
  258. if (!prescale)
  259. prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
  260. clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
  261. set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
  262. return 0;
  263. }
  264. static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
  265. {
  266. struct spi_device *spi = (struct spi_device *)data;
  267. struct davinci_spi *davinci_spi;
  268. struct davinci_spi_dma *davinci_spi_dma;
  269. davinci_spi = spi_master_get_devdata(spi->master);
  270. davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
  271. if (ch_status == DMA_COMPLETE)
  272. edma_stop(davinci_spi_dma->dma_rx_channel);
  273. else
  274. edma_clean_channel(davinci_spi_dma->dma_rx_channel);
  275. complete(&davinci_spi_dma->dma_rx_completion);
  276. /* We must disable the DMA RX request */
  277. davinci_spi_set_dma_req(spi, 0);
  278. }
  279. static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
  280. {
  281. struct spi_device *spi = (struct spi_device *)data;
  282. struct davinci_spi *davinci_spi;
  283. struct davinci_spi_dma *davinci_spi_dma;
  284. davinci_spi = spi_master_get_devdata(spi->master);
  285. davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
  286. if (ch_status == DMA_COMPLETE)
  287. edma_stop(davinci_spi_dma->dma_tx_channel);
  288. else
  289. edma_clean_channel(davinci_spi_dma->dma_tx_channel);
  290. complete(&davinci_spi_dma->dma_tx_completion);
  291. /* We must disable the DMA TX request */
  292. davinci_spi_set_dma_req(spi, 0);
  293. }
  294. static int davinci_spi_request_dma(struct spi_device *spi)
  295. {
  296. struct davinci_spi *davinci_spi;
  297. struct davinci_spi_dma *davinci_spi_dma;
  298. struct device *sdev;
  299. int r;
  300. davinci_spi = spi_master_get_devdata(spi->master);
  301. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  302. sdev = davinci_spi->bitbang.master->dev.parent;
  303. r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
  304. davinci_spi_dma_rx_callback, spi,
  305. davinci_spi_dma->eventq);
  306. if (r < 0) {
  307. dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
  308. return -EAGAIN;
  309. }
  310. davinci_spi_dma->dma_rx_channel = r;
  311. r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
  312. davinci_spi_dma_tx_callback, spi,
  313. davinci_spi_dma->eventq);
  314. if (r < 0) {
  315. edma_free_channel(davinci_spi_dma->dma_rx_channel);
  316. davinci_spi_dma->dma_rx_channel = -1;
  317. dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
  318. return -EAGAIN;
  319. }
  320. davinci_spi_dma->dma_tx_channel = r;
  321. return 0;
  322. }
  323. /**
  324. * davinci_spi_setup - This functions will set default transfer method
  325. * @spi: spi device on which data transfer to be done
  326. *
  327. * This functions sets the default transfer method.
  328. */
  329. static int davinci_spi_setup(struct spi_device *spi)
  330. {
  331. int retval;
  332. struct davinci_spi *davinci_spi;
  333. struct davinci_spi_dma *davinci_spi_dma;
  334. struct device *sdev;
  335. davinci_spi = spi_master_get_devdata(spi->master);
  336. sdev = davinci_spi->bitbang.master->dev.parent;
  337. /* if bits per word length is zero then set it default 8 */
  338. if (!spi->bits_per_word)
  339. spi->bits_per_word = 8;
  340. davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
  341. if (use_dma && davinci_spi->dma_channels) {
  342. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  343. if ((davinci_spi_dma->dma_rx_channel == -1)
  344. || (davinci_spi_dma->dma_tx_channel == -1)) {
  345. retval = davinci_spi_request_dma(spi);
  346. if (retval < 0)
  347. return retval;
  348. }
  349. }
  350. /*
  351. * SPI in DaVinci and DA8xx operate between
  352. * 600 KHz and 50 MHz
  353. */
  354. if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
  355. dev_dbg(sdev, "Operating frequency is not in acceptable "
  356. "range\n");
  357. return -EINVAL;
  358. }
  359. /*
  360. * Set up SPIFMTn register, unique to this chipselect.
  361. *
  362. * NOTE: we could do all of these with one write. Also, some
  363. * of the "version 2" features are found in chips that don't
  364. * support all of them...
  365. */
  366. if (spi->mode & SPI_LSB_FIRST)
  367. set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
  368. spi->chip_select);
  369. else
  370. clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
  371. spi->chip_select);
  372. if (spi->mode & SPI_CPOL)
  373. set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
  374. spi->chip_select);
  375. else
  376. clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
  377. spi->chip_select);
  378. if (!(spi->mode & SPI_CPHA))
  379. set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
  380. spi->chip_select);
  381. else
  382. clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
  383. spi->chip_select);
  384. /*
  385. * Version 1 hardware supports two basic SPI modes:
  386. * - Standard SPI mode uses 4 pins, with chipselect
  387. * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
  388. * (distinct from SPI_3WIRE, with just one data wire;
  389. * or similar variants without MOSI or without MISO)
  390. *
  391. * Version 2 hardware supports an optional handshaking signal,
  392. * so it can support two more modes:
  393. * - 5 pin SPI variant is standard SPI plus SPI_READY
  394. * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
  395. */
  396. if (davinci_spi->version == SPI_VERSION_2) {
  397. clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
  398. spi->chip_select);
  399. set_fmt_bits(davinci_spi->base,
  400. (davinci_spi->pdata->wdelay
  401. << SPIFMT_WDELAY_SHIFT)
  402. & SPIFMT_WDELAY_MASK,
  403. spi->chip_select);
  404. if (davinci_spi->pdata->odd_parity)
  405. set_fmt_bits(davinci_spi->base,
  406. SPIFMT_ODD_PARITY_MASK,
  407. spi->chip_select);
  408. else
  409. clear_fmt_bits(davinci_spi->base,
  410. SPIFMT_ODD_PARITY_MASK,
  411. spi->chip_select);
  412. if (davinci_spi->pdata->parity_enable)
  413. set_fmt_bits(davinci_spi->base,
  414. SPIFMT_PARITYENA_MASK,
  415. spi->chip_select);
  416. else
  417. clear_fmt_bits(davinci_spi->base,
  418. SPIFMT_PARITYENA_MASK,
  419. spi->chip_select);
  420. if (davinci_spi->pdata->wait_enable)
  421. set_fmt_bits(davinci_spi->base,
  422. SPIFMT_WAITENA_MASK,
  423. spi->chip_select);
  424. else
  425. clear_fmt_bits(davinci_spi->base,
  426. SPIFMT_WAITENA_MASK,
  427. spi->chip_select);
  428. if (davinci_spi->pdata->timer_disable)
  429. set_fmt_bits(davinci_spi->base,
  430. SPIFMT_DISTIMER_MASK,
  431. spi->chip_select);
  432. else
  433. clear_fmt_bits(davinci_spi->base,
  434. SPIFMT_DISTIMER_MASK,
  435. spi->chip_select);
  436. }
  437. retval = davinci_spi_setup_transfer(spi, NULL);
  438. return retval;
  439. }
  440. static void davinci_spi_cleanup(struct spi_device *spi)
  441. {
  442. struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
  443. struct davinci_spi_dma *davinci_spi_dma;
  444. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  445. if (use_dma && davinci_spi->dma_channels) {
  446. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  447. if ((davinci_spi_dma->dma_rx_channel != -1)
  448. && (davinci_spi_dma->dma_tx_channel != -1)) {
  449. edma_free_channel(davinci_spi_dma->dma_tx_channel);
  450. edma_free_channel(davinci_spi_dma->dma_rx_channel);
  451. }
  452. }
  453. }
  454. static int davinci_spi_bufs_prep(struct spi_device *spi,
  455. struct davinci_spi *davinci_spi)
  456. {
  457. int op_mode = 0;
  458. /*
  459. * REVISIT unless devices disagree about SPI_LOOP or
  460. * SPI_READY (SPI_NO_CS only allows one device!), this
  461. * should not need to be done before each message...
  462. * optimize for both flags staying cleared.
  463. */
  464. op_mode = SPIPC0_DIFUN_MASK
  465. | SPIPC0_DOFUN_MASK
  466. | SPIPC0_CLKFUN_MASK;
  467. if (!(spi->mode & SPI_NO_CS))
  468. op_mode |= 1 << spi->chip_select;
  469. if (spi->mode & SPI_READY)
  470. op_mode |= SPIPC0_SPIENA_MASK;
  471. iowrite32(op_mode, davinci_spi->base + SPIPC0);
  472. if (spi->mode & SPI_LOOP)
  473. set_io_bits(davinci_spi->base + SPIGCR1,
  474. SPIGCR1_LOOPBACK_MASK);
  475. else
  476. clear_io_bits(davinci_spi->base + SPIGCR1,
  477. SPIGCR1_LOOPBACK_MASK);
  478. return 0;
  479. }
  480. static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
  481. int int_status)
  482. {
  483. struct device *sdev = davinci_spi->bitbang.master->dev.parent;
  484. if (int_status & SPIFLG_TIMEOUT_MASK) {
  485. dev_dbg(sdev, "SPI Time-out Error\n");
  486. return -ETIMEDOUT;
  487. }
  488. if (int_status & SPIFLG_DESYNC_MASK) {
  489. dev_dbg(sdev, "SPI Desynchronization Error\n");
  490. return -EIO;
  491. }
  492. if (int_status & SPIFLG_BITERR_MASK) {
  493. dev_dbg(sdev, "SPI Bit error\n");
  494. return -EIO;
  495. }
  496. if (davinci_spi->version == SPI_VERSION_2) {
  497. if (int_status & SPIFLG_DLEN_ERR_MASK) {
  498. dev_dbg(sdev, "SPI Data Length Error\n");
  499. return -EIO;
  500. }
  501. if (int_status & SPIFLG_PARERR_MASK) {
  502. dev_dbg(sdev, "SPI Parity Error\n");
  503. return -EIO;
  504. }
  505. if (int_status & SPIFLG_OVRRUN_MASK) {
  506. dev_dbg(sdev, "SPI Data Overrun error\n");
  507. return -EIO;
  508. }
  509. if (int_status & SPIFLG_TX_INTR_MASK) {
  510. dev_dbg(sdev, "SPI TX intr bit set\n");
  511. return -EIO;
  512. }
  513. if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
  514. dev_dbg(sdev, "SPI Buffer Init Active\n");
  515. return -EBUSY;
  516. }
  517. }
  518. return 0;
  519. }
  520. /**
  521. * davinci_spi_bufs - functions which will handle transfer data
  522. * @spi: spi device on which data transfer to be done
  523. * @t: spi transfer in which transfer info is filled
  524. *
  525. * This function will put data to be transferred into data register
  526. * of SPI controller and then wait until the completion will be marked
  527. * by the IRQ Handler.
  528. */
  529. static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
  530. {
  531. struct davinci_spi *davinci_spi;
  532. int int_status, count, ret;
  533. u8 conv;
  534. u32 tx_data, data1_reg_val;
  535. u32 buf_val, flg_val;
  536. struct davinci_spi_platform_data *pdata;
  537. davinci_spi = spi_master_get_devdata(spi->master);
  538. pdata = davinci_spi->pdata;
  539. davinci_spi->tx = t->tx_buf;
  540. davinci_spi->rx = t->rx_buf;
  541. /* convert len to words based on bits_per_word */
  542. conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
  543. davinci_spi->count = t->len / conv;
  544. data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
  545. INIT_COMPLETION(davinci_spi->done);
  546. ret = davinci_spi_bufs_prep(spi, davinci_spi);
  547. if (ret)
  548. return ret;
  549. /* Enable SPI */
  550. set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  551. iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
  552. (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
  553. davinci_spi->base + SPIDELAY);
  554. count = davinci_spi->count;
  555. /* Determine the command to execute READ or WRITE */
  556. if (t->tx_buf) {
  557. clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
  558. while (1) {
  559. tx_data = davinci_spi->get_tx(davinci_spi);
  560. data1_reg_val &= ~(0xFFFF);
  561. data1_reg_val |= (0xFFFF & tx_data);
  562. buf_val = ioread32(davinci_spi->base + SPIBUF);
  563. if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
  564. iowrite32(data1_reg_val,
  565. davinci_spi->base + SPIDAT1);
  566. count--;
  567. }
  568. while (ioread32(davinci_spi->base + SPIBUF)
  569. & SPIBUF_RXEMPTY_MASK)
  570. cpu_relax();
  571. /* getting the returned byte */
  572. if (t->rx_buf) {
  573. buf_val = ioread32(davinci_spi->base + SPIBUF);
  574. davinci_spi->get_rx(buf_val, davinci_spi);
  575. }
  576. if (count <= 0)
  577. break;
  578. }
  579. } else {
  580. if (pdata->poll_mode) {
  581. while (1) {
  582. /* keeps the serial clock going */
  583. if ((ioread32(davinci_spi->base + SPIBUF)
  584. & SPIBUF_TXFULL_MASK) == 0)
  585. iowrite32(data1_reg_val,
  586. davinci_spi->base + SPIDAT1);
  587. while (ioread32(davinci_spi->base + SPIBUF) &
  588. SPIBUF_RXEMPTY_MASK)
  589. cpu_relax();
  590. flg_val = ioread32(davinci_spi->base + SPIFLG);
  591. buf_val = ioread32(davinci_spi->base + SPIBUF);
  592. davinci_spi->get_rx(buf_val, davinci_spi);
  593. count--;
  594. if (count <= 0)
  595. break;
  596. }
  597. } else { /* Receive in Interrupt mode */
  598. int i;
  599. for (i = 0; i < davinci_spi->count; i++) {
  600. set_io_bits(davinci_spi->base + SPIINT,
  601. SPIINT_BITERR_INTR
  602. | SPIINT_OVRRUN_INTR
  603. | SPIINT_RX_INTR);
  604. iowrite32(data1_reg_val,
  605. davinci_spi->base + SPIDAT1);
  606. while (ioread32(davinci_spi->base + SPIINT) &
  607. SPIINT_RX_INTR)
  608. cpu_relax();
  609. }
  610. iowrite32((data1_reg_val & 0x0ffcffff),
  611. davinci_spi->base + SPIDAT1);
  612. }
  613. }
  614. /*
  615. * Check for bit error, desync error,parity error,timeout error and
  616. * receive overflow errors
  617. */
  618. int_status = ioread32(davinci_spi->base + SPIFLG);
  619. ret = davinci_spi_check_error(davinci_spi, int_status);
  620. if (ret != 0)
  621. return ret;
  622. /* SPI Framework maintains the count only in bytes so convert back */
  623. davinci_spi->count *= conv;
  624. return t->len;
  625. }
  626. #define DAVINCI_DMA_DATA_TYPE_S8 0x01
  627. #define DAVINCI_DMA_DATA_TYPE_S16 0x02
  628. #define DAVINCI_DMA_DATA_TYPE_S32 0x04
  629. static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
  630. {
  631. struct davinci_spi *davinci_spi;
  632. int int_status = 0;
  633. int count, temp_count;
  634. u8 conv = 1;
  635. u32 data1_reg_val;
  636. struct davinci_spi_dma *davinci_spi_dma;
  637. int word_len, data_type, ret;
  638. unsigned long tx_reg, rx_reg;
  639. struct davinci_spi_platform_data *pdata;
  640. struct device *sdev;
  641. davinci_spi = spi_master_get_devdata(spi->master);
  642. pdata = davinci_spi->pdata;
  643. sdev = davinci_spi->bitbang.master->dev.parent;
  644. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  645. tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
  646. rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
  647. davinci_spi->tx = t->tx_buf;
  648. davinci_spi->rx = t->rx_buf;
  649. /* convert len to words based on bits_per_word */
  650. conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
  651. davinci_spi->count = t->len / conv;
  652. data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
  653. INIT_COMPLETION(davinci_spi->done);
  654. init_completion(&davinci_spi_dma->dma_rx_completion);
  655. init_completion(&davinci_spi_dma->dma_tx_completion);
  656. word_len = conv * 8;
  657. if (word_len <= 8)
  658. data_type = DAVINCI_DMA_DATA_TYPE_S8;
  659. else if (word_len <= 16)
  660. data_type = DAVINCI_DMA_DATA_TYPE_S16;
  661. else if (word_len <= 32)
  662. data_type = DAVINCI_DMA_DATA_TYPE_S32;
  663. else
  664. return -EINVAL;
  665. ret = davinci_spi_bufs_prep(spi, davinci_spi);
  666. if (ret)
  667. return ret;
  668. /* Put delay val if required */
  669. iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
  670. (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
  671. davinci_spi->base + SPIDELAY);
  672. count = davinci_spi->count; /* the number of elements */
  673. /* disable all interrupts for dma transfers */
  674. clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
  675. /* Disable SPI to write configuration bits in SPIDAT */
  676. clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  677. /* Enable SPI */
  678. set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  679. if (t->tx_buf) {
  680. t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
  681. DMA_TO_DEVICE);
  682. if (dma_mapping_error(&spi->dev, t->tx_dma)) {
  683. dev_dbg(sdev, "Unable to DMA map a %d bytes"
  684. " TX buffer\n", count);
  685. return -ENOMEM;
  686. }
  687. temp_count = count;
  688. } else {
  689. /* We need TX clocking for RX transaction */
  690. t->tx_dma = dma_map_single(&spi->dev,
  691. (void *)davinci_spi->tmp_buf, count + 1,
  692. DMA_TO_DEVICE);
  693. if (dma_mapping_error(&spi->dev, t->tx_dma)) {
  694. dev_dbg(sdev, "Unable to DMA map a %d bytes"
  695. " TX tmp buffer\n", count);
  696. return -ENOMEM;
  697. }
  698. temp_count = count + 1;
  699. }
  700. edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
  701. data_type, temp_count, 1, 0, ASYNC);
  702. edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
  703. edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
  704. edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
  705. edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
  706. if (t->rx_buf) {
  707. /* initiate transaction */
  708. iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
  709. t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
  710. DMA_FROM_DEVICE);
  711. if (dma_mapping_error(&spi->dev, t->rx_dma)) {
  712. dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
  713. count);
  714. if (t->tx_buf != NULL)
  715. dma_unmap_single(NULL, t->tx_dma,
  716. count, DMA_TO_DEVICE);
  717. return -ENOMEM;
  718. }
  719. edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
  720. data_type, count, 1, 0, ASYNC);
  721. edma_set_src(davinci_spi_dma->dma_rx_channel,
  722. rx_reg, INCR, W8BIT);
  723. edma_set_dest(davinci_spi_dma->dma_rx_channel,
  724. t->rx_dma, INCR, W8BIT);
  725. edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
  726. edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
  727. data_type, 0);
  728. }
  729. if ((t->tx_buf) || (t->rx_buf))
  730. edma_start(davinci_spi_dma->dma_tx_channel);
  731. if (t->rx_buf)
  732. edma_start(davinci_spi_dma->dma_rx_channel);
  733. if ((t->rx_buf) || (t->tx_buf))
  734. davinci_spi_set_dma_req(spi, 1);
  735. if (t->tx_buf)
  736. wait_for_completion_interruptible(
  737. &davinci_spi_dma->dma_tx_completion);
  738. if (t->rx_buf)
  739. wait_for_completion_interruptible(
  740. &davinci_spi_dma->dma_rx_completion);
  741. dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
  742. if (t->rx_buf)
  743. dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
  744. /*
  745. * Check for bit error, desync error,parity error,timeout error and
  746. * receive overflow errors
  747. */
  748. int_status = ioread32(davinci_spi->base + SPIFLG);
  749. ret = davinci_spi_check_error(davinci_spi, int_status);
  750. if (ret != 0)
  751. return ret;
  752. /* SPI Framework maintains the count only in bytes so convert back */
  753. davinci_spi->count *= conv;
  754. return t->len;
  755. }
  756. /**
  757. * davinci_spi_irq - IRQ handler for DaVinci SPI
  758. * @irq: IRQ number for this SPI Master
  759. * @context_data: structure for SPI Master controller davinci_spi
  760. */
  761. static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
  762. {
  763. struct davinci_spi *davinci_spi = context_data;
  764. u32 int_status, rx_data = 0;
  765. irqreturn_t ret = IRQ_NONE;
  766. int_status = ioread32(davinci_spi->base + SPIFLG);
  767. while ((int_status & SPIFLG_RX_INTR_MASK)) {
  768. if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
  769. ret = IRQ_HANDLED;
  770. rx_data = ioread32(davinci_spi->base + SPIBUF);
  771. davinci_spi->get_rx(rx_data, davinci_spi);
  772. /* Disable Receive Interrupt */
  773. iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
  774. davinci_spi->base + SPIINT);
  775. } else
  776. (void)davinci_spi_check_error(davinci_spi, int_status);
  777. int_status = ioread32(davinci_spi->base + SPIFLG);
  778. }
  779. return ret;
  780. }
  781. /**
  782. * davinci_spi_probe - probe function for SPI Master Controller
  783. * @pdev: platform_device structure which contains plateform specific data
  784. */
  785. static int davinci_spi_probe(struct platform_device *pdev)
  786. {
  787. struct spi_master *master;
  788. struct davinci_spi *davinci_spi;
  789. struct davinci_spi_platform_data *pdata;
  790. struct resource *r, *mem;
  791. resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
  792. resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
  793. resource_size_t dma_eventq = SPI_NO_RESOURCE;
  794. int i = 0, ret = 0;
  795. pdata = pdev->dev.platform_data;
  796. if (pdata == NULL) {
  797. ret = -ENODEV;
  798. goto err;
  799. }
  800. master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
  801. if (master == NULL) {
  802. ret = -ENOMEM;
  803. goto err;
  804. }
  805. dev_set_drvdata(&pdev->dev, master);
  806. davinci_spi = spi_master_get_devdata(master);
  807. if (davinci_spi == NULL) {
  808. ret = -ENOENT;
  809. goto free_master;
  810. }
  811. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  812. if (r == NULL) {
  813. ret = -ENOENT;
  814. goto free_master;
  815. }
  816. davinci_spi->pbase = r->start;
  817. davinci_spi->region_size = resource_size(r);
  818. davinci_spi->pdata = pdata;
  819. mem = request_mem_region(r->start, davinci_spi->region_size,
  820. pdev->name);
  821. if (mem == NULL) {
  822. ret = -EBUSY;
  823. goto free_master;
  824. }
  825. davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
  826. if (davinci_spi->base == NULL) {
  827. ret = -ENOMEM;
  828. goto release_region;
  829. }
  830. davinci_spi->irq = platform_get_irq(pdev, 0);
  831. if (davinci_spi->irq <= 0) {
  832. ret = -EINVAL;
  833. goto unmap_io;
  834. }
  835. ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
  836. dev_name(&pdev->dev), davinci_spi);
  837. if (ret)
  838. goto unmap_io;
  839. /* Allocate tmp_buf for tx_buf */
  840. davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
  841. if (davinci_spi->tmp_buf == NULL) {
  842. ret = -ENOMEM;
  843. goto irq_free;
  844. }
  845. davinci_spi->bitbang.master = spi_master_get(master);
  846. if (davinci_spi->bitbang.master == NULL) {
  847. ret = -ENODEV;
  848. goto free_tmp_buf;
  849. }
  850. davinci_spi->clk = clk_get(&pdev->dev, NULL);
  851. if (IS_ERR(davinci_spi->clk)) {
  852. ret = -ENODEV;
  853. goto put_master;
  854. }
  855. clk_enable(davinci_spi->clk);
  856. master->bus_num = pdev->id;
  857. master->num_chipselect = pdata->num_chipselect;
  858. master->setup = davinci_spi_setup;
  859. master->cleanup = davinci_spi_cleanup;
  860. davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
  861. davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
  862. davinci_spi->version = pdata->version;
  863. use_dma = pdata->use_dma;
  864. davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
  865. if (davinci_spi->version == SPI_VERSION_2)
  866. davinci_spi->bitbang.flags |= SPI_READY;
  867. if (use_dma) {
  868. r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  869. if (r)
  870. dma_rx_chan = r->start;
  871. r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  872. if (r)
  873. dma_tx_chan = r->start;
  874. r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
  875. if (r)
  876. dma_eventq = r->start;
  877. }
  878. if (!use_dma ||
  879. dma_rx_chan == SPI_NO_RESOURCE ||
  880. dma_tx_chan == SPI_NO_RESOURCE ||
  881. dma_eventq == SPI_NO_RESOURCE) {
  882. davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
  883. use_dma = 0;
  884. } else {
  885. davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
  886. davinci_spi->dma_channels = kzalloc(master->num_chipselect
  887. * sizeof(struct davinci_spi_dma), GFP_KERNEL);
  888. if (davinci_spi->dma_channels == NULL) {
  889. ret = -ENOMEM;
  890. goto free_clk;
  891. }
  892. for (i = 0; i < master->num_chipselect; i++) {
  893. davinci_spi->dma_channels[i].dma_rx_channel = -1;
  894. davinci_spi->dma_channels[i].dma_rx_sync_dev =
  895. dma_rx_chan;
  896. davinci_spi->dma_channels[i].dma_tx_channel = -1;
  897. davinci_spi->dma_channels[i].dma_tx_sync_dev =
  898. dma_tx_chan;
  899. davinci_spi->dma_channels[i].eventq = dma_eventq;
  900. }
  901. dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
  902. "Using RX channel = %d , TX channel = %d and "
  903. "event queue = %d", dma_rx_chan, dma_tx_chan,
  904. dma_eventq);
  905. }
  906. davinci_spi->get_rx = davinci_spi_rx_buf_u8;
  907. davinci_spi->get_tx = davinci_spi_tx_buf_u8;
  908. init_completion(&davinci_spi->done);
  909. /* Reset In/OUT SPI module */
  910. iowrite32(0, davinci_spi->base + SPIGCR0);
  911. udelay(100);
  912. iowrite32(1, davinci_spi->base + SPIGCR0);
  913. /* Clock internal */
  914. if (davinci_spi->pdata->clk_internal)
  915. set_io_bits(davinci_spi->base + SPIGCR1,
  916. SPIGCR1_CLKMOD_MASK);
  917. else
  918. clear_io_bits(davinci_spi->base + SPIGCR1,
  919. SPIGCR1_CLKMOD_MASK);
  920. iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
  921. /* master mode default */
  922. set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
  923. if (davinci_spi->pdata->intr_level)
  924. iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
  925. else
  926. iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
  927. ret = spi_bitbang_start(&davinci_spi->bitbang);
  928. if (ret)
  929. goto free_clk;
  930. dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
  931. if (!pdata->poll_mode)
  932. dev_info(&pdev->dev, "Operating in interrupt mode"
  933. " using IRQ %d\n", davinci_spi->irq);
  934. return ret;
  935. free_clk:
  936. clk_disable(davinci_spi->clk);
  937. clk_put(davinci_spi->clk);
  938. put_master:
  939. spi_master_put(master);
  940. free_tmp_buf:
  941. kfree(davinci_spi->tmp_buf);
  942. irq_free:
  943. free_irq(davinci_spi->irq, davinci_spi);
  944. unmap_io:
  945. iounmap(davinci_spi->base);
  946. release_region:
  947. release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
  948. free_master:
  949. kfree(master);
  950. err:
  951. return ret;
  952. }
  953. /**
  954. * davinci_spi_remove - remove function for SPI Master Controller
  955. * @pdev: platform_device structure which contains plateform specific data
  956. *
  957. * This function will do the reverse action of davinci_spi_probe function
  958. * It will free the IRQ and SPI controller's memory region.
  959. * It will also call spi_bitbang_stop to destroy the work queue which was
  960. * created by spi_bitbang_start.
  961. */
  962. static int __exit davinci_spi_remove(struct platform_device *pdev)
  963. {
  964. struct davinci_spi *davinci_spi;
  965. struct spi_master *master;
  966. master = dev_get_drvdata(&pdev->dev);
  967. davinci_spi = spi_master_get_devdata(master);
  968. spi_bitbang_stop(&davinci_spi->bitbang);
  969. clk_disable(davinci_spi->clk);
  970. clk_put(davinci_spi->clk);
  971. spi_master_put(master);
  972. kfree(davinci_spi->tmp_buf);
  973. free_irq(davinci_spi->irq, davinci_spi);
  974. iounmap(davinci_spi->base);
  975. release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
  976. return 0;
  977. }
  978. static struct platform_driver davinci_spi_driver = {
  979. .driver.name = "spi_davinci",
  980. .remove = __exit_p(davinci_spi_remove),
  981. };
  982. static int __init davinci_spi_init(void)
  983. {
  984. return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
  985. }
  986. module_init(davinci_spi_init);
  987. static void __exit davinci_spi_exit(void)
  988. {
  989. platform_driver_unregister(&davinci_spi_driver);
  990. }
  991. module_exit(davinci_spi_exit);
  992. MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
  993. MODULE_LICENSE("GPL");