netxen_nic_init.c 38 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include "netxen_nic.h"
  28. #include "netxen_nic_hw.h"
  29. struct crb_addr_pair {
  30. u32 addr;
  31. u32 data;
  32. };
  33. #define NETXEN_MAX_CRB_XFORM 60
  34. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  35. #define NETXEN_ADDR_ERROR (0xffffffff)
  36. #define crb_addr_transform(name) \
  37. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  38. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  39. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  40. static void
  41. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  42. struct nx_host_rds_ring *rds_ring);
  43. static void crb_addr_transform_setup(void)
  44. {
  45. crb_addr_transform(XDMA);
  46. crb_addr_transform(TIMR);
  47. crb_addr_transform(SRE);
  48. crb_addr_transform(SQN3);
  49. crb_addr_transform(SQN2);
  50. crb_addr_transform(SQN1);
  51. crb_addr_transform(SQN0);
  52. crb_addr_transform(SQS3);
  53. crb_addr_transform(SQS2);
  54. crb_addr_transform(SQS1);
  55. crb_addr_transform(SQS0);
  56. crb_addr_transform(RPMX7);
  57. crb_addr_transform(RPMX6);
  58. crb_addr_transform(RPMX5);
  59. crb_addr_transform(RPMX4);
  60. crb_addr_transform(RPMX3);
  61. crb_addr_transform(RPMX2);
  62. crb_addr_transform(RPMX1);
  63. crb_addr_transform(RPMX0);
  64. crb_addr_transform(ROMUSB);
  65. crb_addr_transform(SN);
  66. crb_addr_transform(QMN);
  67. crb_addr_transform(QMS);
  68. crb_addr_transform(PGNI);
  69. crb_addr_transform(PGND);
  70. crb_addr_transform(PGN3);
  71. crb_addr_transform(PGN2);
  72. crb_addr_transform(PGN1);
  73. crb_addr_transform(PGN0);
  74. crb_addr_transform(PGSI);
  75. crb_addr_transform(PGSD);
  76. crb_addr_transform(PGS3);
  77. crb_addr_transform(PGS2);
  78. crb_addr_transform(PGS1);
  79. crb_addr_transform(PGS0);
  80. crb_addr_transform(PS);
  81. crb_addr_transform(PH);
  82. crb_addr_transform(NIU);
  83. crb_addr_transform(I2Q);
  84. crb_addr_transform(EG);
  85. crb_addr_transform(MN);
  86. crb_addr_transform(MS);
  87. crb_addr_transform(CAS2);
  88. crb_addr_transform(CAS1);
  89. crb_addr_transform(CAS0);
  90. crb_addr_transform(CAM);
  91. crb_addr_transform(C2C1);
  92. crb_addr_transform(C2C0);
  93. crb_addr_transform(SMB);
  94. crb_addr_transform(OCM0);
  95. crb_addr_transform(I2C0);
  96. }
  97. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  98. {
  99. struct netxen_recv_context *recv_ctx;
  100. struct nx_host_rds_ring *rds_ring;
  101. struct netxen_rx_buffer *rx_buf;
  102. int i, ring;
  103. recv_ctx = &adapter->recv_ctx;
  104. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  105. rds_ring = &recv_ctx->rds_rings[ring];
  106. for (i = 0; i < rds_ring->num_desc; ++i) {
  107. rx_buf = &(rds_ring->rx_buf_arr[i]);
  108. if (rx_buf->state == NETXEN_BUFFER_FREE)
  109. continue;
  110. pci_unmap_single(adapter->pdev,
  111. rx_buf->dma,
  112. rds_ring->dma_size,
  113. PCI_DMA_FROMDEVICE);
  114. if (rx_buf->skb != NULL)
  115. dev_kfree_skb_any(rx_buf->skb);
  116. }
  117. }
  118. }
  119. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  120. {
  121. struct netxen_cmd_buffer *cmd_buf;
  122. struct netxen_skb_frag *buffrag;
  123. int i, j;
  124. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  125. cmd_buf = tx_ring->cmd_buf_arr;
  126. for (i = 0; i < tx_ring->num_desc; i++) {
  127. buffrag = cmd_buf->frag_array;
  128. if (buffrag->dma) {
  129. pci_unmap_single(adapter->pdev, buffrag->dma,
  130. buffrag->length, PCI_DMA_TODEVICE);
  131. buffrag->dma = 0ULL;
  132. }
  133. for (j = 0; j < cmd_buf->frag_count; j++) {
  134. buffrag++;
  135. if (buffrag->dma) {
  136. pci_unmap_page(adapter->pdev, buffrag->dma,
  137. buffrag->length,
  138. PCI_DMA_TODEVICE);
  139. buffrag->dma = 0ULL;
  140. }
  141. }
  142. if (cmd_buf->skb) {
  143. dev_kfree_skb_any(cmd_buf->skb);
  144. cmd_buf->skb = NULL;
  145. }
  146. cmd_buf++;
  147. }
  148. }
  149. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  150. {
  151. struct netxen_recv_context *recv_ctx;
  152. struct nx_host_rds_ring *rds_ring;
  153. struct nx_host_tx_ring *tx_ring;
  154. int ring;
  155. recv_ctx = &adapter->recv_ctx;
  156. if (recv_ctx->rds_rings == NULL)
  157. goto skip_rds;
  158. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  159. rds_ring = &recv_ctx->rds_rings[ring];
  160. vfree(rds_ring->rx_buf_arr);
  161. rds_ring->rx_buf_arr = NULL;
  162. }
  163. kfree(recv_ctx->rds_rings);
  164. skip_rds:
  165. if (adapter->tx_ring == NULL)
  166. return;
  167. tx_ring = adapter->tx_ring;
  168. vfree(tx_ring->cmd_buf_arr);
  169. }
  170. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  171. {
  172. struct netxen_recv_context *recv_ctx;
  173. struct nx_host_rds_ring *rds_ring;
  174. struct nx_host_sds_ring *sds_ring;
  175. struct nx_host_tx_ring *tx_ring;
  176. struct netxen_rx_buffer *rx_buf;
  177. int ring, i, size;
  178. struct netxen_cmd_buffer *cmd_buf_arr;
  179. struct net_device *netdev = adapter->netdev;
  180. struct pci_dev *pdev = adapter->pdev;
  181. size = sizeof(struct nx_host_tx_ring);
  182. tx_ring = kzalloc(size, GFP_KERNEL);
  183. if (tx_ring == NULL) {
  184. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  185. netdev->name);
  186. return -ENOMEM;
  187. }
  188. adapter->tx_ring = tx_ring;
  189. tx_ring->num_desc = adapter->num_txd;
  190. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  191. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  192. if (cmd_buf_arr == NULL) {
  193. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  194. netdev->name);
  195. return -ENOMEM;
  196. }
  197. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  198. tx_ring->cmd_buf_arr = cmd_buf_arr;
  199. recv_ctx = &adapter->recv_ctx;
  200. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  201. rds_ring = kzalloc(size, GFP_KERNEL);
  202. if (rds_ring == NULL) {
  203. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  204. netdev->name);
  205. return -ENOMEM;
  206. }
  207. recv_ctx->rds_rings = rds_ring;
  208. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  209. rds_ring = &recv_ctx->rds_rings[ring];
  210. switch (ring) {
  211. case RCV_RING_NORMAL:
  212. rds_ring->num_desc = adapter->num_rxd;
  213. if (adapter->ahw.cut_through) {
  214. rds_ring->dma_size =
  215. NX_CT_DEFAULT_RX_BUF_LEN;
  216. rds_ring->skb_size =
  217. NX_CT_DEFAULT_RX_BUF_LEN;
  218. } else {
  219. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  220. rds_ring->dma_size =
  221. NX_P3_RX_BUF_MAX_LEN;
  222. else
  223. rds_ring->dma_size =
  224. NX_P2_RX_BUF_MAX_LEN;
  225. rds_ring->skb_size =
  226. rds_ring->dma_size + NET_IP_ALIGN;
  227. }
  228. break;
  229. case RCV_RING_JUMBO:
  230. rds_ring->num_desc = adapter->num_jumbo_rxd;
  231. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  232. rds_ring->dma_size =
  233. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  234. else
  235. rds_ring->dma_size =
  236. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  237. if (adapter->capabilities & NX_CAP0_HW_LRO)
  238. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  239. rds_ring->skb_size =
  240. rds_ring->dma_size + NET_IP_ALIGN;
  241. break;
  242. case RCV_RING_LRO:
  243. rds_ring->num_desc = adapter->num_lro_rxd;
  244. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  245. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  246. break;
  247. }
  248. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  249. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  250. if (rds_ring->rx_buf_arr == NULL) {
  251. printk(KERN_ERR "%s: Failed to allocate "
  252. "rx buffer ring %d\n",
  253. netdev->name, ring);
  254. /* free whatever was already allocated */
  255. goto err_out;
  256. }
  257. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  258. INIT_LIST_HEAD(&rds_ring->free_list);
  259. /*
  260. * Now go through all of them, set reference handles
  261. * and put them in the queues.
  262. */
  263. rx_buf = rds_ring->rx_buf_arr;
  264. for (i = 0; i < rds_ring->num_desc; i++) {
  265. list_add_tail(&rx_buf->list,
  266. &rds_ring->free_list);
  267. rx_buf->ref_handle = i;
  268. rx_buf->state = NETXEN_BUFFER_FREE;
  269. rx_buf++;
  270. }
  271. spin_lock_init(&rds_ring->lock);
  272. }
  273. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  274. sds_ring = &recv_ctx->sds_rings[ring];
  275. sds_ring->irq = adapter->msix_entries[ring].vector;
  276. sds_ring->adapter = adapter;
  277. sds_ring->num_desc = adapter->num_rxd;
  278. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  279. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  280. }
  281. return 0;
  282. err_out:
  283. netxen_free_sw_resources(adapter);
  284. return -ENOMEM;
  285. }
  286. /*
  287. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  288. * address to external PCI CRB address.
  289. */
  290. static u32 netxen_decode_crb_addr(u32 addr)
  291. {
  292. int i;
  293. u32 base_addr, offset, pci_base;
  294. crb_addr_transform_setup();
  295. pci_base = NETXEN_ADDR_ERROR;
  296. base_addr = addr & 0xfff00000;
  297. offset = addr & 0x000fffff;
  298. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  299. if (crb_addr_xform[i] == base_addr) {
  300. pci_base = i << 20;
  301. break;
  302. }
  303. }
  304. if (pci_base == NETXEN_ADDR_ERROR)
  305. return pci_base;
  306. else
  307. return (pci_base + offset);
  308. }
  309. #define NETXEN_MAX_ROM_WAIT_USEC 100
  310. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  311. {
  312. long timeout = 0;
  313. long done = 0;
  314. cond_resched();
  315. while (done == 0) {
  316. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  317. done &= 2;
  318. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  319. dev_err(&adapter->pdev->dev,
  320. "Timeout reached waiting for rom done");
  321. return -EIO;
  322. }
  323. udelay(1);
  324. }
  325. return 0;
  326. }
  327. static int do_rom_fast_read(struct netxen_adapter *adapter,
  328. int addr, int *valp)
  329. {
  330. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  331. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  332. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  334. if (netxen_wait_rom_done(adapter)) {
  335. printk("Error waiting for rom done\n");
  336. return -EIO;
  337. }
  338. /* reset abyte_cnt and dummy_byte_cnt */
  339. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  340. udelay(10);
  341. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  342. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  343. return 0;
  344. }
  345. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  346. u8 *bytes, size_t size)
  347. {
  348. int addridx;
  349. int ret = 0;
  350. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  351. int v;
  352. ret = do_rom_fast_read(adapter, addridx, &v);
  353. if (ret != 0)
  354. break;
  355. *(__le32 *)bytes = cpu_to_le32(v);
  356. bytes += 4;
  357. }
  358. return ret;
  359. }
  360. int
  361. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  362. u8 *bytes, size_t size)
  363. {
  364. int ret;
  365. ret = netxen_rom_lock(adapter);
  366. if (ret < 0)
  367. return ret;
  368. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  369. netxen_rom_unlock(adapter);
  370. return ret;
  371. }
  372. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  373. {
  374. int ret;
  375. if (netxen_rom_lock(adapter) != 0)
  376. return -EIO;
  377. ret = do_rom_fast_read(adapter, addr, valp);
  378. netxen_rom_unlock(adapter);
  379. return ret;
  380. }
  381. #define NETXEN_BOARDTYPE 0x4008
  382. #define NETXEN_BOARDNUM 0x400c
  383. #define NETXEN_CHIPNUM 0x4010
  384. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  385. {
  386. int addr, val;
  387. int i, n, init_delay = 0;
  388. struct crb_addr_pair *buf;
  389. unsigned offset;
  390. u32 off;
  391. /* resetall */
  392. netxen_rom_lock(adapter);
  393. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  394. netxen_rom_unlock(adapter);
  395. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  396. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  397. (n != 0xcafecafe) ||
  398. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  399. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  400. "n: %08x\n", netxen_nic_driver_name, n);
  401. return -EIO;
  402. }
  403. offset = n & 0xffffU;
  404. n = (n >> 16) & 0xffffU;
  405. } else {
  406. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  407. !(n & 0x80000000)) {
  408. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  409. "n: %08x\n", netxen_nic_driver_name, n);
  410. return -EIO;
  411. }
  412. offset = 1;
  413. n &= ~0x80000000;
  414. }
  415. if (n >= 1024) {
  416. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  417. " initialized.\n", __func__, n);
  418. return -EIO;
  419. }
  420. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  421. if (buf == NULL) {
  422. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  423. netxen_nic_driver_name);
  424. return -ENOMEM;
  425. }
  426. for (i = 0; i < n; i++) {
  427. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  428. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  429. kfree(buf);
  430. return -EIO;
  431. }
  432. buf[i].addr = addr;
  433. buf[i].data = val;
  434. }
  435. for (i = 0; i < n; i++) {
  436. off = netxen_decode_crb_addr(buf[i].addr);
  437. if (off == NETXEN_ADDR_ERROR) {
  438. printk(KERN_ERR"CRB init value out of range %x\n",
  439. buf[i].addr);
  440. continue;
  441. }
  442. off += NETXEN_PCI_CRBSPACE;
  443. if (off & 1)
  444. continue;
  445. /* skipping cold reboot MAGIC */
  446. if (off == NETXEN_CAM_RAM(0x1fc))
  447. continue;
  448. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  449. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  450. continue;
  451. /* do not reset PCI */
  452. if (off == (ROMUSB_GLB + 0xbc))
  453. continue;
  454. if (off == (ROMUSB_GLB + 0xa8))
  455. continue;
  456. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  457. continue;
  458. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  459. continue;
  460. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  461. continue;
  462. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  463. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  464. buf[i].data = 0x1020;
  465. /* skip the function enable register */
  466. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  467. continue;
  468. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  469. continue;
  470. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  471. continue;
  472. }
  473. init_delay = 1;
  474. /* After writing this register, HW needs time for CRB */
  475. /* to quiet down (else crb_window returns 0xffffffff) */
  476. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  477. init_delay = 1000;
  478. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  479. /* hold xdma in reset also */
  480. buf[i].data = NETXEN_NIC_XDMA_RESET;
  481. buf[i].data = 0x8000ff;
  482. }
  483. }
  484. NXWR32(adapter, off, buf[i].data);
  485. msleep(init_delay);
  486. }
  487. kfree(buf);
  488. /* disable_peg_cache_all */
  489. /* unreset_net_cache */
  490. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  491. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  492. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  493. }
  494. /* p2dn replyCount */
  495. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  496. /* disable_peg_cache 0 */
  497. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  498. /* disable_peg_cache 1 */
  499. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  500. /* peg_clr_all */
  501. /* peg_clr 0 */
  502. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  503. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  504. /* peg_clr 1 */
  505. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  506. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  507. /* peg_clr 2 */
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  509. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  510. /* peg_clr 3 */
  511. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  512. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  513. return 0;
  514. }
  515. int
  516. netxen_need_fw_reset(struct netxen_adapter *adapter)
  517. {
  518. u32 count, old_count;
  519. u32 val, version, major, minor, build;
  520. int i, timeout;
  521. u8 fw_type;
  522. /* NX2031 firmware doesn't support heartbit */
  523. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  524. return 1;
  525. /* last attempt had failed */
  526. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  527. return 1;
  528. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  529. for (i = 0; i < 10; i++) {
  530. timeout = msleep_interruptible(200);
  531. if (timeout) {
  532. NXWR32(adapter, CRB_CMDPEG_STATE,
  533. PHAN_INITIALIZE_FAILED);
  534. return -EINTR;
  535. }
  536. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  537. if (count != old_count)
  538. break;
  539. }
  540. /* firmware is dead */
  541. if (count == old_count)
  542. return 1;
  543. /* check if we have got newer or different file firmware */
  544. if (adapter->fw) {
  545. const struct firmware *fw = adapter->fw;
  546. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  547. version = NETXEN_DECODE_VERSION(val);
  548. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  549. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  550. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  551. if (version > NETXEN_VERSION_CODE(major, minor, build))
  552. return 1;
  553. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  554. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  555. fw_type = (val & 0x4) ?
  556. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  557. if (adapter->fw_type != fw_type)
  558. return 1;
  559. }
  560. }
  561. return 0;
  562. }
  563. static char *fw_name[] = {
  564. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  565. };
  566. int
  567. netxen_load_firmware(struct netxen_adapter *adapter)
  568. {
  569. u64 *ptr64;
  570. u32 i, flashaddr, size;
  571. const struct firmware *fw = adapter->fw;
  572. struct pci_dev *pdev = adapter->pdev;
  573. dev_info(&pdev->dev, "loading firmware from %s\n",
  574. fw_name[adapter->fw_type]);
  575. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  576. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  577. if (fw) {
  578. __le64 data;
  579. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  580. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  581. flashaddr = NETXEN_BOOTLD_START;
  582. for (i = 0; i < size; i++) {
  583. data = cpu_to_le64(ptr64[i]);
  584. if (adapter->pci_mem_write(adapter,
  585. flashaddr, data))
  586. return -EIO;
  587. flashaddr += 8;
  588. }
  589. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  590. size = (__force u32)cpu_to_le32(size) / 8;
  591. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  592. flashaddr = NETXEN_IMAGE_START;
  593. for (i = 0; i < size; i++) {
  594. data = cpu_to_le64(ptr64[i]);
  595. if (adapter->pci_mem_write(adapter,
  596. flashaddr, data))
  597. return -EIO;
  598. flashaddr += 8;
  599. }
  600. } else {
  601. u64 data;
  602. u32 hi, lo;
  603. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  604. flashaddr = NETXEN_BOOTLD_START;
  605. for (i = 0; i < size; i++) {
  606. if (netxen_rom_fast_read(adapter,
  607. flashaddr, (int *)&lo) != 0)
  608. return -EIO;
  609. if (netxen_rom_fast_read(adapter,
  610. flashaddr + 4, (int *)&hi) != 0)
  611. return -EIO;
  612. /* hi, lo are already in host endian byteorder */
  613. data = (((u64)hi << 32) | lo);
  614. if (adapter->pci_mem_write(adapter,
  615. flashaddr, data))
  616. return -EIO;
  617. flashaddr += 8;
  618. }
  619. }
  620. msleep(1);
  621. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  622. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  623. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  624. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  625. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  626. else {
  627. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  628. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  629. }
  630. return 0;
  631. }
  632. static int
  633. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  634. {
  635. __le32 val;
  636. u32 ver, min_ver, bios;
  637. struct pci_dev *pdev = adapter->pdev;
  638. const struct firmware *fw = adapter->fw;
  639. if (fw->size < NX_FW_MIN_SIZE)
  640. return -EINVAL;
  641. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  642. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  643. return -EINVAL;
  644. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  645. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  646. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  647. else
  648. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  649. ver = NETXEN_DECODE_VERSION(val);
  650. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  651. dev_err(&pdev->dev,
  652. "%s: firmware version %d.%d.%d unsupported\n",
  653. fwname, _major(ver), _minor(ver), _build(ver));
  654. return -EINVAL;
  655. }
  656. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  657. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  658. if ((__force u32)val != bios) {
  659. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  660. fwname);
  661. return -EINVAL;
  662. }
  663. /* check if flashed firmware is newer */
  664. if (netxen_rom_fast_read(adapter,
  665. NX_FW_VERSION_OFFSET, (int *)&val))
  666. return -EIO;
  667. val = NETXEN_DECODE_VERSION(val);
  668. if (val > ver) {
  669. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  670. fwname);
  671. return -EINVAL;
  672. }
  673. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  674. return 0;
  675. }
  676. static int
  677. netxen_p3_has_mn(struct netxen_adapter *adapter)
  678. {
  679. u32 capability, flashed_ver;
  680. capability = 0;
  681. netxen_rom_fast_read(adapter,
  682. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  683. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  684. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  685. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  686. if (capability & NX_PEG_TUNE_MN_PRESENT)
  687. return 1;
  688. }
  689. return 0;
  690. }
  691. void netxen_request_firmware(struct netxen_adapter *adapter)
  692. {
  693. u8 fw_type;
  694. struct pci_dev *pdev = adapter->pdev;
  695. int rc = 0;
  696. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  697. fw_type = NX_P2_MN_ROMIMAGE;
  698. goto request_fw;
  699. }
  700. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  701. /* No file firmware for the time being */
  702. fw_type = NX_FLASH_ROMIMAGE;
  703. goto done;
  704. }
  705. fw_type = netxen_p3_has_mn(adapter) ?
  706. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  707. request_fw:
  708. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  709. if (rc != 0) {
  710. if (fw_type == NX_P3_MN_ROMIMAGE) {
  711. msleep(1);
  712. fw_type = NX_P3_CT_ROMIMAGE;
  713. goto request_fw;
  714. }
  715. fw_type = NX_FLASH_ROMIMAGE;
  716. adapter->fw = NULL;
  717. goto done;
  718. }
  719. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  720. if (rc != 0) {
  721. release_firmware(adapter->fw);
  722. if (fw_type == NX_P3_MN_ROMIMAGE) {
  723. msleep(1);
  724. fw_type = NX_P3_CT_ROMIMAGE;
  725. goto request_fw;
  726. }
  727. fw_type = NX_FLASH_ROMIMAGE;
  728. adapter->fw = NULL;
  729. goto done;
  730. }
  731. done:
  732. adapter->fw_type = fw_type;
  733. }
  734. void
  735. netxen_release_firmware(struct netxen_adapter *adapter)
  736. {
  737. if (adapter->fw)
  738. release_firmware(adapter->fw);
  739. adapter->fw = NULL;
  740. }
  741. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  742. {
  743. u64 addr;
  744. u32 hi, lo;
  745. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  746. return 0;
  747. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  748. NETXEN_HOST_DUMMY_DMA_SIZE,
  749. &adapter->dummy_dma.phys_addr);
  750. if (adapter->dummy_dma.addr == NULL) {
  751. dev_err(&adapter->pdev->dev,
  752. "ERROR: Could not allocate dummy DMA memory\n");
  753. return -ENOMEM;
  754. }
  755. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  756. hi = (addr >> 32) & 0xffffffff;
  757. lo = addr & 0xffffffff;
  758. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  759. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  760. return 0;
  761. }
  762. /*
  763. * NetXen DMA watchdog control:
  764. *
  765. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  766. * Bit 1 : disable_request => 1 req disable dma watchdog
  767. * Bit 2 : enable_request => 1 req enable dma watchdog
  768. * Bit 3-31 : unused
  769. */
  770. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  771. {
  772. int i = 100;
  773. u32 ctrl;
  774. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  775. return;
  776. if (!adapter->dummy_dma.addr)
  777. return;
  778. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  779. if ((ctrl & 0x1) != 0) {
  780. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  781. while ((ctrl & 0x1) != 0) {
  782. msleep(50);
  783. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  784. if (--i == 0)
  785. break;
  786. };
  787. }
  788. if (i) {
  789. pci_free_consistent(adapter->pdev,
  790. NETXEN_HOST_DUMMY_DMA_SIZE,
  791. adapter->dummy_dma.addr,
  792. adapter->dummy_dma.phys_addr);
  793. adapter->dummy_dma.addr = NULL;
  794. } else
  795. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  796. }
  797. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  798. {
  799. u32 val = 0;
  800. int retries = 60;
  801. if (pegtune_val)
  802. return 0;
  803. do {
  804. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  805. switch (val) {
  806. case PHAN_INITIALIZE_COMPLETE:
  807. case PHAN_INITIALIZE_ACK:
  808. return 0;
  809. case PHAN_INITIALIZE_FAILED:
  810. goto out_err;
  811. default:
  812. break;
  813. }
  814. msleep(500);
  815. } while (--retries);
  816. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  817. out_err:
  818. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  819. return -EIO;
  820. }
  821. static int
  822. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  823. {
  824. u32 val = 0;
  825. int retries = 2000;
  826. do {
  827. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  828. if (val == PHAN_PEG_RCV_INITIALIZED)
  829. return 0;
  830. msleep(10);
  831. } while (--retries);
  832. if (!retries) {
  833. printk(KERN_ERR "Receive Peg initialization not "
  834. "complete, state: 0x%x.\n", val);
  835. return -EIO;
  836. }
  837. return 0;
  838. }
  839. int netxen_init_firmware(struct netxen_adapter *adapter)
  840. {
  841. int err;
  842. err = netxen_receive_peg_ready(adapter);
  843. if (err)
  844. return err;
  845. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  846. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  847. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  848. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  849. return err;
  850. }
  851. static void
  852. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  853. {
  854. u32 cable_OUI;
  855. u16 cable_len;
  856. u16 link_speed;
  857. u8 link_status, module, duplex, autoneg;
  858. struct net_device *netdev = adapter->netdev;
  859. adapter->has_link_events = 1;
  860. cable_OUI = msg->body[1] & 0xffffffff;
  861. cable_len = (msg->body[1] >> 32) & 0xffff;
  862. link_speed = (msg->body[1] >> 48) & 0xffff;
  863. link_status = msg->body[2] & 0xff;
  864. duplex = (msg->body[2] >> 16) & 0xff;
  865. autoneg = (msg->body[2] >> 24) & 0xff;
  866. module = (msg->body[2] >> 8) & 0xff;
  867. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  868. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  869. netdev->name, cable_OUI, cable_len);
  870. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  871. printk(KERN_INFO "%s: unsupported cable length %d\n",
  872. netdev->name, cable_len);
  873. }
  874. netxen_advert_link_change(adapter, link_status);
  875. /* update link parameters */
  876. if (duplex == LINKEVENT_FULL_DUPLEX)
  877. adapter->link_duplex = DUPLEX_FULL;
  878. else
  879. adapter->link_duplex = DUPLEX_HALF;
  880. adapter->module_type = module;
  881. adapter->link_autoneg = autoneg;
  882. adapter->link_speed = link_speed;
  883. }
  884. static void
  885. netxen_handle_fw_message(int desc_cnt, int index,
  886. struct nx_host_sds_ring *sds_ring)
  887. {
  888. nx_fw_msg_t msg;
  889. struct status_desc *desc;
  890. int i = 0, opcode;
  891. while (desc_cnt > 0 && i < 8) {
  892. desc = &sds_ring->desc_head[index];
  893. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  894. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  895. index = get_next_index(index, sds_ring->num_desc);
  896. desc_cnt--;
  897. }
  898. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  899. switch (opcode) {
  900. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  901. netxen_handle_linkevent(sds_ring->adapter, &msg);
  902. break;
  903. default:
  904. break;
  905. }
  906. }
  907. static int
  908. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  909. struct nx_host_rds_ring *rds_ring,
  910. struct netxen_rx_buffer *buffer)
  911. {
  912. struct sk_buff *skb;
  913. dma_addr_t dma;
  914. struct pci_dev *pdev = adapter->pdev;
  915. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  916. if (!buffer->skb)
  917. return 1;
  918. skb = buffer->skb;
  919. if (!adapter->ahw.cut_through)
  920. skb_reserve(skb, 2);
  921. dma = pci_map_single(pdev, skb->data,
  922. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  923. if (pci_dma_mapping_error(pdev, dma)) {
  924. dev_kfree_skb_any(skb);
  925. buffer->skb = NULL;
  926. return 1;
  927. }
  928. buffer->skb = skb;
  929. buffer->dma = dma;
  930. buffer->state = NETXEN_BUFFER_BUSY;
  931. return 0;
  932. }
  933. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  934. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  935. {
  936. struct netxen_rx_buffer *buffer;
  937. struct sk_buff *skb;
  938. buffer = &rds_ring->rx_buf_arr[index];
  939. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  940. PCI_DMA_FROMDEVICE);
  941. skb = buffer->skb;
  942. if (!skb)
  943. goto no_skb;
  944. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  945. adapter->stats.csummed++;
  946. skb->ip_summed = CHECKSUM_UNNECESSARY;
  947. } else
  948. skb->ip_summed = CHECKSUM_NONE;
  949. skb->dev = adapter->netdev;
  950. buffer->skb = NULL;
  951. no_skb:
  952. buffer->state = NETXEN_BUFFER_FREE;
  953. return skb;
  954. }
  955. static struct netxen_rx_buffer *
  956. netxen_process_rcv(struct netxen_adapter *adapter,
  957. struct nx_host_sds_ring *sds_ring,
  958. int ring, u64 sts_data0)
  959. {
  960. struct net_device *netdev = adapter->netdev;
  961. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  962. struct netxen_rx_buffer *buffer;
  963. struct sk_buff *skb;
  964. struct nx_host_rds_ring *rds_ring;
  965. int index, length, cksum, pkt_offset;
  966. if (unlikely(ring >= adapter->max_rds_rings))
  967. return NULL;
  968. rds_ring = &recv_ctx->rds_rings[ring];
  969. index = netxen_get_sts_refhandle(sts_data0);
  970. if (unlikely(index >= rds_ring->num_desc))
  971. return NULL;
  972. buffer = &rds_ring->rx_buf_arr[index];
  973. length = netxen_get_sts_totallength(sts_data0);
  974. cksum = netxen_get_sts_status(sts_data0);
  975. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  976. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  977. if (!skb)
  978. return buffer;
  979. if (length > rds_ring->skb_size)
  980. skb_put(skb, rds_ring->skb_size);
  981. else
  982. skb_put(skb, length);
  983. if (pkt_offset)
  984. skb_pull(skb, pkt_offset);
  985. skb->truesize = skb->len + sizeof(struct sk_buff);
  986. skb->protocol = eth_type_trans(skb, netdev);
  987. napi_gro_receive(&sds_ring->napi, skb);
  988. adapter->stats.rx_pkts++;
  989. adapter->stats.rxbytes += length;
  990. return buffer;
  991. }
  992. #define TCP_HDR_SIZE 20
  993. #define TCP_TS_OPTION_SIZE 12
  994. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  995. static struct netxen_rx_buffer *
  996. netxen_process_lro(struct netxen_adapter *adapter,
  997. struct nx_host_sds_ring *sds_ring,
  998. int ring, u64 sts_data0, u64 sts_data1)
  999. {
  1000. struct net_device *netdev = adapter->netdev;
  1001. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1002. struct netxen_rx_buffer *buffer;
  1003. struct sk_buff *skb;
  1004. struct nx_host_rds_ring *rds_ring;
  1005. struct iphdr *iph;
  1006. struct tcphdr *th;
  1007. bool push, timestamp;
  1008. int l2_hdr_offset, l4_hdr_offset;
  1009. int index;
  1010. u16 lro_length, length, data_offset;
  1011. u32 seq_number;
  1012. if (unlikely(ring > adapter->max_rds_rings))
  1013. return NULL;
  1014. rds_ring = &recv_ctx->rds_rings[ring];
  1015. index = netxen_get_lro_sts_refhandle(sts_data0);
  1016. if (unlikely(index > rds_ring->num_desc))
  1017. return NULL;
  1018. buffer = &rds_ring->rx_buf_arr[index];
  1019. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1020. lro_length = netxen_get_lro_sts_length(sts_data0);
  1021. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1022. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1023. push = netxen_get_lro_sts_push_flag(sts_data0);
  1024. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1025. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1026. if (!skb)
  1027. return buffer;
  1028. if (timestamp)
  1029. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1030. else
  1031. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1032. skb_put(skb, lro_length + data_offset);
  1033. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1034. skb_pull(skb, l2_hdr_offset);
  1035. skb->protocol = eth_type_trans(skb, netdev);
  1036. iph = (struct iphdr *)skb->data;
  1037. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1038. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1039. iph->tot_len = htons(length);
  1040. iph->check = 0;
  1041. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1042. th->psh = push;
  1043. th->seq = htonl(seq_number);
  1044. length = skb->len;
  1045. netif_receive_skb(skb);
  1046. adapter->stats.lro_pkts++;
  1047. adapter->stats.rxbytes += length;
  1048. return buffer;
  1049. }
  1050. #define netxen_merge_rx_buffers(list, head) \
  1051. do { list_splice_tail_init(list, head); } while (0);
  1052. int
  1053. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1054. {
  1055. struct netxen_adapter *adapter = sds_ring->adapter;
  1056. struct list_head *cur;
  1057. struct status_desc *desc;
  1058. struct netxen_rx_buffer *rxbuf;
  1059. u32 consumer = sds_ring->consumer;
  1060. int count = 0;
  1061. u64 sts_data0, sts_data1;
  1062. int opcode, ring = 0, desc_cnt;
  1063. while (count < max) {
  1064. desc = &sds_ring->desc_head[consumer];
  1065. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1066. if (!(sts_data0 & STATUS_OWNER_HOST))
  1067. break;
  1068. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1069. opcode = netxen_get_sts_opcode(sts_data0);
  1070. switch (opcode) {
  1071. case NETXEN_NIC_RXPKT_DESC:
  1072. case NETXEN_OLD_RXPKT_DESC:
  1073. case NETXEN_NIC_SYN_OFFLOAD:
  1074. ring = netxen_get_sts_type(sts_data0);
  1075. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1076. ring, sts_data0);
  1077. break;
  1078. case NETXEN_NIC_LRO_DESC:
  1079. ring = netxen_get_lro_sts_type(sts_data0);
  1080. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1081. rxbuf = netxen_process_lro(adapter, sds_ring,
  1082. ring, sts_data0, sts_data1);
  1083. break;
  1084. case NETXEN_NIC_RESPONSE_DESC:
  1085. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1086. default:
  1087. goto skip;
  1088. }
  1089. WARN_ON(desc_cnt > 1);
  1090. if (rxbuf)
  1091. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1092. skip:
  1093. for (; desc_cnt > 0; desc_cnt--) {
  1094. desc = &sds_ring->desc_head[consumer];
  1095. desc->status_desc_data[0] =
  1096. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1097. consumer = get_next_index(consumer, sds_ring->num_desc);
  1098. }
  1099. count++;
  1100. }
  1101. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1102. struct nx_host_rds_ring *rds_ring =
  1103. &adapter->recv_ctx.rds_rings[ring];
  1104. if (!list_empty(&sds_ring->free_list[ring])) {
  1105. list_for_each(cur, &sds_ring->free_list[ring]) {
  1106. rxbuf = list_entry(cur,
  1107. struct netxen_rx_buffer, list);
  1108. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1109. }
  1110. spin_lock(&rds_ring->lock);
  1111. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1112. &rds_ring->free_list);
  1113. spin_unlock(&rds_ring->lock);
  1114. }
  1115. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1116. }
  1117. if (count) {
  1118. sds_ring->consumer = consumer;
  1119. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1120. }
  1121. return count;
  1122. }
  1123. /* Process Command status ring */
  1124. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1125. {
  1126. u32 sw_consumer, hw_consumer;
  1127. int count = 0, i;
  1128. struct netxen_cmd_buffer *buffer;
  1129. struct pci_dev *pdev = adapter->pdev;
  1130. struct net_device *netdev = adapter->netdev;
  1131. struct netxen_skb_frag *frag;
  1132. int done = 0;
  1133. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1134. if (!spin_trylock(&adapter->tx_clean_lock))
  1135. return 1;
  1136. sw_consumer = tx_ring->sw_consumer;
  1137. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1138. while (sw_consumer != hw_consumer) {
  1139. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1140. if (buffer->skb) {
  1141. frag = &buffer->frag_array[0];
  1142. pci_unmap_single(pdev, frag->dma, frag->length,
  1143. PCI_DMA_TODEVICE);
  1144. frag->dma = 0ULL;
  1145. for (i = 1; i < buffer->frag_count; i++) {
  1146. frag++; /* Get the next frag */
  1147. pci_unmap_page(pdev, frag->dma, frag->length,
  1148. PCI_DMA_TODEVICE);
  1149. frag->dma = 0ULL;
  1150. }
  1151. adapter->stats.xmitfinished++;
  1152. dev_kfree_skb_any(buffer->skb);
  1153. buffer->skb = NULL;
  1154. }
  1155. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1156. if (++count >= MAX_STATUS_HANDLE)
  1157. break;
  1158. }
  1159. if (count && netif_running(netdev)) {
  1160. tx_ring->sw_consumer = sw_consumer;
  1161. smp_mb();
  1162. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1163. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1164. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1165. netif_wake_queue(netdev);
  1166. adapter->tx_timeo_cnt = 0;
  1167. }
  1168. __netif_tx_unlock(tx_ring->txq);
  1169. }
  1170. }
  1171. /*
  1172. * If everything is freed up to consumer then check if the ring is full
  1173. * If the ring is full then check if more needs to be freed and
  1174. * schedule the call back again.
  1175. *
  1176. * This happens when there are 2 CPUs. One could be freeing and the
  1177. * other filling it. If the ring is full when we get out of here and
  1178. * the card has already interrupted the host then the host can miss the
  1179. * interrupt.
  1180. *
  1181. * There is still a possible race condition and the host could miss an
  1182. * interrupt. The card has to take care of this.
  1183. */
  1184. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1185. done = (sw_consumer == hw_consumer);
  1186. spin_unlock(&adapter->tx_clean_lock);
  1187. return (done);
  1188. }
  1189. void
  1190. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1191. struct nx_host_rds_ring *rds_ring)
  1192. {
  1193. struct rcv_desc *pdesc;
  1194. struct netxen_rx_buffer *buffer;
  1195. int producer, count = 0;
  1196. netxen_ctx_msg msg = 0;
  1197. struct list_head *head;
  1198. producer = rds_ring->producer;
  1199. spin_lock(&rds_ring->lock);
  1200. head = &rds_ring->free_list;
  1201. while (!list_empty(head)) {
  1202. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1203. if (!buffer->skb) {
  1204. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1205. break;
  1206. }
  1207. count++;
  1208. list_del(&buffer->list);
  1209. /* make a rcv descriptor */
  1210. pdesc = &rds_ring->desc_head[producer];
  1211. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1212. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1213. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1214. producer = get_next_index(producer, rds_ring->num_desc);
  1215. }
  1216. spin_unlock(&rds_ring->lock);
  1217. if (count) {
  1218. rds_ring->producer = producer;
  1219. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1220. (producer-1) & (rds_ring->num_desc-1));
  1221. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1222. /*
  1223. * Write a doorbell msg to tell phanmon of change in
  1224. * receive ring producer
  1225. * Only for firmware version < 4.0.0
  1226. */
  1227. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1228. netxen_set_msg_privid(msg);
  1229. netxen_set_msg_count(msg,
  1230. ((producer - 1) &
  1231. (rds_ring->num_desc - 1)));
  1232. netxen_set_msg_ctxid(msg, adapter->portnum);
  1233. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1234. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1235. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1236. }
  1237. }
  1238. }
  1239. static void
  1240. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1241. struct nx_host_rds_ring *rds_ring)
  1242. {
  1243. struct rcv_desc *pdesc;
  1244. struct netxen_rx_buffer *buffer;
  1245. int producer, count = 0;
  1246. struct list_head *head;
  1247. producer = rds_ring->producer;
  1248. if (!spin_trylock(&rds_ring->lock))
  1249. return;
  1250. head = &rds_ring->free_list;
  1251. while (!list_empty(head)) {
  1252. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1253. if (!buffer->skb) {
  1254. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1255. break;
  1256. }
  1257. count++;
  1258. list_del(&buffer->list);
  1259. /* make a rcv descriptor */
  1260. pdesc = &rds_ring->desc_head[producer];
  1261. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1262. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1263. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1264. producer = get_next_index(producer, rds_ring->num_desc);
  1265. }
  1266. if (count) {
  1267. rds_ring->producer = producer;
  1268. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1269. (producer - 1) & (rds_ring->num_desc - 1));
  1270. }
  1271. spin_unlock(&rds_ring->lock);
  1272. }
  1273. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1274. {
  1275. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1276. return;
  1277. }