omap_wdt.c 11 KB

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  1. /*
  2. * omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/fs.h>
  32. #include <linux/mm.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/watchdog.h>
  35. #include <linux/reboot.h>
  36. #include <linux/init.h>
  37. #include <linux/err.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/moduleparam.h>
  40. #include <linux/clk.h>
  41. #include <linux/bitops.h>
  42. #include <linux/io.h>
  43. #include <linux/uaccess.h>
  44. #include <linux/slab.h>
  45. #include <mach/hardware.h>
  46. #include <plat/prcm.h>
  47. #include "omap_wdt.h"
  48. static struct platform_device *omap_wdt_dev;
  49. static unsigned timer_margin;
  50. module_param(timer_margin, uint, 0);
  51. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  52. static unsigned int wdt_trgr_pattern = 0x1234;
  53. static spinlock_t wdt_lock;
  54. struct omap_wdt_dev {
  55. void __iomem *base; /* physical */
  56. struct device *dev;
  57. int omap_wdt_users;
  58. struct clk *ick;
  59. struct clk *fck;
  60. struct resource *mem;
  61. struct miscdevice omap_wdt_miscdev;
  62. };
  63. static void omap_wdt_ping(struct omap_wdt_dev *wdev)
  64. {
  65. void __iomem *base = wdev->base;
  66. /* wait for posted write to complete */
  67. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  68. cpu_relax();
  69. wdt_trgr_pattern = ~wdt_trgr_pattern;
  70. __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
  71. /* wait for posted write to complete */
  72. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  73. cpu_relax();
  74. /* reloaded WCRR from WLDR */
  75. }
  76. static void omap_wdt_enable(struct omap_wdt_dev *wdev)
  77. {
  78. void __iomem *base = wdev->base;
  79. /* Sequence to enable the watchdog */
  80. __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
  81. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  82. cpu_relax();
  83. __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
  84. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  85. cpu_relax();
  86. }
  87. static void omap_wdt_disable(struct omap_wdt_dev *wdev)
  88. {
  89. void __iomem *base = wdev->base;
  90. /* sequence required to disable watchdog */
  91. __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  92. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  93. cpu_relax();
  94. __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  95. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  96. cpu_relax();
  97. }
  98. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  99. {
  100. if (new_timeout < TIMER_MARGIN_MIN)
  101. new_timeout = TIMER_MARGIN_DEFAULT;
  102. if (new_timeout > TIMER_MARGIN_MAX)
  103. new_timeout = TIMER_MARGIN_MAX;
  104. timer_margin = new_timeout;
  105. }
  106. static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
  107. {
  108. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  109. void __iomem *base = wdev->base;
  110. /* just count up at 32 KHz */
  111. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  112. cpu_relax();
  113. __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
  114. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  115. cpu_relax();
  116. }
  117. /*
  118. * Allow only one task to hold it open
  119. */
  120. static int omap_wdt_open(struct inode *inode, struct file *file)
  121. {
  122. struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
  123. void __iomem *base = wdev->base;
  124. if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
  125. return -EBUSY;
  126. clk_enable(wdev->ick); /* Enable the interface clock */
  127. clk_enable(wdev->fck); /* Enable the functional clock */
  128. /* initialize prescaler */
  129. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  130. cpu_relax();
  131. __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
  132. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  133. cpu_relax();
  134. file->private_data = (void *) wdev;
  135. omap_wdt_set_timeout(wdev);
  136. omap_wdt_ping(wdev); /* trigger loading of new timeout value */
  137. omap_wdt_enable(wdev);
  138. return nonseekable_open(inode, file);
  139. }
  140. static int omap_wdt_release(struct inode *inode, struct file *file)
  141. {
  142. struct omap_wdt_dev *wdev = file->private_data;
  143. /*
  144. * Shut off the timer unless NOWAYOUT is defined.
  145. */
  146. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  147. omap_wdt_disable(wdev);
  148. clk_disable(wdev->ick);
  149. clk_disable(wdev->fck);
  150. #else
  151. printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
  152. #endif
  153. wdev->omap_wdt_users = 0;
  154. return 0;
  155. }
  156. static ssize_t omap_wdt_write(struct file *file, const char __user *data,
  157. size_t len, loff_t *ppos)
  158. {
  159. struct omap_wdt_dev *wdev = file->private_data;
  160. /* Refresh LOAD_TIME. */
  161. if (len) {
  162. spin_lock(&wdt_lock);
  163. omap_wdt_ping(wdev);
  164. spin_unlock(&wdt_lock);
  165. }
  166. return len;
  167. }
  168. static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
  169. unsigned long arg)
  170. {
  171. struct omap_wdt_dev *wdev;
  172. int new_margin;
  173. static const struct watchdog_info ident = {
  174. .identity = "OMAP Watchdog",
  175. .options = WDIOF_SETTIMEOUT,
  176. .firmware_version = 0,
  177. };
  178. wdev = file->private_data;
  179. switch (cmd) {
  180. case WDIOC_GETSUPPORT:
  181. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  182. sizeof(ident));
  183. case WDIOC_GETSTATUS:
  184. return put_user(0, (int __user *)arg);
  185. case WDIOC_GETBOOTSTATUS:
  186. if (cpu_is_omap16xx())
  187. return put_user(__raw_readw(ARM_SYSST),
  188. (int __user *)arg);
  189. if (cpu_is_omap24xx())
  190. return put_user(omap_prcm_get_reset_sources(),
  191. (int __user *)arg);
  192. case WDIOC_KEEPALIVE:
  193. spin_lock(&wdt_lock);
  194. omap_wdt_ping(wdev);
  195. spin_unlock(&wdt_lock);
  196. return 0;
  197. case WDIOC_SETTIMEOUT:
  198. if (get_user(new_margin, (int __user *)arg))
  199. return -EFAULT;
  200. omap_wdt_adjust_timeout(new_margin);
  201. spin_lock(&wdt_lock);
  202. omap_wdt_disable(wdev);
  203. omap_wdt_set_timeout(wdev);
  204. omap_wdt_enable(wdev);
  205. omap_wdt_ping(wdev);
  206. spin_unlock(&wdt_lock);
  207. /* Fall */
  208. case WDIOC_GETTIMEOUT:
  209. return put_user(timer_margin, (int __user *)arg);
  210. default:
  211. return -ENOTTY;
  212. }
  213. }
  214. static const struct file_operations omap_wdt_fops = {
  215. .owner = THIS_MODULE,
  216. .write = omap_wdt_write,
  217. .unlocked_ioctl = omap_wdt_ioctl,
  218. .open = omap_wdt_open,
  219. .release = omap_wdt_release,
  220. };
  221. static int __devinit omap_wdt_probe(struct platform_device *pdev)
  222. {
  223. struct resource *res, *mem;
  224. struct omap_wdt_dev *wdev;
  225. int ret;
  226. /* reserve static register mappings */
  227. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  228. if (!res) {
  229. ret = -ENOENT;
  230. goto err_get_resource;
  231. }
  232. if (omap_wdt_dev) {
  233. ret = -EBUSY;
  234. goto err_busy;
  235. }
  236. mem = request_mem_region(res->start, resource_size(res), pdev->name);
  237. if (!mem) {
  238. ret = -EBUSY;
  239. goto err_busy;
  240. }
  241. wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
  242. if (!wdev) {
  243. ret = -ENOMEM;
  244. goto err_kzalloc;
  245. }
  246. wdev->omap_wdt_users = 0;
  247. wdev->mem = mem;
  248. wdev->ick = clk_get(&pdev->dev, "ick");
  249. if (IS_ERR(wdev->ick)) {
  250. ret = PTR_ERR(wdev->ick);
  251. wdev->ick = NULL;
  252. goto err_clk;
  253. }
  254. wdev->fck = clk_get(&pdev->dev, "fck");
  255. if (IS_ERR(wdev->fck)) {
  256. ret = PTR_ERR(wdev->fck);
  257. wdev->fck = NULL;
  258. goto err_clk;
  259. }
  260. wdev->base = ioremap(res->start, resource_size(res));
  261. if (!wdev->base) {
  262. ret = -ENOMEM;
  263. goto err_ioremap;
  264. }
  265. platform_set_drvdata(pdev, wdev);
  266. clk_enable(wdev->ick);
  267. clk_enable(wdev->fck);
  268. omap_wdt_disable(wdev);
  269. omap_wdt_adjust_timeout(timer_margin);
  270. wdev->omap_wdt_miscdev.parent = &pdev->dev;
  271. wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
  272. wdev->omap_wdt_miscdev.name = "watchdog";
  273. wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
  274. ret = misc_register(&(wdev->omap_wdt_miscdev));
  275. if (ret)
  276. goto err_misc;
  277. pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
  278. __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
  279. timer_margin);
  280. /* autogate OCP interface clock */
  281. __raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
  282. clk_disable(wdev->ick);
  283. clk_disable(wdev->fck);
  284. omap_wdt_dev = pdev;
  285. return 0;
  286. err_misc:
  287. platform_set_drvdata(pdev, NULL);
  288. iounmap(wdev->base);
  289. err_ioremap:
  290. wdev->base = NULL;
  291. err_clk:
  292. if (wdev->ick)
  293. clk_put(wdev->ick);
  294. if (wdev->fck)
  295. clk_put(wdev->fck);
  296. kfree(wdev);
  297. err_kzalloc:
  298. release_mem_region(res->start, resource_size(res));
  299. err_busy:
  300. err_get_resource:
  301. return ret;
  302. }
  303. static void omap_wdt_shutdown(struct platform_device *pdev)
  304. {
  305. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  306. if (wdev->omap_wdt_users)
  307. omap_wdt_disable(wdev);
  308. }
  309. static int __devexit omap_wdt_remove(struct platform_device *pdev)
  310. {
  311. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  312. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  313. if (!res)
  314. return -ENOENT;
  315. misc_deregister(&(wdev->omap_wdt_miscdev));
  316. release_mem_region(res->start, resource_size(res));
  317. platform_set_drvdata(pdev, NULL);
  318. clk_put(wdev->ick);
  319. clk_put(wdev->fck);
  320. iounmap(wdev->base);
  321. kfree(wdev);
  322. omap_wdt_dev = NULL;
  323. return 0;
  324. }
  325. #ifdef CONFIG_PM
  326. /* REVISIT ... not clear this is the best way to handle system suspend; and
  327. * it's very inappropriate for selective device suspend (e.g. suspending this
  328. * through sysfs rather than by stopping the watchdog daemon). Also, this
  329. * may not play well enough with NOWAYOUT...
  330. */
  331. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  332. {
  333. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  334. if (wdev->omap_wdt_users)
  335. omap_wdt_disable(wdev);
  336. return 0;
  337. }
  338. static int omap_wdt_resume(struct platform_device *pdev)
  339. {
  340. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  341. if (wdev->omap_wdt_users) {
  342. omap_wdt_enable(wdev);
  343. omap_wdt_ping(wdev);
  344. }
  345. return 0;
  346. }
  347. #else
  348. #define omap_wdt_suspend NULL
  349. #define omap_wdt_resume NULL
  350. #endif
  351. static struct platform_driver omap_wdt_driver = {
  352. .probe = omap_wdt_probe,
  353. .remove = __devexit_p(omap_wdt_remove),
  354. .shutdown = omap_wdt_shutdown,
  355. .suspend = omap_wdt_suspend,
  356. .resume = omap_wdt_resume,
  357. .driver = {
  358. .owner = THIS_MODULE,
  359. .name = "omap_wdt",
  360. },
  361. };
  362. static int __init omap_wdt_init(void)
  363. {
  364. spin_lock_init(&wdt_lock);
  365. return platform_driver_register(&omap_wdt_driver);
  366. }
  367. static void __exit omap_wdt_exit(void)
  368. {
  369. platform_driver_unregister(&omap_wdt_driver);
  370. }
  371. module_init(omap_wdt_init);
  372. module_exit(omap_wdt_exit);
  373. MODULE_AUTHOR("George G. Davis");
  374. MODULE_LICENSE("GPL");
  375. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  376. MODULE_ALIAS("platform:omap_wdt");