omap2430.c 8.4 KB

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  1. /*
  2. * Copyright (C) 2005-2007 by Texas Instruments
  3. * Some code has been taken from tusb6010.c
  4. * Copyrights for that are attributable to:
  5. * Copyright (C) 2006 Nokia Corporation
  6. * Tony Lindgren <tony@atomide.com>
  7. *
  8. * This file is part of the Inventra Controller Driver for Linux.
  9. *
  10. * The Inventra Controller Driver for Linux is free software; you
  11. * can redistribute it and/or modify it under the terms of the GNU
  12. * General Public License version 2 as published by the Free Software
  13. * Foundation.
  14. *
  15. * The Inventra Controller Driver for Linux is distributed in
  16. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17. * without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19. * License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with The Inventra Controller Driver for Linux ; if not,
  23. * write to the Free Software Foundation, Inc., 59 Temple Place,
  24. * Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/sched.h>
  30. #include <linux/init.h>
  31. #include <linux/list.h>
  32. #include <linux/clk.h>
  33. #include <linux/io.h>
  34. #include <plat/mux.h>
  35. #include "musb_core.h"
  36. #include "omap2430.h"
  37. static struct timer_list musb_idle_timer;
  38. static void musb_do_idle(unsigned long _musb)
  39. {
  40. struct musb *musb = (void *)_musb;
  41. unsigned long flags;
  42. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  43. u8 power;
  44. #endif
  45. u8 devctl;
  46. spin_lock_irqsave(&musb->lock, flags);
  47. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  48. switch (musb->xceiv->state) {
  49. case OTG_STATE_A_WAIT_BCON:
  50. devctl &= ~MUSB_DEVCTL_SESSION;
  51. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  52. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  53. if (devctl & MUSB_DEVCTL_BDEVICE) {
  54. musb->xceiv->state = OTG_STATE_B_IDLE;
  55. MUSB_DEV_MODE(musb);
  56. } else {
  57. musb->xceiv->state = OTG_STATE_A_IDLE;
  58. MUSB_HST_MODE(musb);
  59. }
  60. break;
  61. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  62. case OTG_STATE_A_SUSPEND:
  63. /* finish RESUME signaling? */
  64. if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
  65. power = musb_readb(musb->mregs, MUSB_POWER);
  66. power &= ~MUSB_POWER_RESUME;
  67. DBG(1, "root port resume stopped, power %02x\n", power);
  68. musb_writeb(musb->mregs, MUSB_POWER, power);
  69. musb->is_active = 1;
  70. musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
  71. | MUSB_PORT_STAT_RESUME);
  72. musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
  73. usb_hcd_poll_rh_status(musb_to_hcd(musb));
  74. /* NOTE: it might really be A_WAIT_BCON ... */
  75. musb->xceiv->state = OTG_STATE_A_HOST;
  76. }
  77. break;
  78. #endif
  79. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  80. case OTG_STATE_A_HOST:
  81. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  82. if (devctl & MUSB_DEVCTL_BDEVICE)
  83. musb->xceiv->state = OTG_STATE_B_IDLE;
  84. else
  85. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  86. #endif
  87. default:
  88. break;
  89. }
  90. spin_unlock_irqrestore(&musb->lock, flags);
  91. }
  92. void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
  93. {
  94. unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
  95. static unsigned long last_timer;
  96. if (timeout == 0)
  97. timeout = default_timeout;
  98. /* Never idle if active, or when VBUS timeout is not set as host */
  99. if (musb->is_active || ((musb->a_wait_bcon == 0)
  100. && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
  101. DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
  102. del_timer(&musb_idle_timer);
  103. last_timer = jiffies;
  104. return;
  105. }
  106. if (time_after(last_timer, timeout)) {
  107. if (!timer_pending(&musb_idle_timer))
  108. last_timer = timeout;
  109. else {
  110. DBG(4, "Longer idle timer already pending, ignoring\n");
  111. return;
  112. }
  113. }
  114. last_timer = timeout;
  115. DBG(4, "%s inactive, for idle timer for %lu ms\n",
  116. otg_state_string(musb),
  117. (unsigned long)jiffies_to_msecs(timeout - jiffies));
  118. mod_timer(&musb_idle_timer, timeout);
  119. }
  120. void musb_platform_enable(struct musb *musb)
  121. {
  122. }
  123. void musb_platform_disable(struct musb *musb)
  124. {
  125. }
  126. static void omap_set_vbus(struct musb *musb, int is_on)
  127. {
  128. u8 devctl;
  129. /* HDRC controls CPEN, but beware current surges during device
  130. * connect. They can trigger transient overcurrent conditions
  131. * that must be ignored.
  132. */
  133. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  134. if (is_on) {
  135. musb->is_active = 1;
  136. musb->xceiv->default_a = 1;
  137. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  138. devctl |= MUSB_DEVCTL_SESSION;
  139. MUSB_HST_MODE(musb);
  140. } else {
  141. musb->is_active = 0;
  142. /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
  143. * jumping right to B_IDLE...
  144. */
  145. musb->xceiv->default_a = 0;
  146. musb->xceiv->state = OTG_STATE_B_IDLE;
  147. devctl &= ~MUSB_DEVCTL_SESSION;
  148. MUSB_DEV_MODE(musb);
  149. }
  150. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  151. DBG(1, "VBUS %s, devctl %02x "
  152. /* otg %3x conf %08x prcm %08x */ "\n",
  153. otg_state_string(musb),
  154. musb_readb(musb->mregs, MUSB_DEVCTL));
  155. }
  156. static int musb_platform_resume(struct musb *musb);
  157. int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
  158. {
  159. u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  160. devctl |= MUSB_DEVCTL_SESSION;
  161. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  162. return 0;
  163. }
  164. int __init musb_platform_init(struct musb *musb, void *board_data)
  165. {
  166. u32 l;
  167. struct omap_musb_board_data *data = board_data;
  168. #if defined(CONFIG_ARCH_OMAP2430)
  169. omap_cfg_reg(AE5_2430_USB0HS_STP);
  170. #endif
  171. /* We require some kind of external transceiver, hooked
  172. * up through ULPI. TWL4030-family PMICs include one,
  173. * which needs a driver, drivers aren't always needed.
  174. */
  175. musb->xceiv = otg_get_transceiver();
  176. if (!musb->xceiv) {
  177. pr_err("HS USB OTG: no transceiver configured\n");
  178. return -ENODEV;
  179. }
  180. musb_platform_resume(musb);
  181. l = musb_readl(musb->mregs, OTG_SYSCONFIG);
  182. l &= ~ENABLEWAKEUP; /* disable wakeup */
  183. l &= ~NOSTDBY; /* remove possible nostdby */
  184. l |= SMARTSTDBY; /* enable smart standby */
  185. l &= ~AUTOIDLE; /* disable auto idle */
  186. l &= ~NOIDLE; /* remove possible noidle */
  187. l |= SMARTIDLE; /* enable smart idle */
  188. /*
  189. * MUSB AUTOIDLE don't work in 3430.
  190. * Workaround by Richard Woodruff/TI
  191. */
  192. if (!cpu_is_omap3430())
  193. l |= AUTOIDLE; /* enable auto idle */
  194. musb_writel(musb->mregs, OTG_SYSCONFIG, l);
  195. l = musb_readl(musb->mregs, OTG_INTERFSEL);
  196. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  197. /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
  198. l &= ~ULPI_12PIN; /* Disable ULPI */
  199. l |= UTMI_8BIT; /* Enable UTMI */
  200. } else {
  201. l |= ULPI_12PIN;
  202. }
  203. musb_writel(musb->mregs, OTG_INTERFSEL, l);
  204. pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
  205. "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
  206. musb_readl(musb->mregs, OTG_REVISION),
  207. musb_readl(musb->mregs, OTG_SYSCONFIG),
  208. musb_readl(musb->mregs, OTG_SYSSTATUS),
  209. musb_readl(musb->mregs, OTG_INTERFSEL),
  210. musb_readl(musb->mregs, OTG_SIMENABLE));
  211. if (is_host_enabled(musb))
  212. musb->board_set_vbus = omap_set_vbus;
  213. setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
  214. return 0;
  215. }
  216. #ifdef CONFIG_PM
  217. void musb_platform_save_context(struct musb *musb,
  218. struct musb_context_registers *musb_context)
  219. {
  220. musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG);
  221. musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY);
  222. }
  223. void musb_platform_restore_context(struct musb *musb,
  224. struct musb_context_registers *musb_context)
  225. {
  226. musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig);
  227. musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby);
  228. }
  229. #endif
  230. static int musb_platform_suspend(struct musb *musb)
  231. {
  232. u32 l;
  233. if (!musb->clock)
  234. return 0;
  235. /* in any role */
  236. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  237. l |= ENABLEFORCE; /* enable MSTANDBY */
  238. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  239. l = musb_readl(musb->mregs, OTG_SYSCONFIG);
  240. l |= ENABLEWAKEUP; /* enable wakeup */
  241. musb_writel(musb->mregs, OTG_SYSCONFIG, l);
  242. otg_set_suspend(musb->xceiv, 1);
  243. if (musb->set_clock)
  244. musb->set_clock(musb->clock, 0);
  245. else
  246. clk_disable(musb->clock);
  247. return 0;
  248. }
  249. static int musb_platform_resume(struct musb *musb)
  250. {
  251. u32 l;
  252. if (!musb->clock)
  253. return 0;
  254. otg_set_suspend(musb->xceiv, 0);
  255. if (musb->set_clock)
  256. musb->set_clock(musb->clock, 1);
  257. else
  258. clk_enable(musb->clock);
  259. l = musb_readl(musb->mregs, OTG_SYSCONFIG);
  260. l &= ~ENABLEWAKEUP; /* disable wakeup */
  261. musb_writel(musb->mregs, OTG_SYSCONFIG, l);
  262. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  263. l &= ~ENABLEFORCE; /* disable MSTANDBY */
  264. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  265. return 0;
  266. }
  267. int musb_platform_exit(struct musb *musb)
  268. {
  269. musb_platform_suspend(musb);
  270. return 0;
  271. }