oxu210hp-hcd.c 99 KB

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  1. /*
  2. * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it>
  3. * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it>
  4. *
  5. * This code is *strongly* based on EHCI-HCD code by David Brownell since
  6. * the chip is a quasi-EHCI compatible.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/dmapool.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/errno.h>
  31. #include <linux/init.h>
  32. #include <linux/timer.h>
  33. #include <linux/list.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/usb.h>
  36. #include <linux/usb/hcd.h>
  37. #include <linux/moduleparam.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/io.h>
  40. #include <asm/irq.h>
  41. #include <asm/system.h>
  42. #include <asm/unaligned.h>
  43. #include <linux/irq.h>
  44. #include <linux/platform_device.h>
  45. #include "oxu210hp.h"
  46. #define DRIVER_VERSION "0.0.50"
  47. /*
  48. * Main defines
  49. */
  50. #define oxu_dbg(oxu, fmt, args...) \
  51. dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  52. #define oxu_err(oxu, fmt, args...) \
  53. dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  54. #define oxu_info(oxu, fmt, args...) \
  55. dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  56. static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu)
  57. {
  58. return container_of((void *) oxu, struct usb_hcd, hcd_priv);
  59. }
  60. static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd)
  61. {
  62. return (struct oxu_hcd *) (hcd->hcd_priv);
  63. }
  64. /*
  65. * Debug stuff
  66. */
  67. #undef OXU_URB_TRACE
  68. #undef OXU_VERBOSE_DEBUG
  69. #ifdef OXU_VERBOSE_DEBUG
  70. #define oxu_vdbg oxu_dbg
  71. #else
  72. #define oxu_vdbg(oxu, fmt, args...) /* Nop */
  73. #endif
  74. #ifdef DEBUG
  75. static int __attribute__((__unused__))
  76. dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
  77. {
  78. return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
  79. label, label[0] ? " " : "", status,
  80. (status & STS_ASS) ? " Async" : "",
  81. (status & STS_PSS) ? " Periodic" : "",
  82. (status & STS_RECL) ? " Recl" : "",
  83. (status & STS_HALT) ? " Halt" : "",
  84. (status & STS_IAA) ? " IAA" : "",
  85. (status & STS_FATAL) ? " FATAL" : "",
  86. (status & STS_FLR) ? " FLR" : "",
  87. (status & STS_PCD) ? " PCD" : "",
  88. (status & STS_ERR) ? " ERR" : "",
  89. (status & STS_INT) ? " INT" : ""
  90. );
  91. }
  92. static int __attribute__((__unused__))
  93. dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
  94. {
  95. return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
  96. label, label[0] ? " " : "", enable,
  97. (enable & STS_IAA) ? " IAA" : "",
  98. (enable & STS_FATAL) ? " FATAL" : "",
  99. (enable & STS_FLR) ? " FLR" : "",
  100. (enable & STS_PCD) ? " PCD" : "",
  101. (enable & STS_ERR) ? " ERR" : "",
  102. (enable & STS_INT) ? " INT" : ""
  103. );
  104. }
  105. static const char *const fls_strings[] =
  106. { "1024", "512", "256", "??" };
  107. static int dbg_command_buf(char *buf, unsigned len,
  108. const char *label, u32 command)
  109. {
  110. return scnprintf(buf, len,
  111. "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
  112. label, label[0] ? " " : "", command,
  113. (command & CMD_PARK) ? "park" : "(park)",
  114. CMD_PARK_CNT(command),
  115. (command >> 16) & 0x3f,
  116. (command & CMD_LRESET) ? " LReset" : "",
  117. (command & CMD_IAAD) ? " IAAD" : "",
  118. (command & CMD_ASE) ? " Async" : "",
  119. (command & CMD_PSE) ? " Periodic" : "",
  120. fls_strings[(command >> 2) & 0x3],
  121. (command & CMD_RESET) ? " Reset" : "",
  122. (command & CMD_RUN) ? "RUN" : "HALT"
  123. );
  124. }
  125. static int dbg_port_buf(char *buf, unsigned len, const char *label,
  126. int port, u32 status)
  127. {
  128. char *sig;
  129. /* signaling state */
  130. switch (status & (3 << 10)) {
  131. case 0 << 10:
  132. sig = "se0";
  133. break;
  134. case 1 << 10:
  135. sig = "k"; /* low speed */
  136. break;
  137. case 2 << 10:
  138. sig = "j";
  139. break;
  140. default:
  141. sig = "?";
  142. break;
  143. }
  144. return scnprintf(buf, len,
  145. "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
  146. label, label[0] ? " " : "", port, status,
  147. (status & PORT_POWER) ? " POWER" : "",
  148. (status & PORT_OWNER) ? " OWNER" : "",
  149. sig,
  150. (status & PORT_RESET) ? " RESET" : "",
  151. (status & PORT_SUSPEND) ? " SUSPEND" : "",
  152. (status & PORT_RESUME) ? " RESUME" : "",
  153. (status & PORT_OCC) ? " OCC" : "",
  154. (status & PORT_OC) ? " OC" : "",
  155. (status & PORT_PEC) ? " PEC" : "",
  156. (status & PORT_PE) ? " PE" : "",
  157. (status & PORT_CSC) ? " CSC" : "",
  158. (status & PORT_CONNECT) ? " CONNECT" : ""
  159. );
  160. }
  161. #else
  162. static inline int __attribute__((__unused__))
  163. dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
  164. { return 0; }
  165. static inline int __attribute__((__unused__))
  166. dbg_command_buf(char *buf, unsigned len, const char *label, u32 command)
  167. { return 0; }
  168. static inline int __attribute__((__unused__))
  169. dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
  170. { return 0; }
  171. static inline int __attribute__((__unused__))
  172. dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status)
  173. { return 0; }
  174. #endif /* DEBUG */
  175. /* functions have the "wrong" filename when they're output... */
  176. #define dbg_status(oxu, label, status) { \
  177. char _buf[80]; \
  178. dbg_status_buf(_buf, sizeof _buf, label, status); \
  179. oxu_dbg(oxu, "%s\n", _buf); \
  180. }
  181. #define dbg_cmd(oxu, label, command) { \
  182. char _buf[80]; \
  183. dbg_command_buf(_buf, sizeof _buf, label, command); \
  184. oxu_dbg(oxu, "%s\n", _buf); \
  185. }
  186. #define dbg_port(oxu, label, port, status) { \
  187. char _buf[80]; \
  188. dbg_port_buf(_buf, sizeof _buf, label, port, status); \
  189. oxu_dbg(oxu, "%s\n", _buf); \
  190. }
  191. /*
  192. * Module parameters
  193. */
  194. /* Initial IRQ latency: faster than hw default */
  195. static int log2_irq_thresh; /* 0 to 6 */
  196. module_param(log2_irq_thresh, int, S_IRUGO);
  197. MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
  198. /* Initial park setting: slower than hw default */
  199. static unsigned park;
  200. module_param(park, uint, S_IRUGO);
  201. MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
  202. /* For flakey hardware, ignore overcurrent indicators */
  203. static int ignore_oc;
  204. module_param(ignore_oc, bool, S_IRUGO);
  205. MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications");
  206. static void ehci_work(struct oxu_hcd *oxu);
  207. static int oxu_hub_control(struct usb_hcd *hcd,
  208. u16 typeReq, u16 wValue, u16 wIndex,
  209. char *buf, u16 wLength);
  210. /*
  211. * Local functions
  212. */
  213. /* Low level read/write registers functions */
  214. static inline u32 oxu_readl(void *base, u32 reg)
  215. {
  216. return readl(base + reg);
  217. }
  218. static inline void oxu_writel(void *base, u32 reg, u32 val)
  219. {
  220. writel(val, base + reg);
  221. }
  222. static inline void timer_action_done(struct oxu_hcd *oxu,
  223. enum ehci_timer_action action)
  224. {
  225. clear_bit(action, &oxu->actions);
  226. }
  227. static inline void timer_action(struct oxu_hcd *oxu,
  228. enum ehci_timer_action action)
  229. {
  230. if (!test_and_set_bit(action, &oxu->actions)) {
  231. unsigned long t;
  232. switch (action) {
  233. case TIMER_IAA_WATCHDOG:
  234. t = EHCI_IAA_JIFFIES;
  235. break;
  236. case TIMER_IO_WATCHDOG:
  237. t = EHCI_IO_JIFFIES;
  238. break;
  239. case TIMER_ASYNC_OFF:
  240. t = EHCI_ASYNC_JIFFIES;
  241. break;
  242. case TIMER_ASYNC_SHRINK:
  243. default:
  244. t = EHCI_SHRINK_JIFFIES;
  245. break;
  246. }
  247. t += jiffies;
  248. /* all timings except IAA watchdog can be overridden.
  249. * async queue SHRINK often precedes IAA. while it's ready
  250. * to go OFF neither can matter, and afterwards the IO
  251. * watchdog stops unless there's still periodic traffic.
  252. */
  253. if (action != TIMER_IAA_WATCHDOG
  254. && t > oxu->watchdog.expires
  255. && timer_pending(&oxu->watchdog))
  256. return;
  257. mod_timer(&oxu->watchdog, t);
  258. }
  259. }
  260. /*
  261. * handshake - spin reading hc until handshake completes or fails
  262. * @ptr: address of hc register to be read
  263. * @mask: bits to look at in result of read
  264. * @done: value of those bits when handshake succeeds
  265. * @usec: timeout in microseconds
  266. *
  267. * Returns negative errno, or zero on success
  268. *
  269. * Success happens when the "mask" bits have the specified value (hardware
  270. * handshake done). There are two failure modes: "usec" have passed (major
  271. * hardware flakeout), or the register reads as all-ones (hardware removed).
  272. *
  273. * That last failure should_only happen in cases like physical cardbus eject
  274. * before driver shutdown. But it also seems to be caused by bugs in cardbus
  275. * bridge shutdown: shutting down the bridge before the devices using it.
  276. */
  277. static int handshake(struct oxu_hcd *oxu, void __iomem *ptr,
  278. u32 mask, u32 done, int usec)
  279. {
  280. u32 result;
  281. do {
  282. result = readl(ptr);
  283. if (result == ~(u32)0) /* card removed */
  284. return -ENODEV;
  285. result &= mask;
  286. if (result == done)
  287. return 0;
  288. udelay(1);
  289. usec--;
  290. } while (usec > 0);
  291. return -ETIMEDOUT;
  292. }
  293. /* Force HC to halt state from unknown (EHCI spec section 2.3) */
  294. static int ehci_halt(struct oxu_hcd *oxu)
  295. {
  296. u32 temp = readl(&oxu->regs->status);
  297. /* disable any irqs left enabled by previous code */
  298. writel(0, &oxu->regs->intr_enable);
  299. if ((temp & STS_HALT) != 0)
  300. return 0;
  301. temp = readl(&oxu->regs->command);
  302. temp &= ~CMD_RUN;
  303. writel(temp, &oxu->regs->command);
  304. return handshake(oxu, &oxu->regs->status,
  305. STS_HALT, STS_HALT, 16 * 125);
  306. }
  307. /* Put TDI/ARC silicon into EHCI mode */
  308. static void tdi_reset(struct oxu_hcd *oxu)
  309. {
  310. u32 __iomem *reg_ptr;
  311. u32 tmp;
  312. reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68);
  313. tmp = readl(reg_ptr);
  314. tmp |= 0x3;
  315. writel(tmp, reg_ptr);
  316. }
  317. /* Reset a non-running (STS_HALT == 1) controller */
  318. static int ehci_reset(struct oxu_hcd *oxu)
  319. {
  320. int retval;
  321. u32 command = readl(&oxu->regs->command);
  322. command |= CMD_RESET;
  323. dbg_cmd(oxu, "reset", command);
  324. writel(command, &oxu->regs->command);
  325. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  326. oxu->next_statechange = jiffies;
  327. retval = handshake(oxu, &oxu->regs->command,
  328. CMD_RESET, 0, 250 * 1000);
  329. if (retval)
  330. return retval;
  331. tdi_reset(oxu);
  332. return retval;
  333. }
  334. /* Idle the controller (from running) */
  335. static void ehci_quiesce(struct oxu_hcd *oxu)
  336. {
  337. u32 temp;
  338. #ifdef DEBUG
  339. if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  340. BUG();
  341. #endif
  342. /* wait for any schedule enables/disables to take effect */
  343. temp = readl(&oxu->regs->command) << 10;
  344. temp &= STS_ASS | STS_PSS;
  345. if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
  346. temp, 16 * 125) != 0) {
  347. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  348. return;
  349. }
  350. /* then disable anything that's still active */
  351. temp = readl(&oxu->regs->command);
  352. temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
  353. writel(temp, &oxu->regs->command);
  354. /* hardware can take 16 microframes to turn off ... */
  355. if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
  356. 0, 16 * 125) != 0) {
  357. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  358. return;
  359. }
  360. }
  361. static int check_reset_complete(struct oxu_hcd *oxu, int index,
  362. u32 __iomem *status_reg, int port_status)
  363. {
  364. if (!(port_status & PORT_CONNECT)) {
  365. oxu->reset_done[index] = 0;
  366. return port_status;
  367. }
  368. /* if reset finished and it's still not enabled -- handoff */
  369. if (!(port_status & PORT_PE)) {
  370. oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n",
  371. index+1);
  372. return port_status;
  373. } else
  374. oxu_dbg(oxu, "port %d high speed\n", index + 1);
  375. return port_status;
  376. }
  377. static void ehci_hub_descriptor(struct oxu_hcd *oxu,
  378. struct usb_hub_descriptor *desc)
  379. {
  380. int ports = HCS_N_PORTS(oxu->hcs_params);
  381. u16 temp;
  382. desc->bDescriptorType = 0x29;
  383. desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */
  384. desc->bHubContrCurrent = 0;
  385. desc->bNbrPorts = ports;
  386. temp = 1 + (ports / 8);
  387. desc->bDescLength = 7 + 2 * temp;
  388. /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
  389. memset(&desc->bitmap[0], 0, temp);
  390. memset(&desc->bitmap[temp], 0xff, temp);
  391. temp = 0x0008; /* per-port overcurrent reporting */
  392. if (HCS_PPC(oxu->hcs_params))
  393. temp |= 0x0001; /* per-port power control */
  394. else
  395. temp |= 0x0002; /* no power switching */
  396. desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp);
  397. }
  398. /* Allocate an OXU210HP on-chip memory data buffer
  399. *
  400. * An on-chip memory data buffer is required for each OXU210HP USB transfer.
  401. * Each transfer descriptor has one or more on-chip memory data buffers.
  402. *
  403. * Data buffers are allocated from a fix sized pool of data blocks.
  404. * To minimise fragmentation and give reasonable memory utlisation,
  405. * data buffers are allocated with sizes the power of 2 multiples of
  406. * the block size, starting on an address a multiple of the allocated size.
  407. *
  408. * FIXME: callers of this function require a buffer to be allocated for
  409. * len=0. This is a waste of on-chip memory and should be fix. Then this
  410. * function should be changed to not allocate a buffer for len=0.
  411. */
  412. static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len)
  413. {
  414. int n_blocks; /* minium blocks needed to hold len */
  415. int a_blocks; /* blocks allocated */
  416. int i, j;
  417. /* Don't allocte bigger than supported */
  418. if (len > BUFFER_SIZE * BUFFER_NUM) {
  419. oxu_err(oxu, "buffer too big (%d)\n", len);
  420. return -ENOMEM;
  421. }
  422. spin_lock(&oxu->mem_lock);
  423. /* Number of blocks needed to hold len */
  424. n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE;
  425. /* Round the number of blocks up to the power of 2 */
  426. for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1)
  427. ;
  428. /* Find a suitable available data buffer */
  429. for (i = 0; i < BUFFER_NUM;
  430. i += max(a_blocks, (int)oxu->db_used[i])) {
  431. /* Check all the required blocks are available */
  432. for (j = 0; j < a_blocks; j++)
  433. if (oxu->db_used[i + j])
  434. break;
  435. if (j != a_blocks)
  436. continue;
  437. /* Allocate blocks found! */
  438. qtd->buffer = (void *) &oxu->mem->db_pool[i];
  439. qtd->buffer_dma = virt_to_phys(qtd->buffer);
  440. qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks;
  441. oxu->db_used[i] = a_blocks;
  442. spin_unlock(&oxu->mem_lock);
  443. return 0;
  444. }
  445. /* Failed */
  446. spin_unlock(&oxu->mem_lock);
  447. return -ENOMEM;
  448. }
  449. static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
  450. {
  451. int index;
  452. spin_lock(&oxu->mem_lock);
  453. index = (qtd->buffer - (void *) &oxu->mem->db_pool[0])
  454. / BUFFER_SIZE;
  455. oxu->db_used[index] = 0;
  456. qtd->qtd_buffer_len = 0;
  457. qtd->buffer_dma = 0;
  458. qtd->buffer = NULL;
  459. spin_unlock(&oxu->mem_lock);
  460. return;
  461. }
  462. static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma)
  463. {
  464. memset(qtd, 0, sizeof *qtd);
  465. qtd->qtd_dma = dma;
  466. qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
  467. qtd->hw_next = EHCI_LIST_END;
  468. qtd->hw_alt_next = EHCI_LIST_END;
  469. INIT_LIST_HEAD(&qtd->qtd_list);
  470. }
  471. static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
  472. {
  473. int index;
  474. if (qtd->buffer)
  475. oxu_buf_free(oxu, qtd);
  476. spin_lock(&oxu->mem_lock);
  477. index = qtd - &oxu->mem->qtd_pool[0];
  478. oxu->qtd_used[index] = 0;
  479. spin_unlock(&oxu->mem_lock);
  480. return;
  481. }
  482. static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu)
  483. {
  484. int i;
  485. struct ehci_qtd *qtd = NULL;
  486. spin_lock(&oxu->mem_lock);
  487. for (i = 0; i < QTD_NUM; i++)
  488. if (!oxu->qtd_used[i])
  489. break;
  490. if (i < QTD_NUM) {
  491. qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i];
  492. memset(qtd, 0, sizeof *qtd);
  493. qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
  494. qtd->hw_next = EHCI_LIST_END;
  495. qtd->hw_alt_next = EHCI_LIST_END;
  496. INIT_LIST_HEAD(&qtd->qtd_list);
  497. qtd->qtd_dma = virt_to_phys(qtd);
  498. oxu->qtd_used[i] = 1;
  499. }
  500. spin_unlock(&oxu->mem_lock);
  501. return qtd;
  502. }
  503. static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh)
  504. {
  505. int index;
  506. spin_lock(&oxu->mem_lock);
  507. index = qh - &oxu->mem->qh_pool[0];
  508. oxu->qh_used[index] = 0;
  509. spin_unlock(&oxu->mem_lock);
  510. return;
  511. }
  512. static void qh_destroy(struct kref *kref)
  513. {
  514. struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
  515. struct oxu_hcd *oxu = qh->oxu;
  516. /* clean qtds first, and know this is not linked */
  517. if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
  518. oxu_dbg(oxu, "unused qh not empty!\n");
  519. BUG();
  520. }
  521. if (qh->dummy)
  522. oxu_qtd_free(oxu, qh->dummy);
  523. oxu_qh_free(oxu, qh);
  524. }
  525. static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu)
  526. {
  527. int i;
  528. struct ehci_qh *qh = NULL;
  529. spin_lock(&oxu->mem_lock);
  530. for (i = 0; i < QHEAD_NUM; i++)
  531. if (!oxu->qh_used[i])
  532. break;
  533. if (i < QHEAD_NUM) {
  534. qh = (struct ehci_qh *) &oxu->mem->qh_pool[i];
  535. memset(qh, 0, sizeof *qh);
  536. kref_init(&qh->kref);
  537. qh->oxu = oxu;
  538. qh->qh_dma = virt_to_phys(qh);
  539. INIT_LIST_HEAD(&qh->qtd_list);
  540. /* dummy td enables safe urb queuing */
  541. qh->dummy = ehci_qtd_alloc(oxu);
  542. if (qh->dummy == NULL) {
  543. oxu_dbg(oxu, "no dummy td\n");
  544. oxu->qh_used[i] = 0;
  545. qh = NULL;
  546. goto unlock;
  547. }
  548. oxu->qh_used[i] = 1;
  549. }
  550. unlock:
  551. spin_unlock(&oxu->mem_lock);
  552. return qh;
  553. }
  554. /* to share a qh (cpu threads, or hc) */
  555. static inline struct ehci_qh *qh_get(struct ehci_qh *qh)
  556. {
  557. kref_get(&qh->kref);
  558. return qh;
  559. }
  560. static inline void qh_put(struct ehci_qh *qh)
  561. {
  562. kref_put(&qh->kref, qh_destroy);
  563. }
  564. static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb)
  565. {
  566. int index;
  567. spin_lock(&oxu->mem_lock);
  568. index = murb - &oxu->murb_pool[0];
  569. oxu->murb_used[index] = 0;
  570. spin_unlock(&oxu->mem_lock);
  571. return;
  572. }
  573. static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu)
  574. {
  575. int i;
  576. struct oxu_murb *murb = NULL;
  577. spin_lock(&oxu->mem_lock);
  578. for (i = 0; i < MURB_NUM; i++)
  579. if (!oxu->murb_used[i])
  580. break;
  581. if (i < MURB_NUM) {
  582. murb = &(oxu->murb_pool)[i];
  583. oxu->murb_used[i] = 1;
  584. }
  585. spin_unlock(&oxu->mem_lock);
  586. return murb;
  587. }
  588. /* The queue heads and transfer descriptors are managed from pools tied
  589. * to each of the "per device" structures.
  590. * This is the initialisation and cleanup code.
  591. */
  592. static void ehci_mem_cleanup(struct oxu_hcd *oxu)
  593. {
  594. kfree(oxu->murb_pool);
  595. oxu->murb_pool = NULL;
  596. if (oxu->async)
  597. qh_put(oxu->async);
  598. oxu->async = NULL;
  599. del_timer(&oxu->urb_timer);
  600. oxu->periodic = NULL;
  601. /* shadow periodic table */
  602. kfree(oxu->pshadow);
  603. oxu->pshadow = NULL;
  604. }
  605. /* Remember to add cleanup code (above) if you add anything here.
  606. */
  607. static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags)
  608. {
  609. int i;
  610. for (i = 0; i < oxu->periodic_size; i++)
  611. oxu->mem->frame_list[i] = EHCI_LIST_END;
  612. for (i = 0; i < QHEAD_NUM; i++)
  613. oxu->qh_used[i] = 0;
  614. for (i = 0; i < QTD_NUM; i++)
  615. oxu->qtd_used[i] = 0;
  616. oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags);
  617. if (!oxu->murb_pool)
  618. goto fail;
  619. for (i = 0; i < MURB_NUM; i++)
  620. oxu->murb_used[i] = 0;
  621. oxu->async = oxu_qh_alloc(oxu);
  622. if (!oxu->async)
  623. goto fail;
  624. oxu->periodic = (__le32 *) &oxu->mem->frame_list;
  625. oxu->periodic_dma = virt_to_phys(oxu->periodic);
  626. for (i = 0; i < oxu->periodic_size; i++)
  627. oxu->periodic[i] = EHCI_LIST_END;
  628. /* software shadow of hardware table */
  629. oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags);
  630. if (oxu->pshadow != NULL)
  631. return 0;
  632. fail:
  633. oxu_dbg(oxu, "couldn't init memory\n");
  634. ehci_mem_cleanup(oxu);
  635. return -ENOMEM;
  636. }
  637. /* Fill a qtd, returning how much of the buffer we were able to queue up.
  638. */
  639. static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len,
  640. int token, int maxpacket)
  641. {
  642. int i, count;
  643. u64 addr = buf;
  644. /* one buffer entry per 4K ... first might be short or unaligned */
  645. qtd->hw_buf[0] = cpu_to_le32((u32)addr);
  646. qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32));
  647. count = 0x1000 - (buf & 0x0fff); /* rest of that page */
  648. if (likely(len < count)) /* ... iff needed */
  649. count = len;
  650. else {
  651. buf += 0x1000;
  652. buf &= ~0x0fff;
  653. /* per-qtd limit: from 16K to 20K (best alignment) */
  654. for (i = 1; count < len && i < 5; i++) {
  655. addr = buf;
  656. qtd->hw_buf[i] = cpu_to_le32((u32)addr);
  657. qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32));
  658. buf += 0x1000;
  659. if ((count + 0x1000) < len)
  660. count += 0x1000;
  661. else
  662. count = len;
  663. }
  664. /* short packets may only terminate transfers */
  665. if (count != len)
  666. count -= (count % maxpacket);
  667. }
  668. qtd->hw_token = cpu_to_le32((count << 16) | token);
  669. qtd->length = count;
  670. return count;
  671. }
  672. static inline void qh_update(struct oxu_hcd *oxu,
  673. struct ehci_qh *qh, struct ehci_qtd *qtd)
  674. {
  675. /* writes to an active overlay are unsafe */
  676. BUG_ON(qh->qh_state != QH_STATE_IDLE);
  677. qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma);
  678. qh->hw_alt_next = EHCI_LIST_END;
  679. /* Except for control endpoints, we make hardware maintain data
  680. * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
  681. * and set the pseudo-toggle in udev. Only usb_clear_halt() will
  682. * ever clear it.
  683. */
  684. if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) {
  685. unsigned is_out, epnum;
  686. is_out = !(qtd->hw_token & cpu_to_le32(1 << 8));
  687. epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f;
  688. if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
  689. qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE);
  690. usb_settoggle(qh->dev, epnum, is_out, 1);
  691. }
  692. }
  693. /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
  694. wmb();
  695. qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING);
  696. }
  697. /* If it weren't for a common silicon quirk (writing the dummy into the qh
  698. * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
  699. * recovery (including urb dequeue) would need software changes to a QH...
  700. */
  701. static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh)
  702. {
  703. struct ehci_qtd *qtd;
  704. if (list_empty(&qh->qtd_list))
  705. qtd = qh->dummy;
  706. else {
  707. qtd = list_entry(qh->qtd_list.next,
  708. struct ehci_qtd, qtd_list);
  709. /* first qtd may already be partially processed */
  710. if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current)
  711. qtd = NULL;
  712. }
  713. if (qtd)
  714. qh_update(oxu, qh, qtd);
  715. }
  716. static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb,
  717. size_t length, u32 token)
  718. {
  719. /* count IN/OUT bytes, not SETUP (even short packets) */
  720. if (likely(QTD_PID(token) != 2))
  721. urb->actual_length += length - QTD_LENGTH(token);
  722. /* don't modify error codes */
  723. if (unlikely(urb->status != -EINPROGRESS))
  724. return;
  725. /* force cleanup after short read; not always an error */
  726. if (unlikely(IS_SHORT_READ(token)))
  727. urb->status = -EREMOTEIO;
  728. /* serious "can't proceed" faults reported by the hardware */
  729. if (token & QTD_STS_HALT) {
  730. if (token & QTD_STS_BABBLE) {
  731. /* FIXME "must" disable babbling device's port too */
  732. urb->status = -EOVERFLOW;
  733. } else if (token & QTD_STS_MMF) {
  734. /* fs/ls interrupt xfer missed the complete-split */
  735. urb->status = -EPROTO;
  736. } else if (token & QTD_STS_DBE) {
  737. urb->status = (QTD_PID(token) == 1) /* IN ? */
  738. ? -ENOSR /* hc couldn't read data */
  739. : -ECOMM; /* hc couldn't write data */
  740. } else if (token & QTD_STS_XACT) {
  741. /* timeout, bad crc, wrong PID, etc; retried */
  742. if (QTD_CERR(token))
  743. urb->status = -EPIPE;
  744. else {
  745. oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n",
  746. urb->dev->devpath,
  747. usb_pipeendpoint(urb->pipe),
  748. usb_pipein(urb->pipe) ? "in" : "out");
  749. urb->status = -EPROTO;
  750. }
  751. /* CERR nonzero + no errors + halt --> stall */
  752. } else if (QTD_CERR(token))
  753. urb->status = -EPIPE;
  754. else /* unknown */
  755. urb->status = -EPROTO;
  756. oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n",
  757. usb_pipedevice(urb->pipe),
  758. usb_pipeendpoint(urb->pipe),
  759. usb_pipein(urb->pipe) ? "in" : "out",
  760. token, urb->status);
  761. }
  762. }
  763. static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb)
  764. __releases(oxu->lock)
  765. __acquires(oxu->lock)
  766. {
  767. if (likely(urb->hcpriv != NULL)) {
  768. struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv;
  769. /* S-mask in a QH means it's an interrupt urb */
  770. if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) {
  771. /* ... update hc-wide periodic stats (for usbfs) */
  772. oxu_to_hcd(oxu)->self.bandwidth_int_reqs--;
  773. }
  774. qh_put(qh);
  775. }
  776. urb->hcpriv = NULL;
  777. switch (urb->status) {
  778. case -EINPROGRESS: /* success */
  779. urb->status = 0;
  780. default: /* fault */
  781. break;
  782. case -EREMOTEIO: /* fault or normal */
  783. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  784. urb->status = 0;
  785. break;
  786. case -ECONNRESET: /* canceled */
  787. case -ENOENT:
  788. break;
  789. }
  790. #ifdef OXU_URB_TRACE
  791. oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n",
  792. __func__, urb->dev->devpath, urb,
  793. usb_pipeendpoint(urb->pipe),
  794. usb_pipein(urb->pipe) ? "in" : "out",
  795. urb->status,
  796. urb->actual_length, urb->transfer_buffer_length);
  797. #endif
  798. /* complete() can reenter this HCD */
  799. spin_unlock(&oxu->lock);
  800. usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status);
  801. spin_lock(&oxu->lock);
  802. }
  803. static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
  804. static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
  805. static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
  806. static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
  807. #define HALT_BIT cpu_to_le32(QTD_STS_HALT)
  808. /* Process and free completed qtds for a qh, returning URBs to drivers.
  809. * Chases up to qh->hw_current. Returns number of completions called,
  810. * indicating how much "real" work we did.
  811. */
  812. static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh)
  813. {
  814. struct ehci_qtd *last = NULL, *end = qh->dummy;
  815. struct list_head *entry, *tmp;
  816. int stopped;
  817. unsigned count = 0;
  818. int do_status = 0;
  819. u8 state;
  820. struct oxu_murb *murb = NULL;
  821. if (unlikely(list_empty(&qh->qtd_list)))
  822. return count;
  823. /* completions (or tasks on other cpus) must never clobber HALT
  824. * till we've gone through and cleaned everything up, even when
  825. * they add urbs to this qh's queue or mark them for unlinking.
  826. *
  827. * NOTE: unlinking expects to be done in queue order.
  828. */
  829. state = qh->qh_state;
  830. qh->qh_state = QH_STATE_COMPLETING;
  831. stopped = (state == QH_STATE_IDLE);
  832. /* remove de-activated QTDs from front of queue.
  833. * after faults (including short reads), cleanup this urb
  834. * then let the queue advance.
  835. * if queue is stopped, handles unlinks.
  836. */
  837. list_for_each_safe(entry, tmp, &qh->qtd_list) {
  838. struct ehci_qtd *qtd;
  839. struct urb *urb;
  840. u32 token = 0;
  841. qtd = list_entry(entry, struct ehci_qtd, qtd_list);
  842. urb = qtd->urb;
  843. /* Clean up any state from previous QTD ...*/
  844. if (last) {
  845. if (likely(last->urb != urb)) {
  846. if (last->urb->complete == NULL) {
  847. murb = (struct oxu_murb *) last->urb;
  848. last->urb = murb->main;
  849. if (murb->last) {
  850. ehci_urb_done(oxu, last->urb);
  851. count++;
  852. }
  853. oxu_murb_free(oxu, murb);
  854. } else {
  855. ehci_urb_done(oxu, last->urb);
  856. count++;
  857. }
  858. }
  859. oxu_qtd_free(oxu, last);
  860. last = NULL;
  861. }
  862. /* ignore urbs submitted during completions we reported */
  863. if (qtd == end)
  864. break;
  865. /* hardware copies qtd out of qh overlay */
  866. rmb();
  867. token = le32_to_cpu(qtd->hw_token);
  868. /* always clean up qtds the hc de-activated */
  869. if ((token & QTD_STS_ACTIVE) == 0) {
  870. if ((token & QTD_STS_HALT) != 0) {
  871. stopped = 1;
  872. /* magic dummy for some short reads; qh won't advance.
  873. * that silicon quirk can kick in with this dummy too.
  874. */
  875. } else if (IS_SHORT_READ(token) &&
  876. !(qtd->hw_alt_next & EHCI_LIST_END)) {
  877. stopped = 1;
  878. goto halt;
  879. }
  880. /* stop scanning when we reach qtds the hc is using */
  881. } else if (likely(!stopped &&
  882. HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) {
  883. break;
  884. } else {
  885. stopped = 1;
  886. if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)))
  887. urb->status = -ESHUTDOWN;
  888. /* ignore active urbs unless some previous qtd
  889. * for the urb faulted (including short read) or
  890. * its urb was canceled. we may patch qh or qtds.
  891. */
  892. if (likely(urb->status == -EINPROGRESS))
  893. continue;
  894. /* issue status after short control reads */
  895. if (unlikely(do_status != 0)
  896. && QTD_PID(token) == 0 /* OUT */) {
  897. do_status = 0;
  898. continue;
  899. }
  900. /* token in overlay may be most current */
  901. if (state == QH_STATE_IDLE
  902. && cpu_to_le32(qtd->qtd_dma)
  903. == qh->hw_current)
  904. token = le32_to_cpu(qh->hw_token);
  905. /* force halt for unlinked or blocked qh, so we'll
  906. * patch the qh later and so that completions can't
  907. * activate it while we "know" it's stopped.
  908. */
  909. if ((HALT_BIT & qh->hw_token) == 0) {
  910. halt:
  911. qh->hw_token |= HALT_BIT;
  912. wmb();
  913. }
  914. }
  915. /* Remove it from the queue */
  916. qtd_copy_status(oxu, urb->complete ?
  917. urb : ((struct oxu_murb *) urb)->main,
  918. qtd->length, token);
  919. if ((usb_pipein(qtd->urb->pipe)) &&
  920. (NULL != qtd->transfer_buffer))
  921. memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length);
  922. do_status = (urb->status == -EREMOTEIO)
  923. && usb_pipecontrol(urb->pipe);
  924. if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
  925. last = list_entry(qtd->qtd_list.prev,
  926. struct ehci_qtd, qtd_list);
  927. last->hw_next = qtd->hw_next;
  928. }
  929. list_del(&qtd->qtd_list);
  930. last = qtd;
  931. }
  932. /* last urb's completion might still need calling */
  933. if (likely(last != NULL)) {
  934. if (last->urb->complete == NULL) {
  935. murb = (struct oxu_murb *) last->urb;
  936. last->urb = murb->main;
  937. if (murb->last) {
  938. ehci_urb_done(oxu, last->urb);
  939. count++;
  940. }
  941. oxu_murb_free(oxu, murb);
  942. } else {
  943. ehci_urb_done(oxu, last->urb);
  944. count++;
  945. }
  946. oxu_qtd_free(oxu, last);
  947. }
  948. /* restore original state; caller must unlink or relink */
  949. qh->qh_state = state;
  950. /* be sure the hardware's done with the qh before refreshing
  951. * it after fault cleanup, or recovering from silicon wrongly
  952. * overlaying the dummy qtd (which reduces DMA chatter).
  953. */
  954. if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) {
  955. switch (state) {
  956. case QH_STATE_IDLE:
  957. qh_refresh(oxu, qh);
  958. break;
  959. case QH_STATE_LINKED:
  960. /* should be rare for periodic transfers,
  961. * except maybe high bandwidth ...
  962. */
  963. if ((cpu_to_le32(QH_SMASK)
  964. & qh->hw_info2) != 0) {
  965. intr_deschedule(oxu, qh);
  966. (void) qh_schedule(oxu, qh);
  967. } else
  968. unlink_async(oxu, qh);
  969. break;
  970. /* otherwise, unlink already started */
  971. }
  972. }
  973. return count;
  974. }
  975. /* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */
  976. #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
  977. /* ... and packet size, for any kind of endpoint descriptor */
  978. #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
  979. /* Reverse of qh_urb_transaction: free a list of TDs.
  980. * used for cleanup after errors, before HC sees an URB's TDs.
  981. */
  982. static void qtd_list_free(struct oxu_hcd *oxu,
  983. struct urb *urb, struct list_head *qtd_list)
  984. {
  985. struct list_head *entry, *temp;
  986. list_for_each_safe(entry, temp, qtd_list) {
  987. struct ehci_qtd *qtd;
  988. qtd = list_entry(entry, struct ehci_qtd, qtd_list);
  989. list_del(&qtd->qtd_list);
  990. oxu_qtd_free(oxu, qtd);
  991. }
  992. }
  993. /* Create a list of filled qtds for this URB; won't link into qh.
  994. */
  995. static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu,
  996. struct urb *urb,
  997. struct list_head *head,
  998. gfp_t flags)
  999. {
  1000. struct ehci_qtd *qtd, *qtd_prev;
  1001. dma_addr_t buf;
  1002. int len, maxpacket;
  1003. int is_input;
  1004. u32 token;
  1005. void *transfer_buf = NULL;
  1006. int ret;
  1007. /*
  1008. * URBs map to sequences of QTDs: one logical transaction
  1009. */
  1010. qtd = ehci_qtd_alloc(oxu);
  1011. if (unlikely(!qtd))
  1012. return NULL;
  1013. list_add_tail(&qtd->qtd_list, head);
  1014. qtd->urb = urb;
  1015. token = QTD_STS_ACTIVE;
  1016. token |= (EHCI_TUNE_CERR << 10);
  1017. /* for split transactions, SplitXState initialized to zero */
  1018. len = urb->transfer_buffer_length;
  1019. is_input = usb_pipein(urb->pipe);
  1020. if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input)
  1021. urb->transfer_buffer = phys_to_virt(urb->transfer_dma);
  1022. if (usb_pipecontrol(urb->pipe)) {
  1023. /* SETUP pid */
  1024. ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest));
  1025. if (ret)
  1026. goto cleanup;
  1027. qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest),
  1028. token | (2 /* "setup" */ << 8), 8);
  1029. memcpy(qtd->buffer, qtd->urb->setup_packet,
  1030. sizeof(struct usb_ctrlrequest));
  1031. /* ... and always at least one more pid */
  1032. token ^= QTD_TOGGLE;
  1033. qtd_prev = qtd;
  1034. qtd = ehci_qtd_alloc(oxu);
  1035. if (unlikely(!qtd))
  1036. goto cleanup;
  1037. qtd->urb = urb;
  1038. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1039. list_add_tail(&qtd->qtd_list, head);
  1040. /* for zero length DATA stages, STATUS is always IN */
  1041. if (len == 0)
  1042. token |= (1 /* "in" */ << 8);
  1043. }
  1044. /*
  1045. * Data transfer stage: buffer setup
  1046. */
  1047. ret = oxu_buf_alloc(oxu, qtd, len);
  1048. if (ret)
  1049. goto cleanup;
  1050. buf = qtd->buffer_dma;
  1051. transfer_buf = urb->transfer_buffer;
  1052. if (!is_input)
  1053. memcpy(qtd->buffer, qtd->urb->transfer_buffer, len);
  1054. if (is_input)
  1055. token |= (1 /* "in" */ << 8);
  1056. /* else it's already initted to "out" pid (0 << 8) */
  1057. maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
  1058. /*
  1059. * buffer gets wrapped in one or more qtds;
  1060. * last one may be "short" (including zero len)
  1061. * and may serve as a control status ack
  1062. */
  1063. for (;;) {
  1064. int this_qtd_len;
  1065. this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket);
  1066. qtd->transfer_buffer = transfer_buf;
  1067. len -= this_qtd_len;
  1068. buf += this_qtd_len;
  1069. transfer_buf += this_qtd_len;
  1070. if (is_input)
  1071. qtd->hw_alt_next = oxu->async->hw_alt_next;
  1072. /* qh makes control packets use qtd toggle; maybe switch it */
  1073. if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
  1074. token ^= QTD_TOGGLE;
  1075. if (likely(len <= 0))
  1076. break;
  1077. qtd_prev = qtd;
  1078. qtd = ehci_qtd_alloc(oxu);
  1079. if (unlikely(!qtd))
  1080. goto cleanup;
  1081. if (likely(len > 0)) {
  1082. ret = oxu_buf_alloc(oxu, qtd, len);
  1083. if (ret)
  1084. goto cleanup;
  1085. }
  1086. qtd->urb = urb;
  1087. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1088. list_add_tail(&qtd->qtd_list, head);
  1089. }
  1090. /* unless the bulk/interrupt caller wants a chance to clean
  1091. * up after short reads, hc should advance qh past this urb
  1092. */
  1093. if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
  1094. || usb_pipecontrol(urb->pipe)))
  1095. qtd->hw_alt_next = EHCI_LIST_END;
  1096. /*
  1097. * control requests may need a terminating data "status" ack;
  1098. * bulk ones may need a terminating short packet (zero length).
  1099. */
  1100. if (likely(urb->transfer_buffer_length != 0)) {
  1101. int one_more = 0;
  1102. if (usb_pipecontrol(urb->pipe)) {
  1103. one_more = 1;
  1104. token ^= 0x0100; /* "in" <--> "out" */
  1105. token |= QTD_TOGGLE; /* force DATA1 */
  1106. } else if (usb_pipebulk(urb->pipe)
  1107. && (urb->transfer_flags & URB_ZERO_PACKET)
  1108. && !(urb->transfer_buffer_length % maxpacket)) {
  1109. one_more = 1;
  1110. }
  1111. if (one_more) {
  1112. qtd_prev = qtd;
  1113. qtd = ehci_qtd_alloc(oxu);
  1114. if (unlikely(!qtd))
  1115. goto cleanup;
  1116. qtd->urb = urb;
  1117. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1118. list_add_tail(&qtd->qtd_list, head);
  1119. /* never any data in such packets */
  1120. qtd_fill(qtd, 0, 0, token, 0);
  1121. }
  1122. }
  1123. /* by default, enable interrupt on urb completion */
  1124. qtd->hw_token |= cpu_to_le32(QTD_IOC);
  1125. return head;
  1126. cleanup:
  1127. qtd_list_free(oxu, urb, head);
  1128. return NULL;
  1129. }
  1130. /* Each QH holds a qtd list; a QH is used for everything except iso.
  1131. *
  1132. * For interrupt urbs, the scheduler must set the microframe scheduling
  1133. * mask(s) each time the QH gets scheduled. For highspeed, that's
  1134. * just one microframe in the s-mask. For split interrupt transactions
  1135. * there are additional complications: c-mask, maybe FSTNs.
  1136. */
  1137. static struct ehci_qh *qh_make(struct oxu_hcd *oxu,
  1138. struct urb *urb, gfp_t flags)
  1139. {
  1140. struct ehci_qh *qh = oxu_qh_alloc(oxu);
  1141. u32 info1 = 0, info2 = 0;
  1142. int is_input, type;
  1143. int maxp = 0;
  1144. if (!qh)
  1145. return qh;
  1146. /*
  1147. * init endpoint/device data for this QH
  1148. */
  1149. info1 |= usb_pipeendpoint(urb->pipe) << 8;
  1150. info1 |= usb_pipedevice(urb->pipe) << 0;
  1151. is_input = usb_pipein(urb->pipe);
  1152. type = usb_pipetype(urb->pipe);
  1153. maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input);
  1154. /* Compute interrupt scheduling parameters just once, and save.
  1155. * - allowing for high bandwidth, how many nsec/uframe are used?
  1156. * - split transactions need a second CSPLIT uframe; same question
  1157. * - splits also need a schedule gap (for full/low speed I/O)
  1158. * - qh has a polling interval
  1159. *
  1160. * For control/bulk requests, the HC or TT handles these.
  1161. */
  1162. if (type == PIPE_INTERRUPT) {
  1163. qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
  1164. is_input, 0,
  1165. hb_mult(maxp) * max_packet(maxp)));
  1166. qh->start = NO_FRAME;
  1167. if (urb->dev->speed == USB_SPEED_HIGH) {
  1168. qh->c_usecs = 0;
  1169. qh->gap_uf = 0;
  1170. qh->period = urb->interval >> 3;
  1171. if (qh->period == 0 && urb->interval != 1) {
  1172. /* NOTE interval 2 or 4 uframes could work.
  1173. * But interval 1 scheduling is simpler, and
  1174. * includes high bandwidth.
  1175. */
  1176. dbg("intr period %d uframes, NYET!",
  1177. urb->interval);
  1178. goto done;
  1179. }
  1180. } else {
  1181. struct usb_tt *tt = urb->dev->tt;
  1182. int think_time;
  1183. /* gap is f(FS/LS transfer times) */
  1184. qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
  1185. is_input, 0, maxp) / (125 * 1000);
  1186. /* FIXME this just approximates SPLIT/CSPLIT times */
  1187. if (is_input) { /* SPLIT, gap, CSPLIT+DATA */
  1188. qh->c_usecs = qh->usecs + HS_USECS(0);
  1189. qh->usecs = HS_USECS(1);
  1190. } else { /* SPLIT+DATA, gap, CSPLIT */
  1191. qh->usecs += HS_USECS(1);
  1192. qh->c_usecs = HS_USECS(0);
  1193. }
  1194. think_time = tt ? tt->think_time : 0;
  1195. qh->tt_usecs = NS_TO_US(think_time +
  1196. usb_calc_bus_time(urb->dev->speed,
  1197. is_input, 0, max_packet(maxp)));
  1198. qh->period = urb->interval;
  1199. }
  1200. }
  1201. /* support for tt scheduling, and access to toggles */
  1202. qh->dev = urb->dev;
  1203. /* using TT? */
  1204. switch (urb->dev->speed) {
  1205. case USB_SPEED_LOW:
  1206. info1 |= (1 << 12); /* EPS "low" */
  1207. /* FALL THROUGH */
  1208. case USB_SPEED_FULL:
  1209. /* EPS 0 means "full" */
  1210. if (type != PIPE_INTERRUPT)
  1211. info1 |= (EHCI_TUNE_RL_TT << 28);
  1212. if (type == PIPE_CONTROL) {
  1213. info1 |= (1 << 27); /* for TT */
  1214. info1 |= 1 << 14; /* toggle from qtd */
  1215. }
  1216. info1 |= maxp << 16;
  1217. info2 |= (EHCI_TUNE_MULT_TT << 30);
  1218. info2 |= urb->dev->ttport << 23;
  1219. /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
  1220. break;
  1221. case USB_SPEED_HIGH: /* no TT involved */
  1222. info1 |= (2 << 12); /* EPS "high" */
  1223. if (type == PIPE_CONTROL) {
  1224. info1 |= (EHCI_TUNE_RL_HS << 28);
  1225. info1 |= 64 << 16; /* usb2 fixed maxpacket */
  1226. info1 |= 1 << 14; /* toggle from qtd */
  1227. info2 |= (EHCI_TUNE_MULT_HS << 30);
  1228. } else if (type == PIPE_BULK) {
  1229. info1 |= (EHCI_TUNE_RL_HS << 28);
  1230. info1 |= 512 << 16; /* usb2 fixed maxpacket */
  1231. info2 |= (EHCI_TUNE_MULT_HS << 30);
  1232. } else { /* PIPE_INTERRUPT */
  1233. info1 |= max_packet(maxp) << 16;
  1234. info2 |= hb_mult(maxp) << 30;
  1235. }
  1236. break;
  1237. default:
  1238. dbg("bogus dev %p speed %d", urb->dev, urb->dev->speed);
  1239. done:
  1240. qh_put(qh);
  1241. return NULL;
  1242. }
  1243. /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
  1244. /* init as live, toggle clear, advance to dummy */
  1245. qh->qh_state = QH_STATE_IDLE;
  1246. qh->hw_info1 = cpu_to_le32(info1);
  1247. qh->hw_info2 = cpu_to_le32(info2);
  1248. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
  1249. qh_refresh(oxu, qh);
  1250. return qh;
  1251. }
  1252. /* Move qh (and its qtds) onto async queue; maybe enable queue.
  1253. */
  1254. static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1255. {
  1256. __le32 dma = QH_NEXT(qh->qh_dma);
  1257. struct ehci_qh *head;
  1258. /* (re)start the async schedule? */
  1259. head = oxu->async;
  1260. timer_action_done(oxu, TIMER_ASYNC_OFF);
  1261. if (!head->qh_next.qh) {
  1262. u32 cmd = readl(&oxu->regs->command);
  1263. if (!(cmd & CMD_ASE)) {
  1264. /* in case a clear of CMD_ASE didn't take yet */
  1265. (void)handshake(oxu, &oxu->regs->status,
  1266. STS_ASS, 0, 150);
  1267. cmd |= CMD_ASE | CMD_RUN;
  1268. writel(cmd, &oxu->regs->command);
  1269. oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
  1270. /* posted write need not be known to HC yet ... */
  1271. }
  1272. }
  1273. /* clear halt and/or toggle; and maybe recover from silicon quirk */
  1274. if (qh->qh_state == QH_STATE_IDLE)
  1275. qh_refresh(oxu, qh);
  1276. /* splice right after start */
  1277. qh->qh_next = head->qh_next;
  1278. qh->hw_next = head->hw_next;
  1279. wmb();
  1280. head->qh_next.qh = qh;
  1281. head->hw_next = dma;
  1282. qh->qh_state = QH_STATE_LINKED;
  1283. /* qtd completions reported later by interrupt */
  1284. }
  1285. #define QH_ADDR_MASK cpu_to_le32(0x7f)
  1286. /*
  1287. * For control/bulk/interrupt, return QH with these TDs appended.
  1288. * Allocates and initializes the QH if necessary.
  1289. * Returns null if it can't allocate a QH it needs to.
  1290. * If the QH has TDs (urbs) already, that's great.
  1291. */
  1292. static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu,
  1293. struct urb *urb, struct list_head *qtd_list,
  1294. int epnum, void **ptr)
  1295. {
  1296. struct ehci_qh *qh = NULL;
  1297. qh = (struct ehci_qh *) *ptr;
  1298. if (unlikely(qh == NULL)) {
  1299. /* can't sleep here, we have oxu->lock... */
  1300. qh = qh_make(oxu, urb, GFP_ATOMIC);
  1301. *ptr = qh;
  1302. }
  1303. if (likely(qh != NULL)) {
  1304. struct ehci_qtd *qtd;
  1305. if (unlikely(list_empty(qtd_list)))
  1306. qtd = NULL;
  1307. else
  1308. qtd = list_entry(qtd_list->next, struct ehci_qtd,
  1309. qtd_list);
  1310. /* control qh may need patching ... */
  1311. if (unlikely(epnum == 0)) {
  1312. /* usb_reset_device() briefly reverts to address 0 */
  1313. if (usb_pipedevice(urb->pipe) == 0)
  1314. qh->hw_info1 &= ~QH_ADDR_MASK;
  1315. }
  1316. /* just one way to queue requests: swap with the dummy qtd.
  1317. * only hc or qh_refresh() ever modify the overlay.
  1318. */
  1319. if (likely(qtd != NULL)) {
  1320. struct ehci_qtd *dummy;
  1321. dma_addr_t dma;
  1322. __le32 token;
  1323. /* to avoid racing the HC, use the dummy td instead of
  1324. * the first td of our list (becomes new dummy). both
  1325. * tds stay deactivated until we're done, when the
  1326. * HC is allowed to fetch the old dummy (4.10.2).
  1327. */
  1328. token = qtd->hw_token;
  1329. qtd->hw_token = HALT_BIT;
  1330. wmb();
  1331. dummy = qh->dummy;
  1332. dma = dummy->qtd_dma;
  1333. *dummy = *qtd;
  1334. dummy->qtd_dma = dma;
  1335. list_del(&qtd->qtd_list);
  1336. list_add(&dummy->qtd_list, qtd_list);
  1337. list_splice(qtd_list, qh->qtd_list.prev);
  1338. ehci_qtd_init(qtd, qtd->qtd_dma);
  1339. qh->dummy = qtd;
  1340. /* hc must see the new dummy at list end */
  1341. dma = qtd->qtd_dma;
  1342. qtd = list_entry(qh->qtd_list.prev,
  1343. struct ehci_qtd, qtd_list);
  1344. qtd->hw_next = QTD_NEXT(dma);
  1345. /* let the hc process these next qtds */
  1346. dummy->hw_token = (token & ~(0x80));
  1347. wmb();
  1348. dummy->hw_token = token;
  1349. urb->hcpriv = qh_get(qh);
  1350. }
  1351. }
  1352. return qh;
  1353. }
  1354. static int submit_async(struct oxu_hcd *oxu, struct urb *urb,
  1355. struct list_head *qtd_list, gfp_t mem_flags)
  1356. {
  1357. struct ehci_qtd *qtd;
  1358. int epnum;
  1359. unsigned long flags;
  1360. struct ehci_qh *qh = NULL;
  1361. int rc = 0;
  1362. qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
  1363. epnum = urb->ep->desc.bEndpointAddress;
  1364. #ifdef OXU_URB_TRACE
  1365. oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
  1366. __func__, urb->dev->devpath, urb,
  1367. epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
  1368. urb->transfer_buffer_length,
  1369. qtd, urb->ep->hcpriv);
  1370. #endif
  1371. spin_lock_irqsave(&oxu->lock, flags);
  1372. if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
  1373. &oxu_to_hcd(oxu)->flags))) {
  1374. rc = -ESHUTDOWN;
  1375. goto done;
  1376. }
  1377. qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1378. if (unlikely(qh == NULL)) {
  1379. rc = -ENOMEM;
  1380. goto done;
  1381. }
  1382. /* Control/bulk operations through TTs don't need scheduling,
  1383. * the HC and TT handle it when the TT has a buffer ready.
  1384. */
  1385. if (likely(qh->qh_state == QH_STATE_IDLE))
  1386. qh_link_async(oxu, qh_get(qh));
  1387. done:
  1388. spin_unlock_irqrestore(&oxu->lock, flags);
  1389. if (unlikely(qh == NULL))
  1390. qtd_list_free(oxu, urb, qtd_list);
  1391. return rc;
  1392. }
  1393. /* The async qh for the qtds being reclaimed are now unlinked from the HC */
  1394. static void end_unlink_async(struct oxu_hcd *oxu)
  1395. {
  1396. struct ehci_qh *qh = oxu->reclaim;
  1397. struct ehci_qh *next;
  1398. timer_action_done(oxu, TIMER_IAA_WATCHDOG);
  1399. qh->qh_state = QH_STATE_IDLE;
  1400. qh->qh_next.qh = NULL;
  1401. qh_put(qh); /* refcount from reclaim */
  1402. /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
  1403. next = qh->reclaim;
  1404. oxu->reclaim = next;
  1405. oxu->reclaim_ready = 0;
  1406. qh->reclaim = NULL;
  1407. qh_completions(oxu, qh);
  1408. if (!list_empty(&qh->qtd_list)
  1409. && HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1410. qh_link_async(oxu, qh);
  1411. else {
  1412. qh_put(qh); /* refcount from async list */
  1413. /* it's not free to turn the async schedule on/off; leave it
  1414. * active but idle for a while once it empties.
  1415. */
  1416. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)
  1417. && oxu->async->qh_next.qh == NULL)
  1418. timer_action(oxu, TIMER_ASYNC_OFF);
  1419. }
  1420. if (next) {
  1421. oxu->reclaim = NULL;
  1422. start_unlink_async(oxu, next);
  1423. }
  1424. }
  1425. /* makes sure the async qh will become idle */
  1426. /* caller must own oxu->lock */
  1427. static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1428. {
  1429. int cmd = readl(&oxu->regs->command);
  1430. struct ehci_qh *prev;
  1431. #ifdef DEBUG
  1432. assert_spin_locked(&oxu->lock);
  1433. if (oxu->reclaim || (qh->qh_state != QH_STATE_LINKED
  1434. && qh->qh_state != QH_STATE_UNLINK_WAIT))
  1435. BUG();
  1436. #endif
  1437. /* stop async schedule right now? */
  1438. if (unlikely(qh == oxu->async)) {
  1439. /* can't get here without STS_ASS set */
  1440. if (oxu_to_hcd(oxu)->state != HC_STATE_HALT
  1441. && !oxu->reclaim) {
  1442. /* ... and CMD_IAAD clear */
  1443. writel(cmd & ~CMD_ASE, &oxu->regs->command);
  1444. wmb();
  1445. /* handshake later, if we need to */
  1446. timer_action_done(oxu, TIMER_ASYNC_OFF);
  1447. }
  1448. return;
  1449. }
  1450. qh->qh_state = QH_STATE_UNLINK;
  1451. oxu->reclaim = qh = qh_get(qh);
  1452. prev = oxu->async;
  1453. while (prev->qh_next.qh != qh)
  1454. prev = prev->qh_next.qh;
  1455. prev->hw_next = qh->hw_next;
  1456. prev->qh_next = qh->qh_next;
  1457. wmb();
  1458. if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) {
  1459. /* if (unlikely(qh->reclaim != 0))
  1460. * this will recurse, probably not much
  1461. */
  1462. end_unlink_async(oxu);
  1463. return;
  1464. }
  1465. oxu->reclaim_ready = 0;
  1466. cmd |= CMD_IAAD;
  1467. writel(cmd, &oxu->regs->command);
  1468. (void) readl(&oxu->regs->command);
  1469. timer_action(oxu, TIMER_IAA_WATCHDOG);
  1470. }
  1471. static void scan_async(struct oxu_hcd *oxu)
  1472. {
  1473. struct ehci_qh *qh;
  1474. enum ehci_timer_action action = TIMER_IO_WATCHDOG;
  1475. if (!++(oxu->stamp))
  1476. oxu->stamp++;
  1477. timer_action_done(oxu, TIMER_ASYNC_SHRINK);
  1478. rescan:
  1479. qh = oxu->async->qh_next.qh;
  1480. if (likely(qh != NULL)) {
  1481. do {
  1482. /* clean any finished work for this qh */
  1483. if (!list_empty(&qh->qtd_list)
  1484. && qh->stamp != oxu->stamp) {
  1485. int temp;
  1486. /* unlinks could happen here; completion
  1487. * reporting drops the lock. rescan using
  1488. * the latest schedule, but don't rescan
  1489. * qhs we already finished (no looping).
  1490. */
  1491. qh = qh_get(qh);
  1492. qh->stamp = oxu->stamp;
  1493. temp = qh_completions(oxu, qh);
  1494. qh_put(qh);
  1495. if (temp != 0)
  1496. goto rescan;
  1497. }
  1498. /* unlink idle entries, reducing HC PCI usage as well
  1499. * as HCD schedule-scanning costs. delay for any qh
  1500. * we just scanned, there's a not-unusual case that it
  1501. * doesn't stay idle for long.
  1502. * (plus, avoids some kind of re-activation race.)
  1503. */
  1504. if (list_empty(&qh->qtd_list)) {
  1505. if (qh->stamp == oxu->stamp)
  1506. action = TIMER_ASYNC_SHRINK;
  1507. else if (!oxu->reclaim
  1508. && qh->qh_state == QH_STATE_LINKED)
  1509. start_unlink_async(oxu, qh);
  1510. }
  1511. qh = qh->qh_next.qh;
  1512. } while (qh);
  1513. }
  1514. if (action == TIMER_ASYNC_SHRINK)
  1515. timer_action(oxu, TIMER_ASYNC_SHRINK);
  1516. }
  1517. /*
  1518. * periodic_next_shadow - return "next" pointer on shadow list
  1519. * @periodic: host pointer to qh/itd/sitd
  1520. * @tag: hardware tag for type of this record
  1521. */
  1522. static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic,
  1523. __le32 tag)
  1524. {
  1525. switch (tag) {
  1526. default:
  1527. case Q_TYPE_QH:
  1528. return &periodic->qh->qh_next;
  1529. }
  1530. }
  1531. /* caller must hold oxu->lock */
  1532. static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr)
  1533. {
  1534. union ehci_shadow *prev_p = &oxu->pshadow[frame];
  1535. __le32 *hw_p = &oxu->periodic[frame];
  1536. union ehci_shadow here = *prev_p;
  1537. /* find predecessor of "ptr"; hw and shadow lists are in sync */
  1538. while (here.ptr && here.ptr != ptr) {
  1539. prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p));
  1540. hw_p = here.hw_next;
  1541. here = *prev_p;
  1542. }
  1543. /* an interrupt entry (at list end) could have been shared */
  1544. if (!here.ptr)
  1545. return;
  1546. /* update shadow and hardware lists ... the old "next" pointers
  1547. * from ptr may still be in use, the caller updates them.
  1548. */
  1549. *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p));
  1550. *hw_p = *here.hw_next;
  1551. }
  1552. /* how many of the uframe's 125 usecs are allocated? */
  1553. static unsigned short periodic_usecs(struct oxu_hcd *oxu,
  1554. unsigned frame, unsigned uframe)
  1555. {
  1556. __le32 *hw_p = &oxu->periodic[frame];
  1557. union ehci_shadow *q = &oxu->pshadow[frame];
  1558. unsigned usecs = 0;
  1559. while (q->ptr) {
  1560. switch (Q_NEXT_TYPE(*hw_p)) {
  1561. case Q_TYPE_QH:
  1562. default:
  1563. /* is it in the S-mask? */
  1564. if (q->qh->hw_info2 & cpu_to_le32(1 << uframe))
  1565. usecs += q->qh->usecs;
  1566. /* ... or C-mask? */
  1567. if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe)))
  1568. usecs += q->qh->c_usecs;
  1569. hw_p = &q->qh->hw_next;
  1570. q = &q->qh->qh_next;
  1571. break;
  1572. }
  1573. }
  1574. #ifdef DEBUG
  1575. if (usecs > 100)
  1576. oxu_err(oxu, "uframe %d sched overrun: %d usecs\n",
  1577. frame * 8 + uframe, usecs);
  1578. #endif
  1579. return usecs;
  1580. }
  1581. static int enable_periodic(struct oxu_hcd *oxu)
  1582. {
  1583. u32 cmd;
  1584. int status;
  1585. /* did clearing PSE did take effect yet?
  1586. * takes effect only at frame boundaries...
  1587. */
  1588. status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125);
  1589. if (status != 0) {
  1590. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  1591. return status;
  1592. }
  1593. cmd = readl(&oxu->regs->command) | CMD_PSE;
  1594. writel(cmd, &oxu->regs->command);
  1595. /* posted write ... PSS happens later */
  1596. oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
  1597. /* make sure ehci_work scans these */
  1598. oxu->next_uframe = readl(&oxu->regs->frame_index)
  1599. % (oxu->periodic_size << 3);
  1600. return 0;
  1601. }
  1602. static int disable_periodic(struct oxu_hcd *oxu)
  1603. {
  1604. u32 cmd;
  1605. int status;
  1606. /* did setting PSE not take effect yet?
  1607. * takes effect only at frame boundaries...
  1608. */
  1609. status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125);
  1610. if (status != 0) {
  1611. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  1612. return status;
  1613. }
  1614. cmd = readl(&oxu->regs->command) & ~CMD_PSE;
  1615. writel(cmd, &oxu->regs->command);
  1616. /* posted write ... */
  1617. oxu->next_uframe = -1;
  1618. return 0;
  1619. }
  1620. /* periodic schedule slots have iso tds (normal or split) first, then a
  1621. * sparse tree for active interrupt transfers.
  1622. *
  1623. * this just links in a qh; caller guarantees uframe masks are set right.
  1624. * no FSTN support (yet; oxu 0.96+)
  1625. */
  1626. static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1627. {
  1628. unsigned i;
  1629. unsigned period = qh->period;
  1630. dev_dbg(&qh->dev->dev,
  1631. "link qh%d-%04x/%p start %d [%d/%d us]\n",
  1632. period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
  1633. qh, qh->start, qh->usecs, qh->c_usecs);
  1634. /* high bandwidth, or otherwise every microframe */
  1635. if (period == 0)
  1636. period = 1;
  1637. for (i = qh->start; i < oxu->periodic_size; i += period) {
  1638. union ehci_shadow *prev = &oxu->pshadow[i];
  1639. __le32 *hw_p = &oxu->periodic[i];
  1640. union ehci_shadow here = *prev;
  1641. __le32 type = 0;
  1642. /* skip the iso nodes at list head */
  1643. while (here.ptr) {
  1644. type = Q_NEXT_TYPE(*hw_p);
  1645. if (type == Q_TYPE_QH)
  1646. break;
  1647. prev = periodic_next_shadow(prev, type);
  1648. hw_p = &here.qh->hw_next;
  1649. here = *prev;
  1650. }
  1651. /* sorting each branch by period (slow-->fast)
  1652. * enables sharing interior tree nodes
  1653. */
  1654. while (here.ptr && qh != here.qh) {
  1655. if (qh->period > here.qh->period)
  1656. break;
  1657. prev = &here.qh->qh_next;
  1658. hw_p = &here.qh->hw_next;
  1659. here = *prev;
  1660. }
  1661. /* link in this qh, unless some earlier pass did that */
  1662. if (qh != here.qh) {
  1663. qh->qh_next = here;
  1664. if (here.qh)
  1665. qh->hw_next = *hw_p;
  1666. wmb();
  1667. prev->qh = qh;
  1668. *hw_p = QH_NEXT(qh->qh_dma);
  1669. }
  1670. }
  1671. qh->qh_state = QH_STATE_LINKED;
  1672. qh_get(qh);
  1673. /* update per-qh bandwidth for usbfs */
  1674. oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period
  1675. ? ((qh->usecs + qh->c_usecs) / qh->period)
  1676. : (qh->usecs * 8);
  1677. /* maybe enable periodic schedule processing */
  1678. if (!oxu->periodic_sched++)
  1679. return enable_periodic(oxu);
  1680. return 0;
  1681. }
  1682. static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1683. {
  1684. unsigned i;
  1685. unsigned period;
  1686. /* FIXME:
  1687. * IF this isn't high speed
  1688. * and this qh is active in the current uframe
  1689. * (and overlay token SplitXstate is false?)
  1690. * THEN
  1691. * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore");
  1692. */
  1693. /* high bandwidth, or otherwise part of every microframe */
  1694. period = qh->period;
  1695. if (period == 0)
  1696. period = 1;
  1697. for (i = qh->start; i < oxu->periodic_size; i += period)
  1698. periodic_unlink(oxu, i, qh);
  1699. /* update per-qh bandwidth for usbfs */
  1700. oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period
  1701. ? ((qh->usecs + qh->c_usecs) / qh->period)
  1702. : (qh->usecs * 8);
  1703. dev_dbg(&qh->dev->dev,
  1704. "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
  1705. qh->period,
  1706. le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
  1707. qh, qh->start, qh->usecs, qh->c_usecs);
  1708. /* qh->qh_next still "live" to HC */
  1709. qh->qh_state = QH_STATE_UNLINK;
  1710. qh->qh_next.ptr = NULL;
  1711. qh_put(qh);
  1712. /* maybe turn off periodic schedule */
  1713. oxu->periodic_sched--;
  1714. if (!oxu->periodic_sched)
  1715. (void) disable_periodic(oxu);
  1716. }
  1717. static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1718. {
  1719. unsigned wait;
  1720. qh_unlink_periodic(oxu, qh);
  1721. /* simple/paranoid: always delay, expecting the HC needs to read
  1722. * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
  1723. * expect khubd to clean up after any CSPLITs we won't issue.
  1724. * active high speed queues may need bigger delays...
  1725. */
  1726. if (list_empty(&qh->qtd_list)
  1727. || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0)
  1728. wait = 2;
  1729. else
  1730. wait = 55; /* worst case: 3 * 1024 */
  1731. udelay(wait);
  1732. qh->qh_state = QH_STATE_IDLE;
  1733. qh->hw_next = EHCI_LIST_END;
  1734. wmb();
  1735. }
  1736. static int check_period(struct oxu_hcd *oxu,
  1737. unsigned frame, unsigned uframe,
  1738. unsigned period, unsigned usecs)
  1739. {
  1740. int claimed;
  1741. /* complete split running into next frame?
  1742. * given FSTN support, we could sometimes check...
  1743. */
  1744. if (uframe >= 8)
  1745. return 0;
  1746. /*
  1747. * 80% periodic == 100 usec/uframe available
  1748. * convert "usecs we need" to "max already claimed"
  1749. */
  1750. usecs = 100 - usecs;
  1751. /* we "know" 2 and 4 uframe intervals were rejected; so
  1752. * for period 0, check _every_ microframe in the schedule.
  1753. */
  1754. if (unlikely(period == 0)) {
  1755. do {
  1756. for (uframe = 0; uframe < 7; uframe++) {
  1757. claimed = periodic_usecs(oxu, frame, uframe);
  1758. if (claimed > usecs)
  1759. return 0;
  1760. }
  1761. } while ((frame += 1) < oxu->periodic_size);
  1762. /* just check the specified uframe, at that period */
  1763. } else {
  1764. do {
  1765. claimed = periodic_usecs(oxu, frame, uframe);
  1766. if (claimed > usecs)
  1767. return 0;
  1768. } while ((frame += period) < oxu->periodic_size);
  1769. }
  1770. return 1;
  1771. }
  1772. static int check_intr_schedule(struct oxu_hcd *oxu,
  1773. unsigned frame, unsigned uframe,
  1774. const struct ehci_qh *qh, __le32 *c_maskp)
  1775. {
  1776. int retval = -ENOSPC;
  1777. if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
  1778. goto done;
  1779. if (!check_period(oxu, frame, uframe, qh->period, qh->usecs))
  1780. goto done;
  1781. if (!qh->c_usecs) {
  1782. retval = 0;
  1783. *c_maskp = 0;
  1784. goto done;
  1785. }
  1786. done:
  1787. return retval;
  1788. }
  1789. /* "first fit" scheduling policy used the first time through,
  1790. * or when the previous schedule slot can't be re-used.
  1791. */
  1792. static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1793. {
  1794. int status;
  1795. unsigned uframe;
  1796. __le32 c_mask;
  1797. unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
  1798. qh_refresh(oxu, qh);
  1799. qh->hw_next = EHCI_LIST_END;
  1800. frame = qh->start;
  1801. /* reuse the previous schedule slots, if we can */
  1802. if (frame < qh->period) {
  1803. uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK);
  1804. status = check_intr_schedule(oxu, frame, --uframe,
  1805. qh, &c_mask);
  1806. } else {
  1807. uframe = 0;
  1808. c_mask = 0;
  1809. status = -ENOSPC;
  1810. }
  1811. /* else scan the schedule to find a group of slots such that all
  1812. * uframes have enough periodic bandwidth available.
  1813. */
  1814. if (status) {
  1815. /* "normal" case, uframing flexible except with splits */
  1816. if (qh->period) {
  1817. frame = qh->period - 1;
  1818. do {
  1819. for (uframe = 0; uframe < 8; uframe++) {
  1820. status = check_intr_schedule(oxu,
  1821. frame, uframe, qh,
  1822. &c_mask);
  1823. if (status == 0)
  1824. break;
  1825. }
  1826. } while (status && frame--);
  1827. /* qh->period == 0 means every uframe */
  1828. } else {
  1829. frame = 0;
  1830. status = check_intr_schedule(oxu, 0, 0, qh, &c_mask);
  1831. }
  1832. if (status)
  1833. goto done;
  1834. qh->start = frame;
  1835. /* reset S-frame and (maybe) C-frame masks */
  1836. qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK));
  1837. qh->hw_info2 |= qh->period
  1838. ? cpu_to_le32(1 << uframe)
  1839. : cpu_to_le32(QH_SMASK);
  1840. qh->hw_info2 |= c_mask;
  1841. } else
  1842. oxu_dbg(oxu, "reused qh %p schedule\n", qh);
  1843. /* stuff into the periodic schedule */
  1844. status = qh_link_periodic(oxu, qh);
  1845. done:
  1846. return status;
  1847. }
  1848. static int intr_submit(struct oxu_hcd *oxu, struct urb *urb,
  1849. struct list_head *qtd_list, gfp_t mem_flags)
  1850. {
  1851. unsigned epnum;
  1852. unsigned long flags;
  1853. struct ehci_qh *qh;
  1854. int status = 0;
  1855. struct list_head empty;
  1856. /* get endpoint and transfer/schedule data */
  1857. epnum = urb->ep->desc.bEndpointAddress;
  1858. spin_lock_irqsave(&oxu->lock, flags);
  1859. if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
  1860. &oxu_to_hcd(oxu)->flags))) {
  1861. status = -ESHUTDOWN;
  1862. goto done;
  1863. }
  1864. /* get qh and force any scheduling errors */
  1865. INIT_LIST_HEAD(&empty);
  1866. qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv);
  1867. if (qh == NULL) {
  1868. status = -ENOMEM;
  1869. goto done;
  1870. }
  1871. if (qh->qh_state == QH_STATE_IDLE) {
  1872. status = qh_schedule(oxu, qh);
  1873. if (status != 0)
  1874. goto done;
  1875. }
  1876. /* then queue the urb's tds to the qh */
  1877. qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1878. BUG_ON(qh == NULL);
  1879. /* ... update usbfs periodic stats */
  1880. oxu_to_hcd(oxu)->self.bandwidth_int_reqs++;
  1881. done:
  1882. spin_unlock_irqrestore(&oxu->lock, flags);
  1883. if (status)
  1884. qtd_list_free(oxu, urb, qtd_list);
  1885. return status;
  1886. }
  1887. static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb,
  1888. gfp_t mem_flags)
  1889. {
  1890. oxu_dbg(oxu, "iso support is missing!\n");
  1891. return -ENOSYS;
  1892. }
  1893. static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb,
  1894. gfp_t mem_flags)
  1895. {
  1896. oxu_dbg(oxu, "split iso support is missing!\n");
  1897. return -ENOSYS;
  1898. }
  1899. static void scan_periodic(struct oxu_hcd *oxu)
  1900. {
  1901. unsigned frame, clock, now_uframe, mod;
  1902. unsigned modified;
  1903. mod = oxu->periodic_size << 3;
  1904. /*
  1905. * When running, scan from last scan point up to "now"
  1906. * else clean up by scanning everything that's left.
  1907. * Touches as few pages as possible: cache-friendly.
  1908. */
  1909. now_uframe = oxu->next_uframe;
  1910. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1911. clock = readl(&oxu->regs->frame_index);
  1912. else
  1913. clock = now_uframe + mod - 1;
  1914. clock %= mod;
  1915. for (;;) {
  1916. union ehci_shadow q, *q_p;
  1917. __le32 type, *hw_p;
  1918. unsigned uframes;
  1919. /* don't scan past the live uframe */
  1920. frame = now_uframe >> 3;
  1921. if (frame == (clock >> 3))
  1922. uframes = now_uframe & 0x07;
  1923. else {
  1924. /* safe to scan the whole frame at once */
  1925. now_uframe |= 0x07;
  1926. uframes = 8;
  1927. }
  1928. restart:
  1929. /* scan each element in frame's queue for completions */
  1930. q_p = &oxu->pshadow[frame];
  1931. hw_p = &oxu->periodic[frame];
  1932. q.ptr = q_p->ptr;
  1933. type = Q_NEXT_TYPE(*hw_p);
  1934. modified = 0;
  1935. while (q.ptr != NULL) {
  1936. union ehci_shadow temp;
  1937. int live;
  1938. live = HC_IS_RUNNING(oxu_to_hcd(oxu)->state);
  1939. switch (type) {
  1940. case Q_TYPE_QH:
  1941. /* handle any completions */
  1942. temp.qh = qh_get(q.qh);
  1943. type = Q_NEXT_TYPE(q.qh->hw_next);
  1944. q = q.qh->qh_next;
  1945. modified = qh_completions(oxu, temp.qh);
  1946. if (unlikely(list_empty(&temp.qh->qtd_list)))
  1947. intr_deschedule(oxu, temp.qh);
  1948. qh_put(temp.qh);
  1949. break;
  1950. default:
  1951. dbg("corrupt type %d frame %d shadow %p",
  1952. type, frame, q.ptr);
  1953. q.ptr = NULL;
  1954. }
  1955. /* assume completion callbacks modify the queue */
  1956. if (unlikely(modified))
  1957. goto restart;
  1958. }
  1959. /* Stop when we catch up to the HC */
  1960. /* FIXME: this assumes we won't get lapped when
  1961. * latencies climb; that should be rare, but...
  1962. * detect it, and just go all the way around.
  1963. * FLR might help detect this case, so long as latencies
  1964. * don't exceed periodic_size msec (default 1.024 sec).
  1965. */
  1966. /* FIXME: likewise assumes HC doesn't halt mid-scan */
  1967. if (now_uframe == clock) {
  1968. unsigned now;
  1969. if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1970. break;
  1971. oxu->next_uframe = now_uframe;
  1972. now = readl(&oxu->regs->frame_index) % mod;
  1973. if (now_uframe == now)
  1974. break;
  1975. /* rescan the rest of this frame, then ... */
  1976. clock = now;
  1977. } else {
  1978. now_uframe++;
  1979. now_uframe %= mod;
  1980. }
  1981. }
  1982. }
  1983. /* On some systems, leaving remote wakeup enabled prevents system shutdown.
  1984. * The firmware seems to think that powering off is a wakeup event!
  1985. * This routine turns off remote wakeup and everything else, on all ports.
  1986. */
  1987. static void ehci_turn_off_all_ports(struct oxu_hcd *oxu)
  1988. {
  1989. int port = HCS_N_PORTS(oxu->hcs_params);
  1990. while (port--)
  1991. writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
  1992. }
  1993. static void ehci_port_power(struct oxu_hcd *oxu, int is_on)
  1994. {
  1995. unsigned port;
  1996. if (!HCS_PPC(oxu->hcs_params))
  1997. return;
  1998. oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down");
  1999. for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; )
  2000. (void) oxu_hub_control(oxu_to_hcd(oxu),
  2001. is_on ? SetPortFeature : ClearPortFeature,
  2002. USB_PORT_FEAT_POWER,
  2003. port--, NULL, 0);
  2004. msleep(20);
  2005. }
  2006. /* Called from some interrupts, timers, and so on.
  2007. * It calls driver completion functions, after dropping oxu->lock.
  2008. */
  2009. static void ehci_work(struct oxu_hcd *oxu)
  2010. {
  2011. timer_action_done(oxu, TIMER_IO_WATCHDOG);
  2012. if (oxu->reclaim_ready)
  2013. end_unlink_async(oxu);
  2014. /* another CPU may drop oxu->lock during a schedule scan while
  2015. * it reports urb completions. this flag guards against bogus
  2016. * attempts at re-entrant schedule scanning.
  2017. */
  2018. if (oxu->scanning)
  2019. return;
  2020. oxu->scanning = 1;
  2021. scan_async(oxu);
  2022. if (oxu->next_uframe != -1)
  2023. scan_periodic(oxu);
  2024. oxu->scanning = 0;
  2025. /* the IO watchdog guards against hardware or driver bugs that
  2026. * misplace IRQs, and should let us run completely without IRQs.
  2027. * such lossage has been observed on both VT6202 and VT8235.
  2028. */
  2029. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) &&
  2030. (oxu->async->qh_next.ptr != NULL ||
  2031. oxu->periodic_sched != 0))
  2032. timer_action(oxu, TIMER_IO_WATCHDOG);
  2033. }
  2034. static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  2035. {
  2036. /* if we need to use IAA and it's busy, defer */
  2037. if (qh->qh_state == QH_STATE_LINKED
  2038. && oxu->reclaim
  2039. && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) {
  2040. struct ehci_qh *last;
  2041. for (last = oxu->reclaim;
  2042. last->reclaim;
  2043. last = last->reclaim)
  2044. continue;
  2045. qh->qh_state = QH_STATE_UNLINK_WAIT;
  2046. last->reclaim = qh;
  2047. /* bypass IAA if the hc can't care */
  2048. } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim)
  2049. end_unlink_async(oxu);
  2050. /* something else might have unlinked the qh by now */
  2051. if (qh->qh_state == QH_STATE_LINKED)
  2052. start_unlink_async(oxu, qh);
  2053. }
  2054. /*
  2055. * USB host controller methods
  2056. */
  2057. static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd)
  2058. {
  2059. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2060. u32 status, pcd_status = 0;
  2061. int bh;
  2062. spin_lock(&oxu->lock);
  2063. status = readl(&oxu->regs->status);
  2064. /* e.g. cardbus physical eject */
  2065. if (status == ~(u32) 0) {
  2066. oxu_dbg(oxu, "device removed\n");
  2067. goto dead;
  2068. }
  2069. status &= INTR_MASK;
  2070. if (!status) { /* irq sharing? */
  2071. spin_unlock(&oxu->lock);
  2072. return IRQ_NONE;
  2073. }
  2074. /* clear (just) interrupts */
  2075. writel(status, &oxu->regs->status);
  2076. readl(&oxu->regs->command); /* unblock posted write */
  2077. bh = 0;
  2078. #ifdef OXU_VERBOSE_DEBUG
  2079. /* unrequested/ignored: Frame List Rollover */
  2080. dbg_status(oxu, "irq", status);
  2081. #endif
  2082. /* INT, ERR, and IAA interrupt rates can be throttled */
  2083. /* normal [4.15.1.2] or error [4.15.1.1] completion */
  2084. if (likely((status & (STS_INT|STS_ERR)) != 0))
  2085. bh = 1;
  2086. /* complete the unlinking of some qh [4.15.2.3] */
  2087. if (status & STS_IAA) {
  2088. oxu->reclaim_ready = 1;
  2089. bh = 1;
  2090. }
  2091. /* remote wakeup [4.3.1] */
  2092. if (status & STS_PCD) {
  2093. unsigned i = HCS_N_PORTS(oxu->hcs_params);
  2094. pcd_status = status;
  2095. /* resume root hub? */
  2096. if (!(readl(&oxu->regs->command) & CMD_RUN))
  2097. usb_hcd_resume_root_hub(hcd);
  2098. while (i--) {
  2099. int pstatus = readl(&oxu->regs->port_status[i]);
  2100. if (pstatus & PORT_OWNER)
  2101. continue;
  2102. if (!(pstatus & PORT_RESUME)
  2103. || oxu->reset_done[i] != 0)
  2104. continue;
  2105. /* start 20 msec resume signaling from this port,
  2106. * and make khubd collect PORT_STAT_C_SUSPEND to
  2107. * stop that signaling.
  2108. */
  2109. oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
  2110. oxu_dbg(oxu, "port %d remote wakeup\n", i + 1);
  2111. mod_timer(&hcd->rh_timer, oxu->reset_done[i]);
  2112. }
  2113. }
  2114. /* PCI errors [4.15.2.4] */
  2115. if (unlikely((status & STS_FATAL) != 0)) {
  2116. /* bogus "fatal" IRQs appear on some chips... why? */
  2117. status = readl(&oxu->regs->status);
  2118. dbg_cmd(oxu, "fatal", readl(&oxu->regs->command));
  2119. dbg_status(oxu, "fatal", status);
  2120. if (status & STS_HALT) {
  2121. oxu_err(oxu, "fatal error\n");
  2122. dead:
  2123. ehci_reset(oxu);
  2124. writel(0, &oxu->regs->configured_flag);
  2125. /* generic layer kills/unlinks all urbs, then
  2126. * uses oxu_stop to clean up the rest
  2127. */
  2128. bh = 1;
  2129. }
  2130. }
  2131. if (bh)
  2132. ehci_work(oxu);
  2133. spin_unlock(&oxu->lock);
  2134. if (pcd_status & STS_PCD)
  2135. usb_hcd_poll_rh_status(hcd);
  2136. return IRQ_HANDLED;
  2137. }
  2138. static irqreturn_t oxu_irq(struct usb_hcd *hcd)
  2139. {
  2140. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2141. int ret = IRQ_HANDLED;
  2142. u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS);
  2143. u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET);
  2144. /* Disable all interrupt */
  2145. oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable);
  2146. if ((oxu->is_otg && (status & OXU_USBOTGI)) ||
  2147. (!oxu->is_otg && (status & OXU_USBSPHI)))
  2148. oxu210_hcd_irq(hcd);
  2149. else
  2150. ret = IRQ_NONE;
  2151. /* Enable all interrupt back */
  2152. oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable);
  2153. return ret;
  2154. }
  2155. static void oxu_watchdog(unsigned long param)
  2156. {
  2157. struct oxu_hcd *oxu = (struct oxu_hcd *) param;
  2158. unsigned long flags;
  2159. spin_lock_irqsave(&oxu->lock, flags);
  2160. /* lost IAA irqs wedge things badly; seen with a vt8235 */
  2161. if (oxu->reclaim) {
  2162. u32 status = readl(&oxu->regs->status);
  2163. if (status & STS_IAA) {
  2164. oxu_vdbg(oxu, "lost IAA\n");
  2165. writel(STS_IAA, &oxu->regs->status);
  2166. oxu->reclaim_ready = 1;
  2167. }
  2168. }
  2169. /* stop async processing after it's idled a bit */
  2170. if (test_bit(TIMER_ASYNC_OFF, &oxu->actions))
  2171. start_unlink_async(oxu, oxu->async);
  2172. /* oxu could run by timer, without IRQs ... */
  2173. ehci_work(oxu);
  2174. spin_unlock_irqrestore(&oxu->lock, flags);
  2175. }
  2176. /* One-time init, only for memory state.
  2177. */
  2178. static int oxu_hcd_init(struct usb_hcd *hcd)
  2179. {
  2180. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2181. u32 temp;
  2182. int retval;
  2183. u32 hcc_params;
  2184. spin_lock_init(&oxu->lock);
  2185. init_timer(&oxu->watchdog);
  2186. oxu->watchdog.function = oxu_watchdog;
  2187. oxu->watchdog.data = (unsigned long) oxu;
  2188. /*
  2189. * hw default: 1K periodic list heads, one per frame.
  2190. * periodic_size can shrink by USBCMD update if hcc_params allows.
  2191. */
  2192. oxu->periodic_size = DEFAULT_I_TDPS;
  2193. retval = ehci_mem_init(oxu, GFP_KERNEL);
  2194. if (retval < 0)
  2195. return retval;
  2196. /* controllers may cache some of the periodic schedule ... */
  2197. hcc_params = readl(&oxu->caps->hcc_params);
  2198. if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */
  2199. oxu->i_thresh = 8;
  2200. else /* N microframes cached */
  2201. oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  2202. oxu->reclaim = NULL;
  2203. oxu->reclaim_ready = 0;
  2204. oxu->next_uframe = -1;
  2205. /*
  2206. * dedicate a qh for the async ring head, since we couldn't unlink
  2207. * a 'real' qh without stopping the async schedule [4.8]. use it
  2208. * as the 'reclamation list head' too.
  2209. * its dummy is used in hw_alt_next of many tds, to prevent the qh
  2210. * from automatically advancing to the next td after short reads.
  2211. */
  2212. oxu->async->qh_next.qh = NULL;
  2213. oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma);
  2214. oxu->async->hw_info1 = cpu_to_le32(QH_HEAD);
  2215. oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT);
  2216. oxu->async->hw_qtd_next = EHCI_LIST_END;
  2217. oxu->async->qh_state = QH_STATE_LINKED;
  2218. oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma);
  2219. /* clear interrupt enables, set irq latency */
  2220. if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
  2221. log2_irq_thresh = 0;
  2222. temp = 1 << (16 + log2_irq_thresh);
  2223. if (HCC_CANPARK(hcc_params)) {
  2224. /* HW default park == 3, on hardware that supports it (like
  2225. * NVidia and ALI silicon), maximizes throughput on the async
  2226. * schedule by avoiding QH fetches between transfers.
  2227. *
  2228. * With fast usb storage devices and NForce2, "park" seems to
  2229. * make problems: throughput reduction (!), data errors...
  2230. */
  2231. if (park) {
  2232. park = min(park, (unsigned) 3);
  2233. temp |= CMD_PARK;
  2234. temp |= park << 8;
  2235. }
  2236. oxu_dbg(oxu, "park %d\n", park);
  2237. }
  2238. if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
  2239. /* periodic schedule size can be smaller than default */
  2240. temp &= ~(3 << 2);
  2241. temp |= (EHCI_TUNE_FLS << 2);
  2242. }
  2243. oxu->command = temp;
  2244. return 0;
  2245. }
  2246. /* Called during probe() after chip reset completes.
  2247. */
  2248. static int oxu_reset(struct usb_hcd *hcd)
  2249. {
  2250. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2251. int ret;
  2252. spin_lock_init(&oxu->mem_lock);
  2253. INIT_LIST_HEAD(&oxu->urb_list);
  2254. oxu->urb_len = 0;
  2255. /* FIMXE */
  2256. hcd->self.controller->dma_mask = NULL;
  2257. if (oxu->is_otg) {
  2258. oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET;
  2259. oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \
  2260. HC_LENGTH(readl(&oxu->caps->hc_capbase));
  2261. oxu->mem = hcd->regs + OXU_SPH_MEM;
  2262. } else {
  2263. oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET;
  2264. oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \
  2265. HC_LENGTH(readl(&oxu->caps->hc_capbase));
  2266. oxu->mem = hcd->regs + OXU_OTG_MEM;
  2267. }
  2268. oxu->hcs_params = readl(&oxu->caps->hcs_params);
  2269. oxu->sbrn = 0x20;
  2270. ret = oxu_hcd_init(hcd);
  2271. if (ret)
  2272. return ret;
  2273. return 0;
  2274. }
  2275. static int oxu_run(struct usb_hcd *hcd)
  2276. {
  2277. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2278. int retval;
  2279. u32 temp, hcc_params;
  2280. hcd->uses_new_polling = 1;
  2281. hcd->poll_rh = 0;
  2282. /* EHCI spec section 4.1 */
  2283. retval = ehci_reset(oxu);
  2284. if (retval != 0) {
  2285. ehci_mem_cleanup(oxu);
  2286. return retval;
  2287. }
  2288. writel(oxu->periodic_dma, &oxu->regs->frame_list);
  2289. writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
  2290. /* hcc_params controls whether oxu->regs->segment must (!!!)
  2291. * be used; it constrains QH/ITD/SITD and QTD locations.
  2292. * pci_pool consistent memory always uses segment zero.
  2293. * streaming mappings for I/O buffers, like pci_map_single(),
  2294. * can return segments above 4GB, if the device allows.
  2295. *
  2296. * NOTE: the dma mask is visible through dma_supported(), so
  2297. * drivers can pass this info along ... like NETIF_F_HIGHDMA,
  2298. * Scsi_Host.highmem_io, and so forth. It's readonly to all
  2299. * host side drivers though.
  2300. */
  2301. hcc_params = readl(&oxu->caps->hcc_params);
  2302. if (HCC_64BIT_ADDR(hcc_params))
  2303. writel(0, &oxu->regs->segment);
  2304. oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE |
  2305. CMD_ASE | CMD_RESET);
  2306. oxu->command |= CMD_RUN;
  2307. writel(oxu->command, &oxu->regs->command);
  2308. dbg_cmd(oxu, "init", oxu->command);
  2309. /*
  2310. * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
  2311. * are explicitly handed to companion controller(s), so no TT is
  2312. * involved with the root hub. (Except where one is integrated,
  2313. * and there's no companion controller unless maybe for USB OTG.)
  2314. */
  2315. hcd->state = HC_STATE_RUNNING;
  2316. writel(FLAG_CF, &oxu->regs->configured_flag);
  2317. readl(&oxu->regs->command); /* unblock posted writes */
  2318. temp = HC_VERSION(readl(&oxu->caps->hc_capbase));
  2319. oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n",
  2320. ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f),
  2321. temp >> 8, temp & 0xff, DRIVER_VERSION,
  2322. ignore_oc ? ", overcurrent ignored" : "");
  2323. writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */
  2324. return 0;
  2325. }
  2326. static void oxu_stop(struct usb_hcd *hcd)
  2327. {
  2328. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2329. /* Turn off port power on all root hub ports. */
  2330. ehci_port_power(oxu, 0);
  2331. /* no more interrupts ... */
  2332. del_timer_sync(&oxu->watchdog);
  2333. spin_lock_irq(&oxu->lock);
  2334. if (HC_IS_RUNNING(hcd->state))
  2335. ehci_quiesce(oxu);
  2336. ehci_reset(oxu);
  2337. writel(0, &oxu->regs->intr_enable);
  2338. spin_unlock_irq(&oxu->lock);
  2339. /* let companion controllers work when we aren't */
  2340. writel(0, &oxu->regs->configured_flag);
  2341. /* root hub is shut down separately (first, when possible) */
  2342. spin_lock_irq(&oxu->lock);
  2343. if (oxu->async)
  2344. ehci_work(oxu);
  2345. spin_unlock_irq(&oxu->lock);
  2346. ehci_mem_cleanup(oxu);
  2347. dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status));
  2348. }
  2349. /* Kick in for silicon on any bus (not just pci, etc).
  2350. * This forcibly disables dma and IRQs, helping kexec and other cases
  2351. * where the next system software may expect clean state.
  2352. */
  2353. static void oxu_shutdown(struct usb_hcd *hcd)
  2354. {
  2355. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2356. (void) ehci_halt(oxu);
  2357. ehci_turn_off_all_ports(oxu);
  2358. /* make BIOS/etc use companion controller during reboot */
  2359. writel(0, &oxu->regs->configured_flag);
  2360. /* unblock posted writes */
  2361. readl(&oxu->regs->configured_flag);
  2362. }
  2363. /* Non-error returns are a promise to giveback() the urb later
  2364. * we drop ownership so next owner (or urb unlink) can get it
  2365. *
  2366. * urb + dev is in hcd.self.controller.urb_list
  2367. * we're queueing TDs onto software and hardware lists
  2368. *
  2369. * hcd-specific init for hcpriv hasn't been done yet
  2370. *
  2371. * NOTE: control, bulk, and interrupt share the same code to append TDs
  2372. * to a (possibly active) QH, and the same QH scanning code.
  2373. */
  2374. static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  2375. gfp_t mem_flags)
  2376. {
  2377. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2378. struct list_head qtd_list;
  2379. INIT_LIST_HEAD(&qtd_list);
  2380. switch (usb_pipetype(urb->pipe)) {
  2381. case PIPE_CONTROL:
  2382. case PIPE_BULK:
  2383. default:
  2384. if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
  2385. return -ENOMEM;
  2386. return submit_async(oxu, urb, &qtd_list, mem_flags);
  2387. case PIPE_INTERRUPT:
  2388. if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
  2389. return -ENOMEM;
  2390. return intr_submit(oxu, urb, &qtd_list, mem_flags);
  2391. case PIPE_ISOCHRONOUS:
  2392. if (urb->dev->speed == USB_SPEED_HIGH)
  2393. return itd_submit(oxu, urb, mem_flags);
  2394. else
  2395. return sitd_submit(oxu, urb, mem_flags);
  2396. }
  2397. }
  2398. /* This function is responsible for breaking URBs with big data size
  2399. * into smaller size and processing small urbs in sequence.
  2400. */
  2401. static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  2402. gfp_t mem_flags)
  2403. {
  2404. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2405. int num, rem;
  2406. int transfer_buffer_length;
  2407. void *transfer_buffer;
  2408. struct urb *murb;
  2409. int i, ret;
  2410. /* If not bulk pipe just enqueue the URB */
  2411. if (!usb_pipebulk(urb->pipe))
  2412. return __oxu_urb_enqueue(hcd, urb, mem_flags);
  2413. /* Otherwise we should verify the USB transfer buffer size! */
  2414. transfer_buffer = urb->transfer_buffer;
  2415. transfer_buffer_length = urb->transfer_buffer_length;
  2416. num = urb->transfer_buffer_length / 4096;
  2417. rem = urb->transfer_buffer_length % 4096;
  2418. if (rem != 0)
  2419. num++;
  2420. /* If URB is smaller than 4096 bytes just enqueue it! */
  2421. if (num == 1)
  2422. return __oxu_urb_enqueue(hcd, urb, mem_flags);
  2423. /* Ok, we have more job to do! :) */
  2424. for (i = 0; i < num - 1; i++) {
  2425. /* Get free micro URB poll till a free urb is recieved */
  2426. do {
  2427. murb = (struct urb *) oxu_murb_alloc(oxu);
  2428. if (!murb)
  2429. schedule();
  2430. } while (!murb);
  2431. /* Coping the urb */
  2432. memcpy(murb, urb, sizeof(struct urb));
  2433. murb->transfer_buffer_length = 4096;
  2434. murb->transfer_buffer = transfer_buffer + i * 4096;
  2435. /* Null pointer for the encodes that this is a micro urb */
  2436. murb->complete = NULL;
  2437. ((struct oxu_murb *) murb)->main = urb;
  2438. ((struct oxu_murb *) murb)->last = 0;
  2439. /* This loop is to guarantee urb to be processed when there's
  2440. * not enough resources at a particular time by retrying.
  2441. */
  2442. do {
  2443. ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
  2444. if (ret)
  2445. schedule();
  2446. } while (ret);
  2447. }
  2448. /* Last urb requires special handling */
  2449. /* Get free micro URB poll till a free urb is recieved */
  2450. do {
  2451. murb = (struct urb *) oxu_murb_alloc(oxu);
  2452. if (!murb)
  2453. schedule();
  2454. } while (!murb);
  2455. /* Coping the urb */
  2456. memcpy(murb, urb, sizeof(struct urb));
  2457. murb->transfer_buffer_length = rem > 0 ? rem : 4096;
  2458. murb->transfer_buffer = transfer_buffer + (num - 1) * 4096;
  2459. /* Null pointer for the encodes that this is a micro urb */
  2460. murb->complete = NULL;
  2461. ((struct oxu_murb *) murb)->main = urb;
  2462. ((struct oxu_murb *) murb)->last = 1;
  2463. do {
  2464. ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
  2465. if (ret)
  2466. schedule();
  2467. } while (ret);
  2468. return ret;
  2469. }
  2470. /* Remove from hardware lists.
  2471. * Completions normally happen asynchronously
  2472. */
  2473. static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  2474. {
  2475. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2476. struct ehci_qh *qh;
  2477. unsigned long flags;
  2478. spin_lock_irqsave(&oxu->lock, flags);
  2479. switch (usb_pipetype(urb->pipe)) {
  2480. case PIPE_CONTROL:
  2481. case PIPE_BULK:
  2482. default:
  2483. qh = (struct ehci_qh *) urb->hcpriv;
  2484. if (!qh)
  2485. break;
  2486. unlink_async(oxu, qh);
  2487. break;
  2488. case PIPE_INTERRUPT:
  2489. qh = (struct ehci_qh *) urb->hcpriv;
  2490. if (!qh)
  2491. break;
  2492. switch (qh->qh_state) {
  2493. case QH_STATE_LINKED:
  2494. intr_deschedule(oxu, qh);
  2495. /* FALL THROUGH */
  2496. case QH_STATE_IDLE:
  2497. qh_completions(oxu, qh);
  2498. break;
  2499. default:
  2500. oxu_dbg(oxu, "bogus qh %p state %d\n",
  2501. qh, qh->qh_state);
  2502. goto done;
  2503. }
  2504. /* reschedule QH iff another request is queued */
  2505. if (!list_empty(&qh->qtd_list)
  2506. && HC_IS_RUNNING(hcd->state)) {
  2507. int status;
  2508. status = qh_schedule(oxu, qh);
  2509. spin_unlock_irqrestore(&oxu->lock, flags);
  2510. if (status != 0) {
  2511. /* shouldn't happen often, but ...
  2512. * FIXME kill those tds' urbs
  2513. */
  2514. err("can't reschedule qh %p, err %d",
  2515. qh, status);
  2516. }
  2517. return status;
  2518. }
  2519. break;
  2520. }
  2521. done:
  2522. spin_unlock_irqrestore(&oxu->lock, flags);
  2523. return 0;
  2524. }
  2525. /* Bulk qh holds the data toggle */
  2526. static void oxu_endpoint_disable(struct usb_hcd *hcd,
  2527. struct usb_host_endpoint *ep)
  2528. {
  2529. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2530. unsigned long flags;
  2531. struct ehci_qh *qh, *tmp;
  2532. /* ASSERT: any requests/urbs are being unlinked */
  2533. /* ASSERT: nobody can be submitting urbs for this any more */
  2534. rescan:
  2535. spin_lock_irqsave(&oxu->lock, flags);
  2536. qh = ep->hcpriv;
  2537. if (!qh)
  2538. goto done;
  2539. /* endpoints can be iso streams. for now, we don't
  2540. * accelerate iso completions ... so spin a while.
  2541. */
  2542. if (qh->hw_info1 == 0) {
  2543. oxu_vdbg(oxu, "iso delay\n");
  2544. goto idle_timeout;
  2545. }
  2546. if (!HC_IS_RUNNING(hcd->state))
  2547. qh->qh_state = QH_STATE_IDLE;
  2548. switch (qh->qh_state) {
  2549. case QH_STATE_LINKED:
  2550. for (tmp = oxu->async->qh_next.qh;
  2551. tmp && tmp != qh;
  2552. tmp = tmp->qh_next.qh)
  2553. continue;
  2554. /* periodic qh self-unlinks on empty */
  2555. if (!tmp)
  2556. goto nogood;
  2557. unlink_async(oxu, qh);
  2558. /* FALL THROUGH */
  2559. case QH_STATE_UNLINK: /* wait for hw to finish? */
  2560. idle_timeout:
  2561. spin_unlock_irqrestore(&oxu->lock, flags);
  2562. schedule_timeout_uninterruptible(1);
  2563. goto rescan;
  2564. case QH_STATE_IDLE: /* fully unlinked */
  2565. if (list_empty(&qh->qtd_list)) {
  2566. qh_put(qh);
  2567. break;
  2568. }
  2569. /* else FALL THROUGH */
  2570. default:
  2571. nogood:
  2572. /* caller was supposed to have unlinked any requests;
  2573. * that's not our job. just leak this memory.
  2574. */
  2575. oxu_err(oxu, "qh %p (#%02x) state %d%s\n",
  2576. qh, ep->desc.bEndpointAddress, qh->qh_state,
  2577. list_empty(&qh->qtd_list) ? "" : "(has tds)");
  2578. break;
  2579. }
  2580. ep->hcpriv = NULL;
  2581. done:
  2582. spin_unlock_irqrestore(&oxu->lock, flags);
  2583. return;
  2584. }
  2585. static int oxu_get_frame(struct usb_hcd *hcd)
  2586. {
  2587. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2588. return (readl(&oxu->regs->frame_index) >> 3) %
  2589. oxu->periodic_size;
  2590. }
  2591. /* Build "status change" packet (one or two bytes) from HC registers */
  2592. static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf)
  2593. {
  2594. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2595. u32 temp, mask, status = 0;
  2596. int ports, i, retval = 1;
  2597. unsigned long flags;
  2598. /* if !USB_SUSPEND, root hub timers won't get shut down ... */
  2599. if (!HC_IS_RUNNING(hcd->state))
  2600. return 0;
  2601. /* init status to no-changes */
  2602. buf[0] = 0;
  2603. ports = HCS_N_PORTS(oxu->hcs_params);
  2604. if (ports > 7) {
  2605. buf[1] = 0;
  2606. retval++;
  2607. }
  2608. /* Some boards (mostly VIA?) report bogus overcurrent indications,
  2609. * causing massive log spam unless we completely ignore them. It
  2610. * may be relevant that VIA VT8235 controlers, where PORT_POWER is
  2611. * always set, seem to clear PORT_OCC and PORT_CSC when writing to
  2612. * PORT_POWER; that's surprising, but maybe within-spec.
  2613. */
  2614. if (!ignore_oc)
  2615. mask = PORT_CSC | PORT_PEC | PORT_OCC;
  2616. else
  2617. mask = PORT_CSC | PORT_PEC;
  2618. /* no hub change reports (bit 0) for now (power, ...) */
  2619. /* port N changes (bit N)? */
  2620. spin_lock_irqsave(&oxu->lock, flags);
  2621. for (i = 0; i < ports; i++) {
  2622. temp = readl(&oxu->regs->port_status[i]);
  2623. /*
  2624. * Return status information even for ports with OWNER set.
  2625. * Otherwise khubd wouldn't see the disconnect event when a
  2626. * high-speed device is switched over to the companion
  2627. * controller by the user.
  2628. */
  2629. if (!(temp & PORT_CONNECT))
  2630. oxu->reset_done[i] = 0;
  2631. if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 &&
  2632. time_after_eq(jiffies, oxu->reset_done[i]))) {
  2633. if (i < 7)
  2634. buf[0] |= 1 << (i + 1);
  2635. else
  2636. buf[1] |= 1 << (i - 7);
  2637. status = STS_PCD;
  2638. }
  2639. }
  2640. /* FIXME autosuspend idle root hubs */
  2641. spin_unlock_irqrestore(&oxu->lock, flags);
  2642. return status ? retval : 0;
  2643. }
  2644. /* Returns the speed of a device attached to a port on the root hub. */
  2645. static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu,
  2646. unsigned int portsc)
  2647. {
  2648. switch ((portsc >> 26) & 3) {
  2649. case 0:
  2650. return 0;
  2651. case 1:
  2652. return USB_PORT_STAT_LOW_SPEED;
  2653. case 2:
  2654. default:
  2655. return USB_PORT_STAT_HIGH_SPEED;
  2656. }
  2657. }
  2658. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  2659. static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq,
  2660. u16 wValue, u16 wIndex, char *buf, u16 wLength)
  2661. {
  2662. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2663. int ports = HCS_N_PORTS(oxu->hcs_params);
  2664. u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1];
  2665. u32 temp, status;
  2666. unsigned long flags;
  2667. int retval = 0;
  2668. unsigned selector;
  2669. /*
  2670. * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
  2671. * HCS_INDICATOR may say we can change LEDs to off/amber/green.
  2672. * (track current state ourselves) ... blink for diagnostics,
  2673. * power, "this is the one", etc. EHCI spec supports this.
  2674. */
  2675. spin_lock_irqsave(&oxu->lock, flags);
  2676. switch (typeReq) {
  2677. case ClearHubFeature:
  2678. switch (wValue) {
  2679. case C_HUB_LOCAL_POWER:
  2680. case C_HUB_OVER_CURRENT:
  2681. /* no hub-wide feature/status flags */
  2682. break;
  2683. default:
  2684. goto error;
  2685. }
  2686. break;
  2687. case ClearPortFeature:
  2688. if (!wIndex || wIndex > ports)
  2689. goto error;
  2690. wIndex--;
  2691. temp = readl(status_reg);
  2692. /*
  2693. * Even if OWNER is set, so the port is owned by the
  2694. * companion controller, khubd needs to be able to clear
  2695. * the port-change status bits (especially
  2696. * USB_PORT_STAT_C_CONNECTION).
  2697. */
  2698. switch (wValue) {
  2699. case USB_PORT_FEAT_ENABLE:
  2700. writel(temp & ~PORT_PE, status_reg);
  2701. break;
  2702. case USB_PORT_FEAT_C_ENABLE:
  2703. writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
  2704. break;
  2705. case USB_PORT_FEAT_SUSPEND:
  2706. if (temp & PORT_RESET)
  2707. goto error;
  2708. if (temp & PORT_SUSPEND) {
  2709. if ((temp & PORT_PE) == 0)
  2710. goto error;
  2711. /* resume signaling for 20 msec */
  2712. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  2713. writel(temp | PORT_RESUME, status_reg);
  2714. oxu->reset_done[wIndex] = jiffies
  2715. + msecs_to_jiffies(20);
  2716. }
  2717. break;
  2718. case USB_PORT_FEAT_C_SUSPEND:
  2719. /* we auto-clear this feature */
  2720. break;
  2721. case USB_PORT_FEAT_POWER:
  2722. if (HCS_PPC(oxu->hcs_params))
  2723. writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
  2724. status_reg);
  2725. break;
  2726. case USB_PORT_FEAT_C_CONNECTION:
  2727. writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
  2728. break;
  2729. case USB_PORT_FEAT_C_OVER_CURRENT:
  2730. writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
  2731. break;
  2732. case USB_PORT_FEAT_C_RESET:
  2733. /* GetPortStatus clears reset */
  2734. break;
  2735. default:
  2736. goto error;
  2737. }
  2738. readl(&oxu->regs->command); /* unblock posted write */
  2739. break;
  2740. case GetHubDescriptor:
  2741. ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *)
  2742. buf);
  2743. break;
  2744. case GetHubStatus:
  2745. /* no hub-wide feature/status flags */
  2746. memset(buf, 0, 4);
  2747. break;
  2748. case GetPortStatus:
  2749. if (!wIndex || wIndex > ports)
  2750. goto error;
  2751. wIndex--;
  2752. status = 0;
  2753. temp = readl(status_reg);
  2754. /* wPortChange bits */
  2755. if (temp & PORT_CSC)
  2756. status |= USB_PORT_STAT_C_CONNECTION << 16;
  2757. if (temp & PORT_PEC)
  2758. status |= USB_PORT_STAT_C_ENABLE << 16;
  2759. if ((temp & PORT_OCC) && !ignore_oc)
  2760. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  2761. /* whoever resumes must GetPortStatus to complete it!! */
  2762. if (temp & PORT_RESUME) {
  2763. /* Remote Wakeup received? */
  2764. if (!oxu->reset_done[wIndex]) {
  2765. /* resume signaling for 20 msec */
  2766. oxu->reset_done[wIndex] = jiffies
  2767. + msecs_to_jiffies(20);
  2768. /* check the port again */
  2769. mod_timer(&oxu_to_hcd(oxu)->rh_timer,
  2770. oxu->reset_done[wIndex]);
  2771. }
  2772. /* resume completed? */
  2773. else if (time_after_eq(jiffies,
  2774. oxu->reset_done[wIndex])) {
  2775. status |= USB_PORT_STAT_C_SUSPEND << 16;
  2776. oxu->reset_done[wIndex] = 0;
  2777. /* stop resume signaling */
  2778. temp = readl(status_reg);
  2779. writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
  2780. status_reg);
  2781. retval = handshake(oxu, status_reg,
  2782. PORT_RESUME, 0, 2000 /* 2msec */);
  2783. if (retval != 0) {
  2784. oxu_err(oxu,
  2785. "port %d resume error %d\n",
  2786. wIndex + 1, retval);
  2787. goto error;
  2788. }
  2789. temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
  2790. }
  2791. }
  2792. /* whoever resets must GetPortStatus to complete it!! */
  2793. if ((temp & PORT_RESET)
  2794. && time_after_eq(jiffies,
  2795. oxu->reset_done[wIndex])) {
  2796. status |= USB_PORT_STAT_C_RESET << 16;
  2797. oxu->reset_done[wIndex] = 0;
  2798. /* force reset to complete */
  2799. writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
  2800. status_reg);
  2801. /* REVISIT: some hardware needs 550+ usec to clear
  2802. * this bit; seems too long to spin routinely...
  2803. */
  2804. retval = handshake(oxu, status_reg,
  2805. PORT_RESET, 0, 750);
  2806. if (retval != 0) {
  2807. oxu_err(oxu, "port %d reset error %d\n",
  2808. wIndex + 1, retval);
  2809. goto error;
  2810. }
  2811. /* see what we found out */
  2812. temp = check_reset_complete(oxu, wIndex, status_reg,
  2813. readl(status_reg));
  2814. }
  2815. /* transfer dedicated ports to the companion hc */
  2816. if ((temp & PORT_CONNECT) &&
  2817. test_bit(wIndex, &oxu->companion_ports)) {
  2818. temp &= ~PORT_RWC_BITS;
  2819. temp |= PORT_OWNER;
  2820. writel(temp, status_reg);
  2821. oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1);
  2822. temp = readl(status_reg);
  2823. }
  2824. /*
  2825. * Even if OWNER is set, there's no harm letting khubd
  2826. * see the wPortStatus values (they should all be 0 except
  2827. * for PORT_POWER anyway).
  2828. */
  2829. if (temp & PORT_CONNECT) {
  2830. status |= USB_PORT_STAT_CONNECTION;
  2831. /* status may be from integrated TT */
  2832. status |= oxu_port_speed(oxu, temp);
  2833. }
  2834. if (temp & PORT_PE)
  2835. status |= USB_PORT_STAT_ENABLE;
  2836. if (temp & (PORT_SUSPEND|PORT_RESUME))
  2837. status |= USB_PORT_STAT_SUSPEND;
  2838. if (temp & PORT_OC)
  2839. status |= USB_PORT_STAT_OVERCURRENT;
  2840. if (temp & PORT_RESET)
  2841. status |= USB_PORT_STAT_RESET;
  2842. if (temp & PORT_POWER)
  2843. status |= USB_PORT_STAT_POWER;
  2844. #ifndef OXU_VERBOSE_DEBUG
  2845. if (status & ~0xffff) /* only if wPortChange is interesting */
  2846. #endif
  2847. dbg_port(oxu, "GetStatus", wIndex + 1, temp);
  2848. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  2849. break;
  2850. case SetHubFeature:
  2851. switch (wValue) {
  2852. case C_HUB_LOCAL_POWER:
  2853. case C_HUB_OVER_CURRENT:
  2854. /* no hub-wide feature/status flags */
  2855. break;
  2856. default:
  2857. goto error;
  2858. }
  2859. break;
  2860. case SetPortFeature:
  2861. selector = wIndex >> 8;
  2862. wIndex &= 0xff;
  2863. if (!wIndex || wIndex > ports)
  2864. goto error;
  2865. wIndex--;
  2866. temp = readl(status_reg);
  2867. if (temp & PORT_OWNER)
  2868. break;
  2869. temp &= ~PORT_RWC_BITS;
  2870. switch (wValue) {
  2871. case USB_PORT_FEAT_SUSPEND:
  2872. if ((temp & PORT_PE) == 0
  2873. || (temp & PORT_RESET) != 0)
  2874. goto error;
  2875. if (device_may_wakeup(&hcd->self.root_hub->dev))
  2876. temp |= PORT_WAKE_BITS;
  2877. writel(temp | PORT_SUSPEND, status_reg);
  2878. break;
  2879. case USB_PORT_FEAT_POWER:
  2880. if (HCS_PPC(oxu->hcs_params))
  2881. writel(temp | PORT_POWER, status_reg);
  2882. break;
  2883. case USB_PORT_FEAT_RESET:
  2884. if (temp & PORT_RESUME)
  2885. goto error;
  2886. /* line status bits may report this as low speed,
  2887. * which can be fine if this root hub has a
  2888. * transaction translator built in.
  2889. */
  2890. oxu_vdbg(oxu, "port %d reset\n", wIndex + 1);
  2891. temp |= PORT_RESET;
  2892. temp &= ~PORT_PE;
  2893. /*
  2894. * caller must wait, then call GetPortStatus
  2895. * usb 2.0 spec says 50 ms resets on root
  2896. */
  2897. oxu->reset_done[wIndex] = jiffies
  2898. + msecs_to_jiffies(50);
  2899. writel(temp, status_reg);
  2900. break;
  2901. /* For downstream facing ports (these): one hub port is put
  2902. * into test mode according to USB2 11.24.2.13, then the hub
  2903. * must be reset (which for root hub now means rmmod+modprobe,
  2904. * or else system reboot). See EHCI 2.3.9 and 4.14 for info
  2905. * about the EHCI-specific stuff.
  2906. */
  2907. case USB_PORT_FEAT_TEST:
  2908. if (!selector || selector > 5)
  2909. goto error;
  2910. ehci_quiesce(oxu);
  2911. ehci_halt(oxu);
  2912. temp |= selector << 16;
  2913. writel(temp, status_reg);
  2914. break;
  2915. default:
  2916. goto error;
  2917. }
  2918. readl(&oxu->regs->command); /* unblock posted writes */
  2919. break;
  2920. default:
  2921. error:
  2922. /* "stall" on error */
  2923. retval = -EPIPE;
  2924. }
  2925. spin_unlock_irqrestore(&oxu->lock, flags);
  2926. return retval;
  2927. }
  2928. #ifdef CONFIG_PM
  2929. static int oxu_bus_suspend(struct usb_hcd *hcd)
  2930. {
  2931. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2932. int port;
  2933. int mask;
  2934. oxu_dbg(oxu, "suspend root hub\n");
  2935. if (time_before(jiffies, oxu->next_statechange))
  2936. msleep(5);
  2937. port = HCS_N_PORTS(oxu->hcs_params);
  2938. spin_lock_irq(&oxu->lock);
  2939. /* stop schedules, clean any completed work */
  2940. if (HC_IS_RUNNING(hcd->state)) {
  2941. ehci_quiesce(oxu);
  2942. hcd->state = HC_STATE_QUIESCING;
  2943. }
  2944. oxu->command = readl(&oxu->regs->command);
  2945. if (oxu->reclaim)
  2946. oxu->reclaim_ready = 1;
  2947. ehci_work(oxu);
  2948. /* Unlike other USB host controller types, EHCI doesn't have
  2949. * any notion of "global" or bus-wide suspend. The driver has
  2950. * to manually suspend all the active unsuspended ports, and
  2951. * then manually resume them in the bus_resume() routine.
  2952. */
  2953. oxu->bus_suspended = 0;
  2954. while (port--) {
  2955. u32 __iomem *reg = &oxu->regs->port_status[port];
  2956. u32 t1 = readl(reg) & ~PORT_RWC_BITS;
  2957. u32 t2 = t1;
  2958. /* keep track of which ports we suspend */
  2959. if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) &&
  2960. !(t1 & PORT_SUSPEND)) {
  2961. t2 |= PORT_SUSPEND;
  2962. set_bit(port, &oxu->bus_suspended);
  2963. }
  2964. /* enable remote wakeup on all ports */
  2965. if (device_may_wakeup(&hcd->self.root_hub->dev))
  2966. t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E;
  2967. else
  2968. t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E);
  2969. if (t1 != t2) {
  2970. oxu_vdbg(oxu, "port %d, %08x -> %08x\n",
  2971. port + 1, t1, t2);
  2972. writel(t2, reg);
  2973. }
  2974. }
  2975. /* turn off now-idle HC */
  2976. del_timer_sync(&oxu->watchdog);
  2977. ehci_halt(oxu);
  2978. hcd->state = HC_STATE_SUSPENDED;
  2979. /* allow remote wakeup */
  2980. mask = INTR_MASK;
  2981. if (!device_may_wakeup(&hcd->self.root_hub->dev))
  2982. mask &= ~STS_PCD;
  2983. writel(mask, &oxu->regs->intr_enable);
  2984. readl(&oxu->regs->intr_enable);
  2985. oxu->next_statechange = jiffies + msecs_to_jiffies(10);
  2986. spin_unlock_irq(&oxu->lock);
  2987. return 0;
  2988. }
  2989. /* Caller has locked the root hub, and should reset/reinit on error */
  2990. static int oxu_bus_resume(struct usb_hcd *hcd)
  2991. {
  2992. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2993. u32 temp;
  2994. int i;
  2995. if (time_before(jiffies, oxu->next_statechange))
  2996. msleep(5);
  2997. spin_lock_irq(&oxu->lock);
  2998. /* Ideally and we've got a real resume here, and no port's power
  2999. * was lost. (For PCI, that means Vaux was maintained.) But we
  3000. * could instead be restoring a swsusp snapshot -- so that BIOS was
  3001. * the last user of the controller, not reset/pm hardware keeping
  3002. * state we gave to it.
  3003. */
  3004. temp = readl(&oxu->regs->intr_enable);
  3005. oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss");
  3006. /* at least some APM implementations will try to deliver
  3007. * IRQs right away, so delay them until we're ready.
  3008. */
  3009. writel(0, &oxu->regs->intr_enable);
  3010. /* re-init operational registers */
  3011. writel(0, &oxu->regs->segment);
  3012. writel(oxu->periodic_dma, &oxu->regs->frame_list);
  3013. writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
  3014. /* restore CMD_RUN, framelist size, and irq threshold */
  3015. writel(oxu->command, &oxu->regs->command);
  3016. /* Some controller/firmware combinations need a delay during which
  3017. * they set up the port statuses. See Bugzilla #8190. */
  3018. mdelay(8);
  3019. /* manually resume the ports we suspended during bus_suspend() */
  3020. i = HCS_N_PORTS(oxu->hcs_params);
  3021. while (i--) {
  3022. temp = readl(&oxu->regs->port_status[i]);
  3023. temp &= ~(PORT_RWC_BITS
  3024. | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E);
  3025. if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
  3026. oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
  3027. temp |= PORT_RESUME;
  3028. }
  3029. writel(temp, &oxu->regs->port_status[i]);
  3030. }
  3031. i = HCS_N_PORTS(oxu->hcs_params);
  3032. mdelay(20);
  3033. while (i--) {
  3034. temp = readl(&oxu->regs->port_status[i]);
  3035. if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
  3036. temp &= ~(PORT_RWC_BITS | PORT_RESUME);
  3037. writel(temp, &oxu->regs->port_status[i]);
  3038. oxu_vdbg(oxu, "resumed port %d\n", i + 1);
  3039. }
  3040. }
  3041. (void) readl(&oxu->regs->command);
  3042. /* maybe re-activate the schedule(s) */
  3043. temp = 0;
  3044. if (oxu->async->qh_next.qh)
  3045. temp |= CMD_ASE;
  3046. if (oxu->periodic_sched)
  3047. temp |= CMD_PSE;
  3048. if (temp) {
  3049. oxu->command |= temp;
  3050. writel(oxu->command, &oxu->regs->command);
  3051. }
  3052. oxu->next_statechange = jiffies + msecs_to_jiffies(5);
  3053. hcd->state = HC_STATE_RUNNING;
  3054. /* Now we can safely re-enable irqs */
  3055. writel(INTR_MASK, &oxu->regs->intr_enable);
  3056. spin_unlock_irq(&oxu->lock);
  3057. return 0;
  3058. }
  3059. #else
  3060. static int oxu_bus_suspend(struct usb_hcd *hcd)
  3061. {
  3062. return 0;
  3063. }
  3064. static int oxu_bus_resume(struct usb_hcd *hcd)
  3065. {
  3066. return 0;
  3067. }
  3068. #endif /* CONFIG_PM */
  3069. static const struct hc_driver oxu_hc_driver = {
  3070. .description = "oxu210hp_hcd",
  3071. .product_desc = "oxu210hp HCD",
  3072. .hcd_priv_size = sizeof(struct oxu_hcd),
  3073. /*
  3074. * Generic hardware linkage
  3075. */
  3076. .irq = oxu_irq,
  3077. .flags = HCD_MEMORY | HCD_USB2,
  3078. /*
  3079. * Basic lifecycle operations
  3080. */
  3081. .reset = oxu_reset,
  3082. .start = oxu_run,
  3083. .stop = oxu_stop,
  3084. .shutdown = oxu_shutdown,
  3085. /*
  3086. * Managing i/o requests and associated device resources
  3087. */
  3088. .urb_enqueue = oxu_urb_enqueue,
  3089. .urb_dequeue = oxu_urb_dequeue,
  3090. .endpoint_disable = oxu_endpoint_disable,
  3091. /*
  3092. * Scheduling support
  3093. */
  3094. .get_frame_number = oxu_get_frame,
  3095. /*
  3096. * Root hub support
  3097. */
  3098. .hub_status_data = oxu_hub_status_data,
  3099. .hub_control = oxu_hub_control,
  3100. .bus_suspend = oxu_bus_suspend,
  3101. .bus_resume = oxu_bus_resume,
  3102. };
  3103. /*
  3104. * Module stuff
  3105. */
  3106. static void oxu_configuration(struct platform_device *pdev, void *base)
  3107. {
  3108. u32 tmp;
  3109. /* Initialize top level registers.
  3110. * First write ever
  3111. */
  3112. oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
  3113. oxu_writel(base, OXU_SOFTRESET, OXU_SRESET);
  3114. oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
  3115. tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL);
  3116. oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040);
  3117. oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN |
  3118. OXU_COMPARATOR | OXU_ASO_OP);
  3119. tmp = oxu_readl(base, OXU_CLKCTRL_SET);
  3120. oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN);
  3121. /* Clear all top interrupt enable */
  3122. oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff);
  3123. /* Clear all top interrupt status */
  3124. oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff);
  3125. /* Enable all needed top interrupt except OTG SPH core */
  3126. oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI);
  3127. }
  3128. static int oxu_verify_id(struct platform_device *pdev, void *base)
  3129. {
  3130. u32 id;
  3131. char *bo[] = {
  3132. "reserved",
  3133. "128-pin LQFP",
  3134. "84-pin TFBGA",
  3135. "reserved",
  3136. };
  3137. /* Read controller signature register to find a match */
  3138. id = oxu_readl(base, OXU_DEVICEID);
  3139. dev_info(&pdev->dev, "device ID %x\n", id);
  3140. if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT))
  3141. return -1;
  3142. dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n",
  3143. id >> OXU_REV_SHIFT,
  3144. bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT],
  3145. (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT,
  3146. (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT);
  3147. return 0;
  3148. }
  3149. static const struct hc_driver oxu_hc_driver;
  3150. static struct usb_hcd *oxu_create(struct platform_device *pdev,
  3151. unsigned long memstart, unsigned long memlen,
  3152. void *base, int irq, int otg)
  3153. {
  3154. struct device *dev = &pdev->dev;
  3155. struct usb_hcd *hcd;
  3156. struct oxu_hcd *oxu;
  3157. int ret;
  3158. /* Set endian mode and host mode */
  3159. oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET),
  3160. OXU_USBMODE,
  3161. OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS);
  3162. hcd = usb_create_hcd(&oxu_hc_driver, dev,
  3163. otg ? "oxu210hp_otg" : "oxu210hp_sph");
  3164. if (!hcd)
  3165. return ERR_PTR(-ENOMEM);
  3166. hcd->rsrc_start = memstart;
  3167. hcd->rsrc_len = memlen;
  3168. hcd->regs = base;
  3169. hcd->irq = irq;
  3170. hcd->state = HC_STATE_HALT;
  3171. oxu = hcd_to_oxu(hcd);
  3172. oxu->is_otg = otg;
  3173. ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
  3174. if (ret < 0)
  3175. return ERR_PTR(ret);
  3176. return hcd;
  3177. }
  3178. static int oxu_init(struct platform_device *pdev,
  3179. unsigned long memstart, unsigned long memlen,
  3180. void *base, int irq)
  3181. {
  3182. struct oxu_info *info = platform_get_drvdata(pdev);
  3183. struct usb_hcd *hcd;
  3184. int ret;
  3185. /* First time configuration at start up */
  3186. oxu_configuration(pdev, base);
  3187. ret = oxu_verify_id(pdev, base);
  3188. if (ret) {
  3189. dev_err(&pdev->dev, "no devices found!\n");
  3190. return -ENODEV;
  3191. }
  3192. /* Create the OTG controller */
  3193. hcd = oxu_create(pdev, memstart, memlen, base, irq, 1);
  3194. if (IS_ERR(hcd)) {
  3195. dev_err(&pdev->dev, "cannot create OTG controller!\n");
  3196. ret = PTR_ERR(hcd);
  3197. goto error_create_otg;
  3198. }
  3199. info->hcd[0] = hcd;
  3200. /* Create the SPH host controller */
  3201. hcd = oxu_create(pdev, memstart, memlen, base, irq, 0);
  3202. if (IS_ERR(hcd)) {
  3203. dev_err(&pdev->dev, "cannot create SPH controller!\n");
  3204. ret = PTR_ERR(hcd);
  3205. goto error_create_sph;
  3206. }
  3207. info->hcd[1] = hcd;
  3208. oxu_writel(base, OXU_CHIPIRQEN_SET,
  3209. oxu_readl(base, OXU_CHIPIRQEN_SET) | 3);
  3210. return 0;
  3211. error_create_sph:
  3212. usb_remove_hcd(info->hcd[0]);
  3213. usb_put_hcd(info->hcd[0]);
  3214. error_create_otg:
  3215. return ret;
  3216. }
  3217. static int oxu_drv_probe(struct platform_device *pdev)
  3218. {
  3219. struct resource *res;
  3220. void *base;
  3221. unsigned long memstart, memlen;
  3222. int irq, ret;
  3223. struct oxu_info *info;
  3224. if (usb_disabled())
  3225. return -ENODEV;
  3226. /*
  3227. * Get the platform resources
  3228. */
  3229. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  3230. if (!res) {
  3231. dev_err(&pdev->dev,
  3232. "no IRQ! Check %s setup!\n", dev_name(&pdev->dev));
  3233. return -ENODEV;
  3234. }
  3235. irq = res->start;
  3236. dev_dbg(&pdev->dev, "IRQ resource %d\n", irq);
  3237. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3238. if (!res) {
  3239. dev_err(&pdev->dev, "no registers address! Check %s setup!\n",
  3240. dev_name(&pdev->dev));
  3241. return -ENODEV;
  3242. }
  3243. memstart = res->start;
  3244. memlen = res->end - res->start + 1;
  3245. dev_dbg(&pdev->dev, "MEM resource %lx-%lx\n", memstart, memlen);
  3246. if (!request_mem_region(memstart, memlen,
  3247. oxu_hc_driver.description)) {
  3248. dev_dbg(&pdev->dev, "memory area already in use\n");
  3249. return -EBUSY;
  3250. }
  3251. ret = set_irq_type(irq, IRQF_TRIGGER_FALLING);
  3252. if (ret) {
  3253. dev_err(&pdev->dev, "error setting irq type\n");
  3254. ret = -EFAULT;
  3255. goto error_set_irq_type;
  3256. }
  3257. base = ioremap(memstart, memlen);
  3258. if (!base) {
  3259. dev_dbg(&pdev->dev, "error mapping memory\n");
  3260. ret = -EFAULT;
  3261. goto error_ioremap;
  3262. }
  3263. /* Allocate a driver data struct to hold useful info for both
  3264. * SPH & OTG devices
  3265. */
  3266. info = kzalloc(sizeof(struct oxu_info), GFP_KERNEL);
  3267. if (!info) {
  3268. dev_dbg(&pdev->dev, "error allocating memory\n");
  3269. ret = -EFAULT;
  3270. goto error_alloc;
  3271. }
  3272. platform_set_drvdata(pdev, info);
  3273. ret = oxu_init(pdev, memstart, memlen, base, irq);
  3274. if (ret < 0) {
  3275. dev_dbg(&pdev->dev, "cannot init USB devices\n");
  3276. goto error_init;
  3277. }
  3278. dev_info(&pdev->dev, "devices enabled and running\n");
  3279. platform_set_drvdata(pdev, info);
  3280. return 0;
  3281. error_init:
  3282. kfree(info);
  3283. platform_set_drvdata(pdev, NULL);
  3284. error_alloc:
  3285. iounmap(base);
  3286. error_set_irq_type:
  3287. error_ioremap:
  3288. release_mem_region(memstart, memlen);
  3289. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret);
  3290. return ret;
  3291. }
  3292. static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd)
  3293. {
  3294. usb_remove_hcd(hcd);
  3295. usb_put_hcd(hcd);
  3296. }
  3297. static int oxu_drv_remove(struct platform_device *pdev)
  3298. {
  3299. struct oxu_info *info = platform_get_drvdata(pdev);
  3300. unsigned long memstart = info->hcd[0]->rsrc_start,
  3301. memlen = info->hcd[0]->rsrc_len;
  3302. void *base = info->hcd[0]->regs;
  3303. oxu_remove(pdev, info->hcd[0]);
  3304. oxu_remove(pdev, info->hcd[1]);
  3305. iounmap(base);
  3306. release_mem_region(memstart, memlen);
  3307. kfree(info);
  3308. platform_set_drvdata(pdev, NULL);
  3309. return 0;
  3310. }
  3311. static void oxu_drv_shutdown(struct platform_device *pdev)
  3312. {
  3313. oxu_drv_remove(pdev);
  3314. }
  3315. #if 0
  3316. /* FIXME: TODO */
  3317. static int oxu_drv_suspend(struct device *dev)
  3318. {
  3319. struct platform_device *pdev = to_platform_device(dev);
  3320. struct usb_hcd *hcd = dev_get_drvdata(dev);
  3321. return 0;
  3322. }
  3323. static int oxu_drv_resume(struct device *dev)
  3324. {
  3325. struct platform_device *pdev = to_platform_device(dev);
  3326. struct usb_hcd *hcd = dev_get_drvdata(dev);
  3327. return 0;
  3328. }
  3329. #else
  3330. #define oxu_drv_suspend NULL
  3331. #define oxu_drv_resume NULL
  3332. #endif
  3333. static struct platform_driver oxu_driver = {
  3334. .probe = oxu_drv_probe,
  3335. .remove = oxu_drv_remove,
  3336. .shutdown = oxu_drv_shutdown,
  3337. .suspend = oxu_drv_suspend,
  3338. .resume = oxu_drv_resume,
  3339. .driver = {
  3340. .name = "oxu210hp-hcd",
  3341. .bus = &platform_bus_type
  3342. }
  3343. };
  3344. static int __init oxu_module_init(void)
  3345. {
  3346. int retval = 0;
  3347. retval = platform_driver_register(&oxu_driver);
  3348. if (retval < 0)
  3349. return retval;
  3350. return retval;
  3351. }
  3352. static void __exit oxu_module_cleanup(void)
  3353. {
  3354. platform_driver_unregister(&oxu_driver);
  3355. }
  3356. module_init(oxu_module_init);
  3357. module_exit(oxu_module_cleanup);
  3358. MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION);
  3359. MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
  3360. MODULE_LICENSE("GPL");