gdth.c 174 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: unused
  87. * buffer: unused
  88. * dma_handle: unused
  89. * buffers_residual: unused
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #include <linux/smp_lock.h>
  117. #include <linux/slab.h>
  118. #ifdef GDTH_RTC
  119. #include <linux/mc146818rtc.h>
  120. #endif
  121. #include <linux/reboot.h>
  122. #include <asm/dma.h>
  123. #include <asm/system.h>
  124. #include <asm/io.h>
  125. #include <asm/uaccess.h>
  126. #include <linux/spinlock.h>
  127. #include <linux/blkdev.h>
  128. #include <linux/scatterlist.h>
  129. #include "scsi.h"
  130. #include <scsi/scsi_host.h>
  131. #include "gdth.h"
  132. static void gdth_delay(int milliseconds);
  133. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs);
  134. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  135. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  136. int gdth_from_wait, int* pIndex);
  137. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  138. Scsi_Cmnd *scp);
  139. static int gdth_async_event(gdth_ha_str *ha);
  140. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  141. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority);
  142. static void gdth_next(gdth_ha_str *ha);
  143. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b);
  144. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  145. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  146. u16 idx, gdth_evt_data *evt);
  147. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  148. static void gdth_readapp_event(gdth_ha_str *ha, u8 application,
  149. gdth_evt_str *estr);
  150. static void gdth_clear_events(void);
  151. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  152. char *buffer, u16 count);
  153. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  154. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive);
  155. static void gdth_enable_int(gdth_ha_str *ha);
  156. static int gdth_test_busy(gdth_ha_str *ha);
  157. static int gdth_get_cmd_index(gdth_ha_str *ha);
  158. static void gdth_release_event(gdth_ha_str *ha);
  159. static int gdth_wait(gdth_ha_str *ha, int index,u32 time);
  160. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  161. u32 p1, u64 p2,u64 p3);
  162. static int gdth_search_drives(gdth_ha_str *ha);
  163. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive);
  164. static const char *gdth_ctr_name(gdth_ha_str *ha);
  165. static int gdth_open(struct inode *inode, struct file *filep);
  166. static int gdth_close(struct inode *inode, struct file *filep);
  167. static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd,
  168. unsigned long arg);
  169. static void gdth_flush(gdth_ha_str *ha);
  170. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  171. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  172. struct gdth_cmndinfo *cmndinfo);
  173. static void gdth_scsi_done(struct scsi_cmnd *scp);
  174. #ifdef DEBUG_GDTH
  175. static u8 DebugState = DEBUG_GDTH;
  176. #ifdef __SERIAL__
  177. #define MAX_SERBUF 160
  178. static void ser_init(void);
  179. static void ser_puts(char *str);
  180. static void ser_putc(char c);
  181. static int ser_printk(const char *fmt, ...);
  182. static char strbuf[MAX_SERBUF+1];
  183. #ifdef __COM2__
  184. #define COM_BASE 0x2f8
  185. #else
  186. #define COM_BASE 0x3f8
  187. #endif
  188. static void ser_init()
  189. {
  190. unsigned port=COM_BASE;
  191. outb(0x80,port+3);
  192. outb(0,port+1);
  193. /* 19200 Baud, if 9600: outb(12,port) */
  194. outb(6, port);
  195. outb(3,port+3);
  196. outb(0,port+1);
  197. /*
  198. ser_putc('I');
  199. ser_putc(' ');
  200. */
  201. }
  202. static void ser_puts(char *str)
  203. {
  204. char *ptr;
  205. ser_init();
  206. for (ptr=str;*ptr;++ptr)
  207. ser_putc(*ptr);
  208. }
  209. static void ser_putc(char c)
  210. {
  211. unsigned port=COM_BASE;
  212. while ((inb(port+5) & 0x20)==0);
  213. outb(c,port);
  214. if (c==0x0a)
  215. {
  216. while ((inb(port+5) & 0x20)==0);
  217. outb(0x0d,port);
  218. }
  219. }
  220. static int ser_printk(const char *fmt, ...)
  221. {
  222. va_list args;
  223. int i;
  224. va_start(args,fmt);
  225. i = vsprintf(strbuf,fmt,args);
  226. ser_puts(strbuf);
  227. va_end(args);
  228. return i;
  229. }
  230. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  231. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  232. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  233. #else /* !__SERIAL__ */
  234. #define TRACE(a) {if (DebugState==1) {printk a;}}
  235. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  236. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  237. #endif
  238. #else /* !DEBUG */
  239. #define TRACE(a)
  240. #define TRACE2(a)
  241. #define TRACE3(a)
  242. #endif
  243. #ifdef GDTH_STATISTICS
  244. static u32 max_rq=0, max_index=0, max_sg=0;
  245. #ifdef INT_COAL
  246. static u32 max_int_coal=0;
  247. #endif
  248. static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  249. static struct timer_list gdth_timer;
  250. #endif
  251. #define PTR2USHORT(a) (u16)(unsigned long)(a)
  252. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  253. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  254. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  255. #ifdef CONFIG_ISA
  256. static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  257. #endif
  258. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  259. static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  260. #endif
  261. static u8 gdth_polling; /* polling if TRUE */
  262. static int gdth_ctr_count = 0; /* controller count */
  263. static LIST_HEAD(gdth_instances); /* controller list */
  264. static u8 gdth_write_through = FALSE; /* write through */
  265. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  266. static int elastidx;
  267. static int eoldidx;
  268. static int major;
  269. #define DIN 1 /* IN data direction */
  270. #define DOU 2 /* OUT data direction */
  271. #define DNO DIN /* no data transfer */
  272. #define DUN DIN /* unknown data direction */
  273. static u8 gdth_direction_tab[0x100] = {
  274. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  275. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  276. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  277. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  278. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  284. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  285. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  290. };
  291. /* LILO and modprobe/insmod parameters */
  292. /* IRQ list for GDT3000/3020 EISA controllers */
  293. static int irq[MAXHA] __initdata =
  294. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  295. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  296. /* disable driver flag */
  297. static int disable __initdata = 0;
  298. /* reserve flag */
  299. static int reserve_mode = 1;
  300. /* reserve list */
  301. static int reserve_list[MAX_RES_ARGS] =
  302. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  304. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  305. /* scan order for PCI controllers */
  306. static int reverse_scan = 0;
  307. /* virtual channel for the host drives */
  308. static int hdr_channel = 0;
  309. /* max. IDs per channel */
  310. static int max_ids = MAXID;
  311. /* rescan all IDs */
  312. static int rescan = 0;
  313. /* shared access */
  314. static int shared_access = 1;
  315. /* enable support for EISA and ISA controllers */
  316. static int probe_eisa_isa = 0;
  317. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  318. static int force_dma32 = 0;
  319. /* parameters for modprobe/insmod */
  320. module_param_array(irq, int, NULL, 0);
  321. module_param(disable, int, 0);
  322. module_param(reserve_mode, int, 0);
  323. module_param_array(reserve_list, int, NULL, 0);
  324. module_param(reverse_scan, int, 0);
  325. module_param(hdr_channel, int, 0);
  326. module_param(max_ids, int, 0);
  327. module_param(rescan, int, 0);
  328. module_param(shared_access, int, 0);
  329. module_param(probe_eisa_isa, int, 0);
  330. module_param(force_dma32, int, 0);
  331. MODULE_AUTHOR("Achim Leubner");
  332. MODULE_LICENSE("GPL");
  333. /* ioctl interface */
  334. static const struct file_operations gdth_fops = {
  335. .unlocked_ioctl = gdth_unlocked_ioctl,
  336. .open = gdth_open,
  337. .release = gdth_close,
  338. };
  339. #include "gdth_proc.h"
  340. #include "gdth_proc.c"
  341. static gdth_ha_str *gdth_find_ha(int hanum)
  342. {
  343. gdth_ha_str *ha;
  344. list_for_each_entry(ha, &gdth_instances, list)
  345. if (hanum == ha->hanum)
  346. return ha;
  347. return NULL;
  348. }
  349. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  350. {
  351. struct gdth_cmndinfo *priv = NULL;
  352. unsigned long flags;
  353. int i;
  354. spin_lock_irqsave(&ha->smp_lock, flags);
  355. for (i=0; i<GDTH_MAXCMDS; ++i) {
  356. if (ha->cmndinfo[i].index == 0) {
  357. priv = &ha->cmndinfo[i];
  358. memset(priv, 0, sizeof(*priv));
  359. priv->index = i+1;
  360. break;
  361. }
  362. }
  363. spin_unlock_irqrestore(&ha->smp_lock, flags);
  364. return priv;
  365. }
  366. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  367. {
  368. BUG_ON(!priv);
  369. priv->index = 0;
  370. }
  371. static void gdth_delay(int milliseconds)
  372. {
  373. if (milliseconds == 0) {
  374. udelay(1);
  375. } else {
  376. mdelay(milliseconds);
  377. }
  378. }
  379. static void gdth_scsi_done(struct scsi_cmnd *scp)
  380. {
  381. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  382. int internal_command = cmndinfo->internal_command;
  383. TRACE2(("gdth_scsi_done()\n"));
  384. gdth_put_cmndinfo(cmndinfo);
  385. scp->host_scribble = NULL;
  386. if (internal_command)
  387. complete((struct completion *)scp->request);
  388. else
  389. scp->scsi_done(scp);
  390. }
  391. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  392. int timeout, u32 *info)
  393. {
  394. gdth_ha_str *ha = shost_priv(sdev->host);
  395. Scsi_Cmnd *scp;
  396. struct gdth_cmndinfo cmndinfo;
  397. DECLARE_COMPLETION_ONSTACK(wait);
  398. int rval;
  399. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  400. if (!scp)
  401. return -ENOMEM;
  402. scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  403. if (!scp->sense_buffer) {
  404. kfree(scp);
  405. return -ENOMEM;
  406. }
  407. scp->device = sdev;
  408. memset(&cmndinfo, 0, sizeof(cmndinfo));
  409. /* use request field to save the ptr. to completion struct. */
  410. scp->request = (struct request *)&wait;
  411. scp->cmd_len = 12;
  412. scp->cmnd = cmnd;
  413. cmndinfo.priority = IOCTL_PRI;
  414. cmndinfo.internal_cmd_str = gdtcmd;
  415. cmndinfo.internal_command = 1;
  416. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  417. __gdth_queuecommand(ha, scp, &cmndinfo);
  418. wait_for_completion(&wait);
  419. rval = cmndinfo.status;
  420. if (info)
  421. *info = cmndinfo.info;
  422. kfree(scp->sense_buffer);
  423. kfree(scp);
  424. return rval;
  425. }
  426. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  427. int timeout, u32 *info)
  428. {
  429. struct scsi_device *sdev = scsi_get_host_dev(shost);
  430. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  431. scsi_free_host_dev(sdev);
  432. return rval;
  433. }
  434. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
  435. {
  436. *cyls = size /HEADS/SECS;
  437. if (*cyls <= MAXCYLS) {
  438. *heads = HEADS;
  439. *secs = SECS;
  440. } else { /* too high for 64*32 */
  441. *cyls = size /MEDHEADS/MEDSECS;
  442. if (*cyls <= MAXCYLS) {
  443. *heads = MEDHEADS;
  444. *secs = MEDSECS;
  445. } else { /* too high for 127*63 */
  446. *cyls = size /BIGHEADS/BIGSECS;
  447. *heads = BIGHEADS;
  448. *secs = BIGSECS;
  449. }
  450. }
  451. }
  452. /* controller search and initialization functions */
  453. #ifdef CONFIG_EISA
  454. static int __init gdth_search_eisa(u16 eisa_adr)
  455. {
  456. u32 id;
  457. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  458. id = inl(eisa_adr+ID0REG);
  459. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  460. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  461. return 0; /* not EISA configured */
  462. return 1;
  463. }
  464. if (id == GDT3_ID) /* GDT3000 */
  465. return 1;
  466. return 0;
  467. }
  468. #endif /* CONFIG_EISA */
  469. #ifdef CONFIG_ISA
  470. static int __init gdth_search_isa(u32 bios_adr)
  471. {
  472. void __iomem *addr;
  473. u32 id;
  474. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  475. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
  476. id = readl(addr);
  477. iounmap(addr);
  478. if (id == GDT2_ID) /* GDT2000 */
  479. return 1;
  480. }
  481. return 0;
  482. }
  483. #endif /* CONFIG_ISA */
  484. #ifdef CONFIG_PCI
  485. static bool gdth_search_vortex(u16 device)
  486. {
  487. if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
  488. return true;
  489. if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
  490. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
  491. return true;
  492. if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
  493. device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
  494. return true;
  495. return false;
  496. }
  497. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
  498. static int gdth_pci_init_one(struct pci_dev *pdev,
  499. const struct pci_device_id *ent);
  500. static void gdth_pci_remove_one(struct pci_dev *pdev);
  501. static void gdth_remove_one(gdth_ha_str *ha);
  502. /* Vortex only makes RAID controllers.
  503. * We do not really want to specify all 550 ids here, so wildcard match.
  504. */
  505. static const struct pci_device_id gdthtable[] = {
  506. { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
  507. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
  508. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
  509. { } /* terminate list */
  510. };
  511. MODULE_DEVICE_TABLE(pci, gdthtable);
  512. static struct pci_driver gdth_pci_driver = {
  513. .name = "gdth",
  514. .id_table = gdthtable,
  515. .probe = gdth_pci_init_one,
  516. .remove = gdth_pci_remove_one,
  517. };
  518. static void __devexit gdth_pci_remove_one(struct pci_dev *pdev)
  519. {
  520. gdth_ha_str *ha = pci_get_drvdata(pdev);
  521. pci_set_drvdata(pdev, NULL);
  522. list_del(&ha->list);
  523. gdth_remove_one(ha);
  524. pci_disable_device(pdev);
  525. }
  526. static int __devinit gdth_pci_init_one(struct pci_dev *pdev,
  527. const struct pci_device_id *ent)
  528. {
  529. u16 vendor = pdev->vendor;
  530. u16 device = pdev->device;
  531. unsigned long base0, base1, base2;
  532. int rc;
  533. gdth_pci_str gdth_pcistr;
  534. gdth_ha_str *ha = NULL;
  535. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  536. gdth_ctr_count, vendor, device));
  537. memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
  538. if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
  539. return -ENODEV;
  540. rc = pci_enable_device(pdev);
  541. if (rc)
  542. return rc;
  543. if (gdth_ctr_count >= MAXHA)
  544. return -EBUSY;
  545. /* GDT PCI controller found, resources are already in pdev */
  546. gdth_pcistr.pdev = pdev;
  547. base0 = pci_resource_flags(pdev, 0);
  548. base1 = pci_resource_flags(pdev, 1);
  549. base2 = pci_resource_flags(pdev, 2);
  550. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  551. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  552. if (!(base0 & IORESOURCE_MEM))
  553. return -ENODEV;
  554. gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
  555. } else { /* GDT6110, GDT6120, .. */
  556. if (!(base0 & IORESOURCE_MEM) ||
  557. !(base2 & IORESOURCE_MEM) ||
  558. !(base1 & IORESOURCE_IO))
  559. return -ENODEV;
  560. gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
  561. gdth_pcistr.io = pci_resource_start(pdev, 1);
  562. }
  563. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  564. gdth_pcistr.pdev->bus->number,
  565. PCI_SLOT(gdth_pcistr.pdev->devfn),
  566. gdth_pcistr.irq,
  567. gdth_pcistr.dpmem));
  568. rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
  569. if (rc)
  570. return rc;
  571. return 0;
  572. }
  573. #endif /* CONFIG_PCI */
  574. #ifdef CONFIG_EISA
  575. static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
  576. {
  577. u32 retries,id;
  578. u8 prot_ver,eisacf,i,irq_found;
  579. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  580. /* disable board interrupts, deinitialize services */
  581. outb(0xff,eisa_adr+EDOORREG);
  582. outb(0x00,eisa_adr+EDENABREG);
  583. outb(0x00,eisa_adr+EINTENABREG);
  584. outb(0xff,eisa_adr+LDOORREG);
  585. retries = INIT_RETRIES;
  586. gdth_delay(20);
  587. while (inb(eisa_adr+EDOORREG) != 0xff) {
  588. if (--retries == 0) {
  589. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  590. return 0;
  591. }
  592. gdth_delay(1);
  593. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  594. }
  595. prot_ver = inb(eisa_adr+MAILBOXREG);
  596. outb(0xff,eisa_adr+EDOORREG);
  597. if (prot_ver != PROTOCOL_VERSION) {
  598. printk("GDT-EISA: Illegal protocol version\n");
  599. return 0;
  600. }
  601. ha->bmic = eisa_adr;
  602. ha->brd_phys = (u32)eisa_adr >> 12;
  603. outl(0,eisa_adr+MAILBOXREG);
  604. outl(0,eisa_adr+MAILBOXREG+4);
  605. outl(0,eisa_adr+MAILBOXREG+8);
  606. outl(0,eisa_adr+MAILBOXREG+12);
  607. /* detect IRQ */
  608. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  609. ha->oem_id = OEM_ID_ICP;
  610. ha->type = GDT_EISA;
  611. ha->stype = id;
  612. outl(1,eisa_adr+MAILBOXREG+8);
  613. outb(0xfe,eisa_adr+LDOORREG);
  614. retries = INIT_RETRIES;
  615. gdth_delay(20);
  616. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  617. if (--retries == 0) {
  618. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  619. return 0;
  620. }
  621. gdth_delay(1);
  622. }
  623. ha->irq = inb(eisa_adr+MAILBOXREG);
  624. outb(0xff,eisa_adr+EDOORREG);
  625. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  626. /* check the result */
  627. if (ha->irq == 0) {
  628. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  629. for (i = 0, irq_found = FALSE;
  630. i < MAXHA && irq[i] != 0xff; ++i) {
  631. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  632. irq_found = TRUE;
  633. break;
  634. }
  635. }
  636. if (irq_found) {
  637. ha->irq = irq[i];
  638. irq[i] = 0;
  639. printk("GDT-EISA: Can not detect controller IRQ,\n");
  640. printk("Use IRQ setting from command line (IRQ = %d)\n",
  641. ha->irq);
  642. } else {
  643. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  644. printk("the controller BIOS or use command line parameters\n");
  645. return 0;
  646. }
  647. }
  648. } else {
  649. eisacf = inb(eisa_adr+EISAREG) & 7;
  650. if (eisacf > 4) /* level triggered */
  651. eisacf -= 4;
  652. ha->irq = gdth_irq_tab[eisacf];
  653. ha->oem_id = OEM_ID_ICP;
  654. ha->type = GDT_EISA;
  655. ha->stype = id;
  656. }
  657. ha->dma64_support = 0;
  658. return 1;
  659. }
  660. #endif /* CONFIG_EISA */
  661. #ifdef CONFIG_ISA
  662. static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
  663. {
  664. register gdt2_dpram_str __iomem *dp2_ptr;
  665. int i;
  666. u8 irq_drq,prot_ver;
  667. u32 retries;
  668. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  669. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  670. if (ha->brd == NULL) {
  671. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  672. return 0;
  673. }
  674. dp2_ptr = ha->brd;
  675. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  676. /* reset interface area */
  677. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  678. if (readl(&dp2_ptr->u) != 0) {
  679. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  680. iounmap(ha->brd);
  681. return 0;
  682. }
  683. /* disable board interrupts, read DRQ and IRQ */
  684. writeb(0xff, &dp2_ptr->io.irqdel);
  685. writeb(0x00, &dp2_ptr->io.irqen);
  686. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  687. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  688. irq_drq = readb(&dp2_ptr->io.rq);
  689. for (i=0; i<3; ++i) {
  690. if ((irq_drq & 1)==0)
  691. break;
  692. irq_drq >>= 1;
  693. }
  694. ha->drq = gdth_drq_tab[i];
  695. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  696. for (i=1; i<5; ++i) {
  697. if ((irq_drq & 1)==0)
  698. break;
  699. irq_drq >>= 1;
  700. }
  701. ha->irq = gdth_irq_tab[i];
  702. /* deinitialize services */
  703. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  704. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  705. writeb(0, &dp2_ptr->io.event);
  706. retries = INIT_RETRIES;
  707. gdth_delay(20);
  708. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  709. if (--retries == 0) {
  710. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  711. iounmap(ha->brd);
  712. return 0;
  713. }
  714. gdth_delay(1);
  715. }
  716. prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
  717. writeb(0, &dp2_ptr->u.ic.Status);
  718. writeb(0xff, &dp2_ptr->io.irqdel);
  719. if (prot_ver != PROTOCOL_VERSION) {
  720. printk("GDT-ISA: Illegal protocol version\n");
  721. iounmap(ha->brd);
  722. return 0;
  723. }
  724. ha->oem_id = OEM_ID_ICP;
  725. ha->type = GDT_ISA;
  726. ha->ic_all_size = sizeof(dp2_ptr->u);
  727. ha->stype= GDT2_ID;
  728. ha->brd_phys = bios_adr >> 4;
  729. /* special request to controller BIOS */
  730. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  731. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  732. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  733. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  734. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  735. writeb(0, &dp2_ptr->io.event);
  736. retries = INIT_RETRIES;
  737. gdth_delay(20);
  738. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  739. if (--retries == 0) {
  740. printk("GDT-ISA: Initialization error\n");
  741. iounmap(ha->brd);
  742. return 0;
  743. }
  744. gdth_delay(1);
  745. }
  746. writeb(0, &dp2_ptr->u.ic.Status);
  747. writeb(0xff, &dp2_ptr->io.irqdel);
  748. ha->dma64_support = 0;
  749. return 1;
  750. }
  751. #endif /* CONFIG_ISA */
  752. #ifdef CONFIG_PCI
  753. static int __devinit gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
  754. gdth_ha_str *ha)
  755. {
  756. register gdt6_dpram_str __iomem *dp6_ptr;
  757. register gdt6c_dpram_str __iomem *dp6c_ptr;
  758. register gdt6m_dpram_str __iomem *dp6m_ptr;
  759. u32 retries;
  760. u8 prot_ver;
  761. u16 command;
  762. int i, found = FALSE;
  763. TRACE(("gdth_init_pci()\n"));
  764. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  765. ha->oem_id = OEM_ID_INTEL;
  766. else
  767. ha->oem_id = OEM_ID_ICP;
  768. ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
  769. ha->stype = (u32)pdev->device;
  770. ha->irq = pdev->irq;
  771. ha->pdev = pdev;
  772. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  773. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  774. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  775. if (ha->brd == NULL) {
  776. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  777. return 0;
  778. }
  779. /* check and reset interface area */
  780. dp6_ptr = ha->brd;
  781. writel(DPMEM_MAGIC, &dp6_ptr->u);
  782. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  783. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  784. pcistr->dpmem);
  785. found = FALSE;
  786. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  787. iounmap(ha->brd);
  788. ha->brd = ioremap(i, sizeof(u16));
  789. if (ha->brd == NULL) {
  790. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  791. return 0;
  792. }
  793. if (readw(ha->brd) != 0xffff) {
  794. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  795. continue;
  796. }
  797. iounmap(ha->brd);
  798. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  799. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  800. if (ha->brd == NULL) {
  801. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  802. return 0;
  803. }
  804. dp6_ptr = ha->brd;
  805. writel(DPMEM_MAGIC, &dp6_ptr->u);
  806. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  807. printk("GDT-PCI: Use free address at 0x%x\n", i);
  808. found = TRUE;
  809. break;
  810. }
  811. }
  812. if (!found) {
  813. printk("GDT-PCI: No free address found!\n");
  814. iounmap(ha->brd);
  815. return 0;
  816. }
  817. }
  818. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  819. if (readl(&dp6_ptr->u) != 0) {
  820. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  821. iounmap(ha->brd);
  822. return 0;
  823. }
  824. /* disable board interrupts, deinit services */
  825. writeb(0xff, &dp6_ptr->io.irqdel);
  826. writeb(0x00, &dp6_ptr->io.irqen);
  827. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  828. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  829. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  830. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  831. writeb(0, &dp6_ptr->io.event);
  832. retries = INIT_RETRIES;
  833. gdth_delay(20);
  834. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  835. if (--retries == 0) {
  836. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  837. iounmap(ha->brd);
  838. return 0;
  839. }
  840. gdth_delay(1);
  841. }
  842. prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]);
  843. writeb(0, &dp6_ptr->u.ic.S_Status);
  844. writeb(0xff, &dp6_ptr->io.irqdel);
  845. if (prot_ver != PROTOCOL_VERSION) {
  846. printk("GDT-PCI: Illegal protocol version\n");
  847. iounmap(ha->brd);
  848. return 0;
  849. }
  850. ha->type = GDT_PCI;
  851. ha->ic_all_size = sizeof(dp6_ptr->u);
  852. /* special command to controller BIOS */
  853. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  854. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  855. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  856. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  857. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  858. writeb(0, &dp6_ptr->io.event);
  859. retries = INIT_RETRIES;
  860. gdth_delay(20);
  861. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  862. if (--retries == 0) {
  863. printk("GDT-PCI: Initialization error\n");
  864. iounmap(ha->brd);
  865. return 0;
  866. }
  867. gdth_delay(1);
  868. }
  869. writeb(0, &dp6_ptr->u.ic.S_Status);
  870. writeb(0xff, &dp6_ptr->io.irqdel);
  871. ha->dma64_support = 0;
  872. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  873. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  874. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  875. pcistr->dpmem,ha->irq));
  876. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  877. if (ha->brd == NULL) {
  878. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  879. iounmap(ha->brd);
  880. return 0;
  881. }
  882. /* check and reset interface area */
  883. dp6c_ptr = ha->brd;
  884. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  885. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  886. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  887. pcistr->dpmem);
  888. found = FALSE;
  889. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  890. iounmap(ha->brd);
  891. ha->brd = ioremap(i, sizeof(u16));
  892. if (ha->brd == NULL) {
  893. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  894. return 0;
  895. }
  896. if (readw(ha->brd) != 0xffff) {
  897. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  898. continue;
  899. }
  900. iounmap(ha->brd);
  901. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
  902. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  903. if (ha->brd == NULL) {
  904. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  905. return 0;
  906. }
  907. dp6c_ptr = ha->brd;
  908. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  909. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  910. printk("GDT-PCI: Use free address at 0x%x\n", i);
  911. found = TRUE;
  912. break;
  913. }
  914. }
  915. if (!found) {
  916. printk("GDT-PCI: No free address found!\n");
  917. iounmap(ha->brd);
  918. return 0;
  919. }
  920. }
  921. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  922. if (readl(&dp6c_ptr->u) != 0) {
  923. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  924. iounmap(ha->brd);
  925. return 0;
  926. }
  927. /* disable board interrupts, deinit services */
  928. outb(0x00,PTR2USHORT(&ha->plx->control1));
  929. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  930. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  931. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  932. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  933. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  934. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  935. retries = INIT_RETRIES;
  936. gdth_delay(20);
  937. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  938. if (--retries == 0) {
  939. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  940. iounmap(ha->brd);
  941. return 0;
  942. }
  943. gdth_delay(1);
  944. }
  945. prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]);
  946. writeb(0, &dp6c_ptr->u.ic.Status);
  947. if (prot_ver != PROTOCOL_VERSION) {
  948. printk("GDT-PCI: Illegal protocol version\n");
  949. iounmap(ha->brd);
  950. return 0;
  951. }
  952. ha->type = GDT_PCINEW;
  953. ha->ic_all_size = sizeof(dp6c_ptr->u);
  954. /* special command to controller BIOS */
  955. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  956. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  957. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  958. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  959. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  960. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  961. retries = INIT_RETRIES;
  962. gdth_delay(20);
  963. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  964. if (--retries == 0) {
  965. printk("GDT-PCI: Initialization error\n");
  966. iounmap(ha->brd);
  967. return 0;
  968. }
  969. gdth_delay(1);
  970. }
  971. writeb(0, &dp6c_ptr->u.ic.S_Status);
  972. ha->dma64_support = 0;
  973. } else { /* MPR */
  974. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  975. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  976. if (ha->brd == NULL) {
  977. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  978. return 0;
  979. }
  980. /* manipulate config. space to enable DPMEM, start RP controller */
  981. pci_read_config_word(pdev, PCI_COMMAND, &command);
  982. command |= 6;
  983. pci_write_config_word(pdev, PCI_COMMAND, command);
  984. if (pci_resource_start(pdev, 8) == 1UL)
  985. pci_resource_start(pdev, 8) = 0UL;
  986. i = 0xFEFF0001UL;
  987. pci_write_config_dword(pdev, PCI_ROM_ADDRESS, i);
  988. gdth_delay(1);
  989. pci_write_config_dword(pdev, PCI_ROM_ADDRESS,
  990. pci_resource_start(pdev, 8));
  991. dp6m_ptr = ha->brd;
  992. /* Ensure that it is safe to access the non HW portions of DPMEM.
  993. * Aditional check needed for Xscale based RAID controllers */
  994. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  995. gdth_delay(1);
  996. /* check and reset interface area */
  997. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  998. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  999. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1000. pcistr->dpmem);
  1001. found = FALSE;
  1002. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1003. iounmap(ha->brd);
  1004. ha->brd = ioremap(i, sizeof(u16));
  1005. if (ha->brd == NULL) {
  1006. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1007. return 0;
  1008. }
  1009. if (readw(ha->brd) != 0xffff) {
  1010. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1011. continue;
  1012. }
  1013. iounmap(ha->brd);
  1014. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  1015. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1016. if (ha->brd == NULL) {
  1017. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1018. return 0;
  1019. }
  1020. dp6m_ptr = ha->brd;
  1021. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1022. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1023. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1024. found = TRUE;
  1025. break;
  1026. }
  1027. }
  1028. if (!found) {
  1029. printk("GDT-PCI: No free address found!\n");
  1030. iounmap(ha->brd);
  1031. return 0;
  1032. }
  1033. }
  1034. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1035. /* disable board interrupts, deinit services */
  1036. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1037. &dp6m_ptr->i960r.edoor_en_reg);
  1038. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1039. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1040. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1041. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1042. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1043. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1044. retries = INIT_RETRIES;
  1045. gdth_delay(20);
  1046. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1047. if (--retries == 0) {
  1048. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1049. iounmap(ha->brd);
  1050. return 0;
  1051. }
  1052. gdth_delay(1);
  1053. }
  1054. prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1055. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1056. if (prot_ver != PROTOCOL_VERSION) {
  1057. printk("GDT-PCI: Illegal protocol version\n");
  1058. iounmap(ha->brd);
  1059. return 0;
  1060. }
  1061. ha->type = GDT_PCIMPR;
  1062. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1063. /* special command to controller BIOS */
  1064. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1065. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1066. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1067. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1068. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1069. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1070. retries = INIT_RETRIES;
  1071. gdth_delay(20);
  1072. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1073. if (--retries == 0) {
  1074. printk("GDT-PCI: Initialization error\n");
  1075. iounmap(ha->brd);
  1076. return 0;
  1077. }
  1078. gdth_delay(1);
  1079. }
  1080. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1081. /* read FW version to detect 64-bit DMA support */
  1082. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1083. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1084. retries = INIT_RETRIES;
  1085. gdth_delay(20);
  1086. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1087. if (--retries == 0) {
  1088. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1089. iounmap(ha->brd);
  1090. return 0;
  1091. }
  1092. gdth_delay(1);
  1093. }
  1094. prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1095. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1096. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1097. ha->dma64_support = 0;
  1098. else
  1099. ha->dma64_support = 1;
  1100. }
  1101. return 1;
  1102. }
  1103. #endif /* CONFIG_PCI */
  1104. /* controller protocol functions */
  1105. static void __devinit gdth_enable_int(gdth_ha_str *ha)
  1106. {
  1107. unsigned long flags;
  1108. gdt2_dpram_str __iomem *dp2_ptr;
  1109. gdt6_dpram_str __iomem *dp6_ptr;
  1110. gdt6m_dpram_str __iomem *dp6m_ptr;
  1111. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1112. spin_lock_irqsave(&ha->smp_lock, flags);
  1113. if (ha->type == GDT_EISA) {
  1114. outb(0xff, ha->bmic + EDOORREG);
  1115. outb(0xff, ha->bmic + EDENABREG);
  1116. outb(0x01, ha->bmic + EINTENABREG);
  1117. } else if (ha->type == GDT_ISA) {
  1118. dp2_ptr = ha->brd;
  1119. writeb(1, &dp2_ptr->io.irqdel);
  1120. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1121. writeb(1, &dp2_ptr->io.irqen);
  1122. } else if (ha->type == GDT_PCI) {
  1123. dp6_ptr = ha->brd;
  1124. writeb(1, &dp6_ptr->io.irqdel);
  1125. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1126. writeb(1, &dp6_ptr->io.irqen);
  1127. } else if (ha->type == GDT_PCINEW) {
  1128. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1129. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1130. } else if (ha->type == GDT_PCIMPR) {
  1131. dp6m_ptr = ha->brd;
  1132. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1133. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1134. &dp6m_ptr->i960r.edoor_en_reg);
  1135. }
  1136. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1137. }
  1138. /* return IStatus if interrupt was from this card else 0 */
  1139. static u8 gdth_get_status(gdth_ha_str *ha)
  1140. {
  1141. u8 IStatus = 0;
  1142. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1143. if (ha->type == GDT_EISA)
  1144. IStatus = inb((u16)ha->bmic + EDOORREG);
  1145. else if (ha->type == GDT_ISA)
  1146. IStatus =
  1147. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1148. else if (ha->type == GDT_PCI)
  1149. IStatus =
  1150. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1151. else if (ha->type == GDT_PCINEW)
  1152. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1153. else if (ha->type == GDT_PCIMPR)
  1154. IStatus =
  1155. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1156. return IStatus;
  1157. }
  1158. static int gdth_test_busy(gdth_ha_str *ha)
  1159. {
  1160. register int gdtsema0 = 0;
  1161. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1162. if (ha->type == GDT_EISA)
  1163. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1164. else if (ha->type == GDT_ISA)
  1165. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1166. else if (ha->type == GDT_PCI)
  1167. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1168. else if (ha->type == GDT_PCINEW)
  1169. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1170. else if (ha->type == GDT_PCIMPR)
  1171. gdtsema0 =
  1172. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1173. return (gdtsema0 & 1);
  1174. }
  1175. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1176. {
  1177. int i;
  1178. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1179. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1180. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1181. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1182. ha->cmd_tab[i].service = ha->pccb->Service;
  1183. ha->pccb->CommandIndex = (u32)i+2;
  1184. return (i+2);
  1185. }
  1186. }
  1187. return 0;
  1188. }
  1189. static void gdth_set_sema0(gdth_ha_str *ha)
  1190. {
  1191. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1192. if (ha->type == GDT_EISA) {
  1193. outb(1, ha->bmic + SEMA0REG);
  1194. } else if (ha->type == GDT_ISA) {
  1195. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1196. } else if (ha->type == GDT_PCI) {
  1197. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1198. } else if (ha->type == GDT_PCINEW) {
  1199. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1200. } else if (ha->type == GDT_PCIMPR) {
  1201. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1202. }
  1203. }
  1204. static void gdth_copy_command(gdth_ha_str *ha)
  1205. {
  1206. register gdth_cmd_str *cmd_ptr;
  1207. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1208. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1209. gdt6_dpram_str __iomem *dp6_ptr;
  1210. gdt2_dpram_str __iomem *dp2_ptr;
  1211. u16 cp_count,dp_offset,cmd_no;
  1212. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1213. cp_count = ha->cmd_len;
  1214. dp_offset= ha->cmd_offs_dpmem;
  1215. cmd_no = ha->cmd_cnt;
  1216. cmd_ptr = ha->pccb;
  1217. ++ha->cmd_cnt;
  1218. if (ha->type == GDT_EISA)
  1219. return; /* no DPMEM, no copy */
  1220. /* set cpcount dword aligned */
  1221. if (cp_count & 3)
  1222. cp_count += (4 - (cp_count & 3));
  1223. ha->cmd_offs_dpmem += cp_count;
  1224. /* set offset and service, copy command to DPMEM */
  1225. if (ha->type == GDT_ISA) {
  1226. dp2_ptr = ha->brd;
  1227. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1228. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1229. writew((u16)cmd_ptr->Service,
  1230. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1231. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1232. } else if (ha->type == GDT_PCI) {
  1233. dp6_ptr = ha->brd;
  1234. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1235. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1236. writew((u16)cmd_ptr->Service,
  1237. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1238. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1239. } else if (ha->type == GDT_PCINEW) {
  1240. dp6c_ptr = ha->brd;
  1241. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1242. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1243. writew((u16)cmd_ptr->Service,
  1244. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1245. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1246. } else if (ha->type == GDT_PCIMPR) {
  1247. dp6m_ptr = ha->brd;
  1248. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1249. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1250. writew((u16)cmd_ptr->Service,
  1251. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1252. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1253. }
  1254. }
  1255. static void gdth_release_event(gdth_ha_str *ha)
  1256. {
  1257. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1258. #ifdef GDTH_STATISTICS
  1259. {
  1260. u32 i,j;
  1261. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1262. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1263. ++i;
  1264. }
  1265. if (max_index < i) {
  1266. max_index = i;
  1267. TRACE3(("GDT: max_index = %d\n",(u16)i));
  1268. }
  1269. }
  1270. #endif
  1271. if (ha->pccb->OpCode == GDT_INIT)
  1272. ha->pccb->Service |= 0x80;
  1273. if (ha->type == GDT_EISA) {
  1274. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1275. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1276. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1277. } else if (ha->type == GDT_ISA) {
  1278. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1279. } else if (ha->type == GDT_PCI) {
  1280. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1281. } else if (ha->type == GDT_PCINEW) {
  1282. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1283. } else if (ha->type == GDT_PCIMPR) {
  1284. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1285. }
  1286. }
  1287. static int gdth_wait(gdth_ha_str *ha, int index, u32 time)
  1288. {
  1289. int answer_found = FALSE;
  1290. int wait_index = 0;
  1291. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1292. if (index == 0)
  1293. return 1; /* no wait required */
  1294. do {
  1295. __gdth_interrupt(ha, true, &wait_index);
  1296. if (wait_index == index) {
  1297. answer_found = TRUE;
  1298. break;
  1299. }
  1300. gdth_delay(1);
  1301. } while (--time);
  1302. while (gdth_test_busy(ha))
  1303. gdth_delay(0);
  1304. return (answer_found);
  1305. }
  1306. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  1307. u32 p1, u64 p2, u64 p3)
  1308. {
  1309. register gdth_cmd_str *cmd_ptr;
  1310. int retries,index;
  1311. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1312. cmd_ptr = ha->pccb;
  1313. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1314. /* make command */
  1315. for (retries = INIT_RETRIES;;) {
  1316. cmd_ptr->Service = service;
  1317. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1318. if (!(index=gdth_get_cmd_index(ha))) {
  1319. TRACE(("GDT: No free command index found\n"));
  1320. return 0;
  1321. }
  1322. gdth_set_sema0(ha);
  1323. cmd_ptr->OpCode = opcode;
  1324. cmd_ptr->BoardNode = LOCALBOARD;
  1325. if (service == CACHESERVICE) {
  1326. if (opcode == GDT_IOCTL) {
  1327. cmd_ptr->u.ioctl.subfunc = p1;
  1328. cmd_ptr->u.ioctl.channel = (u32)p2;
  1329. cmd_ptr->u.ioctl.param_size = (u16)p3;
  1330. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1331. } else {
  1332. if (ha->cache_feat & GDT_64BIT) {
  1333. cmd_ptr->u.cache64.DeviceNo = (u16)p1;
  1334. cmd_ptr->u.cache64.BlockNo = p2;
  1335. } else {
  1336. cmd_ptr->u.cache.DeviceNo = (u16)p1;
  1337. cmd_ptr->u.cache.BlockNo = (u32)p2;
  1338. }
  1339. }
  1340. } else if (service == SCSIRAWSERVICE) {
  1341. if (ha->raw_feat & GDT_64BIT) {
  1342. cmd_ptr->u.raw64.direction = p1;
  1343. cmd_ptr->u.raw64.bus = (u8)p2;
  1344. cmd_ptr->u.raw64.target = (u8)p3;
  1345. cmd_ptr->u.raw64.lun = (u8)(p3 >> 8);
  1346. } else {
  1347. cmd_ptr->u.raw.direction = p1;
  1348. cmd_ptr->u.raw.bus = (u8)p2;
  1349. cmd_ptr->u.raw.target = (u8)p3;
  1350. cmd_ptr->u.raw.lun = (u8)(p3 >> 8);
  1351. }
  1352. } else if (service == SCREENSERVICE) {
  1353. if (opcode == GDT_REALTIME) {
  1354. *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1355. *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2;
  1356. *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3;
  1357. }
  1358. }
  1359. ha->cmd_len = sizeof(gdth_cmd_str);
  1360. ha->cmd_offs_dpmem = 0;
  1361. ha->cmd_cnt = 0;
  1362. gdth_copy_command(ha);
  1363. gdth_release_event(ha);
  1364. gdth_delay(20);
  1365. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1366. printk("GDT: Initialization error (timeout service %d)\n",service);
  1367. return 0;
  1368. }
  1369. if (ha->status != S_BSY || --retries == 0)
  1370. break;
  1371. gdth_delay(1);
  1372. }
  1373. return (ha->status != S_OK ? 0:1);
  1374. }
  1375. /* search for devices */
  1376. static int __devinit gdth_search_drives(gdth_ha_str *ha)
  1377. {
  1378. u16 cdev_cnt, i;
  1379. int ok;
  1380. u32 bus_no, drv_cnt, drv_no, j;
  1381. gdth_getch_str *chn;
  1382. gdth_drlist_str *drl;
  1383. gdth_iochan_str *ioc;
  1384. gdth_raw_iochan_str *iocr;
  1385. gdth_arcdl_str *alst;
  1386. gdth_alist_str *alst2;
  1387. gdth_oem_str_ioctl *oemstr;
  1388. #ifdef INT_COAL
  1389. gdth_perf_modes *pmod;
  1390. #endif
  1391. #ifdef GDTH_RTC
  1392. u8 rtc[12];
  1393. unsigned long flags;
  1394. #endif
  1395. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1396. ok = 0;
  1397. /* initialize controller services, at first: screen service */
  1398. ha->screen_feat = 0;
  1399. if (!force_dma32) {
  1400. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1401. if (ok)
  1402. ha->screen_feat = GDT_64BIT;
  1403. }
  1404. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1405. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1406. if (!ok) {
  1407. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1408. ha->hanum, ha->status);
  1409. return 0;
  1410. }
  1411. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1412. #ifdef GDTH_RTC
  1413. /* read realtime clock info, send to controller */
  1414. /* 1. wait for the falling edge of update flag */
  1415. spin_lock_irqsave(&rtc_lock, flags);
  1416. for (j = 0; j < 1000000; ++j)
  1417. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1418. break;
  1419. for (j = 0; j < 1000000; ++j)
  1420. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1421. break;
  1422. /* 2. read info */
  1423. do {
  1424. for (j = 0; j < 12; ++j)
  1425. rtc[j] = CMOS_READ(j);
  1426. } while (rtc[0] != CMOS_READ(0));
  1427. spin_unlock_irqrestore(&rtc_lock, flags);
  1428. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0],
  1429. *(u32 *)&rtc[4], *(u32 *)&rtc[8]));
  1430. /* 3. send to controller firmware */
  1431. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0],
  1432. *(u32 *)&rtc[4], *(u32 *)&rtc[8]);
  1433. #endif
  1434. /* unfreeze all IOs */
  1435. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1436. /* initialize cache service */
  1437. ha->cache_feat = 0;
  1438. if (!force_dma32) {
  1439. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1440. 0, 0);
  1441. if (ok)
  1442. ha->cache_feat = GDT_64BIT;
  1443. }
  1444. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1445. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1446. if (!ok) {
  1447. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1448. ha->hanum, ha->status);
  1449. return 0;
  1450. }
  1451. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1452. cdev_cnt = (u16)ha->info;
  1453. ha->fw_vers = ha->service;
  1454. #ifdef INT_COAL
  1455. if (ha->type == GDT_PCIMPR) {
  1456. /* set perf. modes */
  1457. pmod = (gdth_perf_modes *)ha->pscratch;
  1458. pmod->version = 1;
  1459. pmod->st_mode = 1; /* enable one status buffer */
  1460. *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1461. pmod->st_buff_indx1 = COALINDEX;
  1462. pmod->st_buff_addr2 = 0;
  1463. pmod->st_buff_u_addr2 = 0;
  1464. pmod->st_buff_indx2 = 0;
  1465. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1466. pmod->cmd_mode = 0; // disable all cmd buffers
  1467. pmod->cmd_buff_addr1 = 0;
  1468. pmod->cmd_buff_u_addr1 = 0;
  1469. pmod->cmd_buff_indx1 = 0;
  1470. pmod->cmd_buff_addr2 = 0;
  1471. pmod->cmd_buff_u_addr2 = 0;
  1472. pmod->cmd_buff_indx2 = 0;
  1473. pmod->cmd_buff_size = 0;
  1474. pmod->reserved1 = 0;
  1475. pmod->reserved2 = 0;
  1476. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1477. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1478. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1479. }
  1480. }
  1481. #endif
  1482. /* detect number of buses - try new IOCTL */
  1483. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1484. iocr->hdr.version = 0xffffffff;
  1485. iocr->hdr.list_entries = MAXBUS;
  1486. iocr->hdr.first_chan = 0;
  1487. iocr->hdr.last_chan = MAXBUS-1;
  1488. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1489. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1490. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1491. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1492. ha->bus_cnt = iocr->hdr.chan_count;
  1493. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1494. if (iocr->list[bus_no].proc_id < MAXID)
  1495. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1496. else
  1497. ha->bus_id[bus_no] = 0xff;
  1498. }
  1499. } else {
  1500. /* old method */
  1501. chn = (gdth_getch_str *)ha->pscratch;
  1502. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1503. chn->channel_no = bus_no;
  1504. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1505. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1506. IO_CHANNEL | INVALID_CHANNEL,
  1507. sizeof(gdth_getch_str))) {
  1508. if (bus_no == 0) {
  1509. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1510. ha->hanum, ha->status);
  1511. return 0;
  1512. }
  1513. break;
  1514. }
  1515. if (chn->siop_id < MAXID)
  1516. ha->bus_id[bus_no] = chn->siop_id;
  1517. else
  1518. ha->bus_id[bus_no] = 0xff;
  1519. }
  1520. ha->bus_cnt = (u8)bus_no;
  1521. }
  1522. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1523. /* read cache configuration */
  1524. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1525. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1526. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1527. ha->hanum, ha->status);
  1528. return 0;
  1529. }
  1530. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1531. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1532. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1533. ha->cpar.write_back,ha->cpar.block_size));
  1534. /* read board info and features */
  1535. ha->more_proc = FALSE;
  1536. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1537. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1538. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1539. sizeof(gdth_binfo_str));
  1540. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1541. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1542. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1543. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1544. ha->more_proc = TRUE;
  1545. }
  1546. } else {
  1547. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1548. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1549. }
  1550. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1551. /* read more informations */
  1552. if (ha->more_proc) {
  1553. /* physical drives, channel addresses */
  1554. ioc = (gdth_iochan_str *)ha->pscratch;
  1555. ioc->hdr.version = 0xffffffff;
  1556. ioc->hdr.list_entries = MAXBUS;
  1557. ioc->hdr.first_chan = 0;
  1558. ioc->hdr.last_chan = MAXBUS-1;
  1559. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1560. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1561. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1562. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1563. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1564. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1565. }
  1566. } else {
  1567. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1568. ha->raw[bus_no].address = IO_CHANNEL;
  1569. ha->raw[bus_no].local_no = bus_no;
  1570. }
  1571. }
  1572. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1573. chn = (gdth_getch_str *)ha->pscratch;
  1574. chn->channel_no = ha->raw[bus_no].local_no;
  1575. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1576. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1577. ha->raw[bus_no].address | INVALID_CHANNEL,
  1578. sizeof(gdth_getch_str))) {
  1579. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1580. TRACE2(("Channel %d: %d phys. drives\n",
  1581. bus_no,chn->drive_cnt));
  1582. }
  1583. if (ha->raw[bus_no].pdev_cnt > 0) {
  1584. drl = (gdth_drlist_str *)ha->pscratch;
  1585. drl->sc_no = ha->raw[bus_no].local_no;
  1586. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1587. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1588. SCSI_DR_LIST | L_CTRL_PATTERN,
  1589. ha->raw[bus_no].address | INVALID_CHANNEL,
  1590. sizeof(gdth_drlist_str))) {
  1591. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1592. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1593. } else {
  1594. ha->raw[bus_no].pdev_cnt = 0;
  1595. }
  1596. }
  1597. }
  1598. /* logical drives */
  1599. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1600. INVALID_CHANNEL,sizeof(u32))) {
  1601. drv_cnt = *(u32 *)ha->pscratch;
  1602. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1603. INVALID_CHANNEL,drv_cnt * sizeof(u32))) {
  1604. for (j = 0; j < drv_cnt; ++j) {
  1605. drv_no = ((u32 *)ha->pscratch)[j];
  1606. if (drv_no < MAX_LDRIVES) {
  1607. ha->hdr[drv_no].is_logdrv = TRUE;
  1608. TRACE2(("Drive %d is log. drive\n",drv_no));
  1609. }
  1610. }
  1611. }
  1612. alst = (gdth_arcdl_str *)ha->pscratch;
  1613. alst->entries_avail = MAX_LDRIVES;
  1614. alst->first_entry = 0;
  1615. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1616. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1617. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1618. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1619. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1620. for (j = 0; j < alst->entries_init; ++j) {
  1621. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1622. ha->hdr[j].is_master = alst->list[j].is_master;
  1623. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1624. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1625. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1626. }
  1627. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1628. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1629. 0, 35 * sizeof(gdth_alist_str))) {
  1630. for (j = 0; j < 35; ++j) {
  1631. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1632. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1633. ha->hdr[j].is_master = alst2->is_master;
  1634. ha->hdr[j].is_parity = alst2->is_parity;
  1635. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1636. ha->hdr[j].master_no = alst2->cd_handle;
  1637. }
  1638. }
  1639. }
  1640. }
  1641. /* initialize raw service */
  1642. ha->raw_feat = 0;
  1643. if (!force_dma32) {
  1644. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1645. if (ok)
  1646. ha->raw_feat = GDT_64BIT;
  1647. }
  1648. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1649. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1650. if (!ok) {
  1651. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1652. ha->hanum, ha->status);
  1653. return 0;
  1654. }
  1655. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1656. /* set/get features raw service (scatter/gather) */
  1657. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1658. 0, 0)) {
  1659. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1660. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1661. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1662. ha->info));
  1663. ha->raw_feat |= (u16)ha->info;
  1664. }
  1665. }
  1666. /* set/get features cache service (equal to raw service) */
  1667. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1668. SCATTER_GATHER,0)) {
  1669. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1670. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1671. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1672. ha->info));
  1673. ha->cache_feat |= (u16)ha->info;
  1674. }
  1675. }
  1676. /* reserve drives for raw service */
  1677. if (reserve_mode != 0) {
  1678. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1679. reserve_mode == 1 ? 1 : 3, 0, 0);
  1680. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1681. ha->status));
  1682. }
  1683. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1684. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1685. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1686. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1687. reserve_list[i], reserve_list[i+1],
  1688. reserve_list[i+2], reserve_list[i+3]));
  1689. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1690. reserve_list[i+1], reserve_list[i+2] |
  1691. (reserve_list[i+3] << 8))) {
  1692. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1693. ha->hanum, ha->status);
  1694. }
  1695. }
  1696. }
  1697. /* Determine OEM string using IOCTL */
  1698. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1699. oemstr->params.ctl_version = 0x01;
  1700. oemstr->params.buffer_size = sizeof(oemstr->text);
  1701. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1702. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1703. sizeof(gdth_oem_str_ioctl))) {
  1704. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1705. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1706. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1707. /* Save the Host Drive inquiry data */
  1708. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1709. sizeof(ha->oem_name));
  1710. } else {
  1711. /* Old method, based on PCI ID */
  1712. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1713. printk("GDT-HA %d: Name: %s\n",
  1714. ha->hanum, ha->binfo.type_string);
  1715. if (ha->oem_id == OEM_ID_INTEL)
  1716. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1717. else
  1718. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1719. }
  1720. /* scanning for host drives */
  1721. for (i = 0; i < cdev_cnt; ++i)
  1722. gdth_analyse_hdrive(ha, i);
  1723. TRACE(("gdth_search_drives() OK\n"));
  1724. return 1;
  1725. }
  1726. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive)
  1727. {
  1728. u32 drv_cyls;
  1729. int drv_hds, drv_secs;
  1730. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1731. if (hdrive >= MAX_HDRIVES)
  1732. return 0;
  1733. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1734. return 0;
  1735. ha->hdr[hdrive].present = TRUE;
  1736. ha->hdr[hdrive].size = ha->info;
  1737. /* evaluate mapping (sectors per head, heads per cylinder) */
  1738. ha->hdr[hdrive].size &= ~SECS32;
  1739. if (ha->info2 == 0) {
  1740. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1741. } else {
  1742. drv_hds = ha->info2 & 0xff;
  1743. drv_secs = (ha->info2 >> 8) & 0xff;
  1744. drv_cyls = (u32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1745. }
  1746. ha->hdr[hdrive].heads = (u8)drv_hds;
  1747. ha->hdr[hdrive].secs = (u8)drv_secs;
  1748. /* round size */
  1749. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1750. if (ha->cache_feat & GDT_64BIT) {
  1751. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1752. && ha->info2 != 0) {
  1753. ha->hdr[hdrive].size = ((u64)ha->info2 << 32) | ha->info;
  1754. }
  1755. }
  1756. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1757. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1758. /* get informations about device */
  1759. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1760. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1761. hdrive,ha->info));
  1762. ha->hdr[hdrive].devtype = (u16)ha->info;
  1763. }
  1764. /* cluster info */
  1765. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1766. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1767. hdrive,ha->info));
  1768. if (!shared_access)
  1769. ha->hdr[hdrive].cluster_type = (u8)ha->info;
  1770. }
  1771. /* R/W attributes */
  1772. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1773. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1774. hdrive,ha->info));
  1775. ha->hdr[hdrive].rw_attribs = (u8)ha->info;
  1776. }
  1777. return 1;
  1778. }
  1779. /* command queueing/sending functions */
  1780. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority)
  1781. {
  1782. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1783. register Scsi_Cmnd *pscp;
  1784. register Scsi_Cmnd *nscp;
  1785. unsigned long flags;
  1786. TRACE(("gdth_putq() priority %d\n",priority));
  1787. spin_lock_irqsave(&ha->smp_lock, flags);
  1788. if (!cmndinfo->internal_command)
  1789. cmndinfo->priority = priority;
  1790. if (ha->req_first==NULL) {
  1791. ha->req_first = scp; /* queue was empty */
  1792. scp->SCp.ptr = NULL;
  1793. } else { /* queue not empty */
  1794. pscp = ha->req_first;
  1795. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1796. /* priority: 0-highest,..,0xff-lowest */
  1797. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1798. pscp = nscp;
  1799. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1800. }
  1801. pscp->SCp.ptr = (char *)scp;
  1802. scp->SCp.ptr = (char *)nscp;
  1803. }
  1804. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1805. #ifdef GDTH_STATISTICS
  1806. flags = 0;
  1807. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1808. ++flags;
  1809. if (max_rq < flags) {
  1810. max_rq = flags;
  1811. TRACE3(("GDT: max_rq = %d\n",(u16)max_rq));
  1812. }
  1813. #endif
  1814. }
  1815. static void gdth_next(gdth_ha_str *ha)
  1816. {
  1817. register Scsi_Cmnd *pscp;
  1818. register Scsi_Cmnd *nscp;
  1819. u8 b, t, l, firsttime;
  1820. u8 this_cmd, next_cmd;
  1821. unsigned long flags = 0;
  1822. int cmd_index;
  1823. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1824. if (!gdth_polling)
  1825. spin_lock_irqsave(&ha->smp_lock, flags);
  1826. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1827. this_cmd = firsttime = TRUE;
  1828. next_cmd = gdth_polling ? FALSE:TRUE;
  1829. cmd_index = 0;
  1830. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1831. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1832. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1833. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1834. if (!nscp_cmndinfo->internal_command) {
  1835. b = nscp->device->channel;
  1836. t = nscp->device->id;
  1837. l = nscp->device->lun;
  1838. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1839. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1840. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1841. continue;
  1842. }
  1843. } else
  1844. b = t = l = 0;
  1845. if (firsttime) {
  1846. if (gdth_test_busy(ha)) { /* controller busy ? */
  1847. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1848. if (!gdth_polling) {
  1849. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1850. return;
  1851. }
  1852. while (gdth_test_busy(ha))
  1853. gdth_delay(1);
  1854. }
  1855. firsttime = FALSE;
  1856. }
  1857. if (!nscp_cmndinfo->internal_command) {
  1858. if (nscp_cmndinfo->phase == -1) {
  1859. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1860. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1861. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1862. b, t, l));
  1863. /* TEST_UNIT_READY -> set scan mode */
  1864. if ((ha->scan_mode & 0x0f) == 0) {
  1865. if (b == 0 && t == 0 && l == 0) {
  1866. ha->scan_mode |= 1;
  1867. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1868. }
  1869. } else if ((ha->scan_mode & 0x0f) == 1) {
  1870. if (b == 0 && ((t == 0 && l == 1) ||
  1871. (t == 1 && l == 0))) {
  1872. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1873. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1874. | SCSIRAWSERVICE;
  1875. ha->scan_mode = 0x12;
  1876. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1877. ha->scan_mode));
  1878. } else {
  1879. ha->scan_mode &= 0x10;
  1880. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1881. }
  1882. } else if (ha->scan_mode == 0x12) {
  1883. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1884. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1885. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1886. ha->scan_mode &= 0x10;
  1887. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1888. ha->scan_mode));
  1889. }
  1890. }
  1891. }
  1892. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1893. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1894. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1895. /* always GDT_CLUST_INFO! */
  1896. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1897. }
  1898. }
  1899. }
  1900. if (nscp_cmndinfo->OpCode != -1) {
  1901. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1902. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1903. this_cmd = FALSE;
  1904. next_cmd = FALSE;
  1905. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1906. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1907. this_cmd = FALSE;
  1908. next_cmd = FALSE;
  1909. } else {
  1910. memset((char*)nscp->sense_buffer,0,16);
  1911. nscp->sense_buffer[0] = 0x70;
  1912. nscp->sense_buffer[2] = NOT_READY;
  1913. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1914. if (!nscp_cmndinfo->wait_for_completion)
  1915. nscp_cmndinfo->wait_for_completion++;
  1916. else
  1917. gdth_scsi_done(nscp);
  1918. }
  1919. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1920. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1921. this_cmd = FALSE;
  1922. next_cmd = FALSE;
  1923. } else if (b != ha->virt_bus) {
  1924. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1925. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1926. this_cmd = FALSE;
  1927. else
  1928. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1929. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1930. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1931. nscp->cmnd[0], b, t, l));
  1932. nscp->result = DID_BAD_TARGET << 16;
  1933. if (!nscp_cmndinfo->wait_for_completion)
  1934. nscp_cmndinfo->wait_for_completion++;
  1935. else
  1936. gdth_scsi_done(nscp);
  1937. } else {
  1938. switch (nscp->cmnd[0]) {
  1939. case TEST_UNIT_READY:
  1940. case INQUIRY:
  1941. case REQUEST_SENSE:
  1942. case READ_CAPACITY:
  1943. case VERIFY:
  1944. case START_STOP:
  1945. case MODE_SENSE:
  1946. case SERVICE_ACTION_IN:
  1947. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1948. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1949. nscp->cmnd[4],nscp->cmnd[5]));
  1950. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1951. /* return UNIT_ATTENTION */
  1952. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1953. nscp->cmnd[0], t));
  1954. ha->hdr[t].media_changed = FALSE;
  1955. memset((char*)nscp->sense_buffer,0,16);
  1956. nscp->sense_buffer[0] = 0x70;
  1957. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1958. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1959. if (!nscp_cmndinfo->wait_for_completion)
  1960. nscp_cmndinfo->wait_for_completion++;
  1961. else
  1962. gdth_scsi_done(nscp);
  1963. } else if (gdth_internal_cache_cmd(ha, nscp))
  1964. gdth_scsi_done(nscp);
  1965. break;
  1966. case ALLOW_MEDIUM_REMOVAL:
  1967. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1968. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1969. nscp->cmnd[4],nscp->cmnd[5]));
  1970. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1971. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1972. nscp->result = DID_OK << 16;
  1973. nscp->sense_buffer[0] = 0;
  1974. if (!nscp_cmndinfo->wait_for_completion)
  1975. nscp_cmndinfo->wait_for_completion++;
  1976. else
  1977. gdth_scsi_done(nscp);
  1978. } else {
  1979. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1980. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1981. nscp->cmnd[4],nscp->cmnd[3]));
  1982. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1983. this_cmd = FALSE;
  1984. }
  1985. break;
  1986. case RESERVE:
  1987. case RELEASE:
  1988. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1989. "RESERVE" : "RELEASE"));
  1990. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1991. this_cmd = FALSE;
  1992. break;
  1993. case READ_6:
  1994. case WRITE_6:
  1995. case READ_10:
  1996. case WRITE_10:
  1997. case READ_16:
  1998. case WRITE_16:
  1999. if (ha->hdr[t].media_changed) {
  2000. /* return UNIT_ATTENTION */
  2001. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2002. nscp->cmnd[0], t));
  2003. ha->hdr[t].media_changed = FALSE;
  2004. memset((char*)nscp->sense_buffer,0,16);
  2005. nscp->sense_buffer[0] = 0x70;
  2006. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2007. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2008. if (!nscp_cmndinfo->wait_for_completion)
  2009. nscp_cmndinfo->wait_for_completion++;
  2010. else
  2011. gdth_scsi_done(nscp);
  2012. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2013. this_cmd = FALSE;
  2014. break;
  2015. default:
  2016. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2017. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2018. nscp->cmnd[4],nscp->cmnd[5]));
  2019. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2020. ha->hanum, nscp->cmnd[0]);
  2021. nscp->result = DID_ABORT << 16;
  2022. if (!nscp_cmndinfo->wait_for_completion)
  2023. nscp_cmndinfo->wait_for_completion++;
  2024. else
  2025. gdth_scsi_done(nscp);
  2026. break;
  2027. }
  2028. }
  2029. if (!this_cmd)
  2030. break;
  2031. if (nscp == ha->req_first)
  2032. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2033. else
  2034. pscp->SCp.ptr = nscp->SCp.ptr;
  2035. if (!next_cmd)
  2036. break;
  2037. }
  2038. if (ha->cmd_cnt > 0) {
  2039. gdth_release_event(ha);
  2040. }
  2041. if (!gdth_polling)
  2042. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2043. if (gdth_polling && ha->cmd_cnt > 0) {
  2044. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2045. printk("GDT-HA %d: Command %d timed out !\n",
  2046. ha->hanum, cmd_index);
  2047. }
  2048. }
  2049. /*
  2050. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2051. * buffers, kmap_atomic() as needed.
  2052. */
  2053. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2054. char *buffer, u16 count)
  2055. {
  2056. u16 cpcount,i, max_sg = scsi_sg_count(scp);
  2057. u16 cpsum,cpnow;
  2058. struct scatterlist *sl;
  2059. char *address;
  2060. cpcount = min_t(u16, count, scsi_bufflen(scp));
  2061. if (cpcount) {
  2062. cpsum=0;
  2063. scsi_for_each_sg(scp, sl, max_sg, i) {
  2064. unsigned long flags;
  2065. cpnow = (u16)sl->length;
  2066. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2067. cpnow, cpsum, cpcount, scsi_bufflen(scp)));
  2068. if (cpsum+cpnow > cpcount)
  2069. cpnow = cpcount - cpsum;
  2070. cpsum += cpnow;
  2071. if (!sg_page(sl)) {
  2072. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2073. ha->hanum);
  2074. return;
  2075. }
  2076. local_irq_save(flags);
  2077. address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
  2078. memcpy(address, buffer, cpnow);
  2079. flush_dcache_page(sg_page(sl));
  2080. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2081. local_irq_restore(flags);
  2082. if (cpsum == cpcount)
  2083. break;
  2084. buffer += cpnow;
  2085. }
  2086. } else if (count) {
  2087. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2088. ha->hanum);
  2089. WARN_ON(1);
  2090. }
  2091. }
  2092. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2093. {
  2094. u8 t;
  2095. gdth_inq_data inq;
  2096. gdth_rdcap_data rdc;
  2097. gdth_sense_data sd;
  2098. gdth_modep_data mpd;
  2099. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2100. t = scp->device->id;
  2101. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2102. scp->cmnd[0],t));
  2103. scp->result = DID_OK << 16;
  2104. scp->sense_buffer[0] = 0;
  2105. switch (scp->cmnd[0]) {
  2106. case TEST_UNIT_READY:
  2107. case VERIFY:
  2108. case START_STOP:
  2109. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2110. break;
  2111. case INQUIRY:
  2112. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2113. t,ha->hdr[t].devtype));
  2114. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2115. /* you can here set all disks to removable, if you want to do
  2116. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2117. inq.modif_rmb = 0x00;
  2118. if ((ha->hdr[t].devtype & 1) ||
  2119. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2120. inq.modif_rmb = 0x80;
  2121. inq.version = 2;
  2122. inq.resp_aenc = 2;
  2123. inq.add_length= 32;
  2124. strcpy(inq.vendor,ha->oem_name);
  2125. sprintf(inq.product,"Host Drive #%02d",t);
  2126. strcpy(inq.revision," ");
  2127. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2128. break;
  2129. case REQUEST_SENSE:
  2130. TRACE2(("Request sense hdrive %d\n",t));
  2131. sd.errorcode = 0x70;
  2132. sd.segno = 0x00;
  2133. sd.key = NO_SENSE;
  2134. sd.info = 0;
  2135. sd.add_length= 0;
  2136. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2137. break;
  2138. case MODE_SENSE:
  2139. TRACE2(("Mode sense hdrive %d\n",t));
  2140. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2141. mpd.hd.data_length = sizeof(gdth_modep_data);
  2142. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2143. mpd.hd.bd_length = sizeof(mpd.bd);
  2144. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2145. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2146. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2147. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2148. break;
  2149. case READ_CAPACITY:
  2150. TRACE2(("Read capacity hdrive %d\n",t));
  2151. if (ha->hdr[t].size > (u64)0xffffffff)
  2152. rdc.last_block_no = 0xffffffff;
  2153. else
  2154. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2155. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2156. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2157. break;
  2158. case SERVICE_ACTION_IN:
  2159. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2160. (ha->cache_feat & GDT_64BIT)) {
  2161. gdth_rdcap16_data rdc16;
  2162. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2163. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2164. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2165. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2166. sizeof(gdth_rdcap16_data));
  2167. } else {
  2168. scp->result = DID_ABORT << 16;
  2169. }
  2170. break;
  2171. default:
  2172. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2173. break;
  2174. }
  2175. if (!cmndinfo->wait_for_completion)
  2176. cmndinfo->wait_for_completion++;
  2177. else
  2178. return 1;
  2179. return 0;
  2180. }
  2181. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive)
  2182. {
  2183. register gdth_cmd_str *cmdp;
  2184. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2185. u32 cnt, blockcnt;
  2186. u64 no, blockno;
  2187. int i, cmd_index, read_write, sgcnt, mode64;
  2188. cmdp = ha->pccb;
  2189. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2190. scp->cmnd[0],scp->cmd_len,hdrive));
  2191. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2192. return 0;
  2193. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2194. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2195. not required, should not occur due to error return on
  2196. READ_CAPACITY_16 */
  2197. cmdp->Service = CACHESERVICE;
  2198. cmdp->RequestBuffer = scp;
  2199. /* search free command index */
  2200. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2201. TRACE(("GDT: No free command index found\n"));
  2202. return 0;
  2203. }
  2204. /* if it's the first command, set command semaphore */
  2205. if (ha->cmd_cnt == 0)
  2206. gdth_set_sema0(ha);
  2207. /* fill command */
  2208. read_write = 0;
  2209. if (cmndinfo->OpCode != -1)
  2210. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2211. else if (scp->cmnd[0] == RESERVE)
  2212. cmdp->OpCode = GDT_RESERVE_DRV;
  2213. else if (scp->cmnd[0] == RELEASE)
  2214. cmdp->OpCode = GDT_RELEASE_DRV;
  2215. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2216. if (scp->cmnd[4] & 1) /* prevent ? */
  2217. cmdp->OpCode = GDT_MOUNT;
  2218. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2219. cmdp->OpCode = GDT_UNMOUNT;
  2220. else
  2221. cmdp->OpCode = GDT_FLUSH;
  2222. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2223. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2224. ) {
  2225. read_write = 1;
  2226. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2227. (ha->cache_feat & GDT_WR_THROUGH)))
  2228. cmdp->OpCode = GDT_WRITE_THR;
  2229. else
  2230. cmdp->OpCode = GDT_WRITE;
  2231. } else {
  2232. read_write = 2;
  2233. cmdp->OpCode = GDT_READ;
  2234. }
  2235. cmdp->BoardNode = LOCALBOARD;
  2236. if (mode64) {
  2237. cmdp->u.cache64.DeviceNo = hdrive;
  2238. cmdp->u.cache64.BlockNo = 1;
  2239. cmdp->u.cache64.sg_canz = 0;
  2240. } else {
  2241. cmdp->u.cache.DeviceNo = hdrive;
  2242. cmdp->u.cache.BlockNo = 1;
  2243. cmdp->u.cache.sg_canz = 0;
  2244. }
  2245. if (read_write) {
  2246. if (scp->cmd_len == 16) {
  2247. memcpy(&no, &scp->cmnd[2], sizeof(u64));
  2248. blockno = be64_to_cpu(no);
  2249. memcpy(&cnt, &scp->cmnd[10], sizeof(u32));
  2250. blockcnt = be32_to_cpu(cnt);
  2251. } else if (scp->cmd_len == 10) {
  2252. memcpy(&no, &scp->cmnd[2], sizeof(u32));
  2253. blockno = be32_to_cpu(no);
  2254. memcpy(&cnt, &scp->cmnd[7], sizeof(u16));
  2255. blockcnt = be16_to_cpu(cnt);
  2256. } else {
  2257. memcpy(&no, &scp->cmnd[0], sizeof(u32));
  2258. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2259. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2260. }
  2261. if (mode64) {
  2262. cmdp->u.cache64.BlockNo = blockno;
  2263. cmdp->u.cache64.BlockCnt = blockcnt;
  2264. } else {
  2265. cmdp->u.cache.BlockNo = (u32)blockno;
  2266. cmdp->u.cache.BlockCnt = blockcnt;
  2267. }
  2268. if (scsi_bufflen(scp)) {
  2269. cmndinfo->dma_dir = (read_write == 1 ?
  2270. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2271. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2272. cmndinfo->dma_dir);
  2273. if (mode64) {
  2274. struct scatterlist *sl;
  2275. cmdp->u.cache64.DestAddr= (u64)-1;
  2276. cmdp->u.cache64.sg_canz = sgcnt;
  2277. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2278. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2279. #ifdef GDTH_DMA_STATISTICS
  2280. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2281. ha->dma64_cnt++;
  2282. else
  2283. ha->dma32_cnt++;
  2284. #endif
  2285. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2286. }
  2287. } else {
  2288. struct scatterlist *sl;
  2289. cmdp->u.cache.DestAddr= 0xffffffff;
  2290. cmdp->u.cache.sg_canz = sgcnt;
  2291. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2292. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2293. #ifdef GDTH_DMA_STATISTICS
  2294. ha->dma32_cnt++;
  2295. #endif
  2296. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2297. }
  2298. }
  2299. #ifdef GDTH_STATISTICS
  2300. if (max_sg < (u32)sgcnt) {
  2301. max_sg = (u32)sgcnt;
  2302. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2303. }
  2304. #endif
  2305. }
  2306. }
  2307. /* evaluate command size, check space */
  2308. if (mode64) {
  2309. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2310. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2311. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2312. cmdp->u.cache64.sg_lst[0].sg_len));
  2313. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2314. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2315. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2316. (u16)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2317. } else {
  2318. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2319. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2320. cmdp->u.cache.sg_lst[0].sg_ptr,
  2321. cmdp->u.cache.sg_lst[0].sg_len));
  2322. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2323. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2324. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2325. (u16)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2326. }
  2327. if (ha->cmd_len & 3)
  2328. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2329. if (ha->cmd_cnt > 0) {
  2330. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2331. ha->ic_all_size) {
  2332. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2333. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2334. return 0;
  2335. }
  2336. }
  2337. /* copy command */
  2338. gdth_copy_command(ha);
  2339. return cmd_index;
  2340. }
  2341. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b)
  2342. {
  2343. register gdth_cmd_str *cmdp;
  2344. u16 i;
  2345. dma_addr_t sense_paddr;
  2346. int cmd_index, sgcnt, mode64;
  2347. u8 t,l;
  2348. struct page *page;
  2349. unsigned long offset;
  2350. struct gdth_cmndinfo *cmndinfo;
  2351. t = scp->device->id;
  2352. l = scp->device->lun;
  2353. cmdp = ha->pccb;
  2354. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2355. scp->cmnd[0],b,t,l));
  2356. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2357. return 0;
  2358. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2359. cmdp->Service = SCSIRAWSERVICE;
  2360. cmdp->RequestBuffer = scp;
  2361. /* search free command index */
  2362. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2363. TRACE(("GDT: No free command index found\n"));
  2364. return 0;
  2365. }
  2366. /* if it's the first command, set command semaphore */
  2367. if (ha->cmd_cnt == 0)
  2368. gdth_set_sema0(ha);
  2369. cmndinfo = gdth_cmnd_priv(scp);
  2370. /* fill command */
  2371. if (cmndinfo->OpCode != -1) {
  2372. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2373. cmdp->BoardNode = LOCALBOARD;
  2374. if (mode64) {
  2375. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2376. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2377. cmdp->OpCode, cmdp->u.raw64.direction));
  2378. /* evaluate command size */
  2379. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2380. } else {
  2381. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2382. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2383. cmdp->OpCode, cmdp->u.raw.direction));
  2384. /* evaluate command size */
  2385. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2386. }
  2387. } else {
  2388. page = virt_to_page(scp->sense_buffer);
  2389. offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
  2390. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2391. 16,PCI_DMA_FROMDEVICE);
  2392. cmndinfo->sense_paddr = sense_paddr;
  2393. cmdp->OpCode = GDT_WRITE; /* always */
  2394. cmdp->BoardNode = LOCALBOARD;
  2395. if (mode64) {
  2396. cmdp->u.raw64.reserved = 0;
  2397. cmdp->u.raw64.mdisc_time = 0;
  2398. cmdp->u.raw64.mcon_time = 0;
  2399. cmdp->u.raw64.clen = scp->cmd_len;
  2400. cmdp->u.raw64.target = t;
  2401. cmdp->u.raw64.lun = l;
  2402. cmdp->u.raw64.bus = b;
  2403. cmdp->u.raw64.priority = 0;
  2404. cmdp->u.raw64.sdlen = scsi_bufflen(scp);
  2405. cmdp->u.raw64.sense_len = 16;
  2406. cmdp->u.raw64.sense_data = sense_paddr;
  2407. cmdp->u.raw64.direction =
  2408. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2409. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2410. cmdp->u.raw64.sg_ranz = 0;
  2411. } else {
  2412. cmdp->u.raw.reserved = 0;
  2413. cmdp->u.raw.mdisc_time = 0;
  2414. cmdp->u.raw.mcon_time = 0;
  2415. cmdp->u.raw.clen = scp->cmd_len;
  2416. cmdp->u.raw.target = t;
  2417. cmdp->u.raw.lun = l;
  2418. cmdp->u.raw.bus = b;
  2419. cmdp->u.raw.priority = 0;
  2420. cmdp->u.raw.link_p = 0;
  2421. cmdp->u.raw.sdlen = scsi_bufflen(scp);
  2422. cmdp->u.raw.sense_len = 16;
  2423. cmdp->u.raw.sense_data = sense_paddr;
  2424. cmdp->u.raw.direction =
  2425. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2426. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2427. cmdp->u.raw.sg_ranz = 0;
  2428. }
  2429. if (scsi_bufflen(scp)) {
  2430. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2431. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2432. cmndinfo->dma_dir);
  2433. if (mode64) {
  2434. struct scatterlist *sl;
  2435. cmdp->u.raw64.sdata = (u64)-1;
  2436. cmdp->u.raw64.sg_ranz = sgcnt;
  2437. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2438. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2439. #ifdef GDTH_DMA_STATISTICS
  2440. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2441. ha->dma64_cnt++;
  2442. else
  2443. ha->dma32_cnt++;
  2444. #endif
  2445. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2446. }
  2447. } else {
  2448. struct scatterlist *sl;
  2449. cmdp->u.raw.sdata = 0xffffffff;
  2450. cmdp->u.raw.sg_ranz = sgcnt;
  2451. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2452. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2453. #ifdef GDTH_DMA_STATISTICS
  2454. ha->dma32_cnt++;
  2455. #endif
  2456. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2457. }
  2458. }
  2459. #ifdef GDTH_STATISTICS
  2460. if (max_sg < sgcnt) {
  2461. max_sg = sgcnt;
  2462. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2463. }
  2464. #endif
  2465. }
  2466. if (mode64) {
  2467. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2468. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2469. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2470. cmdp->u.raw64.sg_lst[0].sg_len));
  2471. /* evaluate command size */
  2472. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2473. (u16)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2474. } else {
  2475. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2476. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2477. cmdp->u.raw.sg_lst[0].sg_ptr,
  2478. cmdp->u.raw.sg_lst[0].sg_len));
  2479. /* evaluate command size */
  2480. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2481. (u16)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2482. }
  2483. }
  2484. /* check space */
  2485. if (ha->cmd_len & 3)
  2486. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2487. if (ha->cmd_cnt > 0) {
  2488. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2489. ha->ic_all_size) {
  2490. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2491. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2492. return 0;
  2493. }
  2494. }
  2495. /* copy command */
  2496. gdth_copy_command(ha);
  2497. return cmd_index;
  2498. }
  2499. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2500. {
  2501. register gdth_cmd_str *cmdp;
  2502. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2503. int cmd_index;
  2504. cmdp= ha->pccb;
  2505. TRACE2(("gdth_special_cmd(): "));
  2506. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2507. return 0;
  2508. *cmdp = *cmndinfo->internal_cmd_str;
  2509. cmdp->RequestBuffer = scp;
  2510. /* search free command index */
  2511. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2512. TRACE(("GDT: No free command index found\n"));
  2513. return 0;
  2514. }
  2515. /* if it's the first command, set command semaphore */
  2516. if (ha->cmd_cnt == 0)
  2517. gdth_set_sema0(ha);
  2518. /* evaluate command size, check space */
  2519. if (cmdp->OpCode == GDT_IOCTL) {
  2520. TRACE2(("IOCTL\n"));
  2521. ha->cmd_len =
  2522. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(u64);
  2523. } else if (cmdp->Service == CACHESERVICE) {
  2524. TRACE2(("cache command %d\n",cmdp->OpCode));
  2525. if (ha->cache_feat & GDT_64BIT)
  2526. ha->cmd_len =
  2527. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2528. else
  2529. ha->cmd_len =
  2530. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2531. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2532. TRACE2(("raw command %d\n",cmdp->OpCode));
  2533. if (ha->raw_feat & GDT_64BIT)
  2534. ha->cmd_len =
  2535. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2536. else
  2537. ha->cmd_len =
  2538. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2539. }
  2540. if (ha->cmd_len & 3)
  2541. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2542. if (ha->cmd_cnt > 0) {
  2543. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2544. ha->ic_all_size) {
  2545. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2546. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2547. return 0;
  2548. }
  2549. }
  2550. /* copy command */
  2551. gdth_copy_command(ha);
  2552. return cmd_index;
  2553. }
  2554. /* Controller event handling functions */
  2555. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  2556. u16 idx, gdth_evt_data *evt)
  2557. {
  2558. gdth_evt_str *e;
  2559. struct timeval tv;
  2560. /* no GDTH_LOCK_HA() ! */
  2561. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2562. if (source == 0) /* no source -> no event */
  2563. return NULL;
  2564. if (ebuffer[elastidx].event_source == source &&
  2565. ebuffer[elastidx].event_idx == idx &&
  2566. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2567. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2568. (char *)&evt->eu, evt->size)) ||
  2569. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2570. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2571. (char *)&evt->event_string)))) {
  2572. e = &ebuffer[elastidx];
  2573. do_gettimeofday(&tv);
  2574. e->last_stamp = tv.tv_sec;
  2575. ++e->same_count;
  2576. } else {
  2577. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2578. ++elastidx;
  2579. if (elastidx == MAX_EVENTS)
  2580. elastidx = 0;
  2581. if (elastidx == eoldidx) { /* reached mark ? */
  2582. ++eoldidx;
  2583. if (eoldidx == MAX_EVENTS)
  2584. eoldidx = 0;
  2585. }
  2586. }
  2587. e = &ebuffer[elastidx];
  2588. e->event_source = source;
  2589. e->event_idx = idx;
  2590. do_gettimeofday(&tv);
  2591. e->first_stamp = e->last_stamp = tv.tv_sec;
  2592. e->same_count = 1;
  2593. e->event_data = *evt;
  2594. e->application = 0;
  2595. }
  2596. return e;
  2597. }
  2598. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2599. {
  2600. gdth_evt_str *e;
  2601. int eindex;
  2602. unsigned long flags;
  2603. TRACE2(("gdth_read_event() handle %d\n", handle));
  2604. spin_lock_irqsave(&ha->smp_lock, flags);
  2605. if (handle == -1)
  2606. eindex = eoldidx;
  2607. else
  2608. eindex = handle;
  2609. estr->event_source = 0;
  2610. if (eindex < 0 || eindex >= MAX_EVENTS) {
  2611. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2612. return eindex;
  2613. }
  2614. e = &ebuffer[eindex];
  2615. if (e->event_source != 0) {
  2616. if (eindex != elastidx) {
  2617. if (++eindex == MAX_EVENTS)
  2618. eindex = 0;
  2619. } else {
  2620. eindex = -1;
  2621. }
  2622. memcpy(estr, e, sizeof(gdth_evt_str));
  2623. }
  2624. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2625. return eindex;
  2626. }
  2627. static void gdth_readapp_event(gdth_ha_str *ha,
  2628. u8 application, gdth_evt_str *estr)
  2629. {
  2630. gdth_evt_str *e;
  2631. int eindex;
  2632. unsigned long flags;
  2633. u8 found = FALSE;
  2634. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2635. spin_lock_irqsave(&ha->smp_lock, flags);
  2636. eindex = eoldidx;
  2637. for (;;) {
  2638. e = &ebuffer[eindex];
  2639. if (e->event_source == 0)
  2640. break;
  2641. if ((e->application & application) == 0) {
  2642. e->application |= application;
  2643. found = TRUE;
  2644. break;
  2645. }
  2646. if (eindex == elastidx)
  2647. break;
  2648. if (++eindex == MAX_EVENTS)
  2649. eindex = 0;
  2650. }
  2651. if (found)
  2652. memcpy(estr, e, sizeof(gdth_evt_str));
  2653. else
  2654. estr->event_source = 0;
  2655. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2656. }
  2657. static void gdth_clear_events(void)
  2658. {
  2659. TRACE(("gdth_clear_events()"));
  2660. eoldidx = elastidx = 0;
  2661. ebuffer[0].event_source = 0;
  2662. }
  2663. /* SCSI interface functions */
  2664. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2665. int gdth_from_wait, int* pIndex)
  2666. {
  2667. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2668. gdt6_dpram_str __iomem *dp6_ptr;
  2669. gdt2_dpram_str __iomem *dp2_ptr;
  2670. Scsi_Cmnd *scp;
  2671. int rval, i;
  2672. u8 IStatus;
  2673. u16 Service;
  2674. unsigned long flags = 0;
  2675. #ifdef INT_COAL
  2676. int coalesced = FALSE;
  2677. int next = FALSE;
  2678. gdth_coal_status *pcs = NULL;
  2679. int act_int_coal = 0;
  2680. #endif
  2681. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2682. /* if polling and not from gdth_wait() -> return */
  2683. if (gdth_polling) {
  2684. if (!gdth_from_wait) {
  2685. return IRQ_HANDLED;
  2686. }
  2687. }
  2688. if (!gdth_polling)
  2689. spin_lock_irqsave(&ha->smp_lock, flags);
  2690. /* search controller */
  2691. IStatus = gdth_get_status(ha);
  2692. if (IStatus == 0) {
  2693. /* spurious interrupt */
  2694. if (!gdth_polling)
  2695. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2696. return IRQ_HANDLED;
  2697. }
  2698. #ifdef GDTH_STATISTICS
  2699. ++act_ints;
  2700. #endif
  2701. #ifdef INT_COAL
  2702. /* See if the fw is returning coalesced status */
  2703. if (IStatus == COALINDEX) {
  2704. /* Coalesced status. Setup the initial status
  2705. buffer pointer and flags */
  2706. pcs = ha->coal_stat;
  2707. coalesced = TRUE;
  2708. next = TRUE;
  2709. }
  2710. do {
  2711. if (coalesced) {
  2712. /* For coalesced requests all status
  2713. information is found in the status buffer */
  2714. IStatus = (u8)(pcs->status & 0xff);
  2715. }
  2716. #endif
  2717. if (ha->type == GDT_EISA) {
  2718. if (IStatus & 0x80) { /* error flag */
  2719. IStatus &= ~0x80;
  2720. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2721. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2722. } else /* no error */
  2723. ha->status = S_OK;
  2724. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2725. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2726. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2727. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2728. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2729. } else if (ha->type == GDT_ISA) {
  2730. dp2_ptr = ha->brd;
  2731. if (IStatus & 0x80) { /* error flag */
  2732. IStatus &= ~0x80;
  2733. ha->status = readw(&dp2_ptr->u.ic.Status);
  2734. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2735. } else /* no error */
  2736. ha->status = S_OK;
  2737. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2738. ha->service = readw(&dp2_ptr->u.ic.Service);
  2739. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2740. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2741. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2742. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2743. } else if (ha->type == GDT_PCI) {
  2744. dp6_ptr = ha->brd;
  2745. if (IStatus & 0x80) { /* error flag */
  2746. IStatus &= ~0x80;
  2747. ha->status = readw(&dp6_ptr->u.ic.Status);
  2748. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2749. } else /* no error */
  2750. ha->status = S_OK;
  2751. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2752. ha->service = readw(&dp6_ptr->u.ic.Service);
  2753. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2754. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2755. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2756. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2757. } else if (ha->type == GDT_PCINEW) {
  2758. if (IStatus & 0x80) { /* error flag */
  2759. IStatus &= ~0x80;
  2760. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2761. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2762. } else
  2763. ha->status = S_OK;
  2764. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2765. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2766. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2767. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2768. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2769. } else if (ha->type == GDT_PCIMPR) {
  2770. dp6m_ptr = ha->brd;
  2771. if (IStatus & 0x80) { /* error flag */
  2772. IStatus &= ~0x80;
  2773. #ifdef INT_COAL
  2774. if (coalesced)
  2775. ha->status = pcs->ext_status & 0xffff;
  2776. else
  2777. #endif
  2778. ha->status = readw(&dp6m_ptr->i960r.status);
  2779. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2780. } else /* no error */
  2781. ha->status = S_OK;
  2782. #ifdef INT_COAL
  2783. /* get information */
  2784. if (coalesced) {
  2785. ha->info = pcs->info0;
  2786. ha->info2 = pcs->info1;
  2787. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2788. } else
  2789. #endif
  2790. {
  2791. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2792. ha->service = readw(&dp6m_ptr->i960r.service);
  2793. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2794. }
  2795. /* event string */
  2796. if (IStatus == ASYNCINDEX) {
  2797. if (ha->service != SCREENSERVICE &&
  2798. (ha->fw_vers & 0xff) >= 0x1a) {
  2799. ha->dvr.severity = readb
  2800. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2801. for (i = 0; i < 256; ++i) {
  2802. ha->dvr.event_string[i] = readb
  2803. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2804. if (ha->dvr.event_string[i] == 0)
  2805. break;
  2806. }
  2807. }
  2808. }
  2809. #ifdef INT_COAL
  2810. /* Make sure that non coalesced interrupts get cleared
  2811. before being handled by gdth_async_event/gdth_sync_event */
  2812. if (!coalesced)
  2813. #endif
  2814. {
  2815. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2816. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2817. }
  2818. } else {
  2819. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2820. if (!gdth_polling)
  2821. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2822. return IRQ_HANDLED;
  2823. }
  2824. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2825. IStatus,ha->status,ha->info));
  2826. if (gdth_from_wait) {
  2827. *pIndex = (int)IStatus;
  2828. }
  2829. if (IStatus == ASYNCINDEX) {
  2830. TRACE2(("gdth_interrupt() async. event\n"));
  2831. gdth_async_event(ha);
  2832. if (!gdth_polling)
  2833. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2834. gdth_next(ha);
  2835. return IRQ_HANDLED;
  2836. }
  2837. if (IStatus == SPEZINDEX) {
  2838. TRACE2(("Service unknown or not initialized !\n"));
  2839. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2840. ha->dvr.eu.driver.ionode = ha->hanum;
  2841. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2842. if (!gdth_polling)
  2843. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2844. return IRQ_HANDLED;
  2845. }
  2846. scp = ha->cmd_tab[IStatus-2].cmnd;
  2847. Service = ha->cmd_tab[IStatus-2].service;
  2848. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2849. if (scp == UNUSED_CMND) {
  2850. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2851. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2852. ha->dvr.eu.driver.ionode = ha->hanum;
  2853. ha->dvr.eu.driver.index = IStatus;
  2854. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2855. if (!gdth_polling)
  2856. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2857. return IRQ_HANDLED;
  2858. }
  2859. if (scp == INTERNAL_CMND) {
  2860. TRACE(("gdth_interrupt() answer to internal command\n"));
  2861. if (!gdth_polling)
  2862. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2863. return IRQ_HANDLED;
  2864. }
  2865. TRACE(("gdth_interrupt() sync. status\n"));
  2866. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2867. if (!gdth_polling)
  2868. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2869. if (rval == 2) {
  2870. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2871. } else if (rval == 1) {
  2872. gdth_scsi_done(scp);
  2873. }
  2874. #ifdef INT_COAL
  2875. if (coalesced) {
  2876. /* go to the next status in the status buffer */
  2877. ++pcs;
  2878. #ifdef GDTH_STATISTICS
  2879. ++act_int_coal;
  2880. if (act_int_coal > max_int_coal) {
  2881. max_int_coal = act_int_coal;
  2882. printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
  2883. }
  2884. #endif
  2885. /* see if there is another status */
  2886. if (pcs->status == 0)
  2887. /* Stop the coalesce loop */
  2888. next = FALSE;
  2889. }
  2890. } while (next);
  2891. /* coalescing only for new GDT_PCIMPR controllers available */
  2892. if (ha->type == GDT_PCIMPR && coalesced) {
  2893. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2894. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2895. }
  2896. #endif
  2897. gdth_next(ha);
  2898. return IRQ_HANDLED;
  2899. }
  2900. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2901. {
  2902. gdth_ha_str *ha = dev_id;
  2903. return __gdth_interrupt(ha, false, NULL);
  2904. }
  2905. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  2906. Scsi_Cmnd *scp)
  2907. {
  2908. gdth_msg_str *msg;
  2909. gdth_cmd_str *cmdp;
  2910. u8 b, t;
  2911. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2912. cmdp = ha->pccb;
  2913. TRACE(("gdth_sync_event() serv %d status %d\n",
  2914. service,ha->status));
  2915. if (service == SCREENSERVICE) {
  2916. msg = ha->pmsg;
  2917. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2918. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2919. if (msg->msg_len > MSGLEN+1)
  2920. msg->msg_len = MSGLEN+1;
  2921. if (msg->msg_len)
  2922. if (!(msg->msg_answer && msg->msg_ext)) {
  2923. msg->msg_text[msg->msg_len] = '\0';
  2924. printk("%s",msg->msg_text);
  2925. }
  2926. if (msg->msg_ext && !msg->msg_answer) {
  2927. while (gdth_test_busy(ha))
  2928. gdth_delay(0);
  2929. cmdp->Service = SCREENSERVICE;
  2930. cmdp->RequestBuffer = SCREEN_CMND;
  2931. gdth_get_cmd_index(ha);
  2932. gdth_set_sema0(ha);
  2933. cmdp->OpCode = GDT_READ;
  2934. cmdp->BoardNode = LOCALBOARD;
  2935. cmdp->u.screen.reserved = 0;
  2936. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2937. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2938. ha->cmd_offs_dpmem = 0;
  2939. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2940. + sizeof(u64);
  2941. ha->cmd_cnt = 0;
  2942. gdth_copy_command(ha);
  2943. gdth_release_event(ha);
  2944. return 0;
  2945. }
  2946. if (msg->msg_answer && msg->msg_alen) {
  2947. /* default answers (getchar() not possible) */
  2948. if (msg->msg_alen == 1) {
  2949. msg->msg_alen = 0;
  2950. msg->msg_len = 1;
  2951. msg->msg_text[0] = 0;
  2952. } else {
  2953. msg->msg_alen -= 2;
  2954. msg->msg_len = 2;
  2955. msg->msg_text[0] = 1;
  2956. msg->msg_text[1] = 0;
  2957. }
  2958. msg->msg_ext = 0;
  2959. msg->msg_answer = 0;
  2960. while (gdth_test_busy(ha))
  2961. gdth_delay(0);
  2962. cmdp->Service = SCREENSERVICE;
  2963. cmdp->RequestBuffer = SCREEN_CMND;
  2964. gdth_get_cmd_index(ha);
  2965. gdth_set_sema0(ha);
  2966. cmdp->OpCode = GDT_WRITE;
  2967. cmdp->BoardNode = LOCALBOARD;
  2968. cmdp->u.screen.reserved = 0;
  2969. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2970. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2971. ha->cmd_offs_dpmem = 0;
  2972. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2973. + sizeof(u64);
  2974. ha->cmd_cnt = 0;
  2975. gdth_copy_command(ha);
  2976. gdth_release_event(ha);
  2977. return 0;
  2978. }
  2979. printk("\n");
  2980. } else {
  2981. b = scp->device->channel;
  2982. t = scp->device->id;
  2983. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  2984. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  2985. }
  2986. /* cache or raw service */
  2987. if (ha->status == S_BSY) {
  2988. TRACE2(("Controller busy -> retry !\n"));
  2989. if (cmndinfo->OpCode == GDT_MOUNT)
  2990. cmndinfo->OpCode = GDT_CLUST_INFO;
  2991. /* retry */
  2992. return 2;
  2993. }
  2994. if (scsi_bufflen(scp))
  2995. pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2996. cmndinfo->dma_dir);
  2997. if (cmndinfo->sense_paddr)
  2998. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  2999. PCI_DMA_FROMDEVICE);
  3000. if (ha->status == S_OK) {
  3001. cmndinfo->status = S_OK;
  3002. cmndinfo->info = ha->info;
  3003. if (cmndinfo->OpCode != -1) {
  3004. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3005. cmndinfo->OpCode));
  3006. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3007. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3008. ha->hdr[t].cluster_type = (u8)ha->info;
  3009. if (!(ha->hdr[t].cluster_type &
  3010. CLUSTER_MOUNTED)) {
  3011. /* NOT MOUNTED -> MOUNT */
  3012. cmndinfo->OpCode = GDT_MOUNT;
  3013. if (ha->hdr[t].cluster_type &
  3014. CLUSTER_RESERVED) {
  3015. /* cluster drive RESERVED (on the other node) */
  3016. cmndinfo->phase = -2; /* reservation conflict */
  3017. }
  3018. } else {
  3019. cmndinfo->OpCode = -1;
  3020. }
  3021. } else {
  3022. if (cmndinfo->OpCode == GDT_MOUNT) {
  3023. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3024. ha->hdr[t].media_changed = TRUE;
  3025. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3026. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3027. ha->hdr[t].media_changed = TRUE;
  3028. }
  3029. cmndinfo->OpCode = -1;
  3030. }
  3031. /* retry */
  3032. cmndinfo->priority = HIGH_PRI;
  3033. return 2;
  3034. } else {
  3035. /* RESERVE/RELEASE ? */
  3036. if (scp->cmnd[0] == RESERVE) {
  3037. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3038. } else if (scp->cmnd[0] == RELEASE) {
  3039. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3040. }
  3041. scp->result = DID_OK << 16;
  3042. scp->sense_buffer[0] = 0;
  3043. }
  3044. } else {
  3045. cmndinfo->status = ha->status;
  3046. cmndinfo->info = ha->info;
  3047. if (cmndinfo->OpCode != -1) {
  3048. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3049. cmndinfo->OpCode, ha->status));
  3050. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3051. cmndinfo->OpCode == GDT_SCAN_END) {
  3052. cmndinfo->OpCode = -1;
  3053. /* retry */
  3054. cmndinfo->priority = HIGH_PRI;
  3055. return 2;
  3056. }
  3057. memset((char*)scp->sense_buffer,0,16);
  3058. scp->sense_buffer[0] = 0x70;
  3059. scp->sense_buffer[2] = NOT_READY;
  3060. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3061. } else if (service == CACHESERVICE) {
  3062. if (ha->status == S_CACHE_UNKNOWN &&
  3063. (ha->hdr[t].cluster_type &
  3064. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3065. /* bus reset -> force GDT_CLUST_INFO */
  3066. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3067. }
  3068. memset((char*)scp->sense_buffer,0,16);
  3069. if (ha->status == (u16)S_CACHE_RESERV) {
  3070. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3071. } else {
  3072. scp->sense_buffer[0] = 0x70;
  3073. scp->sense_buffer[2] = NOT_READY;
  3074. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3075. }
  3076. if (!cmndinfo->internal_command) {
  3077. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3078. ha->dvr.eu.sync.ionode = ha->hanum;
  3079. ha->dvr.eu.sync.service = service;
  3080. ha->dvr.eu.sync.status = ha->status;
  3081. ha->dvr.eu.sync.info = ha->info;
  3082. ha->dvr.eu.sync.hostdrive = t;
  3083. if (ha->status >= 0x8000)
  3084. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3085. else
  3086. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3087. }
  3088. } else {
  3089. /* sense buffer filled from controller firmware (DMA) */
  3090. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3091. scp->result = DID_BAD_TARGET << 16;
  3092. } else {
  3093. scp->result = (DID_OK << 16) | ha->info;
  3094. }
  3095. }
  3096. }
  3097. if (!cmndinfo->wait_for_completion)
  3098. cmndinfo->wait_for_completion++;
  3099. else
  3100. return 1;
  3101. }
  3102. return 0;
  3103. }
  3104. static char *async_cache_tab[] = {
  3105. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3106. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3107. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3108. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3109. /* 2*/ "\005\000\002\006\004"
  3110. "GDT HA %u, Host Drive %lu not ready",
  3111. /* 3*/ "\005\000\002\006\004"
  3112. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3113. /* 4*/ "\005\000\002\006\004"
  3114. "GDT HA %u, mirror update on Host Drive %lu failed",
  3115. /* 5*/ "\005\000\002\006\004"
  3116. "GDT HA %u, Mirror Drive %lu failed",
  3117. /* 6*/ "\005\000\002\006\004"
  3118. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3119. /* 7*/ "\005\000\002\006\004"
  3120. "GDT HA %u, Host Drive %lu write protected",
  3121. /* 8*/ "\005\000\002\006\004"
  3122. "GDT HA %u, media changed in Host Drive %lu",
  3123. /* 9*/ "\005\000\002\006\004"
  3124. "GDT HA %u, Host Drive %lu is offline",
  3125. /*10*/ "\005\000\002\006\004"
  3126. "GDT HA %u, media change of Mirror Drive %lu",
  3127. /*11*/ "\005\000\002\006\004"
  3128. "GDT HA %u, Mirror Drive %lu is write protected",
  3129. /*12*/ "\005\000\002\006\004"
  3130. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3131. /*13*/ "\007\000\002\006\002\010\002"
  3132. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3133. /*14*/ "\005\000\002\006\002"
  3134. "GDT HA %u, Array Drive %u: FAIL state entered",
  3135. /*15*/ "\005\000\002\006\002"
  3136. "GDT HA %u, Array Drive %u: error",
  3137. /*16*/ "\007\000\002\006\002\010\002"
  3138. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3139. /*17*/ "\005\000\002\006\002"
  3140. "GDT HA %u, Array Drive %u: parity build failed",
  3141. /*18*/ "\005\000\002\006\002"
  3142. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3143. /*19*/ "\005\000\002\010\002"
  3144. "GDT HA %u, Test of Hot Fix %u failed",
  3145. /*20*/ "\005\000\002\006\002"
  3146. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3147. /*21*/ "\005\000\002\006\002"
  3148. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3149. /*22*/ "\007\000\002\006\002\010\002"
  3150. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3151. /*23*/ "\005\000\002\006\002"
  3152. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3153. /*24*/ "\005\000\002\010\002"
  3154. "GDT HA %u, mirror update on Cache Drive %u completed",
  3155. /*25*/ "\005\000\002\010\002"
  3156. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3157. /*26*/ "\005\000\002\006\002"
  3158. "GDT HA %u, Array Drive %u: drive rebuild started",
  3159. /*27*/ "\005\000\002\012\001"
  3160. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3161. /*28*/ "\005\000\002\012\001"
  3162. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3163. /*29*/ "\007\000\002\012\001\013\001"
  3164. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3165. /*30*/ "\007\000\002\012\001\013\001"
  3166. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3167. /*31*/ "\007\000\002\012\001\013\001"
  3168. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3169. /*32*/ "\007\000\002\012\001\013\001"
  3170. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3171. /*33*/ "\007\000\002\012\001\013\001"
  3172. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3173. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3174. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3175. /*35*/ "\007\000\002\012\001\013\001"
  3176. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3177. /*36*/ "\007\000\002\012\001\013\001"
  3178. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3179. /*37*/ "\007\000\002\012\001\006\004"
  3180. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3181. /*38*/ "\007\000\002\012\001\013\001"
  3182. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3183. /*39*/ "\007\000\002\012\001\013\001"
  3184. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3185. /*40*/ "\007\000\002\012\001\013\001"
  3186. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3187. /*41*/ "\007\000\002\012\001\013\001"
  3188. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3189. /*42*/ "\005\000\002\006\002"
  3190. "GDT HA %u, Array Drive %u: drive build started",
  3191. /*43*/ "\003\000\002"
  3192. "GDT HA %u, DRAM parity error detected",
  3193. /*44*/ "\005\000\002\006\002"
  3194. "GDT HA %u, Mirror Drive %u: update started",
  3195. /*45*/ "\007\000\002\006\002\010\002"
  3196. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3197. /*46*/ "\005\000\002\006\002"
  3198. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3199. /*47*/ "\005\000\002\006\002"
  3200. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3201. /*48*/ "\005\000\002\006\002"
  3202. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3203. /*49*/ "\005\000\002\006\002"
  3204. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3205. /*50*/ "\007\000\002\012\001\013\001"
  3206. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3207. /*51*/ "\005\000\002\006\002"
  3208. "GDT HA %u, Array Drive %u: expand started",
  3209. /*52*/ "\005\000\002\006\002"
  3210. "GDT HA %u, Array Drive %u: expand finished successfully",
  3211. /*53*/ "\005\000\002\006\002"
  3212. "GDT HA %u, Array Drive %u: expand failed",
  3213. /*54*/ "\003\000\002"
  3214. "GDT HA %u, CPU temperature critical",
  3215. /*55*/ "\003\000\002"
  3216. "GDT HA %u, CPU temperature OK",
  3217. /*56*/ "\005\000\002\006\004"
  3218. "GDT HA %u, Host drive %lu created",
  3219. /*57*/ "\005\000\002\006\002"
  3220. "GDT HA %u, Array Drive %u: expand restarted",
  3221. /*58*/ "\005\000\002\006\002"
  3222. "GDT HA %u, Array Drive %u: expand stopped",
  3223. /*59*/ "\005\000\002\010\002"
  3224. "GDT HA %u, Mirror Drive %u: drive build quited",
  3225. /*60*/ "\005\000\002\006\002"
  3226. "GDT HA %u, Array Drive %u: parity build quited",
  3227. /*61*/ "\005\000\002\006\002"
  3228. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3229. /*62*/ "\005\000\002\006\002"
  3230. "GDT HA %u, Array Drive %u: parity verify started",
  3231. /*63*/ "\005\000\002\006\002"
  3232. "GDT HA %u, Array Drive %u: parity verify done",
  3233. /*64*/ "\005\000\002\006\002"
  3234. "GDT HA %u, Array Drive %u: parity verify failed",
  3235. /*65*/ "\005\000\002\006\002"
  3236. "GDT HA %u, Array Drive %u: parity error detected",
  3237. /*66*/ "\005\000\002\006\002"
  3238. "GDT HA %u, Array Drive %u: parity verify quited",
  3239. /*67*/ "\005\000\002\006\002"
  3240. "GDT HA %u, Host Drive %u reserved",
  3241. /*68*/ "\005\000\002\006\002"
  3242. "GDT HA %u, Host Drive %u mounted and released",
  3243. /*69*/ "\005\000\002\006\002"
  3244. "GDT HA %u, Host Drive %u released",
  3245. /*70*/ "\003\000\002"
  3246. "GDT HA %u, DRAM error detected and corrected with ECC",
  3247. /*71*/ "\003\000\002"
  3248. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3249. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3250. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3251. /*73*/ "\005\000\002\006\002"
  3252. "GDT HA %u, Host drive %u resetted locally",
  3253. /*74*/ "\005\000\002\006\002"
  3254. "GDT HA %u, Host drive %u resetted remotely",
  3255. /*75*/ "\003\000\002"
  3256. "GDT HA %u, async. status 75 unknown",
  3257. };
  3258. static int gdth_async_event(gdth_ha_str *ha)
  3259. {
  3260. gdth_cmd_str *cmdp;
  3261. int cmd_index;
  3262. cmdp= ha->pccb;
  3263. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3264. ha->hanum, ha->service));
  3265. if (ha->service == SCREENSERVICE) {
  3266. if (ha->status == MSG_REQUEST) {
  3267. while (gdth_test_busy(ha))
  3268. gdth_delay(0);
  3269. cmdp->Service = SCREENSERVICE;
  3270. cmdp->RequestBuffer = SCREEN_CMND;
  3271. cmd_index = gdth_get_cmd_index(ha);
  3272. gdth_set_sema0(ha);
  3273. cmdp->OpCode = GDT_READ;
  3274. cmdp->BoardNode = LOCALBOARD;
  3275. cmdp->u.screen.reserved = 0;
  3276. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3277. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3278. ha->cmd_offs_dpmem = 0;
  3279. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3280. + sizeof(u64);
  3281. ha->cmd_cnt = 0;
  3282. gdth_copy_command(ha);
  3283. if (ha->type == GDT_EISA)
  3284. printk("[EISA slot %d] ",(u16)ha->brd_phys);
  3285. else if (ha->type == GDT_ISA)
  3286. printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
  3287. else
  3288. printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
  3289. (u16)((ha->brd_phys>>3)&0x1f));
  3290. gdth_release_event(ha);
  3291. }
  3292. } else {
  3293. if (ha->type == GDT_PCIMPR &&
  3294. (ha->fw_vers & 0xff) >= 0x1a) {
  3295. ha->dvr.size = 0;
  3296. ha->dvr.eu.async.ionode = ha->hanum;
  3297. ha->dvr.eu.async.status = ha->status;
  3298. /* severity and event_string already set! */
  3299. } else {
  3300. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3301. ha->dvr.eu.async.ionode = ha->hanum;
  3302. ha->dvr.eu.async.service = ha->service;
  3303. ha->dvr.eu.async.status = ha->status;
  3304. ha->dvr.eu.async.info = ha->info;
  3305. *(u32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3306. }
  3307. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3308. gdth_log_event( &ha->dvr, NULL );
  3309. /* new host drive from expand? */
  3310. if (ha->service == CACHESERVICE && ha->status == 56) {
  3311. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3312. (u16)ha->info));
  3313. /* gdth_analyse_hdrive(hanum, (u16)ha->info); */
  3314. }
  3315. }
  3316. return 1;
  3317. }
  3318. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3319. {
  3320. gdth_stackframe stack;
  3321. char *f = NULL;
  3322. int i,j;
  3323. TRACE2(("gdth_log_event()\n"));
  3324. if (dvr->size == 0) {
  3325. if (buffer == NULL) {
  3326. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3327. } else {
  3328. sprintf(buffer,"Adapter %d: %s\n",
  3329. dvr->eu.async.ionode,dvr->event_string);
  3330. }
  3331. } else if (dvr->eu.async.service == CACHESERVICE &&
  3332. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3333. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3334. dvr->eu.async.status));
  3335. f = async_cache_tab[dvr->eu.async.status];
  3336. /* i: parameter to push, j: stack element to fill */
  3337. for (j=0,i=1; i < f[0]; i+=2) {
  3338. switch (f[i+1]) {
  3339. case 4:
  3340. stack.b[j++] = *(u32*)&dvr->eu.stream[(int)f[i]];
  3341. break;
  3342. case 2:
  3343. stack.b[j++] = *(u16*)&dvr->eu.stream[(int)f[i]];
  3344. break;
  3345. case 1:
  3346. stack.b[j++] = *(u8*)&dvr->eu.stream[(int)f[i]];
  3347. break;
  3348. default:
  3349. break;
  3350. }
  3351. }
  3352. if (buffer == NULL) {
  3353. printk(&f[(int)f[0]],stack);
  3354. printk("\n");
  3355. } else {
  3356. sprintf(buffer,&f[(int)f[0]],stack);
  3357. }
  3358. } else {
  3359. if (buffer == NULL) {
  3360. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3361. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3362. } else {
  3363. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3364. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3365. }
  3366. }
  3367. }
  3368. #ifdef GDTH_STATISTICS
  3369. static u8 gdth_timer_running;
  3370. static void gdth_timeout(unsigned long data)
  3371. {
  3372. u32 i;
  3373. Scsi_Cmnd *nscp;
  3374. gdth_ha_str *ha;
  3375. unsigned long flags;
  3376. if(unlikely(list_empty(&gdth_instances))) {
  3377. gdth_timer_running = 0;
  3378. return;
  3379. }
  3380. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3381. spin_lock_irqsave(&ha->smp_lock, flags);
  3382. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3383. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3384. ++act_stats;
  3385. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3386. ++act_rq;
  3387. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3388. act_ints, act_ios, act_stats, act_rq));
  3389. act_ints = act_ios = 0;
  3390. gdth_timer.expires = jiffies + 30 * HZ;
  3391. add_timer(&gdth_timer);
  3392. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3393. }
  3394. static void gdth_timer_init(void)
  3395. {
  3396. if (gdth_timer_running)
  3397. return;
  3398. gdth_timer_running = 1;
  3399. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3400. gdth_timer.expires = jiffies + HZ;
  3401. gdth_timer.data = 0L;
  3402. gdth_timer.function = gdth_timeout;
  3403. add_timer(&gdth_timer);
  3404. }
  3405. #else
  3406. static inline void gdth_timer_init(void)
  3407. {
  3408. }
  3409. #endif
  3410. static void __init internal_setup(char *str,int *ints)
  3411. {
  3412. int i, argc;
  3413. char *cur_str, *argv;
  3414. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3415. str ? str:"NULL", ints ? ints[0]:0));
  3416. /* read irq[] from ints[] */
  3417. if (ints) {
  3418. argc = ints[0];
  3419. if (argc > 0) {
  3420. if (argc > MAXHA)
  3421. argc = MAXHA;
  3422. for (i = 0; i < argc; ++i)
  3423. irq[i] = ints[i+1];
  3424. }
  3425. }
  3426. /* analyse string */
  3427. argv = str;
  3428. while (argv && (cur_str = strchr(argv, ':'))) {
  3429. int val = 0, c = *++cur_str;
  3430. if (c == 'n' || c == 'N')
  3431. val = 0;
  3432. else if (c == 'y' || c == 'Y')
  3433. val = 1;
  3434. else
  3435. val = (int)simple_strtoul(cur_str, NULL, 0);
  3436. if (!strncmp(argv, "disable:", 8))
  3437. disable = val;
  3438. else if (!strncmp(argv, "reserve_mode:", 13))
  3439. reserve_mode = val;
  3440. else if (!strncmp(argv, "reverse_scan:", 13))
  3441. reverse_scan = val;
  3442. else if (!strncmp(argv, "hdr_channel:", 12))
  3443. hdr_channel = val;
  3444. else if (!strncmp(argv, "max_ids:", 8))
  3445. max_ids = val;
  3446. else if (!strncmp(argv, "rescan:", 7))
  3447. rescan = val;
  3448. else if (!strncmp(argv, "shared_access:", 14))
  3449. shared_access = val;
  3450. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3451. probe_eisa_isa = val;
  3452. else if (!strncmp(argv, "reserve_list:", 13)) {
  3453. reserve_list[0] = val;
  3454. for (i = 1; i < MAX_RES_ARGS; i++) {
  3455. cur_str = strchr(cur_str, ',');
  3456. if (!cur_str)
  3457. break;
  3458. if (!isdigit((int)*++cur_str)) {
  3459. --cur_str;
  3460. break;
  3461. }
  3462. reserve_list[i] =
  3463. (int)simple_strtoul(cur_str, NULL, 0);
  3464. }
  3465. if (!cur_str)
  3466. break;
  3467. argv = ++cur_str;
  3468. continue;
  3469. }
  3470. if ((argv = strchr(argv, ',')))
  3471. ++argv;
  3472. }
  3473. }
  3474. int __init option_setup(char *str)
  3475. {
  3476. int ints[MAXHA];
  3477. char *cur = str;
  3478. int i = 1;
  3479. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3480. while (cur && isdigit(*cur) && i < MAXHA) {
  3481. ints[i++] = simple_strtoul(cur, NULL, 0);
  3482. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3483. }
  3484. ints[0] = i - 1;
  3485. internal_setup(cur, ints);
  3486. return 1;
  3487. }
  3488. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3489. {
  3490. TRACE2(("gdth_ctr_name()\n"));
  3491. if (ha->type == GDT_EISA) {
  3492. switch (ha->stype) {
  3493. case GDT3_ID:
  3494. return("GDT3000/3020");
  3495. case GDT3A_ID:
  3496. return("GDT3000A/3020A/3050A");
  3497. case GDT3B_ID:
  3498. return("GDT3000B/3010A");
  3499. }
  3500. } else if (ha->type == GDT_ISA) {
  3501. return("GDT2000/2020");
  3502. } else if (ha->type == GDT_PCI) {
  3503. switch (ha->pdev->device) {
  3504. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3505. return("GDT6000/6020/6050");
  3506. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3507. return("GDT6000B/6010");
  3508. }
  3509. }
  3510. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3511. return("");
  3512. }
  3513. static const char *gdth_info(struct Scsi_Host *shp)
  3514. {
  3515. gdth_ha_str *ha = shost_priv(shp);
  3516. TRACE2(("gdth_info()\n"));
  3517. return ((const char *)ha->binfo.type_string);
  3518. }
  3519. static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
  3520. {
  3521. gdth_ha_str *ha = shost_priv(scp->device->host);
  3522. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  3523. u8 b, t;
  3524. unsigned long flags;
  3525. enum blk_eh_timer_return retval = BLK_EH_NOT_HANDLED;
  3526. TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
  3527. b = scp->device->channel;
  3528. t = scp->device->id;
  3529. /*
  3530. * We don't really honor the command timeout, but we try to
  3531. * honor 6 times of the actual command timeout! So reset the
  3532. * timer if this is less than 6th timeout on this command!
  3533. */
  3534. if (++cmndinfo->timeout_count < 6)
  3535. retval = BLK_EH_RESET_TIMER;
  3536. /* Reset the timeout if it is locked IO */
  3537. spin_lock_irqsave(&ha->smp_lock, flags);
  3538. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
  3539. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  3540. TRACE2(("%s(): locked IO, reset timeout\n", __func__));
  3541. retval = BLK_EH_RESET_TIMER;
  3542. }
  3543. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3544. return retval;
  3545. }
  3546. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3547. {
  3548. gdth_ha_str *ha = shost_priv(scp->device->host);
  3549. int i;
  3550. unsigned long flags;
  3551. Scsi_Cmnd *cmnd;
  3552. u8 b;
  3553. TRACE2(("gdth_eh_bus_reset()\n"));
  3554. b = scp->device->channel;
  3555. /* clear command tab */
  3556. spin_lock_irqsave(&ha->smp_lock, flags);
  3557. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3558. cmnd = ha->cmd_tab[i].cmnd;
  3559. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3560. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3561. }
  3562. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3563. if (b == ha->virt_bus) {
  3564. /* host drives */
  3565. for (i = 0; i < MAX_HDRIVES; ++i) {
  3566. if (ha->hdr[i].present) {
  3567. spin_lock_irqsave(&ha->smp_lock, flags);
  3568. gdth_polling = TRUE;
  3569. while (gdth_test_busy(ha))
  3570. gdth_delay(0);
  3571. if (gdth_internal_cmd(ha, CACHESERVICE,
  3572. GDT_CLUST_RESET, i, 0, 0))
  3573. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3574. gdth_polling = FALSE;
  3575. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3576. }
  3577. }
  3578. } else {
  3579. /* raw devices */
  3580. spin_lock_irqsave(&ha->smp_lock, flags);
  3581. for (i = 0; i < MAXID; ++i)
  3582. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3583. gdth_polling = TRUE;
  3584. while (gdth_test_busy(ha))
  3585. gdth_delay(0);
  3586. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3587. BUS_L2P(ha,b), 0, 0);
  3588. gdth_polling = FALSE;
  3589. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3590. }
  3591. return SUCCESS;
  3592. }
  3593. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3594. {
  3595. u8 b, t;
  3596. gdth_ha_str *ha = shost_priv(sdev->host);
  3597. struct scsi_device *sd;
  3598. unsigned capacity;
  3599. sd = sdev;
  3600. capacity = cap;
  3601. b = sd->channel;
  3602. t = sd->id;
  3603. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3604. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3605. /* raw device or host drive without mapping information */
  3606. TRACE2(("Evaluate mapping\n"));
  3607. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3608. } else {
  3609. ip[0] = ha->hdr[t].heads;
  3610. ip[1] = ha->hdr[t].secs;
  3611. ip[2] = capacity / ip[0] / ip[1];
  3612. }
  3613. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3614. ip[0],ip[1],ip[2]));
  3615. return 0;
  3616. }
  3617. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3618. void (*done)(struct scsi_cmnd *))
  3619. {
  3620. gdth_ha_str *ha = shost_priv(scp->device->host);
  3621. struct gdth_cmndinfo *cmndinfo;
  3622. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3623. cmndinfo = gdth_get_cmndinfo(ha);
  3624. BUG_ON(!cmndinfo);
  3625. scp->scsi_done = done;
  3626. cmndinfo->timeout_count = 0;
  3627. cmndinfo->priority = DEFAULT_PRI;
  3628. return __gdth_queuecommand(ha, scp, cmndinfo);
  3629. }
  3630. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3631. struct gdth_cmndinfo *cmndinfo)
  3632. {
  3633. scp->host_scribble = (unsigned char *)cmndinfo;
  3634. cmndinfo->wait_for_completion = 1;
  3635. cmndinfo->phase = -1;
  3636. cmndinfo->OpCode = -1;
  3637. #ifdef GDTH_STATISTICS
  3638. ++act_ios;
  3639. #endif
  3640. gdth_putq(ha, scp, cmndinfo->priority);
  3641. gdth_next(ha);
  3642. return 0;
  3643. }
  3644. static int gdth_open(struct inode *inode, struct file *filep)
  3645. {
  3646. gdth_ha_str *ha;
  3647. lock_kernel();
  3648. list_for_each_entry(ha, &gdth_instances, list) {
  3649. if (!ha->sdev)
  3650. ha->sdev = scsi_get_host_dev(ha->shost);
  3651. }
  3652. unlock_kernel();
  3653. TRACE(("gdth_open()\n"));
  3654. return 0;
  3655. }
  3656. static int gdth_close(struct inode *inode, struct file *filep)
  3657. {
  3658. TRACE(("gdth_close()\n"));
  3659. return 0;
  3660. }
  3661. static int ioc_event(void __user *arg)
  3662. {
  3663. gdth_ioctl_event evt;
  3664. gdth_ha_str *ha;
  3665. unsigned long flags;
  3666. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3667. return -EFAULT;
  3668. ha = gdth_find_ha(evt.ionode);
  3669. if (!ha)
  3670. return -EFAULT;
  3671. if (evt.erase == 0xff) {
  3672. if (evt.event.event_source == ES_TEST)
  3673. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3674. else if (evt.event.event_source == ES_DRIVER)
  3675. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3676. else if (evt.event.event_source == ES_SYNC)
  3677. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3678. else
  3679. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3680. spin_lock_irqsave(&ha->smp_lock, flags);
  3681. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3682. &evt.event.event_data);
  3683. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3684. } else if (evt.erase == 0xfe) {
  3685. gdth_clear_events();
  3686. } else if (evt.erase == 0) {
  3687. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3688. } else {
  3689. gdth_readapp_event(ha, evt.erase, &evt.event);
  3690. }
  3691. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3692. return -EFAULT;
  3693. return 0;
  3694. }
  3695. static int ioc_lockdrv(void __user *arg)
  3696. {
  3697. gdth_ioctl_lockdrv ldrv;
  3698. u8 i, j;
  3699. unsigned long flags;
  3700. gdth_ha_str *ha;
  3701. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3702. return -EFAULT;
  3703. ha = gdth_find_ha(ldrv.ionode);
  3704. if (!ha)
  3705. return -EFAULT;
  3706. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3707. j = ldrv.drives[i];
  3708. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3709. continue;
  3710. if (ldrv.lock) {
  3711. spin_lock_irqsave(&ha->smp_lock, flags);
  3712. ha->hdr[j].lock = 1;
  3713. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3714. gdth_wait_completion(ha, ha->bus_cnt, j);
  3715. } else {
  3716. spin_lock_irqsave(&ha->smp_lock, flags);
  3717. ha->hdr[j].lock = 0;
  3718. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3719. gdth_next(ha);
  3720. }
  3721. }
  3722. return 0;
  3723. }
  3724. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3725. {
  3726. gdth_ioctl_reset res;
  3727. gdth_cmd_str cmd;
  3728. gdth_ha_str *ha;
  3729. int rval;
  3730. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3731. res.number >= MAX_HDRIVES)
  3732. return -EFAULT;
  3733. ha = gdth_find_ha(res.ionode);
  3734. if (!ha)
  3735. return -EFAULT;
  3736. if (!ha->hdr[res.number].present)
  3737. return 0;
  3738. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3739. cmd.Service = CACHESERVICE;
  3740. cmd.OpCode = GDT_CLUST_RESET;
  3741. if (ha->cache_feat & GDT_64BIT)
  3742. cmd.u.cache64.DeviceNo = res.number;
  3743. else
  3744. cmd.u.cache.DeviceNo = res.number;
  3745. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3746. if (rval < 0)
  3747. return rval;
  3748. res.status = rval;
  3749. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3750. return -EFAULT;
  3751. return 0;
  3752. }
  3753. static int ioc_general(void __user *arg, char *cmnd)
  3754. {
  3755. gdth_ioctl_general gen;
  3756. char *buf = NULL;
  3757. u64 paddr;
  3758. gdth_ha_str *ha;
  3759. int rval;
  3760. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3761. return -EFAULT;
  3762. ha = gdth_find_ha(gen.ionode);
  3763. if (!ha)
  3764. return -EFAULT;
  3765. if (gen.data_len + gen.sense_len != 0) {
  3766. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3767. FALSE, &paddr)))
  3768. return -EFAULT;
  3769. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3770. gen.data_len + gen.sense_len)) {
  3771. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3772. return -EFAULT;
  3773. }
  3774. if (gen.command.OpCode == GDT_IOCTL) {
  3775. gen.command.u.ioctl.p_param = paddr;
  3776. } else if (gen.command.Service == CACHESERVICE) {
  3777. if (ha->cache_feat & GDT_64BIT) {
  3778. /* copy elements from 32-bit IOCTL structure */
  3779. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3780. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3781. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3782. /* addresses */
  3783. if (ha->cache_feat & SCATTER_GATHER) {
  3784. gen.command.u.cache64.DestAddr = (u64)-1;
  3785. gen.command.u.cache64.sg_canz = 1;
  3786. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3787. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3788. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3789. } else {
  3790. gen.command.u.cache64.DestAddr = paddr;
  3791. gen.command.u.cache64.sg_canz = 0;
  3792. }
  3793. } else {
  3794. if (ha->cache_feat & SCATTER_GATHER) {
  3795. gen.command.u.cache.DestAddr = 0xffffffff;
  3796. gen.command.u.cache.sg_canz = 1;
  3797. gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
  3798. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3799. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3800. } else {
  3801. gen.command.u.cache.DestAddr = paddr;
  3802. gen.command.u.cache.sg_canz = 0;
  3803. }
  3804. }
  3805. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3806. if (ha->raw_feat & GDT_64BIT) {
  3807. /* copy elements from 32-bit IOCTL structure */
  3808. char cmd[16];
  3809. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3810. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3811. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3812. gen.command.u.raw64.target = gen.command.u.raw.target;
  3813. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3814. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3815. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3816. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3817. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3818. /* addresses */
  3819. if (ha->raw_feat & SCATTER_GATHER) {
  3820. gen.command.u.raw64.sdata = (u64)-1;
  3821. gen.command.u.raw64.sg_ranz = 1;
  3822. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3823. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3824. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3825. } else {
  3826. gen.command.u.raw64.sdata = paddr;
  3827. gen.command.u.raw64.sg_ranz = 0;
  3828. }
  3829. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3830. } else {
  3831. if (ha->raw_feat & SCATTER_GATHER) {
  3832. gen.command.u.raw.sdata = 0xffffffff;
  3833. gen.command.u.raw.sg_ranz = 1;
  3834. gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
  3835. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3836. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3837. } else {
  3838. gen.command.u.raw.sdata = paddr;
  3839. gen.command.u.raw.sg_ranz = 0;
  3840. }
  3841. gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
  3842. }
  3843. } else {
  3844. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3845. return -EFAULT;
  3846. }
  3847. }
  3848. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3849. if (rval < 0)
  3850. return rval;
  3851. gen.status = rval;
  3852. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3853. gen.data_len + gen.sense_len)) {
  3854. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3855. return -EFAULT;
  3856. }
  3857. if (copy_to_user(arg, &gen,
  3858. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3859. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3860. return -EFAULT;
  3861. }
  3862. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3863. return 0;
  3864. }
  3865. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3866. {
  3867. gdth_ioctl_rescan *rsc;
  3868. gdth_cmd_str *cmd;
  3869. gdth_ha_str *ha;
  3870. u8 i;
  3871. int rc = -ENOMEM;
  3872. u32 cluster_type = 0;
  3873. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3874. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3875. if (!rsc || !cmd)
  3876. goto free_fail;
  3877. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3878. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3879. rc = -EFAULT;
  3880. goto free_fail;
  3881. }
  3882. memset(cmd, 0, sizeof(gdth_cmd_str));
  3883. for (i = 0; i < MAX_HDRIVES; ++i) {
  3884. if (!ha->hdr[i].present) {
  3885. rsc->hdr_list[i].bus = 0xff;
  3886. continue;
  3887. }
  3888. rsc->hdr_list[i].bus = ha->virt_bus;
  3889. rsc->hdr_list[i].target = i;
  3890. rsc->hdr_list[i].lun = 0;
  3891. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3892. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3893. cmd->Service = CACHESERVICE;
  3894. cmd->OpCode = GDT_CLUST_INFO;
  3895. if (ha->cache_feat & GDT_64BIT)
  3896. cmd->u.cache64.DeviceNo = i;
  3897. else
  3898. cmd->u.cache.DeviceNo = i;
  3899. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3900. rsc->hdr_list[i].cluster_type = cluster_type;
  3901. }
  3902. }
  3903. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3904. rc = -EFAULT;
  3905. else
  3906. rc = 0;
  3907. free_fail:
  3908. kfree(rsc);
  3909. kfree(cmd);
  3910. return rc;
  3911. }
  3912. static int ioc_rescan(void __user *arg, char *cmnd)
  3913. {
  3914. gdth_ioctl_rescan *rsc;
  3915. gdth_cmd_str *cmd;
  3916. u16 i, status, hdr_cnt;
  3917. u32 info;
  3918. int cyls, hds, secs;
  3919. int rc = -ENOMEM;
  3920. unsigned long flags;
  3921. gdth_ha_str *ha;
  3922. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3923. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3924. if (!cmd || !rsc)
  3925. goto free_fail;
  3926. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3927. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3928. rc = -EFAULT;
  3929. goto free_fail;
  3930. }
  3931. memset(cmd, 0, sizeof(gdth_cmd_str));
  3932. if (rsc->flag == 0) {
  3933. /* old method: re-init. cache service */
  3934. cmd->Service = CACHESERVICE;
  3935. if (ha->cache_feat & GDT_64BIT) {
  3936. cmd->OpCode = GDT_X_INIT_HOST;
  3937. cmd->u.cache64.DeviceNo = LINUX_OS;
  3938. } else {
  3939. cmd->OpCode = GDT_INIT;
  3940. cmd->u.cache.DeviceNo = LINUX_OS;
  3941. }
  3942. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3943. i = 0;
  3944. hdr_cnt = (status == S_OK ? (u16)info : 0);
  3945. } else {
  3946. i = rsc->hdr_no;
  3947. hdr_cnt = i + 1;
  3948. }
  3949. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3950. cmd->Service = CACHESERVICE;
  3951. cmd->OpCode = GDT_INFO;
  3952. if (ha->cache_feat & GDT_64BIT)
  3953. cmd->u.cache64.DeviceNo = i;
  3954. else
  3955. cmd->u.cache.DeviceNo = i;
  3956. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3957. spin_lock_irqsave(&ha->smp_lock, flags);
  3958. rsc->hdr_list[i].bus = ha->virt_bus;
  3959. rsc->hdr_list[i].target = i;
  3960. rsc->hdr_list[i].lun = 0;
  3961. if (status != S_OK) {
  3962. ha->hdr[i].present = FALSE;
  3963. } else {
  3964. ha->hdr[i].present = TRUE;
  3965. ha->hdr[i].size = info;
  3966. /* evaluate mapping */
  3967. ha->hdr[i].size &= ~SECS32;
  3968. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3969. ha->hdr[i].heads = hds;
  3970. ha->hdr[i].secs = secs;
  3971. /* round size */
  3972. ha->hdr[i].size = cyls * hds * secs;
  3973. }
  3974. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3975. if (status != S_OK)
  3976. continue;
  3977. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3978. /* but we need ha->info2, not yet stored in scp->SCp */
  3979. /* devtype, cluster info, R/W attribs */
  3980. cmd->Service = CACHESERVICE;
  3981. cmd->OpCode = GDT_DEVTYPE;
  3982. if (ha->cache_feat & GDT_64BIT)
  3983. cmd->u.cache64.DeviceNo = i;
  3984. else
  3985. cmd->u.cache.DeviceNo = i;
  3986. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3987. spin_lock_irqsave(&ha->smp_lock, flags);
  3988. ha->hdr[i].devtype = (status == S_OK ? (u16)info : 0);
  3989. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3990. cmd->Service = CACHESERVICE;
  3991. cmd->OpCode = GDT_CLUST_INFO;
  3992. if (ha->cache_feat & GDT_64BIT)
  3993. cmd->u.cache64.DeviceNo = i;
  3994. else
  3995. cmd->u.cache.DeviceNo = i;
  3996. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3997. spin_lock_irqsave(&ha->smp_lock, flags);
  3998. ha->hdr[i].cluster_type =
  3999. ((status == S_OK && !shared_access) ? (u16)info : 0);
  4000. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4001. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4002. cmd->Service = CACHESERVICE;
  4003. cmd->OpCode = GDT_RW_ATTRIBS;
  4004. if (ha->cache_feat & GDT_64BIT)
  4005. cmd->u.cache64.DeviceNo = i;
  4006. else
  4007. cmd->u.cache.DeviceNo = i;
  4008. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4009. spin_lock_irqsave(&ha->smp_lock, flags);
  4010. ha->hdr[i].rw_attribs = (status == S_OK ? (u16)info : 0);
  4011. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4012. }
  4013. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4014. rc = -EFAULT;
  4015. else
  4016. rc = 0;
  4017. free_fail:
  4018. kfree(rsc);
  4019. kfree(cmd);
  4020. return rc;
  4021. }
  4022. static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
  4023. {
  4024. gdth_ha_str *ha;
  4025. Scsi_Cmnd *scp;
  4026. unsigned long flags;
  4027. char cmnd[MAX_COMMAND_SIZE];
  4028. void __user *argp = (void __user *)arg;
  4029. memset(cmnd, 0xff, 12);
  4030. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4031. switch (cmd) {
  4032. case GDTIOCTL_CTRCNT:
  4033. {
  4034. int cnt = gdth_ctr_count;
  4035. if (put_user(cnt, (int __user *)argp))
  4036. return -EFAULT;
  4037. break;
  4038. }
  4039. case GDTIOCTL_DRVERS:
  4040. {
  4041. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4042. if (put_user(ver, (int __user *)argp))
  4043. return -EFAULT;
  4044. break;
  4045. }
  4046. case GDTIOCTL_OSVERS:
  4047. {
  4048. gdth_ioctl_osvers osv;
  4049. osv.version = (u8)(LINUX_VERSION_CODE >> 16);
  4050. osv.subversion = (u8)(LINUX_VERSION_CODE >> 8);
  4051. osv.revision = (u16)(LINUX_VERSION_CODE & 0xff);
  4052. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4053. return -EFAULT;
  4054. break;
  4055. }
  4056. case GDTIOCTL_CTRTYPE:
  4057. {
  4058. gdth_ioctl_ctrtype ctrt;
  4059. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4060. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4061. return -EFAULT;
  4062. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4063. ctrt.type = (u8)((ha->stype>>20) - 0x10);
  4064. } else {
  4065. if (ha->type != GDT_PCIMPR) {
  4066. ctrt.type = (u8)((ha->stype<<4) + 6);
  4067. } else {
  4068. ctrt.type =
  4069. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4070. if (ha->stype >= 0x300)
  4071. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4072. else
  4073. ctrt.ext_type = 0x6000 | ha->stype;
  4074. }
  4075. ctrt.device_id = ha->pdev->device;
  4076. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4077. }
  4078. ctrt.info = ha->brd_phys;
  4079. ctrt.oem_id = ha->oem_id;
  4080. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4081. return -EFAULT;
  4082. break;
  4083. }
  4084. case GDTIOCTL_GENERAL:
  4085. return ioc_general(argp, cmnd);
  4086. case GDTIOCTL_EVENT:
  4087. return ioc_event(argp);
  4088. case GDTIOCTL_LOCKDRV:
  4089. return ioc_lockdrv(argp);
  4090. case GDTIOCTL_LOCKCHN:
  4091. {
  4092. gdth_ioctl_lockchn lchn;
  4093. u8 i, j;
  4094. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4095. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4096. return -EFAULT;
  4097. i = lchn.channel;
  4098. if (i < ha->bus_cnt) {
  4099. if (lchn.lock) {
  4100. spin_lock_irqsave(&ha->smp_lock, flags);
  4101. ha->raw[i].lock = 1;
  4102. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4103. for (j = 0; j < ha->tid_cnt; ++j)
  4104. gdth_wait_completion(ha, i, j);
  4105. } else {
  4106. spin_lock_irqsave(&ha->smp_lock, flags);
  4107. ha->raw[i].lock = 0;
  4108. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4109. for (j = 0; j < ha->tid_cnt; ++j)
  4110. gdth_next(ha);
  4111. }
  4112. }
  4113. break;
  4114. }
  4115. case GDTIOCTL_RESCAN:
  4116. return ioc_rescan(argp, cmnd);
  4117. case GDTIOCTL_HDRLIST:
  4118. return ioc_hdrlist(argp, cmnd);
  4119. case GDTIOCTL_RESET_BUS:
  4120. {
  4121. gdth_ioctl_reset res;
  4122. int rval;
  4123. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4124. (NULL == (ha = gdth_find_ha(res.ionode))))
  4125. return -EFAULT;
  4126. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4127. if (!scp)
  4128. return -ENOMEM;
  4129. scp->device = ha->sdev;
  4130. scp->cmd_len = 12;
  4131. scp->device->channel = res.number;
  4132. rval = gdth_eh_bus_reset(scp);
  4133. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4134. kfree(scp);
  4135. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4136. return -EFAULT;
  4137. break;
  4138. }
  4139. case GDTIOCTL_RESET_DRV:
  4140. return ioc_resetdrv(argp, cmnd);
  4141. default:
  4142. break;
  4143. }
  4144. return 0;
  4145. }
  4146. static long gdth_unlocked_ioctl(struct file *file, unsigned int cmd,
  4147. unsigned long arg)
  4148. {
  4149. int ret;
  4150. lock_kernel();
  4151. ret = gdth_ioctl(file, cmd, arg);
  4152. unlock_kernel();
  4153. return ret;
  4154. }
  4155. /* flush routine */
  4156. static void gdth_flush(gdth_ha_str *ha)
  4157. {
  4158. int i;
  4159. gdth_cmd_str gdtcmd;
  4160. char cmnd[MAX_COMMAND_SIZE];
  4161. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4162. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4163. for (i = 0; i < MAX_HDRIVES; ++i) {
  4164. if (ha->hdr[i].present) {
  4165. gdtcmd.BoardNode = LOCALBOARD;
  4166. gdtcmd.Service = CACHESERVICE;
  4167. gdtcmd.OpCode = GDT_FLUSH;
  4168. if (ha->cache_feat & GDT_64BIT) {
  4169. gdtcmd.u.cache64.DeviceNo = i;
  4170. gdtcmd.u.cache64.BlockNo = 1;
  4171. gdtcmd.u.cache64.sg_canz = 0;
  4172. } else {
  4173. gdtcmd.u.cache.DeviceNo = i;
  4174. gdtcmd.u.cache.BlockNo = 1;
  4175. gdtcmd.u.cache.sg_canz = 0;
  4176. }
  4177. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4178. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4179. }
  4180. }
  4181. }
  4182. /* configure lun */
  4183. static int gdth_slave_configure(struct scsi_device *sdev)
  4184. {
  4185. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4186. sdev->skip_ms_page_3f = 1;
  4187. sdev->skip_ms_page_8 = 1;
  4188. return 0;
  4189. }
  4190. static struct scsi_host_template gdth_template = {
  4191. .name = "GDT SCSI Disk Array Controller",
  4192. .info = gdth_info,
  4193. .queuecommand = gdth_queuecommand,
  4194. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4195. .slave_configure = gdth_slave_configure,
  4196. .bios_param = gdth_bios_param,
  4197. .proc_info = gdth_proc_info,
  4198. .eh_timed_out = gdth_timed_out,
  4199. .proc_name = "gdth",
  4200. .can_queue = GDTH_MAXCMDS,
  4201. .this_id = -1,
  4202. .sg_tablesize = GDTH_MAXSG,
  4203. .cmd_per_lun = GDTH_MAXC_P_L,
  4204. .unchecked_isa_dma = 1,
  4205. .use_clustering = ENABLE_CLUSTERING,
  4206. };
  4207. #ifdef CONFIG_ISA
  4208. static int __init gdth_isa_probe_one(u32 isa_bios)
  4209. {
  4210. struct Scsi_Host *shp;
  4211. gdth_ha_str *ha;
  4212. dma_addr_t scratch_dma_handle = 0;
  4213. int error, i;
  4214. if (!gdth_search_isa(isa_bios))
  4215. return -ENXIO;
  4216. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4217. if (!shp)
  4218. return -ENOMEM;
  4219. ha = shost_priv(shp);
  4220. error = -ENODEV;
  4221. if (!gdth_init_isa(isa_bios,ha))
  4222. goto out_host_put;
  4223. /* controller found and initialized */
  4224. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4225. isa_bios, ha->irq, ha->drq);
  4226. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4227. if (error) {
  4228. printk("GDT-ISA: Unable to allocate IRQ\n");
  4229. goto out_host_put;
  4230. }
  4231. error = request_dma(ha->drq, "gdth");
  4232. if (error) {
  4233. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4234. goto out_free_irq;
  4235. }
  4236. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4237. enable_dma(ha->drq);
  4238. shp->unchecked_isa_dma = 1;
  4239. shp->irq = ha->irq;
  4240. shp->dma_channel = ha->drq;
  4241. ha->hanum = gdth_ctr_count++;
  4242. ha->shost = shp;
  4243. ha->pccb = &ha->cmdext;
  4244. ha->ccb_phys = 0L;
  4245. ha->pdev = NULL;
  4246. error = -ENOMEM;
  4247. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4248. &scratch_dma_handle);
  4249. if (!ha->pscratch)
  4250. goto out_dec_counters;
  4251. ha->scratch_phys = scratch_dma_handle;
  4252. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4253. &scratch_dma_handle);
  4254. if (!ha->pmsg)
  4255. goto out_free_pscratch;
  4256. ha->msg_phys = scratch_dma_handle;
  4257. #ifdef INT_COAL
  4258. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4259. sizeof(gdth_coal_status) * MAXOFFSETS,
  4260. &scratch_dma_handle);
  4261. if (!ha->coal_stat)
  4262. goto out_free_pmsg;
  4263. ha->coal_stat_phys = scratch_dma_handle;
  4264. #endif
  4265. ha->scratch_busy = FALSE;
  4266. ha->req_first = NULL;
  4267. ha->tid_cnt = MAX_HDRIVES;
  4268. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4269. ha->tid_cnt = max_ids;
  4270. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4271. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4272. ha->scan_mode = rescan ? 0x10 : 0;
  4273. error = -ENODEV;
  4274. if (!gdth_search_drives(ha)) {
  4275. printk("GDT-ISA: Error during device scan\n");
  4276. goto out_free_coal_stat;
  4277. }
  4278. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4279. hdr_channel = ha->bus_cnt;
  4280. ha->virt_bus = hdr_channel;
  4281. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4282. shp->max_cmd_len = 16;
  4283. shp->max_id = ha->tid_cnt;
  4284. shp->max_lun = MAXLUN;
  4285. shp->max_channel = ha->bus_cnt;
  4286. spin_lock_init(&ha->smp_lock);
  4287. gdth_enable_int(ha);
  4288. error = scsi_add_host(shp, NULL);
  4289. if (error)
  4290. goto out_free_coal_stat;
  4291. list_add_tail(&ha->list, &gdth_instances);
  4292. gdth_timer_init();
  4293. scsi_scan_host(shp);
  4294. return 0;
  4295. out_free_coal_stat:
  4296. #ifdef INT_COAL
  4297. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4298. ha->coal_stat, ha->coal_stat_phys);
  4299. out_free_pmsg:
  4300. #endif
  4301. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4302. ha->pmsg, ha->msg_phys);
  4303. out_free_pscratch:
  4304. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4305. ha->pscratch, ha->scratch_phys);
  4306. out_dec_counters:
  4307. gdth_ctr_count--;
  4308. out_free_irq:
  4309. free_irq(ha->irq, ha);
  4310. out_host_put:
  4311. scsi_host_put(shp);
  4312. return error;
  4313. }
  4314. #endif /* CONFIG_ISA */
  4315. #ifdef CONFIG_EISA
  4316. static int __init gdth_eisa_probe_one(u16 eisa_slot)
  4317. {
  4318. struct Scsi_Host *shp;
  4319. gdth_ha_str *ha;
  4320. dma_addr_t scratch_dma_handle = 0;
  4321. int error, i;
  4322. if (!gdth_search_eisa(eisa_slot))
  4323. return -ENXIO;
  4324. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4325. if (!shp)
  4326. return -ENOMEM;
  4327. ha = shost_priv(shp);
  4328. error = -ENODEV;
  4329. if (!gdth_init_eisa(eisa_slot,ha))
  4330. goto out_host_put;
  4331. /* controller found and initialized */
  4332. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4333. eisa_slot >> 12, ha->irq);
  4334. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4335. if (error) {
  4336. printk("GDT-EISA: Unable to allocate IRQ\n");
  4337. goto out_host_put;
  4338. }
  4339. shp->unchecked_isa_dma = 0;
  4340. shp->irq = ha->irq;
  4341. shp->dma_channel = 0xff;
  4342. ha->hanum = gdth_ctr_count++;
  4343. ha->shost = shp;
  4344. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4345. ha->pccb = &ha->cmdext;
  4346. ha->ccb_phys = 0L;
  4347. error = -ENOMEM;
  4348. ha->pdev = NULL;
  4349. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4350. &scratch_dma_handle);
  4351. if (!ha->pscratch)
  4352. goto out_free_irq;
  4353. ha->scratch_phys = scratch_dma_handle;
  4354. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4355. &scratch_dma_handle);
  4356. if (!ha->pmsg)
  4357. goto out_free_pscratch;
  4358. ha->msg_phys = scratch_dma_handle;
  4359. #ifdef INT_COAL
  4360. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4361. sizeof(gdth_coal_status) * MAXOFFSETS,
  4362. &scratch_dma_handle);
  4363. if (!ha->coal_stat)
  4364. goto out_free_pmsg;
  4365. ha->coal_stat_phys = scratch_dma_handle;
  4366. #endif
  4367. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4368. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4369. if (!ha->ccb_phys)
  4370. goto out_free_coal_stat;
  4371. ha->scratch_busy = FALSE;
  4372. ha->req_first = NULL;
  4373. ha->tid_cnt = MAX_HDRIVES;
  4374. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4375. ha->tid_cnt = max_ids;
  4376. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4377. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4378. ha->scan_mode = rescan ? 0x10 : 0;
  4379. if (!gdth_search_drives(ha)) {
  4380. printk("GDT-EISA: Error during device scan\n");
  4381. error = -ENODEV;
  4382. goto out_free_ccb_phys;
  4383. }
  4384. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4385. hdr_channel = ha->bus_cnt;
  4386. ha->virt_bus = hdr_channel;
  4387. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4388. shp->max_cmd_len = 16;
  4389. shp->max_id = ha->tid_cnt;
  4390. shp->max_lun = MAXLUN;
  4391. shp->max_channel = ha->bus_cnt;
  4392. spin_lock_init(&ha->smp_lock);
  4393. gdth_enable_int(ha);
  4394. error = scsi_add_host(shp, NULL);
  4395. if (error)
  4396. goto out_free_coal_stat;
  4397. list_add_tail(&ha->list, &gdth_instances);
  4398. gdth_timer_init();
  4399. scsi_scan_host(shp);
  4400. return 0;
  4401. out_free_ccb_phys:
  4402. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4403. PCI_DMA_BIDIRECTIONAL);
  4404. out_free_coal_stat:
  4405. #ifdef INT_COAL
  4406. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4407. ha->coal_stat, ha->coal_stat_phys);
  4408. out_free_pmsg:
  4409. #endif
  4410. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4411. ha->pmsg, ha->msg_phys);
  4412. out_free_pscratch:
  4413. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4414. ha->pscratch, ha->scratch_phys);
  4415. out_free_irq:
  4416. free_irq(ha->irq, ha);
  4417. gdth_ctr_count--;
  4418. out_host_put:
  4419. scsi_host_put(shp);
  4420. return error;
  4421. }
  4422. #endif /* CONFIG_EISA */
  4423. #ifdef CONFIG_PCI
  4424. static int __devinit gdth_pci_probe_one(gdth_pci_str *pcistr,
  4425. gdth_ha_str **ha_out)
  4426. {
  4427. struct Scsi_Host *shp;
  4428. gdth_ha_str *ha;
  4429. dma_addr_t scratch_dma_handle = 0;
  4430. int error, i;
  4431. struct pci_dev *pdev = pcistr->pdev;
  4432. *ha_out = NULL;
  4433. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4434. if (!shp)
  4435. return -ENOMEM;
  4436. ha = shost_priv(shp);
  4437. error = -ENODEV;
  4438. if (!gdth_init_pci(pdev, pcistr, ha))
  4439. goto out_host_put;
  4440. /* controller found and initialized */
  4441. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4442. pdev->bus->number,
  4443. PCI_SLOT(pdev->devfn),
  4444. ha->irq);
  4445. error = request_irq(ha->irq, gdth_interrupt,
  4446. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4447. if (error) {
  4448. printk("GDT-PCI: Unable to allocate IRQ\n");
  4449. goto out_host_put;
  4450. }
  4451. shp->unchecked_isa_dma = 0;
  4452. shp->irq = ha->irq;
  4453. shp->dma_channel = 0xff;
  4454. ha->hanum = gdth_ctr_count++;
  4455. ha->shost = shp;
  4456. ha->pccb = &ha->cmdext;
  4457. ha->ccb_phys = 0L;
  4458. error = -ENOMEM;
  4459. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4460. &scratch_dma_handle);
  4461. if (!ha->pscratch)
  4462. goto out_free_irq;
  4463. ha->scratch_phys = scratch_dma_handle;
  4464. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4465. &scratch_dma_handle);
  4466. if (!ha->pmsg)
  4467. goto out_free_pscratch;
  4468. ha->msg_phys = scratch_dma_handle;
  4469. #ifdef INT_COAL
  4470. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4471. sizeof(gdth_coal_status) * MAXOFFSETS,
  4472. &scratch_dma_handle);
  4473. if (!ha->coal_stat)
  4474. goto out_free_pmsg;
  4475. ha->coal_stat_phys = scratch_dma_handle;
  4476. #endif
  4477. ha->scratch_busy = FALSE;
  4478. ha->req_first = NULL;
  4479. ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4480. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4481. ha->tid_cnt = max_ids;
  4482. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4483. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4484. ha->scan_mode = rescan ? 0x10 : 0;
  4485. error = -ENODEV;
  4486. if (!gdth_search_drives(ha)) {
  4487. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4488. goto out_free_coal_stat;
  4489. }
  4490. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4491. hdr_channel = ha->bus_cnt;
  4492. ha->virt_bus = hdr_channel;
  4493. /* 64-bit DMA only supported from FW >= x.43 */
  4494. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4495. !ha->dma64_support) {
  4496. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4497. printk(KERN_WARNING "GDT-PCI %d: "
  4498. "Unable to set 32-bit DMA\n", ha->hanum);
  4499. goto out_free_coal_stat;
  4500. }
  4501. } else {
  4502. shp->max_cmd_len = 16;
  4503. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  4504. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4505. } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4506. printk(KERN_WARNING "GDT-PCI %d: "
  4507. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4508. goto out_free_coal_stat;
  4509. }
  4510. }
  4511. shp->max_id = ha->tid_cnt;
  4512. shp->max_lun = MAXLUN;
  4513. shp->max_channel = ha->bus_cnt;
  4514. spin_lock_init(&ha->smp_lock);
  4515. gdth_enable_int(ha);
  4516. error = scsi_add_host(shp, &pdev->dev);
  4517. if (error)
  4518. goto out_free_coal_stat;
  4519. list_add_tail(&ha->list, &gdth_instances);
  4520. pci_set_drvdata(ha->pdev, ha);
  4521. gdth_timer_init();
  4522. scsi_scan_host(shp);
  4523. *ha_out = ha;
  4524. return 0;
  4525. out_free_coal_stat:
  4526. #ifdef INT_COAL
  4527. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4528. ha->coal_stat, ha->coal_stat_phys);
  4529. out_free_pmsg:
  4530. #endif
  4531. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4532. ha->pmsg, ha->msg_phys);
  4533. out_free_pscratch:
  4534. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4535. ha->pscratch, ha->scratch_phys);
  4536. out_free_irq:
  4537. free_irq(ha->irq, ha);
  4538. gdth_ctr_count--;
  4539. out_host_put:
  4540. scsi_host_put(shp);
  4541. return error;
  4542. }
  4543. #endif /* CONFIG_PCI */
  4544. static void gdth_remove_one(gdth_ha_str *ha)
  4545. {
  4546. struct Scsi_Host *shp = ha->shost;
  4547. TRACE2(("gdth_remove_one()\n"));
  4548. scsi_remove_host(shp);
  4549. gdth_flush(ha);
  4550. if (ha->sdev) {
  4551. scsi_free_host_dev(ha->sdev);
  4552. ha->sdev = NULL;
  4553. }
  4554. if (shp->irq)
  4555. free_irq(shp->irq,ha);
  4556. #ifdef CONFIG_ISA
  4557. if (shp->dma_channel != 0xff)
  4558. free_dma(shp->dma_channel);
  4559. #endif
  4560. #ifdef INT_COAL
  4561. if (ha->coal_stat)
  4562. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4563. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4564. #endif
  4565. if (ha->pscratch)
  4566. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4567. ha->pscratch, ha->scratch_phys);
  4568. if (ha->pmsg)
  4569. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4570. ha->pmsg, ha->msg_phys);
  4571. if (ha->ccb_phys)
  4572. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4573. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4574. scsi_host_put(shp);
  4575. }
  4576. static int gdth_halt(struct notifier_block *nb, unsigned long event, void *buf)
  4577. {
  4578. gdth_ha_str *ha;
  4579. TRACE2(("gdth_halt() event %d\n", (int)event));
  4580. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4581. return NOTIFY_DONE;
  4582. list_for_each_entry(ha, &gdth_instances, list)
  4583. gdth_flush(ha);
  4584. return NOTIFY_OK;
  4585. }
  4586. static struct notifier_block gdth_notifier = {
  4587. gdth_halt, NULL, 0
  4588. };
  4589. static int __init gdth_init(void)
  4590. {
  4591. if (disable) {
  4592. printk("GDT-HA: Controller driver disabled from"
  4593. " command line !\n");
  4594. return 0;
  4595. }
  4596. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4597. GDTH_VERSION_STR);
  4598. /* initializations */
  4599. gdth_polling = TRUE;
  4600. gdth_clear_events();
  4601. init_timer(&gdth_timer);
  4602. /* As default we do not probe for EISA or ISA controllers */
  4603. if (probe_eisa_isa) {
  4604. /* scanning for controllers, at first: ISA controller */
  4605. #ifdef CONFIG_ISA
  4606. u32 isa_bios;
  4607. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4608. isa_bios += 0x8000UL)
  4609. gdth_isa_probe_one(isa_bios);
  4610. #endif
  4611. #ifdef CONFIG_EISA
  4612. {
  4613. u16 eisa_slot;
  4614. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4615. eisa_slot += 0x1000)
  4616. gdth_eisa_probe_one(eisa_slot);
  4617. }
  4618. #endif
  4619. }
  4620. #ifdef CONFIG_PCI
  4621. /* scanning for PCI controllers */
  4622. if (pci_register_driver(&gdth_pci_driver)) {
  4623. gdth_ha_str *ha;
  4624. list_for_each_entry(ha, &gdth_instances, list)
  4625. gdth_remove_one(ha);
  4626. return -ENODEV;
  4627. }
  4628. #endif /* CONFIG_PCI */
  4629. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4630. major = register_chrdev(0,"gdth", &gdth_fops);
  4631. register_reboot_notifier(&gdth_notifier);
  4632. gdth_polling = FALSE;
  4633. return 0;
  4634. }
  4635. static void __exit gdth_exit(void)
  4636. {
  4637. gdth_ha_str *ha;
  4638. unregister_chrdev(major, "gdth");
  4639. unregister_reboot_notifier(&gdth_notifier);
  4640. #ifdef GDTH_STATISTICS
  4641. del_timer_sync(&gdth_timer);
  4642. #endif
  4643. #ifdef CONFIG_PCI
  4644. pci_unregister_driver(&gdth_pci_driver);
  4645. #endif
  4646. list_for_each_entry(ha, &gdth_instances, list)
  4647. gdth_remove_one(ha);
  4648. }
  4649. module_init(gdth_init);
  4650. module_exit(gdth_exit);
  4651. #ifndef MODULE
  4652. __setup("gdth=", option_setup);
  4653. #endif