pcie_pme.c 14 KB

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  1. /*
  2. * PCIe Native PME support
  3. *
  4. * Copyright (C) 2007 - 2009 Intel Corp
  5. * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
  6. * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License V2. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/pci.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/slab.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/device.h>
  20. #include <linux/pcieport_if.h>
  21. #include <linux/acpi.h>
  22. #include <linux/pci-acpi.h>
  23. #include <linux/pm_runtime.h>
  24. #include "../../pci.h"
  25. #include "pcie_pme.h"
  26. #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
  27. #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
  28. /*
  29. * If set, this switch will prevent the PCIe root port PME service driver from
  30. * being registered. Consequently, the interrupt-based PCIe PME signaling will
  31. * not be used by any PCIe root ports in that case.
  32. */
  33. static bool pcie_pme_disabled = true;
  34. /*
  35. * The PCI Express Base Specification 2.0, Section 6.1.8, states the following:
  36. * "In order to maintain compatibility with non-PCI Express-aware system
  37. * software, system power management logic must be configured by firmware to use
  38. * the legacy mechanism of signaling PME by default. PCI Express-aware system
  39. * software must notify the firmware prior to enabling native, interrupt-based
  40. * PME signaling." However, if the platform doesn't provide us with a suitable
  41. * notification mechanism or the notification fails, it is not clear whether or
  42. * not we are supposed to use the interrupt-based PCIe PME signaling. The
  43. * switch below can be used to indicate the desired behaviour. When set, it
  44. * will make the kernel use the interrupt-based PCIe PME signaling regardless of
  45. * the platform notification status, although the kernel will attempt to notify
  46. * the platform anyway. When unset, it will prevent the kernel from using the
  47. * the interrupt-based PCIe PME signaling if the platform notification fails,
  48. * which is the default.
  49. */
  50. static bool pcie_pme_force_enable;
  51. /*
  52. * If this switch is set, MSI will not be used for PCIe PME signaling. This
  53. * causes the PCIe port driver to use INTx interrupts only, but it turns out
  54. * that using MSI for PCIe PME signaling doesn't play well with PCIe PME-based
  55. * wake-up from system sleep states.
  56. */
  57. bool pcie_pme_msi_disabled;
  58. static int __init pcie_pme_setup(char *str)
  59. {
  60. if (!strncmp(str, "auto", 4))
  61. pcie_pme_disabled = false;
  62. else if (!strncmp(str, "force", 5))
  63. pcie_pme_force_enable = true;
  64. str = strchr(str, ',');
  65. if (str) {
  66. str++;
  67. str += strspn(str, " \t");
  68. if (*str && !strcmp(str, "nomsi"))
  69. pcie_pme_msi_disabled = true;
  70. }
  71. return 1;
  72. }
  73. __setup("pcie_pme=", pcie_pme_setup);
  74. /**
  75. * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME.
  76. * @srv: PCIe PME root port service to use for carrying out the check.
  77. *
  78. * Notify the platform that the native PCIe PME is going to be used and return
  79. * 'true' if the control of the PCIe PME registers has been acquired from the
  80. * platform.
  81. */
  82. static bool pcie_pme_platform_setup(struct pcie_device *srv)
  83. {
  84. if (!pcie_pme_platform_notify(srv))
  85. return true;
  86. return pcie_pme_force_enable;
  87. }
  88. struct pcie_pme_service_data {
  89. spinlock_t lock;
  90. struct pcie_device *srv;
  91. struct work_struct work;
  92. bool noirq; /* Don't enable the PME interrupt used by this service. */
  93. };
  94. /**
  95. * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
  96. * @dev: PCIe root port or event collector.
  97. * @enable: Enable or disable the interrupt.
  98. */
  99. static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
  100. {
  101. int rtctl_pos;
  102. u16 rtctl;
  103. rtctl_pos = pci_pcie_cap(dev) + PCI_EXP_RTCTL;
  104. pci_read_config_word(dev, rtctl_pos, &rtctl);
  105. if (enable)
  106. rtctl |= PCI_EXP_RTCTL_PMEIE;
  107. else
  108. rtctl &= ~PCI_EXP_RTCTL_PMEIE;
  109. pci_write_config_word(dev, rtctl_pos, rtctl);
  110. }
  111. /**
  112. * pcie_pme_clear_status - Clear root port PME interrupt status.
  113. * @dev: PCIe root port or event collector.
  114. */
  115. static void pcie_pme_clear_status(struct pci_dev *dev)
  116. {
  117. int rtsta_pos;
  118. u32 rtsta;
  119. rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
  120. pci_read_config_dword(dev, rtsta_pos, &rtsta);
  121. rtsta |= PCI_EXP_RTSTA_PME;
  122. pci_write_config_dword(dev, rtsta_pos, rtsta);
  123. }
  124. /**
  125. * pcie_pme_walk_bus - Scan a PCI bus for devices asserting PME#.
  126. * @bus: PCI bus to scan.
  127. *
  128. * Scan given PCI bus and all buses under it for devices asserting PME#.
  129. */
  130. static bool pcie_pme_walk_bus(struct pci_bus *bus)
  131. {
  132. struct pci_dev *dev;
  133. bool ret = false;
  134. list_for_each_entry(dev, &bus->devices, bus_list) {
  135. /* Skip PCIe devices in case we started from a root port. */
  136. if (!pci_is_pcie(dev) && pci_check_pme_status(dev)) {
  137. pm_request_resume(&dev->dev);
  138. pci_wakeup_event(dev);
  139. ret = true;
  140. }
  141. if (dev->subordinate && pcie_pme_walk_bus(dev->subordinate))
  142. ret = true;
  143. }
  144. return ret;
  145. }
  146. /**
  147. * pcie_pme_from_pci_bridge - Check if PCIe-PCI bridge generated a PME.
  148. * @bus: Secondary bus of the bridge.
  149. * @devfn: Device/function number to check.
  150. *
  151. * PME from PCI devices under a PCIe-PCI bridge may be converted to an in-band
  152. * PCIe PME message. In such that case the bridge should use the Requester ID
  153. * of device/function number 0 on its secondary bus.
  154. */
  155. static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
  156. {
  157. struct pci_dev *dev;
  158. bool found = false;
  159. if (devfn)
  160. return false;
  161. dev = pci_dev_get(bus->self);
  162. if (!dev)
  163. return false;
  164. if (pci_is_pcie(dev) && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
  165. down_read(&pci_bus_sem);
  166. if (pcie_pme_walk_bus(bus))
  167. found = true;
  168. up_read(&pci_bus_sem);
  169. }
  170. pci_dev_put(dev);
  171. return found;
  172. }
  173. /**
  174. * pcie_pme_handle_request - Find device that generated PME and handle it.
  175. * @port: Root port or event collector that generated the PME interrupt.
  176. * @req_id: PCIe Requester ID of the device that generated the PME.
  177. */
  178. static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
  179. {
  180. u8 busnr = req_id >> 8, devfn = req_id & 0xff;
  181. struct pci_bus *bus;
  182. struct pci_dev *dev;
  183. bool found = false;
  184. /* First, check if the PME is from the root port itself. */
  185. if (port->devfn == devfn && port->bus->number == busnr) {
  186. if (pci_check_pme_status(port)) {
  187. pm_request_resume(&port->dev);
  188. found = true;
  189. } else {
  190. /*
  191. * Apparently, the root port generated the PME on behalf
  192. * of a non-PCIe device downstream. If this is done by
  193. * a root port, the Requester ID field in its status
  194. * register may contain either the root port's, or the
  195. * source device's information (PCI Express Base
  196. * Specification, Rev. 2.0, Section 6.1.9).
  197. */
  198. down_read(&pci_bus_sem);
  199. found = pcie_pme_walk_bus(port->subordinate);
  200. up_read(&pci_bus_sem);
  201. }
  202. goto out;
  203. }
  204. /* Second, find the bus the source device is on. */
  205. bus = pci_find_bus(pci_domain_nr(port->bus), busnr);
  206. if (!bus)
  207. goto out;
  208. /* Next, check if the PME is from a PCIe-PCI bridge. */
  209. found = pcie_pme_from_pci_bridge(bus, devfn);
  210. if (found)
  211. goto out;
  212. /* Finally, try to find the PME source on the bus. */
  213. down_read(&pci_bus_sem);
  214. list_for_each_entry(dev, &bus->devices, bus_list) {
  215. pci_dev_get(dev);
  216. if (dev->devfn == devfn) {
  217. found = true;
  218. break;
  219. }
  220. pci_dev_put(dev);
  221. }
  222. up_read(&pci_bus_sem);
  223. if (found) {
  224. /* The device is there, but we have to check its PME status. */
  225. found = pci_check_pme_status(dev);
  226. if (found) {
  227. pm_request_resume(&dev->dev);
  228. pci_wakeup_event(dev);
  229. }
  230. pci_dev_put(dev);
  231. } else if (devfn) {
  232. /*
  233. * The device is not there, but we can still try to recover by
  234. * assuming that the PME was reported by a PCIe-PCI bridge that
  235. * used devfn different from zero.
  236. */
  237. dev_dbg(&port->dev, "PME interrupt generated for "
  238. "non-existent device %02x:%02x.%d\n",
  239. busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
  240. found = pcie_pme_from_pci_bridge(bus, 0);
  241. }
  242. out:
  243. if (!found)
  244. dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
  245. }
  246. /**
  247. * pcie_pme_work_fn - Work handler for PCIe PME interrupt.
  248. * @work: Work structure giving access to service data.
  249. */
  250. static void pcie_pme_work_fn(struct work_struct *work)
  251. {
  252. struct pcie_pme_service_data *data =
  253. container_of(work, struct pcie_pme_service_data, work);
  254. struct pci_dev *port = data->srv->port;
  255. int rtsta_pos;
  256. u32 rtsta;
  257. rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
  258. spin_lock_irq(&data->lock);
  259. for (;;) {
  260. if (data->noirq)
  261. break;
  262. pci_read_config_dword(port, rtsta_pos, &rtsta);
  263. if (rtsta & PCI_EXP_RTSTA_PME) {
  264. /*
  265. * Clear PME status of the port. If there are other
  266. * pending PMEs, the status will be set again.
  267. */
  268. pcie_pme_clear_status(port);
  269. spin_unlock_irq(&data->lock);
  270. pcie_pme_handle_request(port, rtsta & 0xffff);
  271. spin_lock_irq(&data->lock);
  272. continue;
  273. }
  274. /* No need to loop if there are no more PMEs pending. */
  275. if (!(rtsta & PCI_EXP_RTSTA_PENDING))
  276. break;
  277. spin_unlock_irq(&data->lock);
  278. cpu_relax();
  279. spin_lock_irq(&data->lock);
  280. }
  281. if (!data->noirq)
  282. pcie_pme_interrupt_enable(port, true);
  283. spin_unlock_irq(&data->lock);
  284. }
  285. /**
  286. * pcie_pme_irq - Interrupt handler for PCIe root port PME interrupt.
  287. * @irq: Interrupt vector.
  288. * @context: Interrupt context pointer.
  289. */
  290. static irqreturn_t pcie_pme_irq(int irq, void *context)
  291. {
  292. struct pci_dev *port;
  293. struct pcie_pme_service_data *data;
  294. int rtsta_pos;
  295. u32 rtsta;
  296. unsigned long flags;
  297. port = ((struct pcie_device *)context)->port;
  298. data = get_service_data((struct pcie_device *)context);
  299. rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
  300. spin_lock_irqsave(&data->lock, flags);
  301. pci_read_config_dword(port, rtsta_pos, &rtsta);
  302. if (!(rtsta & PCI_EXP_RTSTA_PME)) {
  303. spin_unlock_irqrestore(&data->lock, flags);
  304. return IRQ_NONE;
  305. }
  306. pcie_pme_interrupt_enable(port, false);
  307. spin_unlock_irqrestore(&data->lock, flags);
  308. /* We don't use pm_wq, because it's freezable. */
  309. schedule_work(&data->work);
  310. return IRQ_HANDLED;
  311. }
  312. /**
  313. * pcie_pme_set_native - Set the PME interrupt flag for given device.
  314. * @dev: PCI device to handle.
  315. * @ign: Ignored.
  316. */
  317. static int pcie_pme_set_native(struct pci_dev *dev, void *ign)
  318. {
  319. dev_info(&dev->dev, "Signaling PME through PCIe PME interrupt\n");
  320. device_set_run_wake(&dev->dev, true);
  321. dev->pme_interrupt = true;
  322. return 0;
  323. }
  324. /**
  325. * pcie_pme_mark_devices - Set the PME interrupt flag for devices below a port.
  326. * @port: PCIe root port or event collector to handle.
  327. *
  328. * For each device below given root port, including the port itself (or for each
  329. * root complex integrated endpoint if @port is a root complex event collector)
  330. * set the flag indicating that it can signal run-time wake-up events via PCIe
  331. * PME interrupts.
  332. */
  333. static void pcie_pme_mark_devices(struct pci_dev *port)
  334. {
  335. pcie_pme_set_native(port, NULL);
  336. if (port->subordinate) {
  337. pci_walk_bus(port->subordinate, pcie_pme_set_native, NULL);
  338. } else {
  339. struct pci_bus *bus = port->bus;
  340. struct pci_dev *dev;
  341. /* Check if this is a root port event collector. */
  342. if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus)
  343. return;
  344. down_read(&pci_bus_sem);
  345. list_for_each_entry(dev, &bus->devices, bus_list)
  346. if (pci_is_pcie(dev)
  347. && dev->pcie_type == PCI_EXP_TYPE_RC_END)
  348. pcie_pme_set_native(dev, NULL);
  349. up_read(&pci_bus_sem);
  350. }
  351. }
  352. /**
  353. * pcie_pme_probe - Initialize PCIe PME service for given root port.
  354. * @srv: PCIe service to initialize.
  355. */
  356. static int pcie_pme_probe(struct pcie_device *srv)
  357. {
  358. struct pci_dev *port;
  359. struct pcie_pme_service_data *data;
  360. int ret;
  361. if (!pcie_pme_platform_setup(srv))
  362. return -EACCES;
  363. data = kzalloc(sizeof(*data), GFP_KERNEL);
  364. if (!data)
  365. return -ENOMEM;
  366. spin_lock_init(&data->lock);
  367. INIT_WORK(&data->work, pcie_pme_work_fn);
  368. data->srv = srv;
  369. set_service_data(srv, data);
  370. port = srv->port;
  371. pcie_pme_interrupt_enable(port, false);
  372. pcie_pme_clear_status(port);
  373. ret = request_irq(srv->irq, pcie_pme_irq, IRQF_SHARED, "PCIe PME", srv);
  374. if (ret) {
  375. kfree(data);
  376. } else {
  377. pcie_pme_mark_devices(port);
  378. pcie_pme_interrupt_enable(port, true);
  379. }
  380. return ret;
  381. }
  382. /**
  383. * pcie_pme_suspend - Suspend PCIe PME service device.
  384. * @srv: PCIe service device to suspend.
  385. */
  386. static int pcie_pme_suspend(struct pcie_device *srv)
  387. {
  388. struct pcie_pme_service_data *data = get_service_data(srv);
  389. struct pci_dev *port = srv->port;
  390. spin_lock_irq(&data->lock);
  391. pcie_pme_interrupt_enable(port, false);
  392. pcie_pme_clear_status(port);
  393. data->noirq = true;
  394. spin_unlock_irq(&data->lock);
  395. synchronize_irq(srv->irq);
  396. return 0;
  397. }
  398. /**
  399. * pcie_pme_resume - Resume PCIe PME service device.
  400. * @srv - PCIe service device to resume.
  401. */
  402. static int pcie_pme_resume(struct pcie_device *srv)
  403. {
  404. struct pcie_pme_service_data *data = get_service_data(srv);
  405. struct pci_dev *port = srv->port;
  406. spin_lock_irq(&data->lock);
  407. data->noirq = false;
  408. pcie_pme_clear_status(port);
  409. pcie_pme_interrupt_enable(port, true);
  410. spin_unlock_irq(&data->lock);
  411. return 0;
  412. }
  413. /**
  414. * pcie_pme_remove - Prepare PCIe PME service device for removal.
  415. * @srv - PCIe service device to resume.
  416. */
  417. static void pcie_pme_remove(struct pcie_device *srv)
  418. {
  419. pcie_pme_suspend(srv);
  420. free_irq(srv->irq, srv);
  421. kfree(get_service_data(srv));
  422. }
  423. static struct pcie_port_service_driver pcie_pme_driver = {
  424. .name = "pcie_pme",
  425. .port_type = PCI_EXP_TYPE_ROOT_PORT,
  426. .service = PCIE_PORT_SERVICE_PME,
  427. .probe = pcie_pme_probe,
  428. .suspend = pcie_pme_suspend,
  429. .resume = pcie_pme_resume,
  430. .remove = pcie_pme_remove,
  431. };
  432. /**
  433. * pcie_pme_service_init - Register the PCIe PME service driver.
  434. */
  435. static int __init pcie_pme_service_init(void)
  436. {
  437. return pcie_pme_disabled ?
  438. -ENODEV : pcie_port_service_register(&pcie_pme_driver);
  439. }
  440. module_init(pcie_pme_service_init);