radeon_ring.c 12 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/slab.h>
  30. #include "drmP.h"
  31. #include "radeon_drm.h"
  32. #include "radeon_reg.h"
  33. #include "radeon.h"
  34. #include "atom.h"
  35. int radeon_debugfs_ib_init(struct radeon_device *rdev);
  36. void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
  37. {
  38. struct radeon_ib *ib, *n;
  39. list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
  40. list_del(&ib->list);
  41. vfree(ib->ptr);
  42. kfree(ib);
  43. }
  44. }
  45. void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
  46. {
  47. struct radeon_ib *bib;
  48. bib = kmalloc(sizeof(*bib), GFP_KERNEL);
  49. if (bib == NULL)
  50. return;
  51. bib->ptr = vmalloc(ib->length_dw * 4);
  52. if (bib->ptr == NULL) {
  53. kfree(bib);
  54. return;
  55. }
  56. memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
  57. bib->length_dw = ib->length_dw;
  58. mutex_lock(&rdev->ib_pool.mutex);
  59. list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
  60. mutex_unlock(&rdev->ib_pool.mutex);
  61. }
  62. /*
  63. * IB.
  64. */
  65. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
  66. {
  67. struct radeon_fence *fence;
  68. struct radeon_ib *nib;
  69. int r = 0, i, c;
  70. *ib = NULL;
  71. r = radeon_fence_create(rdev, &fence);
  72. if (r) {
  73. dev_err(rdev->dev, "failed to create fence for new IB\n");
  74. return r;
  75. }
  76. mutex_lock(&rdev->ib_pool.mutex);
  77. for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
  78. i &= (RADEON_IB_POOL_SIZE - 1);
  79. if (rdev->ib_pool.ibs[i].free) {
  80. nib = &rdev->ib_pool.ibs[i];
  81. break;
  82. }
  83. }
  84. if (nib == NULL) {
  85. /* This should never happen, it means we allocated all
  86. * IB and haven't scheduled one yet, return EBUSY to
  87. * userspace hoping that on ioctl recall we get better
  88. * luck
  89. */
  90. dev_err(rdev->dev, "no free indirect buffer !\n");
  91. mutex_unlock(&rdev->ib_pool.mutex);
  92. radeon_fence_unref(&fence);
  93. return -EBUSY;
  94. }
  95. rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
  96. nib->free = false;
  97. if (nib->fence) {
  98. mutex_unlock(&rdev->ib_pool.mutex);
  99. r = radeon_fence_wait(nib->fence, false);
  100. if (r) {
  101. dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
  102. nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
  103. mutex_lock(&rdev->ib_pool.mutex);
  104. nib->free = true;
  105. mutex_unlock(&rdev->ib_pool.mutex);
  106. radeon_fence_unref(&fence);
  107. return r;
  108. }
  109. mutex_lock(&rdev->ib_pool.mutex);
  110. }
  111. radeon_fence_unref(&nib->fence);
  112. nib->fence = fence;
  113. nib->length_dw = 0;
  114. mutex_unlock(&rdev->ib_pool.mutex);
  115. *ib = nib;
  116. return 0;
  117. }
  118. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
  119. {
  120. struct radeon_ib *tmp = *ib;
  121. *ib = NULL;
  122. if (tmp == NULL) {
  123. return;
  124. }
  125. if (!tmp->fence->emited)
  126. radeon_fence_unref(&tmp->fence);
  127. mutex_lock(&rdev->ib_pool.mutex);
  128. tmp->free = true;
  129. mutex_unlock(&rdev->ib_pool.mutex);
  130. }
  131. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
  132. {
  133. int r = 0;
  134. if (!ib->length_dw || !rdev->cp.ready) {
  135. /* TODO: Nothings in the ib we should report. */
  136. DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
  137. return -EINVAL;
  138. }
  139. /* 64 dwords should be enough for fence too */
  140. r = radeon_ring_lock(rdev, 64);
  141. if (r) {
  142. DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
  143. return r;
  144. }
  145. radeon_ring_ib_execute(rdev, ib);
  146. radeon_fence_emit(rdev, ib->fence);
  147. mutex_lock(&rdev->ib_pool.mutex);
  148. /* once scheduled IB is considered free and protected by the fence */
  149. ib->free = true;
  150. mutex_unlock(&rdev->ib_pool.mutex);
  151. radeon_ring_unlock_commit(rdev);
  152. return 0;
  153. }
  154. int radeon_ib_pool_init(struct radeon_device *rdev)
  155. {
  156. void *ptr;
  157. uint64_t gpu_addr;
  158. int i;
  159. int r = 0;
  160. if (rdev->ib_pool.robj)
  161. return 0;
  162. INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
  163. /* Allocate 1M object buffer */
  164. r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
  165. true, RADEON_GEM_DOMAIN_GTT,
  166. &rdev->ib_pool.robj);
  167. if (r) {
  168. DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
  169. return r;
  170. }
  171. r = radeon_bo_reserve(rdev->ib_pool.robj, false);
  172. if (unlikely(r != 0))
  173. return r;
  174. r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
  175. if (r) {
  176. radeon_bo_unreserve(rdev->ib_pool.robj);
  177. DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
  178. return r;
  179. }
  180. r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
  181. radeon_bo_unreserve(rdev->ib_pool.robj);
  182. if (r) {
  183. DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
  184. return r;
  185. }
  186. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  187. unsigned offset;
  188. offset = i * 64 * 1024;
  189. rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
  190. rdev->ib_pool.ibs[i].ptr = ptr + offset;
  191. rdev->ib_pool.ibs[i].idx = i;
  192. rdev->ib_pool.ibs[i].length_dw = 0;
  193. rdev->ib_pool.ibs[i].free = true;
  194. }
  195. rdev->ib_pool.head_id = 0;
  196. rdev->ib_pool.ready = true;
  197. DRM_INFO("radeon: ib pool ready.\n");
  198. if (radeon_debugfs_ib_init(rdev)) {
  199. DRM_ERROR("Failed to register debugfs file for IB !\n");
  200. }
  201. return r;
  202. }
  203. void radeon_ib_pool_fini(struct radeon_device *rdev)
  204. {
  205. int r;
  206. struct radeon_bo *robj;
  207. if (!rdev->ib_pool.ready) {
  208. return;
  209. }
  210. mutex_lock(&rdev->ib_pool.mutex);
  211. radeon_ib_bogus_cleanup(rdev);
  212. robj = rdev->ib_pool.robj;
  213. rdev->ib_pool.robj = NULL;
  214. mutex_unlock(&rdev->ib_pool.mutex);
  215. if (robj) {
  216. r = radeon_bo_reserve(robj, false);
  217. if (likely(r == 0)) {
  218. radeon_bo_kunmap(robj);
  219. radeon_bo_unpin(robj);
  220. radeon_bo_unreserve(robj);
  221. }
  222. radeon_bo_unref(&robj);
  223. }
  224. }
  225. /*
  226. * Ring.
  227. */
  228. void radeon_ring_free_size(struct radeon_device *rdev)
  229. {
  230. if (rdev->family >= CHIP_R600)
  231. rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
  232. else
  233. rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
  234. /* This works because ring_size is a power of 2 */
  235. rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
  236. rdev->cp.ring_free_dw -= rdev->cp.wptr;
  237. rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
  238. if (!rdev->cp.ring_free_dw) {
  239. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  240. }
  241. }
  242. int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw)
  243. {
  244. int r;
  245. /* Align requested size with padding so unlock_commit can
  246. * pad safely */
  247. ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
  248. while (ndw > (rdev->cp.ring_free_dw - 1)) {
  249. radeon_ring_free_size(rdev);
  250. if (ndw < rdev->cp.ring_free_dw) {
  251. break;
  252. }
  253. r = radeon_fence_wait_next(rdev);
  254. if (r)
  255. return r;
  256. }
  257. rdev->cp.count_dw = ndw;
  258. rdev->cp.wptr_old = rdev->cp.wptr;
  259. return 0;
  260. }
  261. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
  262. {
  263. int r;
  264. mutex_lock(&rdev->cp.mutex);
  265. r = radeon_ring_alloc(rdev, ndw);
  266. if (r) {
  267. mutex_unlock(&rdev->cp.mutex);
  268. return r;
  269. }
  270. return 0;
  271. }
  272. void radeon_ring_commit(struct radeon_device *rdev)
  273. {
  274. unsigned count_dw_pad;
  275. unsigned i;
  276. /* We pad to match fetch size */
  277. count_dw_pad = (rdev->cp.align_mask + 1) -
  278. (rdev->cp.wptr & rdev->cp.align_mask);
  279. for (i = 0; i < count_dw_pad; i++) {
  280. radeon_ring_write(rdev, 2 << 30);
  281. }
  282. DRM_MEMORYBARRIER();
  283. radeon_cp_commit(rdev);
  284. }
  285. void radeon_ring_unlock_commit(struct radeon_device *rdev)
  286. {
  287. radeon_ring_commit(rdev);
  288. mutex_unlock(&rdev->cp.mutex);
  289. }
  290. void radeon_ring_unlock_undo(struct radeon_device *rdev)
  291. {
  292. rdev->cp.wptr = rdev->cp.wptr_old;
  293. mutex_unlock(&rdev->cp.mutex);
  294. }
  295. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
  296. {
  297. int r;
  298. rdev->cp.ring_size = ring_size;
  299. /* Allocate ring buffer */
  300. if (rdev->cp.ring_obj == NULL) {
  301. r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
  302. RADEON_GEM_DOMAIN_GTT,
  303. &rdev->cp.ring_obj);
  304. if (r) {
  305. dev_err(rdev->dev, "(%d) ring create failed\n", r);
  306. return r;
  307. }
  308. r = radeon_bo_reserve(rdev->cp.ring_obj, false);
  309. if (unlikely(r != 0))
  310. return r;
  311. r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
  312. &rdev->cp.gpu_addr);
  313. if (r) {
  314. radeon_bo_unreserve(rdev->cp.ring_obj);
  315. dev_err(rdev->dev, "(%d) ring pin failed\n", r);
  316. return r;
  317. }
  318. r = radeon_bo_kmap(rdev->cp.ring_obj,
  319. (void **)&rdev->cp.ring);
  320. radeon_bo_unreserve(rdev->cp.ring_obj);
  321. if (r) {
  322. dev_err(rdev->dev, "(%d) ring map failed\n", r);
  323. return r;
  324. }
  325. }
  326. rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
  327. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  328. return 0;
  329. }
  330. void radeon_ring_fini(struct radeon_device *rdev)
  331. {
  332. int r;
  333. struct radeon_bo *ring_obj;
  334. mutex_lock(&rdev->cp.mutex);
  335. ring_obj = rdev->cp.ring_obj;
  336. rdev->cp.ring = NULL;
  337. rdev->cp.ring_obj = NULL;
  338. mutex_unlock(&rdev->cp.mutex);
  339. if (ring_obj) {
  340. r = radeon_bo_reserve(ring_obj, false);
  341. if (likely(r == 0)) {
  342. radeon_bo_kunmap(ring_obj);
  343. radeon_bo_unpin(ring_obj);
  344. radeon_bo_unreserve(ring_obj);
  345. }
  346. radeon_bo_unref(&ring_obj);
  347. }
  348. }
  349. /*
  350. * Debugfs info
  351. */
  352. #if defined(CONFIG_DEBUG_FS)
  353. static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
  354. {
  355. struct drm_info_node *node = (struct drm_info_node *) m->private;
  356. struct radeon_ib *ib = node->info_ent->data;
  357. unsigned i;
  358. if (ib == NULL) {
  359. return 0;
  360. }
  361. seq_printf(m, "IB %04u\n", ib->idx);
  362. seq_printf(m, "IB fence %p\n", ib->fence);
  363. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  364. for (i = 0; i < ib->length_dw; i++) {
  365. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  366. }
  367. return 0;
  368. }
  369. static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
  370. {
  371. struct drm_info_node *node = (struct drm_info_node *) m->private;
  372. struct radeon_device *rdev = node->info_ent->data;
  373. struct radeon_ib *ib;
  374. unsigned i;
  375. mutex_lock(&rdev->ib_pool.mutex);
  376. if (list_empty(&rdev->ib_pool.bogus_ib)) {
  377. mutex_unlock(&rdev->ib_pool.mutex);
  378. seq_printf(m, "no bogus IB recorded\n");
  379. return 0;
  380. }
  381. ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
  382. list_del_init(&ib->list);
  383. mutex_unlock(&rdev->ib_pool.mutex);
  384. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  385. for (i = 0; i < ib->length_dw; i++) {
  386. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  387. }
  388. vfree(ib->ptr);
  389. kfree(ib);
  390. return 0;
  391. }
  392. static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
  393. static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
  394. static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
  395. {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
  396. };
  397. #endif
  398. int radeon_debugfs_ib_init(struct radeon_device *rdev)
  399. {
  400. #if defined(CONFIG_DEBUG_FS)
  401. unsigned i;
  402. int r;
  403. radeon_debugfs_ib_bogus_info_list[0].data = rdev;
  404. r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
  405. if (r)
  406. return r;
  407. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  408. sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
  409. radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
  410. radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
  411. radeon_debugfs_ib_list[i].driver_features = 0;
  412. radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
  413. }
  414. return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
  415. RADEON_IB_POOL_SIZE);
  416. #else
  417. return 0;
  418. #endif
  419. }