radeon_fence.c 11 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  42. {
  43. unsigned long irq_flags;
  44. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  45. if (fence->emited) {
  46. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  47. return 0;
  48. }
  49. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  50. if (!rdev->cp.ready) {
  51. /* FIXME: cp is not running assume everythings is done right
  52. * away
  53. */
  54. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  55. } else
  56. radeon_fence_ring_emit(rdev, fence);
  57. fence->emited = true;
  58. list_del(&fence->list);
  59. list_add_tail(&fence->list, &rdev->fence_drv.emited);
  60. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  61. return 0;
  62. }
  63. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  64. {
  65. struct radeon_fence *fence;
  66. struct list_head *i, *n;
  67. uint32_t seq;
  68. bool wake = false;
  69. unsigned long cjiffies;
  70. seq = RREG32(rdev->fence_drv.scratch_reg);
  71. if (seq != rdev->fence_drv.last_seq) {
  72. rdev->fence_drv.last_seq = seq;
  73. rdev->fence_drv.last_jiffies = jiffies;
  74. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  75. } else {
  76. cjiffies = jiffies;
  77. if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) {
  78. cjiffies -= rdev->fence_drv.last_jiffies;
  79. if (time_after(rdev->fence_drv.last_timeout, cjiffies)) {
  80. /* update the timeout */
  81. rdev->fence_drv.last_timeout -= cjiffies;
  82. } else {
  83. /* the 500ms timeout is elapsed we should test
  84. * for GPU lockup
  85. */
  86. rdev->fence_drv.last_timeout = 1;
  87. }
  88. } else {
  89. /* wrap around update last jiffies, we will just wait
  90. * a little longer
  91. */
  92. rdev->fence_drv.last_jiffies = cjiffies;
  93. }
  94. return false;
  95. }
  96. n = NULL;
  97. list_for_each(i, &rdev->fence_drv.emited) {
  98. fence = list_entry(i, struct radeon_fence, list);
  99. if (fence->seq == seq) {
  100. n = i;
  101. break;
  102. }
  103. }
  104. /* all fence previous to this one are considered as signaled */
  105. if (n) {
  106. i = n;
  107. do {
  108. n = i->prev;
  109. list_del(i);
  110. list_add_tail(i, &rdev->fence_drv.signaled);
  111. fence = list_entry(i, struct radeon_fence, list);
  112. fence->signaled = true;
  113. i = n;
  114. } while (i != &rdev->fence_drv.emited);
  115. wake = true;
  116. }
  117. return wake;
  118. }
  119. static void radeon_fence_destroy(struct kref *kref)
  120. {
  121. unsigned long irq_flags;
  122. struct radeon_fence *fence;
  123. fence = container_of(kref, struct radeon_fence, kref);
  124. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  125. list_del(&fence->list);
  126. fence->emited = false;
  127. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  128. kfree(fence);
  129. }
  130. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  131. {
  132. unsigned long irq_flags;
  133. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  134. if ((*fence) == NULL) {
  135. return -ENOMEM;
  136. }
  137. kref_init(&((*fence)->kref));
  138. (*fence)->rdev = rdev;
  139. (*fence)->emited = false;
  140. (*fence)->signaled = false;
  141. (*fence)->seq = 0;
  142. INIT_LIST_HEAD(&(*fence)->list);
  143. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  144. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  145. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  146. return 0;
  147. }
  148. bool radeon_fence_signaled(struct radeon_fence *fence)
  149. {
  150. unsigned long irq_flags;
  151. bool signaled = false;
  152. if (!fence)
  153. return true;
  154. if (fence->rdev->gpu_lockup)
  155. return true;
  156. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  157. signaled = fence->signaled;
  158. /* if we are shuting down report all fence as signaled */
  159. if (fence->rdev->shutdown) {
  160. signaled = true;
  161. }
  162. if (!fence->emited) {
  163. WARN(1, "Querying an unemited fence : %p !\n", fence);
  164. signaled = true;
  165. }
  166. if (!signaled) {
  167. radeon_fence_poll_locked(fence->rdev);
  168. signaled = fence->signaled;
  169. }
  170. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  171. return signaled;
  172. }
  173. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  174. {
  175. struct radeon_device *rdev;
  176. unsigned long irq_flags, timeout;
  177. u32 seq;
  178. int r;
  179. if (fence == NULL) {
  180. WARN(1, "Querying an invalid fence : %p !\n", fence);
  181. return 0;
  182. }
  183. rdev = fence->rdev;
  184. if (radeon_fence_signaled(fence)) {
  185. return 0;
  186. }
  187. timeout = rdev->fence_drv.last_timeout;
  188. retry:
  189. /* save current sequence used to check for GPU lockup */
  190. seq = rdev->fence_drv.last_seq;
  191. if (intr) {
  192. radeon_irq_kms_sw_irq_get(rdev);
  193. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  194. radeon_fence_signaled(fence), timeout);
  195. radeon_irq_kms_sw_irq_put(rdev);
  196. if (unlikely(r < 0)) {
  197. return r;
  198. }
  199. } else {
  200. radeon_irq_kms_sw_irq_get(rdev);
  201. r = wait_event_timeout(rdev->fence_drv.queue,
  202. radeon_fence_signaled(fence), timeout);
  203. radeon_irq_kms_sw_irq_put(rdev);
  204. }
  205. if (unlikely(!radeon_fence_signaled(fence))) {
  206. /* we were interrupted for some reason and fence isn't
  207. * isn't signaled yet, resume wait
  208. */
  209. if (r) {
  210. timeout = r;
  211. goto retry;
  212. }
  213. /* don't protect read access to rdev->fence_drv.last_seq
  214. * if we experiencing a lockup the value doesn't change
  215. */
  216. if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
  217. /* good news we believe it's a lockup */
  218. WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", fence->seq, seq);
  219. /* FIXME: what should we do ? marking everyone
  220. * as signaled for now
  221. */
  222. rdev->gpu_lockup = true;
  223. r = radeon_gpu_reset(rdev);
  224. if (r)
  225. return r;
  226. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  227. rdev->gpu_lockup = false;
  228. }
  229. timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  230. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  231. rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  232. rdev->fence_drv.last_jiffies = jiffies;
  233. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  234. goto retry;
  235. }
  236. return 0;
  237. }
  238. int radeon_fence_wait_next(struct radeon_device *rdev)
  239. {
  240. unsigned long irq_flags;
  241. struct radeon_fence *fence;
  242. int r;
  243. if (rdev->gpu_lockup) {
  244. return 0;
  245. }
  246. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  247. if (list_empty(&rdev->fence_drv.emited)) {
  248. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  249. return 0;
  250. }
  251. fence = list_entry(rdev->fence_drv.emited.next,
  252. struct radeon_fence, list);
  253. radeon_fence_ref(fence);
  254. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  255. r = radeon_fence_wait(fence, false);
  256. radeon_fence_unref(&fence);
  257. return r;
  258. }
  259. int radeon_fence_wait_last(struct radeon_device *rdev)
  260. {
  261. unsigned long irq_flags;
  262. struct radeon_fence *fence;
  263. int r;
  264. if (rdev->gpu_lockup) {
  265. return 0;
  266. }
  267. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  268. if (list_empty(&rdev->fence_drv.emited)) {
  269. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  270. return 0;
  271. }
  272. fence = list_entry(rdev->fence_drv.emited.prev,
  273. struct radeon_fence, list);
  274. radeon_fence_ref(fence);
  275. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  276. r = radeon_fence_wait(fence, false);
  277. radeon_fence_unref(&fence);
  278. return r;
  279. }
  280. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  281. {
  282. kref_get(&fence->kref);
  283. return fence;
  284. }
  285. void radeon_fence_unref(struct radeon_fence **fence)
  286. {
  287. struct radeon_fence *tmp = *fence;
  288. *fence = NULL;
  289. if (tmp) {
  290. kref_put(&tmp->kref, &radeon_fence_destroy);
  291. }
  292. }
  293. void radeon_fence_process(struct radeon_device *rdev)
  294. {
  295. unsigned long irq_flags;
  296. bool wake;
  297. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  298. wake = radeon_fence_poll_locked(rdev);
  299. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  300. if (wake) {
  301. wake_up_all(&rdev->fence_drv.queue);
  302. }
  303. }
  304. int radeon_fence_driver_init(struct radeon_device *rdev)
  305. {
  306. unsigned long irq_flags;
  307. int r;
  308. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  309. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  310. if (r) {
  311. dev_err(rdev->dev, "fence failed to get scratch register\n");
  312. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  313. return r;
  314. }
  315. WREG32(rdev->fence_drv.scratch_reg, 0);
  316. atomic_set(&rdev->fence_drv.seq, 0);
  317. INIT_LIST_HEAD(&rdev->fence_drv.created);
  318. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  319. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  320. init_waitqueue_head(&rdev->fence_drv.queue);
  321. rdev->fence_drv.initialized = true;
  322. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  323. if (radeon_debugfs_fence_init(rdev)) {
  324. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  325. }
  326. return 0;
  327. }
  328. void radeon_fence_driver_fini(struct radeon_device *rdev)
  329. {
  330. unsigned long irq_flags;
  331. if (!rdev->fence_drv.initialized)
  332. return;
  333. wake_up_all(&rdev->fence_drv.queue);
  334. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  335. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  336. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  337. rdev->fence_drv.initialized = false;
  338. }
  339. /*
  340. * Fence debugfs
  341. */
  342. #if defined(CONFIG_DEBUG_FS)
  343. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  344. {
  345. struct drm_info_node *node = (struct drm_info_node *)m->private;
  346. struct drm_device *dev = node->minor->dev;
  347. struct radeon_device *rdev = dev->dev_private;
  348. struct radeon_fence *fence;
  349. seq_printf(m, "Last signaled fence 0x%08X\n",
  350. RREG32(rdev->fence_drv.scratch_reg));
  351. if (!list_empty(&rdev->fence_drv.emited)) {
  352. fence = list_entry(rdev->fence_drv.emited.prev,
  353. struct radeon_fence, list);
  354. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  355. fence, fence->seq);
  356. }
  357. return 0;
  358. }
  359. static struct drm_info_list radeon_debugfs_fence_list[] = {
  360. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  361. };
  362. #endif
  363. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  364. {
  365. #if defined(CONFIG_DEBUG_FS)
  366. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  367. #else
  368. return 0;
  369. #endif
  370. }