i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/slab.h>
  39. #include <linux/pagemap.h>
  40. #define I810_BUF_FREE 2
  41. #define I810_BUF_CLIENT 1
  42. #define I810_BUF_HARDWARE 0
  43. #define I810_BUF_UNMAPPED 0
  44. #define I810_BUF_MAPPED 1
  45. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  46. {
  47. struct drm_device_dma *dma = dev->dma;
  48. int i;
  49. int used;
  50. /* Linear search might not be the best solution */
  51. for (i = 0; i < dma->buf_count; i++) {
  52. struct drm_buf *buf = dma->buflist[i];
  53. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  54. /* In use is already a pointer */
  55. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  56. I810_BUF_CLIENT);
  57. if (used == I810_BUF_FREE) {
  58. return buf;
  59. }
  60. }
  61. return NULL;
  62. }
  63. /* This should only be called if the buffer is not sent to the hardware
  64. * yet, the hardware updates in use for us once its on the ring buffer.
  65. */
  66. static int i810_freelist_put(struct drm_device * dev, struct drm_buf * buf)
  67. {
  68. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  69. int used;
  70. /* In use is already a pointer */
  71. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  72. if (used != I810_BUF_CLIENT) {
  73. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  74. return -EINVAL;
  75. }
  76. return 0;
  77. }
  78. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  79. {
  80. struct drm_file *priv = filp->private_data;
  81. struct drm_device *dev;
  82. drm_i810_private_t *dev_priv;
  83. struct drm_buf *buf;
  84. drm_i810_buf_priv_t *buf_priv;
  85. lock_kernel();
  86. dev = priv->minor->dev;
  87. dev_priv = dev->dev_private;
  88. buf = dev_priv->mmap_buffer;
  89. buf_priv = buf->dev_private;
  90. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  91. vma->vm_file = filp;
  92. buf_priv->currently_mapped = I810_BUF_MAPPED;
  93. unlock_kernel();
  94. if (io_remap_pfn_range(vma, vma->vm_start,
  95. vma->vm_pgoff,
  96. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  97. return -EAGAIN;
  98. return 0;
  99. }
  100. static const struct file_operations i810_buffer_fops = {
  101. .open = drm_open,
  102. .release = drm_release,
  103. .unlocked_ioctl = drm_ioctl,
  104. .mmap = i810_mmap_buffers,
  105. .fasync = drm_fasync,
  106. };
  107. static int i810_map_buffer(struct drm_buf * buf, struct drm_file *file_priv)
  108. {
  109. struct drm_device *dev = file_priv->minor->dev;
  110. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  111. drm_i810_private_t *dev_priv = dev->dev_private;
  112. const struct file_operations *old_fops;
  113. int retcode = 0;
  114. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  115. return -EINVAL;
  116. down_write(&current->mm->mmap_sem);
  117. old_fops = file_priv->filp->f_op;
  118. file_priv->filp->f_op = &i810_buffer_fops;
  119. dev_priv->mmap_buffer = buf;
  120. buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
  121. PROT_READ | PROT_WRITE,
  122. MAP_SHARED, buf->bus_address);
  123. dev_priv->mmap_buffer = NULL;
  124. file_priv->filp->f_op = old_fops;
  125. if (IS_ERR(buf_priv->virtual)) {
  126. /* Real error */
  127. DRM_ERROR("mmap error\n");
  128. retcode = PTR_ERR(buf_priv->virtual);
  129. buf_priv->virtual = NULL;
  130. }
  131. up_write(&current->mm->mmap_sem);
  132. return retcode;
  133. }
  134. static int i810_unmap_buffer(struct drm_buf * buf)
  135. {
  136. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  137. int retcode = 0;
  138. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  139. return -EINVAL;
  140. down_write(&current->mm->mmap_sem);
  141. retcode = do_munmap(current->mm,
  142. (unsigned long)buf_priv->virtual,
  143. (size_t) buf->total);
  144. up_write(&current->mm->mmap_sem);
  145. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  146. buf_priv->virtual = NULL;
  147. return retcode;
  148. }
  149. static int i810_dma_get_buffer(struct drm_device * dev, drm_i810_dma_t * d,
  150. struct drm_file *file_priv)
  151. {
  152. struct drm_buf *buf;
  153. drm_i810_buf_priv_t *buf_priv;
  154. int retcode = 0;
  155. buf = i810_freelist_get(dev);
  156. if (!buf) {
  157. retcode = -ENOMEM;
  158. DRM_DEBUG("retcode=%d\n", retcode);
  159. return retcode;
  160. }
  161. retcode = i810_map_buffer(buf, file_priv);
  162. if (retcode) {
  163. i810_freelist_put(dev, buf);
  164. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  165. return retcode;
  166. }
  167. buf->file_priv = file_priv;
  168. buf_priv = buf->dev_private;
  169. d->granted = 1;
  170. d->request_idx = buf->idx;
  171. d->request_size = buf->total;
  172. d->virtual = buf_priv->virtual;
  173. return retcode;
  174. }
  175. static int i810_dma_cleanup(struct drm_device * dev)
  176. {
  177. struct drm_device_dma *dma = dev->dma;
  178. /* Make sure interrupts are disabled here because the uninstall ioctl
  179. * may not have been called from userspace and after dev_private
  180. * is freed, it's too late.
  181. */
  182. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  183. drm_irq_uninstall(dev);
  184. if (dev->dev_private) {
  185. int i;
  186. drm_i810_private_t *dev_priv =
  187. (drm_i810_private_t *) dev->dev_private;
  188. if (dev_priv->ring.virtual_start) {
  189. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  190. }
  191. if (dev_priv->hw_status_page) {
  192. pci_free_consistent(dev->pdev, PAGE_SIZE,
  193. dev_priv->hw_status_page,
  194. dev_priv->dma_status_page);
  195. /* Need to rewrite hardware status page */
  196. I810_WRITE(0x02080, 0x1ffff000);
  197. }
  198. kfree(dev->dev_private);
  199. dev->dev_private = NULL;
  200. for (i = 0; i < dma->buf_count; i++) {
  201. struct drm_buf *buf = dma->buflist[i];
  202. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  203. if (buf_priv->kernel_virtual && buf->total)
  204. drm_core_ioremapfree(&buf_priv->map, dev);
  205. }
  206. }
  207. return 0;
  208. }
  209. static int i810_wait_ring(struct drm_device * dev, int n)
  210. {
  211. drm_i810_private_t *dev_priv = dev->dev_private;
  212. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  213. int iters = 0;
  214. unsigned long end;
  215. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  216. end = jiffies + (HZ * 3);
  217. while (ring->space < n) {
  218. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  219. ring->space = ring->head - (ring->tail + 8);
  220. if (ring->space < 0)
  221. ring->space += ring->Size;
  222. if (ring->head != last_head) {
  223. end = jiffies + (HZ * 3);
  224. last_head = ring->head;
  225. }
  226. iters++;
  227. if (time_before(end, jiffies)) {
  228. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  229. DRM_ERROR("lockup\n");
  230. goto out_wait_ring;
  231. }
  232. udelay(1);
  233. }
  234. out_wait_ring:
  235. return iters;
  236. }
  237. static void i810_kernel_lost_context(struct drm_device * dev)
  238. {
  239. drm_i810_private_t *dev_priv = dev->dev_private;
  240. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  241. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  242. ring->tail = I810_READ(LP_RING + RING_TAIL);
  243. ring->space = ring->head - (ring->tail + 8);
  244. if (ring->space < 0)
  245. ring->space += ring->Size;
  246. }
  247. static int i810_freelist_init(struct drm_device * dev, drm_i810_private_t * dev_priv)
  248. {
  249. struct drm_device_dma *dma = dev->dma;
  250. int my_idx = 24;
  251. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  252. int i;
  253. if (dma->buf_count > 1019) {
  254. /* Not enough space in the status page for the freelist */
  255. return -EINVAL;
  256. }
  257. for (i = 0; i < dma->buf_count; i++) {
  258. struct drm_buf *buf = dma->buflist[i];
  259. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  260. buf_priv->in_use = hw_status++;
  261. buf_priv->my_use_idx = my_idx;
  262. my_idx += 4;
  263. *buf_priv->in_use = I810_BUF_FREE;
  264. buf_priv->map.offset = buf->bus_address;
  265. buf_priv->map.size = buf->total;
  266. buf_priv->map.type = _DRM_AGP;
  267. buf_priv->map.flags = 0;
  268. buf_priv->map.mtrr = 0;
  269. drm_core_ioremap(&buf_priv->map, dev);
  270. buf_priv->kernel_virtual = buf_priv->map.handle;
  271. }
  272. return 0;
  273. }
  274. static int i810_dma_initialize(struct drm_device * dev,
  275. drm_i810_private_t * dev_priv,
  276. drm_i810_init_t * init)
  277. {
  278. struct drm_map_list *r_list;
  279. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  280. list_for_each_entry(r_list, &dev->maplist, head) {
  281. if (r_list->map &&
  282. r_list->map->type == _DRM_SHM &&
  283. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  284. dev_priv->sarea_map = r_list->map;
  285. break;
  286. }
  287. }
  288. if (!dev_priv->sarea_map) {
  289. dev->dev_private = (void *)dev_priv;
  290. i810_dma_cleanup(dev);
  291. DRM_ERROR("can not find sarea!\n");
  292. return -EINVAL;
  293. }
  294. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  295. if (!dev_priv->mmio_map) {
  296. dev->dev_private = (void *)dev_priv;
  297. i810_dma_cleanup(dev);
  298. DRM_ERROR("can not find mmio map!\n");
  299. return -EINVAL;
  300. }
  301. dev->agp_buffer_token = init->buffers_offset;
  302. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  303. if (!dev->agp_buffer_map) {
  304. dev->dev_private = (void *)dev_priv;
  305. i810_dma_cleanup(dev);
  306. DRM_ERROR("can not find dma buffer map!\n");
  307. return -EINVAL;
  308. }
  309. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  310. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  311. dev_priv->ring.Start = init->ring_start;
  312. dev_priv->ring.End = init->ring_end;
  313. dev_priv->ring.Size = init->ring_size;
  314. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  315. dev_priv->ring.map.size = init->ring_size;
  316. dev_priv->ring.map.type = _DRM_AGP;
  317. dev_priv->ring.map.flags = 0;
  318. dev_priv->ring.map.mtrr = 0;
  319. drm_core_ioremap(&dev_priv->ring.map, dev);
  320. if (dev_priv->ring.map.handle == NULL) {
  321. dev->dev_private = (void *)dev_priv;
  322. i810_dma_cleanup(dev);
  323. DRM_ERROR("can not ioremap virtual address for"
  324. " ring buffer\n");
  325. return -ENOMEM;
  326. }
  327. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  328. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  329. dev_priv->w = init->w;
  330. dev_priv->h = init->h;
  331. dev_priv->pitch = init->pitch;
  332. dev_priv->back_offset = init->back_offset;
  333. dev_priv->depth_offset = init->depth_offset;
  334. dev_priv->front_offset = init->front_offset;
  335. dev_priv->overlay_offset = init->overlay_offset;
  336. dev_priv->overlay_physical = init->overlay_physical;
  337. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  338. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  339. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  340. /* Program Hardware Status Page */
  341. dev_priv->hw_status_page =
  342. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  343. &dev_priv->dma_status_page);
  344. if (!dev_priv->hw_status_page) {
  345. dev->dev_private = (void *)dev_priv;
  346. i810_dma_cleanup(dev);
  347. DRM_ERROR("Can not allocate hardware status page\n");
  348. return -ENOMEM;
  349. }
  350. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  351. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  352. I810_WRITE(0x02080, dev_priv->dma_status_page);
  353. DRM_DEBUG("Enabled hardware status page\n");
  354. /* Now we need to init our freelist */
  355. if (i810_freelist_init(dev, dev_priv) != 0) {
  356. dev->dev_private = (void *)dev_priv;
  357. i810_dma_cleanup(dev);
  358. DRM_ERROR("Not enough space in the status page for"
  359. " the freelist\n");
  360. return -ENOMEM;
  361. }
  362. dev->dev_private = (void *)dev_priv;
  363. return 0;
  364. }
  365. static int i810_dma_init(struct drm_device *dev, void *data,
  366. struct drm_file *file_priv)
  367. {
  368. drm_i810_private_t *dev_priv;
  369. drm_i810_init_t *init = data;
  370. int retcode = 0;
  371. switch (init->func) {
  372. case I810_INIT_DMA_1_4:
  373. DRM_INFO("Using v1.4 init.\n");
  374. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  375. if (dev_priv == NULL)
  376. return -ENOMEM;
  377. retcode = i810_dma_initialize(dev, dev_priv, init);
  378. break;
  379. case I810_CLEANUP_DMA:
  380. DRM_INFO("DMA Cleanup\n");
  381. retcode = i810_dma_cleanup(dev);
  382. break;
  383. default:
  384. return -EINVAL;
  385. }
  386. return retcode;
  387. }
  388. /* Most efficient way to verify state for the i810 is as it is
  389. * emitted. Non-conformant state is silently dropped.
  390. *
  391. * Use 'volatile' & local var tmp to force the emitted values to be
  392. * identical to the verified ones.
  393. */
  394. static void i810EmitContextVerified(struct drm_device * dev,
  395. volatile unsigned int *code)
  396. {
  397. drm_i810_private_t *dev_priv = dev->dev_private;
  398. int i, j = 0;
  399. unsigned int tmp;
  400. RING_LOCALS;
  401. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  402. OUT_RING(GFX_OP_COLOR_FACTOR);
  403. OUT_RING(code[I810_CTXREG_CF1]);
  404. OUT_RING(GFX_OP_STIPPLE);
  405. OUT_RING(code[I810_CTXREG_ST1]);
  406. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  407. tmp = code[i];
  408. if ((tmp & (7 << 29)) == (3 << 29) &&
  409. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  410. OUT_RING(tmp);
  411. j++;
  412. } else
  413. printk("constext state dropped!!!\n");
  414. }
  415. if (j & 1)
  416. OUT_RING(0);
  417. ADVANCE_LP_RING();
  418. }
  419. static void i810EmitTexVerified(struct drm_device * dev, volatile unsigned int *code)
  420. {
  421. drm_i810_private_t *dev_priv = dev->dev_private;
  422. int i, j = 0;
  423. unsigned int tmp;
  424. RING_LOCALS;
  425. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  426. OUT_RING(GFX_OP_MAP_INFO);
  427. OUT_RING(code[I810_TEXREG_MI1]);
  428. OUT_RING(code[I810_TEXREG_MI2]);
  429. OUT_RING(code[I810_TEXREG_MI3]);
  430. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  431. tmp = code[i];
  432. if ((tmp & (7 << 29)) == (3 << 29) &&
  433. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  434. OUT_RING(tmp);
  435. j++;
  436. } else
  437. printk("texture state dropped!!!\n");
  438. }
  439. if (j & 1)
  440. OUT_RING(0);
  441. ADVANCE_LP_RING();
  442. }
  443. /* Need to do some additional checking when setting the dest buffer.
  444. */
  445. static void i810EmitDestVerified(struct drm_device * dev,
  446. volatile unsigned int *code)
  447. {
  448. drm_i810_private_t *dev_priv = dev->dev_private;
  449. unsigned int tmp;
  450. RING_LOCALS;
  451. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  452. tmp = code[I810_DESTREG_DI1];
  453. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  454. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  455. OUT_RING(tmp);
  456. } else
  457. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  458. tmp, dev_priv->front_di1, dev_priv->back_di1);
  459. /* invarient:
  460. */
  461. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  462. OUT_RING(dev_priv->zi1);
  463. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  464. OUT_RING(code[I810_DESTREG_DV1]);
  465. OUT_RING(GFX_OP_DRAWRECT_INFO);
  466. OUT_RING(code[I810_DESTREG_DR1]);
  467. OUT_RING(code[I810_DESTREG_DR2]);
  468. OUT_RING(code[I810_DESTREG_DR3]);
  469. OUT_RING(code[I810_DESTREG_DR4]);
  470. OUT_RING(0);
  471. ADVANCE_LP_RING();
  472. }
  473. static void i810EmitState(struct drm_device * dev)
  474. {
  475. drm_i810_private_t *dev_priv = dev->dev_private;
  476. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  477. unsigned int dirty = sarea_priv->dirty;
  478. DRM_DEBUG("%x\n", dirty);
  479. if (dirty & I810_UPLOAD_BUFFERS) {
  480. i810EmitDestVerified(dev, sarea_priv->BufferState);
  481. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  482. }
  483. if (dirty & I810_UPLOAD_CTX) {
  484. i810EmitContextVerified(dev, sarea_priv->ContextState);
  485. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  486. }
  487. if (dirty & I810_UPLOAD_TEX0) {
  488. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  489. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  490. }
  491. if (dirty & I810_UPLOAD_TEX1) {
  492. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  493. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  494. }
  495. }
  496. /* need to verify
  497. */
  498. static void i810_dma_dispatch_clear(struct drm_device * dev, int flags,
  499. unsigned int clear_color,
  500. unsigned int clear_zval)
  501. {
  502. drm_i810_private_t *dev_priv = dev->dev_private;
  503. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  504. int nbox = sarea_priv->nbox;
  505. struct drm_clip_rect *pbox = sarea_priv->boxes;
  506. int pitch = dev_priv->pitch;
  507. int cpp = 2;
  508. int i;
  509. RING_LOCALS;
  510. if (dev_priv->current_page == 1) {
  511. unsigned int tmp = flags;
  512. flags &= ~(I810_FRONT | I810_BACK);
  513. if (tmp & I810_FRONT)
  514. flags |= I810_BACK;
  515. if (tmp & I810_BACK)
  516. flags |= I810_FRONT;
  517. }
  518. i810_kernel_lost_context(dev);
  519. if (nbox > I810_NR_SAREA_CLIPRECTS)
  520. nbox = I810_NR_SAREA_CLIPRECTS;
  521. for (i = 0; i < nbox; i++, pbox++) {
  522. unsigned int x = pbox->x1;
  523. unsigned int y = pbox->y1;
  524. unsigned int width = (pbox->x2 - x) * cpp;
  525. unsigned int height = pbox->y2 - y;
  526. unsigned int start = y * pitch + x * cpp;
  527. if (pbox->x1 > pbox->x2 ||
  528. pbox->y1 > pbox->y2 ||
  529. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  530. continue;
  531. if (flags & I810_FRONT) {
  532. BEGIN_LP_RING(6);
  533. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  534. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  535. OUT_RING((height << 16) | width);
  536. OUT_RING(start);
  537. OUT_RING(clear_color);
  538. OUT_RING(0);
  539. ADVANCE_LP_RING();
  540. }
  541. if (flags & I810_BACK) {
  542. BEGIN_LP_RING(6);
  543. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  544. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  545. OUT_RING((height << 16) | width);
  546. OUT_RING(dev_priv->back_offset + start);
  547. OUT_RING(clear_color);
  548. OUT_RING(0);
  549. ADVANCE_LP_RING();
  550. }
  551. if (flags & I810_DEPTH) {
  552. BEGIN_LP_RING(6);
  553. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  554. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  555. OUT_RING((height << 16) | width);
  556. OUT_RING(dev_priv->depth_offset + start);
  557. OUT_RING(clear_zval);
  558. OUT_RING(0);
  559. ADVANCE_LP_RING();
  560. }
  561. }
  562. }
  563. static void i810_dma_dispatch_swap(struct drm_device * dev)
  564. {
  565. drm_i810_private_t *dev_priv = dev->dev_private;
  566. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  567. int nbox = sarea_priv->nbox;
  568. struct drm_clip_rect *pbox = sarea_priv->boxes;
  569. int pitch = dev_priv->pitch;
  570. int cpp = 2;
  571. int i;
  572. RING_LOCALS;
  573. DRM_DEBUG("swapbuffers\n");
  574. i810_kernel_lost_context(dev);
  575. if (nbox > I810_NR_SAREA_CLIPRECTS)
  576. nbox = I810_NR_SAREA_CLIPRECTS;
  577. for (i = 0; i < nbox; i++, pbox++) {
  578. unsigned int w = pbox->x2 - pbox->x1;
  579. unsigned int h = pbox->y2 - pbox->y1;
  580. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  581. unsigned int start = dst;
  582. if (pbox->x1 > pbox->x2 ||
  583. pbox->y1 > pbox->y2 ||
  584. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  585. continue;
  586. BEGIN_LP_RING(6);
  587. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  588. OUT_RING(pitch | (0xCC << 16));
  589. OUT_RING((h << 16) | (w * cpp));
  590. if (dev_priv->current_page == 0)
  591. OUT_RING(dev_priv->front_offset + start);
  592. else
  593. OUT_RING(dev_priv->back_offset + start);
  594. OUT_RING(pitch);
  595. if (dev_priv->current_page == 0)
  596. OUT_RING(dev_priv->back_offset + start);
  597. else
  598. OUT_RING(dev_priv->front_offset + start);
  599. ADVANCE_LP_RING();
  600. }
  601. }
  602. static void i810_dma_dispatch_vertex(struct drm_device * dev,
  603. struct drm_buf * buf, int discard, int used)
  604. {
  605. drm_i810_private_t *dev_priv = dev->dev_private;
  606. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  607. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  608. struct drm_clip_rect *box = sarea_priv->boxes;
  609. int nbox = sarea_priv->nbox;
  610. unsigned long address = (unsigned long)buf->bus_address;
  611. unsigned long start = address - dev->agp->base;
  612. int i = 0;
  613. RING_LOCALS;
  614. i810_kernel_lost_context(dev);
  615. if (nbox > I810_NR_SAREA_CLIPRECTS)
  616. nbox = I810_NR_SAREA_CLIPRECTS;
  617. if (used > 4 * 1024)
  618. used = 0;
  619. if (sarea_priv->dirty)
  620. i810EmitState(dev);
  621. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  622. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  623. *(u32 *) buf_priv->kernel_virtual =
  624. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  625. if (used & 4) {
  626. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  627. used += 4;
  628. }
  629. i810_unmap_buffer(buf);
  630. }
  631. if (used) {
  632. do {
  633. if (i < nbox) {
  634. BEGIN_LP_RING(4);
  635. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  636. SC_ENABLE);
  637. OUT_RING(GFX_OP_SCISSOR_INFO);
  638. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  639. OUT_RING((box[i].x2 -
  640. 1) | ((box[i].y2 - 1) << 16));
  641. ADVANCE_LP_RING();
  642. }
  643. BEGIN_LP_RING(4);
  644. OUT_RING(CMD_OP_BATCH_BUFFER);
  645. OUT_RING(start | BB1_PROTECTED);
  646. OUT_RING(start + used - 4);
  647. OUT_RING(0);
  648. ADVANCE_LP_RING();
  649. } while (++i < nbox);
  650. }
  651. if (discard) {
  652. dev_priv->counter++;
  653. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  654. I810_BUF_HARDWARE);
  655. BEGIN_LP_RING(8);
  656. OUT_RING(CMD_STORE_DWORD_IDX);
  657. OUT_RING(20);
  658. OUT_RING(dev_priv->counter);
  659. OUT_RING(CMD_STORE_DWORD_IDX);
  660. OUT_RING(buf_priv->my_use_idx);
  661. OUT_RING(I810_BUF_FREE);
  662. OUT_RING(CMD_REPORT_HEAD);
  663. OUT_RING(0);
  664. ADVANCE_LP_RING();
  665. }
  666. }
  667. static void i810_dma_dispatch_flip(struct drm_device * dev)
  668. {
  669. drm_i810_private_t *dev_priv = dev->dev_private;
  670. int pitch = dev_priv->pitch;
  671. RING_LOCALS;
  672. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  673. dev_priv->current_page,
  674. dev_priv->sarea_priv->pf_current_page);
  675. i810_kernel_lost_context(dev);
  676. BEGIN_LP_RING(2);
  677. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  678. OUT_RING(0);
  679. ADVANCE_LP_RING();
  680. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  681. /* On i815 at least ASYNC is buggy */
  682. /* pitch<<5 is from 11.2.8 p158,
  683. its the pitch / 8 then left shifted 8,
  684. so (pitch >> 3) << 8 */
  685. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  686. if (dev_priv->current_page == 0) {
  687. OUT_RING(dev_priv->back_offset);
  688. dev_priv->current_page = 1;
  689. } else {
  690. OUT_RING(dev_priv->front_offset);
  691. dev_priv->current_page = 0;
  692. }
  693. OUT_RING(0);
  694. ADVANCE_LP_RING();
  695. BEGIN_LP_RING(2);
  696. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  697. OUT_RING(0);
  698. ADVANCE_LP_RING();
  699. /* Increment the frame counter. The client-side 3D driver must
  700. * throttle the framerate by waiting for this value before
  701. * performing the swapbuffer ioctl.
  702. */
  703. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  704. }
  705. static void i810_dma_quiescent(struct drm_device * dev)
  706. {
  707. drm_i810_private_t *dev_priv = dev->dev_private;
  708. RING_LOCALS;
  709. i810_kernel_lost_context(dev);
  710. BEGIN_LP_RING(4);
  711. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  712. OUT_RING(CMD_REPORT_HEAD);
  713. OUT_RING(0);
  714. OUT_RING(0);
  715. ADVANCE_LP_RING();
  716. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  717. }
  718. static int i810_flush_queue(struct drm_device * dev)
  719. {
  720. drm_i810_private_t *dev_priv = dev->dev_private;
  721. struct drm_device_dma *dma = dev->dma;
  722. int i, ret = 0;
  723. RING_LOCALS;
  724. i810_kernel_lost_context(dev);
  725. BEGIN_LP_RING(2);
  726. OUT_RING(CMD_REPORT_HEAD);
  727. OUT_RING(0);
  728. ADVANCE_LP_RING();
  729. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  730. for (i = 0; i < dma->buf_count; i++) {
  731. struct drm_buf *buf = dma->buflist[i];
  732. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  733. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  734. I810_BUF_FREE);
  735. if (used == I810_BUF_HARDWARE)
  736. DRM_DEBUG("reclaimed from HARDWARE\n");
  737. if (used == I810_BUF_CLIENT)
  738. DRM_DEBUG("still on client\n");
  739. }
  740. return ret;
  741. }
  742. /* Must be called with the lock held */
  743. static void i810_reclaim_buffers(struct drm_device * dev,
  744. struct drm_file *file_priv)
  745. {
  746. struct drm_device_dma *dma = dev->dma;
  747. int i;
  748. if (!dma)
  749. return;
  750. if (!dev->dev_private)
  751. return;
  752. if (!dma->buflist)
  753. return;
  754. i810_flush_queue(dev);
  755. for (i = 0; i < dma->buf_count; i++) {
  756. struct drm_buf *buf = dma->buflist[i];
  757. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  758. if (buf->file_priv == file_priv && buf_priv) {
  759. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  760. I810_BUF_FREE);
  761. if (used == I810_BUF_CLIENT)
  762. DRM_DEBUG("reclaimed from client\n");
  763. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  764. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  765. }
  766. }
  767. }
  768. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  769. struct drm_file *file_priv)
  770. {
  771. LOCK_TEST_WITH_RETURN(dev, file_priv);
  772. i810_flush_queue(dev);
  773. return 0;
  774. }
  775. static int i810_dma_vertex(struct drm_device *dev, void *data,
  776. struct drm_file *file_priv)
  777. {
  778. struct drm_device_dma *dma = dev->dma;
  779. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  780. u32 *hw_status = dev_priv->hw_status_page;
  781. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  782. dev_priv->sarea_priv;
  783. drm_i810_vertex_t *vertex = data;
  784. LOCK_TEST_WITH_RETURN(dev, file_priv);
  785. DRM_DEBUG("idx %d used %d discard %d\n",
  786. vertex->idx, vertex->used, vertex->discard);
  787. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  788. return -EINVAL;
  789. i810_dma_dispatch_vertex(dev,
  790. dma->buflist[vertex->idx],
  791. vertex->discard, vertex->used);
  792. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  793. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  794. sarea_priv->last_enqueue = dev_priv->counter - 1;
  795. sarea_priv->last_dispatch = (int)hw_status[5];
  796. return 0;
  797. }
  798. static int i810_clear_bufs(struct drm_device *dev, void *data,
  799. struct drm_file *file_priv)
  800. {
  801. drm_i810_clear_t *clear = data;
  802. LOCK_TEST_WITH_RETURN(dev, file_priv);
  803. /* GH: Someone's doing nasty things... */
  804. if (!dev->dev_private) {
  805. return -EINVAL;
  806. }
  807. i810_dma_dispatch_clear(dev, clear->flags,
  808. clear->clear_color, clear->clear_depth);
  809. return 0;
  810. }
  811. static int i810_swap_bufs(struct drm_device *dev, void *data,
  812. struct drm_file *file_priv)
  813. {
  814. DRM_DEBUG("\n");
  815. LOCK_TEST_WITH_RETURN(dev, file_priv);
  816. i810_dma_dispatch_swap(dev);
  817. return 0;
  818. }
  819. static int i810_getage(struct drm_device *dev, void *data,
  820. struct drm_file *file_priv)
  821. {
  822. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  823. u32 *hw_status = dev_priv->hw_status_page;
  824. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  825. dev_priv->sarea_priv;
  826. sarea_priv->last_dispatch = (int)hw_status[5];
  827. return 0;
  828. }
  829. static int i810_getbuf(struct drm_device *dev, void *data,
  830. struct drm_file *file_priv)
  831. {
  832. int retcode = 0;
  833. drm_i810_dma_t *d = data;
  834. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  835. u32 *hw_status = dev_priv->hw_status_page;
  836. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  837. dev_priv->sarea_priv;
  838. LOCK_TEST_WITH_RETURN(dev, file_priv);
  839. d->granted = 0;
  840. retcode = i810_dma_get_buffer(dev, d, file_priv);
  841. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  842. task_pid_nr(current), retcode, d->granted);
  843. sarea_priv->last_dispatch = (int)hw_status[5];
  844. return retcode;
  845. }
  846. static int i810_copybuf(struct drm_device *dev, void *data,
  847. struct drm_file *file_priv)
  848. {
  849. /* Never copy - 2.4.x doesn't need it */
  850. return 0;
  851. }
  852. static int i810_docopy(struct drm_device *dev, void *data,
  853. struct drm_file *file_priv)
  854. {
  855. /* Never copy - 2.4.x doesn't need it */
  856. return 0;
  857. }
  858. static void i810_dma_dispatch_mc(struct drm_device * dev, struct drm_buf * buf, int used,
  859. unsigned int last_render)
  860. {
  861. drm_i810_private_t *dev_priv = dev->dev_private;
  862. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  863. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  864. unsigned long address = (unsigned long)buf->bus_address;
  865. unsigned long start = address - dev->agp->base;
  866. int u;
  867. RING_LOCALS;
  868. i810_kernel_lost_context(dev);
  869. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  870. if (u != I810_BUF_CLIENT) {
  871. DRM_DEBUG("MC found buffer that isn't mine!\n");
  872. }
  873. if (used > 4 * 1024)
  874. used = 0;
  875. sarea_priv->dirty = 0x7f;
  876. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  877. dev_priv->counter++;
  878. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  879. DRM_DEBUG("start : %lx\n", start);
  880. DRM_DEBUG("used : %d\n", used);
  881. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  882. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  883. if (used & 4) {
  884. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  885. used += 4;
  886. }
  887. i810_unmap_buffer(buf);
  888. }
  889. BEGIN_LP_RING(4);
  890. OUT_RING(CMD_OP_BATCH_BUFFER);
  891. OUT_RING(start | BB1_PROTECTED);
  892. OUT_RING(start + used - 4);
  893. OUT_RING(0);
  894. ADVANCE_LP_RING();
  895. BEGIN_LP_RING(8);
  896. OUT_RING(CMD_STORE_DWORD_IDX);
  897. OUT_RING(buf_priv->my_use_idx);
  898. OUT_RING(I810_BUF_FREE);
  899. OUT_RING(0);
  900. OUT_RING(CMD_STORE_DWORD_IDX);
  901. OUT_RING(16);
  902. OUT_RING(last_render);
  903. OUT_RING(0);
  904. ADVANCE_LP_RING();
  905. }
  906. static int i810_dma_mc(struct drm_device *dev, void *data,
  907. struct drm_file *file_priv)
  908. {
  909. struct drm_device_dma *dma = dev->dma;
  910. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  911. u32 *hw_status = dev_priv->hw_status_page;
  912. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  913. dev_priv->sarea_priv;
  914. drm_i810_mc_t *mc = data;
  915. LOCK_TEST_WITH_RETURN(dev, file_priv);
  916. if (mc->idx >= dma->buf_count || mc->idx < 0)
  917. return -EINVAL;
  918. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  919. mc->last_render);
  920. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  921. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  922. sarea_priv->last_enqueue = dev_priv->counter - 1;
  923. sarea_priv->last_dispatch = (int)hw_status[5];
  924. return 0;
  925. }
  926. static int i810_rstatus(struct drm_device *dev, void *data,
  927. struct drm_file *file_priv)
  928. {
  929. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  930. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  931. }
  932. static int i810_ov0_info(struct drm_device *dev, void *data,
  933. struct drm_file *file_priv)
  934. {
  935. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  936. drm_i810_overlay_t *ov = data;
  937. ov->offset = dev_priv->overlay_offset;
  938. ov->physical = dev_priv->overlay_physical;
  939. return 0;
  940. }
  941. static int i810_fstatus(struct drm_device *dev, void *data,
  942. struct drm_file *file_priv)
  943. {
  944. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  945. LOCK_TEST_WITH_RETURN(dev, file_priv);
  946. return I810_READ(0x30008);
  947. }
  948. static int i810_ov0_flip(struct drm_device *dev, void *data,
  949. struct drm_file *file_priv)
  950. {
  951. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  952. LOCK_TEST_WITH_RETURN(dev, file_priv);
  953. //Tell the overlay to update
  954. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  955. return 0;
  956. }
  957. /* Not sure why this isn't set all the time:
  958. */
  959. static void i810_do_init_pageflip(struct drm_device * dev)
  960. {
  961. drm_i810_private_t *dev_priv = dev->dev_private;
  962. DRM_DEBUG("\n");
  963. dev_priv->page_flipping = 1;
  964. dev_priv->current_page = 0;
  965. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  966. }
  967. static int i810_do_cleanup_pageflip(struct drm_device * dev)
  968. {
  969. drm_i810_private_t *dev_priv = dev->dev_private;
  970. DRM_DEBUG("\n");
  971. if (dev_priv->current_page != 0)
  972. i810_dma_dispatch_flip(dev);
  973. dev_priv->page_flipping = 0;
  974. return 0;
  975. }
  976. static int i810_flip_bufs(struct drm_device *dev, void *data,
  977. struct drm_file *file_priv)
  978. {
  979. drm_i810_private_t *dev_priv = dev->dev_private;
  980. DRM_DEBUG("\n");
  981. LOCK_TEST_WITH_RETURN(dev, file_priv);
  982. if (!dev_priv->page_flipping)
  983. i810_do_init_pageflip(dev);
  984. i810_dma_dispatch_flip(dev);
  985. return 0;
  986. }
  987. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  988. {
  989. /* i810 has 4 more counters */
  990. dev->counters += 4;
  991. dev->types[6] = _DRM_STAT_IRQ;
  992. dev->types[7] = _DRM_STAT_PRIMARY;
  993. dev->types[8] = _DRM_STAT_SECONDARY;
  994. dev->types[9] = _DRM_STAT_DMA;
  995. return 0;
  996. }
  997. void i810_driver_lastclose(struct drm_device * dev)
  998. {
  999. i810_dma_cleanup(dev);
  1000. }
  1001. void i810_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1002. {
  1003. if (dev->dev_private) {
  1004. drm_i810_private_t *dev_priv = dev->dev_private;
  1005. if (dev_priv->page_flipping) {
  1006. i810_do_cleanup_pageflip(dev);
  1007. }
  1008. }
  1009. }
  1010. void i810_driver_reclaim_buffers_locked(struct drm_device * dev,
  1011. struct drm_file *file_priv)
  1012. {
  1013. i810_reclaim_buffers(dev, file_priv);
  1014. }
  1015. int i810_driver_dma_quiescent(struct drm_device * dev)
  1016. {
  1017. i810_dma_quiescent(dev);
  1018. return 0;
  1019. }
  1020. struct drm_ioctl_desc i810_ioctls[] = {
  1021. DRM_IOCTL_DEF(DRM_I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1022. DRM_IOCTL_DEF(DRM_I810_VERTEX, i810_dma_vertex, DRM_AUTH),
  1023. DRM_IOCTL_DEF(DRM_I810_CLEAR, i810_clear_bufs, DRM_AUTH),
  1024. DRM_IOCTL_DEF(DRM_I810_FLUSH, i810_flush_ioctl, DRM_AUTH),
  1025. DRM_IOCTL_DEF(DRM_I810_GETAGE, i810_getage, DRM_AUTH),
  1026. DRM_IOCTL_DEF(DRM_I810_GETBUF, i810_getbuf, DRM_AUTH),
  1027. DRM_IOCTL_DEF(DRM_I810_SWAP, i810_swap_bufs, DRM_AUTH),
  1028. DRM_IOCTL_DEF(DRM_I810_COPY, i810_copybuf, DRM_AUTH),
  1029. DRM_IOCTL_DEF(DRM_I810_DOCOPY, i810_docopy, DRM_AUTH),
  1030. DRM_IOCTL_DEF(DRM_I810_OV0INFO, i810_ov0_info, DRM_AUTH),
  1031. DRM_IOCTL_DEF(DRM_I810_FSTATUS, i810_fstatus, DRM_AUTH),
  1032. DRM_IOCTL_DEF(DRM_I810_OV0FLIP, i810_ov0_flip, DRM_AUTH),
  1033. DRM_IOCTL_DEF(DRM_I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1034. DRM_IOCTL_DEF(DRM_I810_RSTATUS, i810_rstatus, DRM_AUTH),
  1035. DRM_IOCTL_DEF(DRM_I810_FLIP, i810_flip_bufs, DRM_AUTH)
  1036. };
  1037. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1038. /**
  1039. * Determine if the device really is AGP or not.
  1040. *
  1041. * All Intel graphics chipsets are treated as AGP, even if they are really
  1042. * PCI-e.
  1043. *
  1044. * \param dev The device to be tested.
  1045. *
  1046. * \returns
  1047. * A value of 1 is always retured to indictate every i810 is AGP.
  1048. */
  1049. int i810_driver_device_is_agp(struct drm_device * dev)
  1050. {
  1051. return 1;
  1052. }