timbgpio.c 8.4 KB

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  1. /*
  2. * timbgpio.c timberdale FPGA GPIO driver
  3. * Copyright (c) 2009 Intel Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* Supports:
  19. * Timberdale FPGA GPIO
  20. */
  21. #include <linux/module.h>
  22. #include <linux/gpio.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/irq.h>
  25. #include <linux/io.h>
  26. #include <linux/timb_gpio.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/slab.h>
  29. #define DRIVER_NAME "timb-gpio"
  30. #define TGPIOVAL 0x00
  31. #define TGPIODIR 0x04
  32. #define TGPIO_IER 0x08
  33. #define TGPIO_ISR 0x0c
  34. #define TGPIO_IPR 0x10
  35. #define TGPIO_ICR 0x14
  36. #define TGPIO_FLR 0x18
  37. #define TGPIO_LVR 0x1c
  38. #define TGPIO_VER 0x20
  39. #define TGPIO_BFLR 0x24
  40. struct timbgpio {
  41. void __iomem *membase;
  42. spinlock_t lock; /* mutual exclusion */
  43. struct gpio_chip gpio;
  44. int irq_base;
  45. };
  46. static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
  47. unsigned offset, bool enabled)
  48. {
  49. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  50. u32 reg;
  51. spin_lock(&tgpio->lock);
  52. reg = ioread32(tgpio->membase + offset);
  53. if (enabled)
  54. reg |= (1 << index);
  55. else
  56. reg &= ~(1 << index);
  57. iowrite32(reg, tgpio->membase + offset);
  58. spin_unlock(&tgpio->lock);
  59. return 0;
  60. }
  61. static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  62. {
  63. return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
  64. }
  65. static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
  66. {
  67. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  68. u32 value;
  69. value = ioread32(tgpio->membase + TGPIOVAL);
  70. return (value & (1 << nr)) ? 1 : 0;
  71. }
  72. static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
  73. unsigned nr, int val)
  74. {
  75. return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
  76. }
  77. static void timbgpio_gpio_set(struct gpio_chip *gpio,
  78. unsigned nr, int val)
  79. {
  80. timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
  81. }
  82. static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
  83. {
  84. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  85. if (tgpio->irq_base <= 0)
  86. return -EINVAL;
  87. return tgpio->irq_base + offset;
  88. }
  89. /*
  90. * GPIO IRQ
  91. */
  92. static void timbgpio_irq_disable(unsigned irq)
  93. {
  94. struct timbgpio *tgpio = get_irq_chip_data(irq);
  95. int offset = irq - tgpio->irq_base;
  96. timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
  97. }
  98. static void timbgpio_irq_enable(unsigned irq)
  99. {
  100. struct timbgpio *tgpio = get_irq_chip_data(irq);
  101. int offset = irq - tgpio->irq_base;
  102. timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
  103. }
  104. static int timbgpio_irq_type(unsigned irq, unsigned trigger)
  105. {
  106. struct timbgpio *tgpio = get_irq_chip_data(irq);
  107. int offset = irq - tgpio->irq_base;
  108. unsigned long flags;
  109. u32 lvr, flr, bflr = 0;
  110. u32 ver;
  111. int ret = 0;
  112. if (offset < 0 || offset > tgpio->gpio.ngpio)
  113. return -EINVAL;
  114. ver = ioread32(tgpio->membase + TGPIO_VER);
  115. spin_lock_irqsave(&tgpio->lock, flags);
  116. lvr = ioread32(tgpio->membase + TGPIO_LVR);
  117. flr = ioread32(tgpio->membase + TGPIO_FLR);
  118. if (ver > 2)
  119. bflr = ioread32(tgpio->membase + TGPIO_BFLR);
  120. if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  121. bflr &= ~(1 << offset);
  122. flr &= ~(1 << offset);
  123. if (trigger & IRQ_TYPE_LEVEL_HIGH)
  124. lvr |= 1 << offset;
  125. else
  126. lvr &= ~(1 << offset);
  127. }
  128. if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  129. if (ver < 3) {
  130. ret = -EINVAL;
  131. goto out;
  132. }
  133. else {
  134. flr |= 1 << offset;
  135. bflr |= 1 << offset;
  136. }
  137. } else {
  138. bflr &= ~(1 << offset);
  139. flr |= 1 << offset;
  140. if (trigger & IRQ_TYPE_EDGE_FALLING)
  141. lvr &= ~(1 << offset);
  142. else
  143. lvr |= 1 << offset;
  144. }
  145. iowrite32(lvr, tgpio->membase + TGPIO_LVR);
  146. iowrite32(flr, tgpio->membase + TGPIO_FLR);
  147. if (ver > 2)
  148. iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
  149. iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
  150. out:
  151. spin_unlock_irqrestore(&tgpio->lock, flags);
  152. return ret;
  153. }
  154. static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
  155. {
  156. struct timbgpio *tgpio = get_irq_data(irq);
  157. unsigned long ipr;
  158. int offset;
  159. desc->chip->ack(irq);
  160. ipr = ioread32(tgpio->membase + TGPIO_IPR);
  161. iowrite32(ipr, tgpio->membase + TGPIO_ICR);
  162. for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
  163. generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
  164. }
  165. static struct irq_chip timbgpio_irqchip = {
  166. .name = "GPIO",
  167. .enable = timbgpio_irq_enable,
  168. .disable = timbgpio_irq_disable,
  169. .set_type = timbgpio_irq_type,
  170. };
  171. static int __devinit timbgpio_probe(struct platform_device *pdev)
  172. {
  173. int err, i;
  174. struct gpio_chip *gc;
  175. struct timbgpio *tgpio;
  176. struct resource *iomem;
  177. struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
  178. int irq = platform_get_irq(pdev, 0);
  179. if (!pdata || pdata->nr_pins > 32) {
  180. err = -EINVAL;
  181. goto err_mem;
  182. }
  183. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  184. if (!iomem) {
  185. err = -EINVAL;
  186. goto err_mem;
  187. }
  188. tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
  189. if (!tgpio) {
  190. err = -EINVAL;
  191. goto err_mem;
  192. }
  193. tgpio->irq_base = pdata->irq_base;
  194. spin_lock_init(&tgpio->lock);
  195. if (!request_mem_region(iomem->start, resource_size(iomem),
  196. DRIVER_NAME)) {
  197. err = -EBUSY;
  198. goto err_request;
  199. }
  200. tgpio->membase = ioremap(iomem->start, resource_size(iomem));
  201. if (!tgpio->membase) {
  202. err = -ENOMEM;
  203. goto err_ioremap;
  204. }
  205. gc = &tgpio->gpio;
  206. gc->label = dev_name(&pdev->dev);
  207. gc->owner = THIS_MODULE;
  208. gc->dev = &pdev->dev;
  209. gc->direction_input = timbgpio_gpio_direction_input;
  210. gc->get = timbgpio_gpio_get;
  211. gc->direction_output = timbgpio_gpio_direction_output;
  212. gc->set = timbgpio_gpio_set;
  213. gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
  214. gc->dbg_show = NULL;
  215. gc->base = pdata->gpio_base;
  216. gc->ngpio = pdata->nr_pins;
  217. gc->can_sleep = 0;
  218. err = gpiochip_add(gc);
  219. if (err)
  220. goto err_chipadd;
  221. platform_set_drvdata(pdev, tgpio);
  222. /* make sure to disable interrupts */
  223. iowrite32(0x0, tgpio->membase + TGPIO_IER);
  224. if (irq < 0 || tgpio->irq_base <= 0)
  225. return 0;
  226. for (i = 0; i < pdata->nr_pins; i++) {
  227. set_irq_chip_and_handler_name(tgpio->irq_base + i,
  228. &timbgpio_irqchip, handle_simple_irq, "mux");
  229. set_irq_chip_data(tgpio->irq_base + i, tgpio);
  230. #ifdef CONFIG_ARM
  231. set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
  232. #endif
  233. }
  234. set_irq_data(irq, tgpio);
  235. set_irq_chained_handler(irq, timbgpio_irq);
  236. return 0;
  237. err_chipadd:
  238. iounmap(tgpio->membase);
  239. err_ioremap:
  240. release_mem_region(iomem->start, resource_size(iomem));
  241. err_request:
  242. kfree(tgpio);
  243. err_mem:
  244. printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
  245. return err;
  246. }
  247. static int __devexit timbgpio_remove(struct platform_device *pdev)
  248. {
  249. int err;
  250. struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
  251. struct timbgpio *tgpio = platform_get_drvdata(pdev);
  252. struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  253. int irq = platform_get_irq(pdev, 0);
  254. if (irq >= 0 && tgpio->irq_base > 0) {
  255. int i;
  256. for (i = 0; i < pdata->nr_pins; i++) {
  257. set_irq_chip(tgpio->irq_base + i, NULL);
  258. set_irq_chip_data(tgpio->irq_base + i, NULL);
  259. }
  260. set_irq_handler(irq, NULL);
  261. set_irq_data(irq, NULL);
  262. }
  263. err = gpiochip_remove(&tgpio->gpio);
  264. if (err)
  265. printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
  266. iounmap(tgpio->membase);
  267. release_mem_region(iomem->start, resource_size(iomem));
  268. kfree(tgpio);
  269. platform_set_drvdata(pdev, NULL);
  270. return 0;
  271. }
  272. static struct platform_driver timbgpio_platform_driver = {
  273. .driver = {
  274. .name = DRIVER_NAME,
  275. .owner = THIS_MODULE,
  276. },
  277. .probe = timbgpio_probe,
  278. .remove = timbgpio_remove,
  279. };
  280. /*--------------------------------------------------------------------------*/
  281. static int __init timbgpio_init(void)
  282. {
  283. return platform_driver_register(&timbgpio_platform_driver);
  284. }
  285. static void __exit timbgpio_exit(void)
  286. {
  287. platform_driver_unregister(&timbgpio_platform_driver);
  288. }
  289. module_init(timbgpio_init);
  290. module_exit(timbgpio_exit);
  291. MODULE_DESCRIPTION("Timberdale GPIO driver");
  292. MODULE_LICENSE("GPL v2");
  293. MODULE_AUTHOR("Mocean Laboratories");
  294. MODULE_ALIAS("platform:"DRIVER_NAME);