dmaengine.c 28 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #include <linux/init.h>
  47. #include <linux/module.h>
  48. #include <linux/mm.h>
  49. #include <linux/device.h>
  50. #include <linux/dmaengine.h>
  51. #include <linux/hardirq.h>
  52. #include <linux/spinlock.h>
  53. #include <linux/percpu.h>
  54. #include <linux/rcupdate.h>
  55. #include <linux/mutex.h>
  56. #include <linux/jiffies.h>
  57. #include <linux/rculist.h>
  58. #include <linux/idr.h>
  59. #include <linux/slab.h>
  60. static DEFINE_MUTEX(dma_list_mutex);
  61. static LIST_HEAD(dma_device_list);
  62. static long dmaengine_ref_count;
  63. static struct idr dma_idr;
  64. /* --- sysfs implementation --- */
  65. /**
  66. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  67. * @dev - device node
  68. *
  69. * Must be called under dma_list_mutex
  70. */
  71. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  72. {
  73. struct dma_chan_dev *chan_dev;
  74. chan_dev = container_of(dev, typeof(*chan_dev), device);
  75. return chan_dev->chan;
  76. }
  77. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  78. {
  79. struct dma_chan *chan;
  80. unsigned long count = 0;
  81. int i;
  82. int err;
  83. mutex_lock(&dma_list_mutex);
  84. chan = dev_to_dma_chan(dev);
  85. if (chan) {
  86. for_each_possible_cpu(i)
  87. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  88. err = sprintf(buf, "%lu\n", count);
  89. } else
  90. err = -ENODEV;
  91. mutex_unlock(&dma_list_mutex);
  92. return err;
  93. }
  94. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  95. char *buf)
  96. {
  97. struct dma_chan *chan;
  98. unsigned long count = 0;
  99. int i;
  100. int err;
  101. mutex_lock(&dma_list_mutex);
  102. chan = dev_to_dma_chan(dev);
  103. if (chan) {
  104. for_each_possible_cpu(i)
  105. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  106. err = sprintf(buf, "%lu\n", count);
  107. } else
  108. err = -ENODEV;
  109. mutex_unlock(&dma_list_mutex);
  110. return err;
  111. }
  112. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  113. {
  114. struct dma_chan *chan;
  115. int err;
  116. mutex_lock(&dma_list_mutex);
  117. chan = dev_to_dma_chan(dev);
  118. if (chan)
  119. err = sprintf(buf, "%d\n", chan->client_count);
  120. else
  121. err = -ENODEV;
  122. mutex_unlock(&dma_list_mutex);
  123. return err;
  124. }
  125. static struct device_attribute dma_attrs[] = {
  126. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  127. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  128. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  129. __ATTR_NULL
  130. };
  131. static void chan_dev_release(struct device *dev)
  132. {
  133. struct dma_chan_dev *chan_dev;
  134. chan_dev = container_of(dev, typeof(*chan_dev), device);
  135. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  136. mutex_lock(&dma_list_mutex);
  137. idr_remove(&dma_idr, chan_dev->dev_id);
  138. mutex_unlock(&dma_list_mutex);
  139. kfree(chan_dev->idr_ref);
  140. }
  141. kfree(chan_dev);
  142. }
  143. static struct class dma_devclass = {
  144. .name = "dma",
  145. .dev_attrs = dma_attrs,
  146. .dev_release = chan_dev_release,
  147. };
  148. /* --- client and device registration --- */
  149. #define dma_device_satisfies_mask(device, mask) \
  150. __dma_device_satisfies_mask((device), &(mask))
  151. static int
  152. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  153. {
  154. dma_cap_mask_t has;
  155. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  156. DMA_TX_TYPE_END);
  157. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  158. }
  159. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  160. {
  161. return chan->device->dev->driver->owner;
  162. }
  163. /**
  164. * balance_ref_count - catch up the channel reference count
  165. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  166. *
  167. * balance_ref_count must be called under dma_list_mutex
  168. */
  169. static void balance_ref_count(struct dma_chan *chan)
  170. {
  171. struct module *owner = dma_chan_to_owner(chan);
  172. while (chan->client_count < dmaengine_ref_count) {
  173. __module_get(owner);
  174. chan->client_count++;
  175. }
  176. }
  177. /**
  178. * dma_chan_get - try to grab a dma channel's parent driver module
  179. * @chan - channel to grab
  180. *
  181. * Must be called under dma_list_mutex
  182. */
  183. static int dma_chan_get(struct dma_chan *chan)
  184. {
  185. int err = -ENODEV;
  186. struct module *owner = dma_chan_to_owner(chan);
  187. if (chan->client_count) {
  188. __module_get(owner);
  189. err = 0;
  190. } else if (try_module_get(owner))
  191. err = 0;
  192. if (err == 0)
  193. chan->client_count++;
  194. /* allocate upon first client reference */
  195. if (chan->client_count == 1 && err == 0) {
  196. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  197. if (desc_cnt < 0) {
  198. err = desc_cnt;
  199. chan->client_count = 0;
  200. module_put(owner);
  201. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  202. balance_ref_count(chan);
  203. }
  204. return err;
  205. }
  206. /**
  207. * dma_chan_put - drop a reference to a dma channel's parent driver module
  208. * @chan - channel to release
  209. *
  210. * Must be called under dma_list_mutex
  211. */
  212. static void dma_chan_put(struct dma_chan *chan)
  213. {
  214. if (!chan->client_count)
  215. return; /* this channel failed alloc_chan_resources */
  216. chan->client_count--;
  217. module_put(dma_chan_to_owner(chan));
  218. if (chan->client_count == 0)
  219. chan->device->device_free_chan_resources(chan);
  220. }
  221. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  222. {
  223. enum dma_status status;
  224. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  225. dma_async_issue_pending(chan);
  226. do {
  227. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  228. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  229. printk(KERN_ERR "dma_sync_wait_timeout!\n");
  230. return DMA_ERROR;
  231. }
  232. } while (status == DMA_IN_PROGRESS);
  233. return status;
  234. }
  235. EXPORT_SYMBOL(dma_sync_wait);
  236. /**
  237. * dma_cap_mask_all - enable iteration over all operation types
  238. */
  239. static dma_cap_mask_t dma_cap_mask_all;
  240. /**
  241. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  242. * @chan - associated channel for this entry
  243. */
  244. struct dma_chan_tbl_ent {
  245. struct dma_chan *chan;
  246. };
  247. /**
  248. * channel_table - percpu lookup table for memory-to-memory offload providers
  249. */
  250. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  251. static int __init dma_channel_table_init(void)
  252. {
  253. enum dma_transaction_type cap;
  254. int err = 0;
  255. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  256. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  257. * but are not associated with an operation so they do not need
  258. * an entry in the channel_table
  259. */
  260. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  261. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  262. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  263. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  264. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  265. if (!channel_table[cap]) {
  266. err = -ENOMEM;
  267. break;
  268. }
  269. }
  270. if (err) {
  271. pr_err("dmaengine: initialization failure\n");
  272. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  273. if (channel_table[cap])
  274. free_percpu(channel_table[cap]);
  275. }
  276. return err;
  277. }
  278. arch_initcall(dma_channel_table_init);
  279. /**
  280. * dma_find_channel - find a channel to carry out the operation
  281. * @tx_type: transaction type
  282. */
  283. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  284. {
  285. return this_cpu_read(channel_table[tx_type]->chan);
  286. }
  287. EXPORT_SYMBOL(dma_find_channel);
  288. /**
  289. * dma_issue_pending_all - flush all pending operations across all channels
  290. */
  291. void dma_issue_pending_all(void)
  292. {
  293. struct dma_device *device;
  294. struct dma_chan *chan;
  295. rcu_read_lock();
  296. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  297. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  298. continue;
  299. list_for_each_entry(chan, &device->channels, device_node)
  300. if (chan->client_count)
  301. device->device_issue_pending(chan);
  302. }
  303. rcu_read_unlock();
  304. }
  305. EXPORT_SYMBOL(dma_issue_pending_all);
  306. /**
  307. * nth_chan - returns the nth channel of the given capability
  308. * @cap: capability to match
  309. * @n: nth channel desired
  310. *
  311. * Defaults to returning the channel with the desired capability and the
  312. * lowest reference count when 'n' cannot be satisfied. Must be called
  313. * under dma_list_mutex.
  314. */
  315. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  316. {
  317. struct dma_device *device;
  318. struct dma_chan *chan;
  319. struct dma_chan *ret = NULL;
  320. struct dma_chan *min = NULL;
  321. list_for_each_entry(device, &dma_device_list, global_node) {
  322. if (!dma_has_cap(cap, device->cap_mask) ||
  323. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  324. continue;
  325. list_for_each_entry(chan, &device->channels, device_node) {
  326. if (!chan->client_count)
  327. continue;
  328. if (!min)
  329. min = chan;
  330. else if (chan->table_count < min->table_count)
  331. min = chan;
  332. if (n-- == 0) {
  333. ret = chan;
  334. break; /* done */
  335. }
  336. }
  337. if (ret)
  338. break; /* done */
  339. }
  340. if (!ret)
  341. ret = min;
  342. if (ret)
  343. ret->table_count++;
  344. return ret;
  345. }
  346. /**
  347. * dma_channel_rebalance - redistribute the available channels
  348. *
  349. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  350. * operation type) in the SMP case, and operation isolation (avoid
  351. * multi-tasking channels) in the non-SMP case. Must be called under
  352. * dma_list_mutex.
  353. */
  354. static void dma_channel_rebalance(void)
  355. {
  356. struct dma_chan *chan;
  357. struct dma_device *device;
  358. int cpu;
  359. int cap;
  360. int n;
  361. /* undo the last distribution */
  362. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  363. for_each_possible_cpu(cpu)
  364. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  365. list_for_each_entry(device, &dma_device_list, global_node) {
  366. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  367. continue;
  368. list_for_each_entry(chan, &device->channels, device_node)
  369. chan->table_count = 0;
  370. }
  371. /* don't populate the channel_table if no clients are available */
  372. if (!dmaengine_ref_count)
  373. return;
  374. /* redistribute available channels */
  375. n = 0;
  376. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  377. for_each_online_cpu(cpu) {
  378. if (num_possible_cpus() > 1)
  379. chan = nth_chan(cap, n++);
  380. else
  381. chan = nth_chan(cap, -1);
  382. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  383. }
  384. }
  385. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  386. dma_filter_fn fn, void *fn_param)
  387. {
  388. struct dma_chan *chan;
  389. if (!__dma_device_satisfies_mask(dev, mask)) {
  390. pr_debug("%s: wrong capabilities\n", __func__);
  391. return NULL;
  392. }
  393. /* devices with multiple channels need special handling as we need to
  394. * ensure that all channels are either private or public.
  395. */
  396. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  397. list_for_each_entry(chan, &dev->channels, device_node) {
  398. /* some channels are already publicly allocated */
  399. if (chan->client_count)
  400. return NULL;
  401. }
  402. list_for_each_entry(chan, &dev->channels, device_node) {
  403. if (chan->client_count) {
  404. pr_debug("%s: %s busy\n",
  405. __func__, dma_chan_name(chan));
  406. continue;
  407. }
  408. if (fn && !fn(chan, fn_param)) {
  409. pr_debug("%s: %s filter said false\n",
  410. __func__, dma_chan_name(chan));
  411. continue;
  412. }
  413. return chan;
  414. }
  415. return NULL;
  416. }
  417. /**
  418. * dma_request_channel - try to allocate an exclusive channel
  419. * @mask: capabilities that the channel must satisfy
  420. * @fn: optional callback to disposition available channels
  421. * @fn_param: opaque parameter to pass to dma_filter_fn
  422. */
  423. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  424. {
  425. struct dma_device *device, *_d;
  426. struct dma_chan *chan = NULL;
  427. int err;
  428. /* Find a channel */
  429. mutex_lock(&dma_list_mutex);
  430. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  431. chan = private_candidate(mask, device, fn, fn_param);
  432. if (chan) {
  433. /* Found a suitable channel, try to grab, prep, and
  434. * return it. We first set DMA_PRIVATE to disable
  435. * balance_ref_count as this channel will not be
  436. * published in the general-purpose allocator
  437. */
  438. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  439. device->privatecnt++;
  440. err = dma_chan_get(chan);
  441. if (err == -ENODEV) {
  442. pr_debug("%s: %s module removed\n", __func__,
  443. dma_chan_name(chan));
  444. list_del_rcu(&device->global_node);
  445. } else if (err)
  446. pr_err("dmaengine: failed to get %s: (%d)\n",
  447. dma_chan_name(chan), err);
  448. else
  449. break;
  450. if (--device->privatecnt == 0)
  451. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  452. chan = NULL;
  453. }
  454. }
  455. mutex_unlock(&dma_list_mutex);
  456. pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
  457. chan ? dma_chan_name(chan) : NULL);
  458. return chan;
  459. }
  460. EXPORT_SYMBOL_GPL(__dma_request_channel);
  461. void dma_release_channel(struct dma_chan *chan)
  462. {
  463. mutex_lock(&dma_list_mutex);
  464. WARN_ONCE(chan->client_count != 1,
  465. "chan reference count %d != 1\n", chan->client_count);
  466. dma_chan_put(chan);
  467. /* drop PRIVATE cap enabled by __dma_request_channel() */
  468. if (--chan->device->privatecnt == 0)
  469. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  470. mutex_unlock(&dma_list_mutex);
  471. }
  472. EXPORT_SYMBOL_GPL(dma_release_channel);
  473. /**
  474. * dmaengine_get - register interest in dma_channels
  475. */
  476. void dmaengine_get(void)
  477. {
  478. struct dma_device *device, *_d;
  479. struct dma_chan *chan;
  480. int err;
  481. mutex_lock(&dma_list_mutex);
  482. dmaengine_ref_count++;
  483. /* try to grab channels */
  484. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  485. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  486. continue;
  487. list_for_each_entry(chan, &device->channels, device_node) {
  488. err = dma_chan_get(chan);
  489. if (err == -ENODEV) {
  490. /* module removed before we could use it */
  491. list_del_rcu(&device->global_node);
  492. break;
  493. } else if (err)
  494. pr_err("dmaengine: failed to get %s: (%d)\n",
  495. dma_chan_name(chan), err);
  496. }
  497. }
  498. /* if this is the first reference and there were channels
  499. * waiting we need to rebalance to get those channels
  500. * incorporated into the channel table
  501. */
  502. if (dmaengine_ref_count == 1)
  503. dma_channel_rebalance();
  504. mutex_unlock(&dma_list_mutex);
  505. }
  506. EXPORT_SYMBOL(dmaengine_get);
  507. /**
  508. * dmaengine_put - let dma drivers be removed when ref_count == 0
  509. */
  510. void dmaengine_put(void)
  511. {
  512. struct dma_device *device;
  513. struct dma_chan *chan;
  514. mutex_lock(&dma_list_mutex);
  515. dmaengine_ref_count--;
  516. BUG_ON(dmaengine_ref_count < 0);
  517. /* drop channel references */
  518. list_for_each_entry(device, &dma_device_list, global_node) {
  519. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  520. continue;
  521. list_for_each_entry(chan, &device->channels, device_node)
  522. dma_chan_put(chan);
  523. }
  524. mutex_unlock(&dma_list_mutex);
  525. }
  526. EXPORT_SYMBOL(dmaengine_put);
  527. static bool device_has_all_tx_types(struct dma_device *device)
  528. {
  529. /* A device that satisfies this test has channels that will never cause
  530. * an async_tx channel switch event as all possible operation types can
  531. * be handled.
  532. */
  533. #ifdef CONFIG_ASYNC_TX_DMA
  534. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  535. return false;
  536. #endif
  537. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  538. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  539. return false;
  540. #endif
  541. #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
  542. if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
  543. return false;
  544. #endif
  545. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  546. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  547. return false;
  548. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  549. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  550. return false;
  551. #endif
  552. #endif
  553. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  554. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  555. return false;
  556. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  557. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  558. return false;
  559. #endif
  560. #endif
  561. return true;
  562. }
  563. static int get_dma_id(struct dma_device *device)
  564. {
  565. int rc;
  566. idr_retry:
  567. if (!idr_pre_get(&dma_idr, GFP_KERNEL))
  568. return -ENOMEM;
  569. mutex_lock(&dma_list_mutex);
  570. rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
  571. mutex_unlock(&dma_list_mutex);
  572. if (rc == -EAGAIN)
  573. goto idr_retry;
  574. else if (rc != 0)
  575. return rc;
  576. return 0;
  577. }
  578. /**
  579. * dma_async_device_register - registers DMA devices found
  580. * @device: &dma_device
  581. */
  582. int dma_async_device_register(struct dma_device *device)
  583. {
  584. int chancnt = 0, rc;
  585. struct dma_chan* chan;
  586. atomic_t *idr_ref;
  587. if (!device)
  588. return -ENODEV;
  589. /* validate device routines */
  590. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  591. !device->device_prep_dma_memcpy);
  592. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  593. !device->device_prep_dma_xor);
  594. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  595. !device->device_prep_dma_xor_val);
  596. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  597. !device->device_prep_dma_pq);
  598. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  599. !device->device_prep_dma_pq_val);
  600. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  601. !device->device_prep_dma_memset);
  602. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  603. !device->device_prep_dma_interrupt);
  604. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  605. !device->device_prep_slave_sg);
  606. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  607. !device->device_control);
  608. BUG_ON(!device->device_alloc_chan_resources);
  609. BUG_ON(!device->device_free_chan_resources);
  610. BUG_ON(!device->device_tx_status);
  611. BUG_ON(!device->device_issue_pending);
  612. BUG_ON(!device->dev);
  613. /* note: this only matters in the
  614. * CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y case
  615. */
  616. if (device_has_all_tx_types(device))
  617. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  618. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  619. if (!idr_ref)
  620. return -ENOMEM;
  621. rc = get_dma_id(device);
  622. if (rc != 0) {
  623. kfree(idr_ref);
  624. return rc;
  625. }
  626. atomic_set(idr_ref, 0);
  627. /* represent channels in sysfs. Probably want devs too */
  628. list_for_each_entry(chan, &device->channels, device_node) {
  629. rc = -ENOMEM;
  630. chan->local = alloc_percpu(typeof(*chan->local));
  631. if (chan->local == NULL)
  632. goto err_out;
  633. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  634. if (chan->dev == NULL) {
  635. free_percpu(chan->local);
  636. chan->local = NULL;
  637. goto err_out;
  638. }
  639. chan->chan_id = chancnt++;
  640. chan->dev->device.class = &dma_devclass;
  641. chan->dev->device.parent = device->dev;
  642. chan->dev->chan = chan;
  643. chan->dev->idr_ref = idr_ref;
  644. chan->dev->dev_id = device->dev_id;
  645. atomic_inc(idr_ref);
  646. dev_set_name(&chan->dev->device, "dma%dchan%d",
  647. device->dev_id, chan->chan_id);
  648. rc = device_register(&chan->dev->device);
  649. if (rc) {
  650. free_percpu(chan->local);
  651. chan->local = NULL;
  652. kfree(chan->dev);
  653. atomic_dec(idr_ref);
  654. goto err_out;
  655. }
  656. chan->client_count = 0;
  657. }
  658. device->chancnt = chancnt;
  659. mutex_lock(&dma_list_mutex);
  660. /* take references on public channels */
  661. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  662. list_for_each_entry(chan, &device->channels, device_node) {
  663. /* if clients are already waiting for channels we need
  664. * to take references on their behalf
  665. */
  666. if (dma_chan_get(chan) == -ENODEV) {
  667. /* note we can only get here for the first
  668. * channel as the remaining channels are
  669. * guaranteed to get a reference
  670. */
  671. rc = -ENODEV;
  672. mutex_unlock(&dma_list_mutex);
  673. goto err_out;
  674. }
  675. }
  676. list_add_tail_rcu(&device->global_node, &dma_device_list);
  677. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  678. device->privatecnt++; /* Always private */
  679. dma_channel_rebalance();
  680. mutex_unlock(&dma_list_mutex);
  681. return 0;
  682. err_out:
  683. /* if we never registered a channel just release the idr */
  684. if (atomic_read(idr_ref) == 0) {
  685. mutex_lock(&dma_list_mutex);
  686. idr_remove(&dma_idr, device->dev_id);
  687. mutex_unlock(&dma_list_mutex);
  688. kfree(idr_ref);
  689. return rc;
  690. }
  691. list_for_each_entry(chan, &device->channels, device_node) {
  692. if (chan->local == NULL)
  693. continue;
  694. mutex_lock(&dma_list_mutex);
  695. chan->dev->chan = NULL;
  696. mutex_unlock(&dma_list_mutex);
  697. device_unregister(&chan->dev->device);
  698. free_percpu(chan->local);
  699. }
  700. return rc;
  701. }
  702. EXPORT_SYMBOL(dma_async_device_register);
  703. /**
  704. * dma_async_device_unregister - unregister a DMA device
  705. * @device: &dma_device
  706. *
  707. * This routine is called by dma driver exit routines, dmaengine holds module
  708. * references to prevent it being called while channels are in use.
  709. */
  710. void dma_async_device_unregister(struct dma_device *device)
  711. {
  712. struct dma_chan *chan;
  713. mutex_lock(&dma_list_mutex);
  714. list_del_rcu(&device->global_node);
  715. dma_channel_rebalance();
  716. mutex_unlock(&dma_list_mutex);
  717. list_for_each_entry(chan, &device->channels, device_node) {
  718. WARN_ONCE(chan->client_count,
  719. "%s called while %d clients hold a reference\n",
  720. __func__, chan->client_count);
  721. mutex_lock(&dma_list_mutex);
  722. chan->dev->chan = NULL;
  723. mutex_unlock(&dma_list_mutex);
  724. device_unregister(&chan->dev->device);
  725. free_percpu(chan->local);
  726. }
  727. }
  728. EXPORT_SYMBOL(dma_async_device_unregister);
  729. /**
  730. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  731. * @chan: DMA channel to offload copy to
  732. * @dest: destination address (virtual)
  733. * @src: source address (virtual)
  734. * @len: length
  735. *
  736. * Both @dest and @src must be mappable to a bus address according to the
  737. * DMA mapping API rules for streaming mappings.
  738. * Both @dest and @src must stay memory resident (kernel memory or locked
  739. * user space pages).
  740. */
  741. dma_cookie_t
  742. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  743. void *src, size_t len)
  744. {
  745. struct dma_device *dev = chan->device;
  746. struct dma_async_tx_descriptor *tx;
  747. dma_addr_t dma_dest, dma_src;
  748. dma_cookie_t cookie;
  749. unsigned long flags;
  750. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  751. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  752. flags = DMA_CTRL_ACK |
  753. DMA_COMPL_SRC_UNMAP_SINGLE |
  754. DMA_COMPL_DEST_UNMAP_SINGLE;
  755. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  756. if (!tx) {
  757. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  758. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  759. return -ENOMEM;
  760. }
  761. tx->callback = NULL;
  762. cookie = tx->tx_submit(tx);
  763. preempt_disable();
  764. __this_cpu_add(chan->local->bytes_transferred, len);
  765. __this_cpu_inc(chan->local->memcpy_count);
  766. preempt_enable();
  767. return cookie;
  768. }
  769. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  770. /**
  771. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  772. * @chan: DMA channel to offload copy to
  773. * @page: destination page
  774. * @offset: offset in page to copy to
  775. * @kdata: source address (virtual)
  776. * @len: length
  777. *
  778. * Both @page/@offset and @kdata must be mappable to a bus address according
  779. * to the DMA mapping API rules for streaming mappings.
  780. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  781. * locked user space pages)
  782. */
  783. dma_cookie_t
  784. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  785. unsigned int offset, void *kdata, size_t len)
  786. {
  787. struct dma_device *dev = chan->device;
  788. struct dma_async_tx_descriptor *tx;
  789. dma_addr_t dma_dest, dma_src;
  790. dma_cookie_t cookie;
  791. unsigned long flags;
  792. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  793. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  794. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  795. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  796. if (!tx) {
  797. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  798. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  799. return -ENOMEM;
  800. }
  801. tx->callback = NULL;
  802. cookie = tx->tx_submit(tx);
  803. preempt_disable();
  804. __this_cpu_add(chan->local->bytes_transferred, len);
  805. __this_cpu_inc(chan->local->memcpy_count);
  806. preempt_enable();
  807. return cookie;
  808. }
  809. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  810. /**
  811. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  812. * @chan: DMA channel to offload copy to
  813. * @dest_pg: destination page
  814. * @dest_off: offset in page to copy to
  815. * @src_pg: source page
  816. * @src_off: offset in page to copy from
  817. * @len: length
  818. *
  819. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  820. * address according to the DMA mapping API rules for streaming mappings.
  821. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  822. * (kernel memory or locked user space pages).
  823. */
  824. dma_cookie_t
  825. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  826. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  827. size_t len)
  828. {
  829. struct dma_device *dev = chan->device;
  830. struct dma_async_tx_descriptor *tx;
  831. dma_addr_t dma_dest, dma_src;
  832. dma_cookie_t cookie;
  833. unsigned long flags;
  834. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  835. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  836. DMA_FROM_DEVICE);
  837. flags = DMA_CTRL_ACK;
  838. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  839. if (!tx) {
  840. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  841. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  842. return -ENOMEM;
  843. }
  844. tx->callback = NULL;
  845. cookie = tx->tx_submit(tx);
  846. preempt_disable();
  847. __this_cpu_add(chan->local->bytes_transferred, len);
  848. __this_cpu_inc(chan->local->memcpy_count);
  849. preempt_enable();
  850. return cookie;
  851. }
  852. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  853. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  854. struct dma_chan *chan)
  855. {
  856. tx->chan = chan;
  857. #ifndef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
  858. spin_lock_init(&tx->lock);
  859. #endif
  860. }
  861. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  862. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  863. * @tx: in-flight transaction to wait on
  864. */
  865. enum dma_status
  866. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  867. {
  868. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  869. if (!tx)
  870. return DMA_SUCCESS;
  871. while (tx->cookie == -EBUSY) {
  872. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  873. pr_err("%s timeout waiting for descriptor submission\n",
  874. __func__);
  875. return DMA_ERROR;
  876. }
  877. cpu_relax();
  878. }
  879. return dma_sync_wait(tx->chan, tx->cookie);
  880. }
  881. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  882. /* dma_run_dependencies - helper routine for dma drivers to process
  883. * (start) dependent operations on their target channel
  884. * @tx: transaction with dependencies
  885. */
  886. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  887. {
  888. struct dma_async_tx_descriptor *dep = txd_next(tx);
  889. struct dma_async_tx_descriptor *dep_next;
  890. struct dma_chan *chan;
  891. if (!dep)
  892. return;
  893. /* we'll submit tx->next now, so clear the link */
  894. txd_clear_next(tx);
  895. chan = dep->chan;
  896. /* keep submitting up until a channel switch is detected
  897. * in that case we will be called again as a result of
  898. * processing the interrupt from async_tx_channel_switch
  899. */
  900. for (; dep; dep = dep_next) {
  901. txd_lock(dep);
  902. txd_clear_parent(dep);
  903. dep_next = txd_next(dep);
  904. if (dep_next && dep_next->chan == chan)
  905. txd_clear_next(dep); /* ->next will be submitted */
  906. else
  907. dep_next = NULL; /* submit current dep and terminate */
  908. txd_unlock(dep);
  909. dep->tx_submit(dep);
  910. }
  911. chan->device->device_issue_pending(chan);
  912. }
  913. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  914. static int __init dma_bus_init(void)
  915. {
  916. idr_init(&dma_idr);
  917. mutex_init(&dma_list_mutex);
  918. return class_register(&dma_devclass);
  919. }
  920. arch_initcall(dma_bus_init);