usb.c 18 KB

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  1. /*
  2. * arch/arm/plat-omap/usb.c -- platform level USB initialization
  3. *
  4. * Copyright (C) 2004 Texas Instruments, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #undef DEBUG
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/types.h>
  24. #include <linux/errno.h>
  25. #include <linux/init.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/usb/otg.h>
  28. #include <linux/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/system.h>
  31. #include <mach/hardware.h>
  32. #include <plat/control.h>
  33. #include <plat/mux.h>
  34. #include <plat/usb.h>
  35. #include <plat/board.h>
  36. #ifdef CONFIG_ARCH_OMAP1
  37. #define INT_USB_IRQ_GEN IH2_BASE + 20
  38. #define INT_USB_IRQ_NISO IH2_BASE + 30
  39. #define INT_USB_IRQ_ISO IH2_BASE + 29
  40. #define INT_USB_IRQ_HGEN INT_USB_HHC_1
  41. #define INT_USB_IRQ_OTG IH2_BASE + 8
  42. #else
  43. #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN
  44. #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO
  45. #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO
  46. #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN
  47. #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG
  48. #endif
  49. /* These routines should handle the standard chip-specific modes
  50. * for usb0/1/2 ports, covering basic mux and transceiver setup.
  51. *
  52. * Some board-*.c files will need to set up additional mux options,
  53. * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
  54. */
  55. /* TESTED ON:
  56. * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
  57. * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
  58. * - 5912 OSK UDC, with *nonstandard* A-to-A cable
  59. * - 1510 Innovator UDC with bundled usb0 cable
  60. * - 1510 Innovator OHCI with bundled usb1/usb2 cable
  61. * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
  62. * - 1710 custom development board using alternate pin group
  63. * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
  64. */
  65. /*-------------------------------------------------------------------------*/
  66. #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
  67. static void omap2_usb_devconf_clear(u8 port, u32 mask)
  68. {
  69. u32 r;
  70. r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  71. r &= ~USBTXWRMODEI(port, mask);
  72. omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
  73. }
  74. static void omap2_usb_devconf_set(u8 port, u32 mask)
  75. {
  76. u32 r;
  77. r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  78. r |= USBTXWRMODEI(port, mask);
  79. omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
  80. }
  81. static void omap2_usb2_disable_5pinbitll(void)
  82. {
  83. u32 r;
  84. r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  85. r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
  86. omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
  87. }
  88. static void omap2_usb2_enable_5pinunitll(void)
  89. {
  90. u32 r;
  91. r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  92. r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
  93. omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
  94. }
  95. static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
  96. {
  97. u32 syscon1 = 0;
  98. if (cpu_is_omap24xx())
  99. omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
  100. if (nwires == 0) {
  101. if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
  102. u32 l;
  103. /* pulldown D+/D- */
  104. l = omap_readl(USB_TRANSCEIVER_CTRL);
  105. l &= ~(3 << 1);
  106. omap_writel(l, USB_TRANSCEIVER_CTRL);
  107. }
  108. return 0;
  109. }
  110. if (is_device) {
  111. if (cpu_is_omap24xx())
  112. omap_cfg_reg(J20_24XX_USB0_PUEN);
  113. else if (cpu_is_omap7xx()) {
  114. omap_cfg_reg(AA17_7XX_USB_DM);
  115. omap_cfg_reg(W16_7XX_USB_PU_EN);
  116. omap_cfg_reg(W17_7XX_USB_VBUSI);
  117. omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
  118. omap_cfg_reg(W19_7XX_USB_DCRST);
  119. } else
  120. omap_cfg_reg(W4_USB_PUEN);
  121. }
  122. /* internal transceiver (unavailable on 17xx, 24xx) */
  123. if (!cpu_class_is_omap2() && nwires == 2) {
  124. u32 l;
  125. // omap_cfg_reg(P9_USB_DP);
  126. // omap_cfg_reg(R8_USB_DM);
  127. if (cpu_is_omap15xx()) {
  128. /* This works on 1510-Innovator */
  129. return 0;
  130. }
  131. /* NOTES:
  132. * - peripheral should configure VBUS detection!
  133. * - only peripherals may use the internal D+/D- pulldowns
  134. * - OTG support on this port not yet written
  135. */
  136. /* Don't do this for omap7xx -- it causes USB to not work correctly */
  137. if (!cpu_is_omap7xx()) {
  138. l = omap_readl(USB_TRANSCEIVER_CTRL);
  139. l &= ~(7 << 4);
  140. if (!is_device)
  141. l |= (3 << 1);
  142. omap_writel(l, USB_TRANSCEIVER_CTRL);
  143. }
  144. return 3 << 16;
  145. }
  146. /* alternate pin config, external transceiver */
  147. if (cpu_is_omap15xx()) {
  148. printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
  149. return 0;
  150. }
  151. if (cpu_is_omap24xx()) {
  152. omap_cfg_reg(K18_24XX_USB0_DAT);
  153. omap_cfg_reg(K19_24XX_USB0_TXEN);
  154. omap_cfg_reg(J14_24XX_USB0_SE0);
  155. if (nwires != 3)
  156. omap_cfg_reg(J18_24XX_USB0_RCV);
  157. } else {
  158. omap_cfg_reg(V6_USB0_TXD);
  159. omap_cfg_reg(W9_USB0_TXEN);
  160. omap_cfg_reg(W5_USB0_SE0);
  161. if (nwires != 3)
  162. omap_cfg_reg(Y5_USB0_RCV);
  163. }
  164. /* NOTE: SPEED and SUSP aren't configured here. OTG hosts
  165. * may be able to use I2C requests to set those bits along
  166. * with VBUS switching and overcurrent detection.
  167. */
  168. if (cpu_class_is_omap1() && nwires != 6) {
  169. u32 l;
  170. l = omap_readl(USB_TRANSCEIVER_CTRL);
  171. l &= ~CONF_USB2_UNI_R;
  172. omap_writel(l, USB_TRANSCEIVER_CTRL);
  173. }
  174. switch (nwires) {
  175. case 3:
  176. syscon1 = 2;
  177. if (cpu_is_omap24xx())
  178. omap2_usb_devconf_set(0, USB_BIDIR);
  179. break;
  180. case 4:
  181. syscon1 = 1;
  182. if (cpu_is_omap24xx())
  183. omap2_usb_devconf_set(0, USB_BIDIR);
  184. break;
  185. case 6:
  186. syscon1 = 3;
  187. if (cpu_is_omap24xx()) {
  188. omap_cfg_reg(J19_24XX_USB0_VP);
  189. omap_cfg_reg(K20_24XX_USB0_VM);
  190. omap2_usb_devconf_set(0, USB_UNIDIR);
  191. } else {
  192. u32 l;
  193. omap_cfg_reg(AA9_USB0_VP);
  194. omap_cfg_reg(R9_USB0_VM);
  195. l = omap_readl(USB_TRANSCEIVER_CTRL);
  196. l |= CONF_USB2_UNI_R;
  197. omap_writel(l, USB_TRANSCEIVER_CTRL);
  198. }
  199. break;
  200. default:
  201. printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
  202. 0, nwires);
  203. }
  204. return syscon1 << 16;
  205. }
  206. static u32 __init omap_usb1_init(unsigned nwires)
  207. {
  208. u32 syscon1 = 0;
  209. if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
  210. u32 l;
  211. l = omap_readl(USB_TRANSCEIVER_CTRL);
  212. l &= ~CONF_USB1_UNI_R;
  213. omap_writel(l, USB_TRANSCEIVER_CTRL);
  214. }
  215. if (cpu_is_omap24xx())
  216. omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
  217. if (nwires == 0)
  218. return 0;
  219. /* external transceiver */
  220. if (cpu_class_is_omap1()) {
  221. omap_cfg_reg(USB1_TXD);
  222. omap_cfg_reg(USB1_TXEN);
  223. if (nwires != 3)
  224. omap_cfg_reg(USB1_RCV);
  225. }
  226. if (cpu_is_omap15xx()) {
  227. omap_cfg_reg(USB1_SEO);
  228. omap_cfg_reg(USB1_SPEED);
  229. // SUSP
  230. } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
  231. omap_cfg_reg(W13_1610_USB1_SE0);
  232. omap_cfg_reg(R13_1610_USB1_SPEED);
  233. // SUSP
  234. } else if (cpu_is_omap1710()) {
  235. omap_cfg_reg(R13_1710_USB1_SE0);
  236. // SUSP
  237. } else if (cpu_is_omap24xx()) {
  238. /* NOTE: board-specific code must set up pin muxing for usb1,
  239. * since each signal could come out on either of two balls.
  240. */
  241. } else {
  242. pr_debug("usb%d cpu unrecognized\n", 1);
  243. return 0;
  244. }
  245. switch (nwires) {
  246. case 2:
  247. if (!cpu_is_omap24xx())
  248. goto bad;
  249. /* NOTE: board-specific code must override this setting if
  250. * this TLL link is not using DP/DM
  251. */
  252. syscon1 = 1;
  253. omap2_usb_devconf_set(1, USB_BIDIR_TLL);
  254. break;
  255. case 3:
  256. syscon1 = 2;
  257. if (cpu_is_omap24xx())
  258. omap2_usb_devconf_set(1, USB_BIDIR);
  259. break;
  260. case 4:
  261. syscon1 = 1;
  262. if (cpu_is_omap24xx())
  263. omap2_usb_devconf_set(1, USB_BIDIR);
  264. break;
  265. case 6:
  266. if (cpu_is_omap24xx())
  267. goto bad;
  268. syscon1 = 3;
  269. omap_cfg_reg(USB1_VP);
  270. omap_cfg_reg(USB1_VM);
  271. if (!cpu_is_omap15xx()) {
  272. u32 l;
  273. l = omap_readl(USB_TRANSCEIVER_CTRL);
  274. l |= CONF_USB1_UNI_R;
  275. omap_writel(l, USB_TRANSCEIVER_CTRL);
  276. }
  277. break;
  278. default:
  279. bad:
  280. printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
  281. 1, nwires);
  282. }
  283. return syscon1 << 20;
  284. }
  285. static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
  286. {
  287. u32 syscon1 = 0;
  288. if (cpu_is_omap24xx()) {
  289. omap2_usb2_disable_5pinbitll();
  290. alt_pingroup = 0;
  291. }
  292. /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
  293. if (alt_pingroup || nwires == 0)
  294. return 0;
  295. if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
  296. u32 l;
  297. l = omap_readl(USB_TRANSCEIVER_CTRL);
  298. l &= ~CONF_USB2_UNI_R;
  299. omap_writel(l, USB_TRANSCEIVER_CTRL);
  300. }
  301. /* external transceiver */
  302. if (cpu_is_omap15xx()) {
  303. omap_cfg_reg(USB2_TXD);
  304. omap_cfg_reg(USB2_TXEN);
  305. omap_cfg_reg(USB2_SEO);
  306. if (nwires != 3)
  307. omap_cfg_reg(USB2_RCV);
  308. /* there is no USB2_SPEED */
  309. } else if (cpu_is_omap16xx()) {
  310. omap_cfg_reg(V6_USB2_TXD);
  311. omap_cfg_reg(W9_USB2_TXEN);
  312. omap_cfg_reg(W5_USB2_SE0);
  313. if (nwires != 3)
  314. omap_cfg_reg(Y5_USB2_RCV);
  315. // FIXME omap_cfg_reg(USB2_SPEED);
  316. } else if (cpu_is_omap24xx()) {
  317. omap_cfg_reg(Y11_24XX_USB2_DAT);
  318. omap_cfg_reg(AA10_24XX_USB2_SE0);
  319. if (nwires > 2)
  320. omap_cfg_reg(AA12_24XX_USB2_TXEN);
  321. if (nwires > 3)
  322. omap_cfg_reg(AA6_24XX_USB2_RCV);
  323. } else {
  324. pr_debug("usb%d cpu unrecognized\n", 1);
  325. return 0;
  326. }
  327. // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP);
  328. switch (nwires) {
  329. case 2:
  330. if (!cpu_is_omap24xx())
  331. goto bad;
  332. /* NOTE: board-specific code must override this setting if
  333. * this TLL link is not using DP/DM
  334. */
  335. syscon1 = 1;
  336. omap2_usb_devconf_set(2, USB_BIDIR_TLL);
  337. break;
  338. case 3:
  339. syscon1 = 2;
  340. if (cpu_is_omap24xx())
  341. omap2_usb_devconf_set(2, USB_BIDIR);
  342. break;
  343. case 4:
  344. syscon1 = 1;
  345. if (cpu_is_omap24xx())
  346. omap2_usb_devconf_set(2, USB_BIDIR);
  347. break;
  348. case 5:
  349. if (!cpu_is_omap24xx())
  350. goto bad;
  351. omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
  352. /* NOTE: board-specific code must override this setting if
  353. * this TLL link is not using DP/DM. Something must also
  354. * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
  355. */
  356. syscon1 = 3;
  357. omap2_usb2_enable_5pinunitll();
  358. break;
  359. case 6:
  360. if (cpu_is_omap24xx())
  361. goto bad;
  362. syscon1 = 3;
  363. if (cpu_is_omap15xx()) {
  364. omap_cfg_reg(USB2_VP);
  365. omap_cfg_reg(USB2_VM);
  366. } else {
  367. u32 l;
  368. omap_cfg_reg(AA9_USB2_VP);
  369. omap_cfg_reg(R9_USB2_VM);
  370. l = omap_readl(USB_TRANSCEIVER_CTRL);
  371. l |= CONF_USB2_UNI_R;
  372. omap_writel(l, USB_TRANSCEIVER_CTRL);
  373. }
  374. break;
  375. default:
  376. bad:
  377. printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
  378. 2, nwires);
  379. }
  380. return syscon1 << 24;
  381. }
  382. #endif
  383. /*-------------------------------------------------------------------------*/
  384. #ifdef CONFIG_USB_GADGET_OMAP
  385. static struct resource udc_resources[] = {
  386. /* order is significant! */
  387. { /* registers */
  388. .start = UDC_BASE,
  389. .end = UDC_BASE + 0xff,
  390. .flags = IORESOURCE_MEM,
  391. }, { /* general IRQ */
  392. .start = INT_USB_IRQ_GEN,
  393. .flags = IORESOURCE_IRQ,
  394. }, { /* PIO IRQ */
  395. .start = INT_USB_IRQ_NISO,
  396. .flags = IORESOURCE_IRQ,
  397. }, { /* SOF IRQ */
  398. .start = INT_USB_IRQ_ISO,
  399. .flags = IORESOURCE_IRQ,
  400. },
  401. };
  402. static u64 udc_dmamask = ~(u32)0;
  403. static struct platform_device udc_device = {
  404. .name = "omap_udc",
  405. .id = -1,
  406. .dev = {
  407. .dma_mask = &udc_dmamask,
  408. .coherent_dma_mask = 0xffffffff,
  409. },
  410. .num_resources = ARRAY_SIZE(udc_resources),
  411. .resource = udc_resources,
  412. };
  413. #endif
  414. #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  415. /* The dmamask must be set for OHCI to work */
  416. static u64 ohci_dmamask = ~(u32)0;
  417. static struct resource ohci_resources[] = {
  418. {
  419. .start = OMAP_OHCI_BASE,
  420. .end = OMAP_OHCI_BASE + 0xff,
  421. .flags = IORESOURCE_MEM,
  422. },
  423. {
  424. .start = INT_USB_IRQ_HGEN,
  425. .flags = IORESOURCE_IRQ,
  426. },
  427. };
  428. static struct platform_device ohci_device = {
  429. .name = "ohci",
  430. .id = -1,
  431. .dev = {
  432. .dma_mask = &ohci_dmamask,
  433. .coherent_dma_mask = 0xffffffff,
  434. },
  435. .num_resources = ARRAY_SIZE(ohci_resources),
  436. .resource = ohci_resources,
  437. };
  438. #endif
  439. #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
  440. static struct resource otg_resources[] = {
  441. /* order is significant! */
  442. {
  443. .start = OTG_BASE,
  444. .end = OTG_BASE + 0xff,
  445. .flags = IORESOURCE_MEM,
  446. }, {
  447. .start = INT_USB_IRQ_OTG,
  448. .flags = IORESOURCE_IRQ,
  449. },
  450. };
  451. static struct platform_device otg_device = {
  452. .name = "omap_otg",
  453. .id = -1,
  454. .num_resources = ARRAY_SIZE(otg_resources),
  455. .resource = otg_resources,
  456. };
  457. #endif
  458. /*-------------------------------------------------------------------------*/
  459. // FIXME correct answer depends on hmc_mode,
  460. // as does (on omap1) any nonzero value for config->otg port number
  461. #ifdef CONFIG_USB_GADGET_OMAP
  462. #define is_usb0_device(config) 1
  463. #else
  464. #define is_usb0_device(config) 0
  465. #endif
  466. /*-------------------------------------------------------------------------*/
  467. #ifdef CONFIG_ARCH_OMAP_OTG
  468. void __init
  469. omap_otg_init(struct omap_usb_config *config)
  470. {
  471. u32 syscon;
  472. int status;
  473. int alt_pingroup = 0;
  474. /* NOTE: no bus or clock setup (yet?) */
  475. syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
  476. if (!(syscon & OTG_RESET_DONE))
  477. pr_debug("USB resets not complete?\n");
  478. //omap_writew(0, OTG_IRQ_EN);
  479. /* pin muxing and transceiver pinouts */
  480. if (config->pins[0] > 2) /* alt pingroup 2 */
  481. alt_pingroup = 1;
  482. syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
  483. syscon |= omap_usb1_init(config->pins[1]);
  484. syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
  485. pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
  486. omap_writel(syscon, OTG_SYSCON_1);
  487. syscon = config->hmc_mode;
  488. syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
  489. #ifdef CONFIG_USB_OTG
  490. if (config->otg)
  491. syscon |= OTG_EN;
  492. #endif
  493. if (cpu_class_is_omap1())
  494. pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
  495. omap_readl(USB_TRANSCEIVER_CTRL));
  496. pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
  497. omap_writel(syscon, OTG_SYSCON_2);
  498. printk("USB: hmc %d", config->hmc_mode);
  499. if (!alt_pingroup)
  500. printk(", usb2 alt %d wires", config->pins[2]);
  501. else if (config->pins[0])
  502. printk(", usb0 %d wires%s", config->pins[0],
  503. is_usb0_device(config) ? " (dev)" : "");
  504. if (config->pins[1])
  505. printk(", usb1 %d wires", config->pins[1]);
  506. if (!alt_pingroup && config->pins[2])
  507. printk(", usb2 %d wires", config->pins[2]);
  508. if (config->otg)
  509. printk(", Mini-AB on usb%d", config->otg - 1);
  510. printk("\n");
  511. if (cpu_class_is_omap1()) {
  512. u16 w;
  513. /* leave USB clocks/controllers off until needed */
  514. w = omap_readw(ULPD_SOFT_REQ);
  515. w &= ~SOFT_USB_CLK_REQ;
  516. omap_writew(w, ULPD_SOFT_REQ);
  517. w = omap_readw(ULPD_CLOCK_CTRL);
  518. w &= ~USB_MCLK_EN;
  519. w |= DIS_USB_PVCI_CLK;
  520. omap_writew(w, ULPD_CLOCK_CTRL);
  521. }
  522. syscon = omap_readl(OTG_SYSCON_1);
  523. syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
  524. #ifdef CONFIG_USB_GADGET_OMAP
  525. if (config->otg || config->register_dev) {
  526. syscon &= ~DEV_IDLE_EN;
  527. udc_device.dev.platform_data = config;
  528. /* IRQ numbers for omap7xx */
  529. if(cpu_is_omap7xx()) {
  530. udc_resources[1].start = INT_7XX_USB_GENI;
  531. udc_resources[2].start = INT_7XX_USB_NON_ISO;
  532. udc_resources[3].start = INT_7XX_USB_ISO;
  533. }
  534. status = platform_device_register(&udc_device);
  535. if (status)
  536. pr_debug("can't register UDC device, %d\n", status);
  537. }
  538. #endif
  539. #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  540. if (config->otg || config->register_host) {
  541. syscon &= ~HST_IDLE_EN;
  542. ohci_device.dev.platform_data = config;
  543. if (cpu_is_omap7xx())
  544. ohci_resources[1].start = INT_7XX_USB_HHC_1;
  545. status = platform_device_register(&ohci_device);
  546. if (status)
  547. pr_debug("can't register OHCI device, %d\n", status);
  548. }
  549. #endif
  550. #ifdef CONFIG_USB_OTG
  551. if (config->otg) {
  552. syscon &= ~OTG_IDLE_EN;
  553. otg_device.dev.platform_data = config;
  554. if (cpu_is_omap7xx())
  555. otg_resources[1].start = INT_7XX_USB_OTG;
  556. status = platform_device_register(&otg_device);
  557. if (status)
  558. pr_debug("can't register OTG device, %d\n", status);
  559. }
  560. #endif
  561. pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
  562. omap_writel(syscon, OTG_SYSCON_1);
  563. status = 0;
  564. }
  565. #else
  566. static inline void omap_otg_init(struct omap_usb_config *config) {}
  567. #endif
  568. /*-------------------------------------------------------------------------*/
  569. #ifdef CONFIG_ARCH_OMAP15XX
  570. /* ULPD_DPLL_CTRL */
  571. #define DPLL_IOB (1 << 13)
  572. #define DPLL_PLL_ENABLE (1 << 4)
  573. #define DPLL_LOCK (1 << 0)
  574. /* ULPD_APLL_CTRL */
  575. #define APLL_NDPLL_SWITCH (1 << 0)
  576. static void __init omap_1510_usb_init(struct omap_usb_config *config)
  577. {
  578. unsigned int val;
  579. u16 w;
  580. omap_usb0_init(config->pins[0], is_usb0_device(config));
  581. omap_usb1_init(config->pins[1]);
  582. omap_usb2_init(config->pins[2], 0);
  583. val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
  584. val |= (config->hmc_mode << 1);
  585. omap_writel(val, MOD_CONF_CTRL_0);
  586. printk("USB: hmc %d", config->hmc_mode);
  587. if (config->pins[0])
  588. printk(", usb0 %d wires%s", config->pins[0],
  589. is_usb0_device(config) ? " (dev)" : "");
  590. if (config->pins[1])
  591. printk(", usb1 %d wires", config->pins[1]);
  592. if (config->pins[2])
  593. printk(", usb2 %d wires", config->pins[2]);
  594. printk("\n");
  595. /* use DPLL for 48 MHz function clock */
  596. pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
  597. omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
  598. w = omap_readw(ULPD_APLL_CTRL);
  599. w &= ~APLL_NDPLL_SWITCH;
  600. omap_writew(w, ULPD_APLL_CTRL);
  601. w = omap_readw(ULPD_DPLL_CTRL);
  602. w |= DPLL_IOB | DPLL_PLL_ENABLE;
  603. omap_writew(w, ULPD_DPLL_CTRL);
  604. w = omap_readw(ULPD_SOFT_REQ);
  605. w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
  606. omap_writew(w, ULPD_SOFT_REQ);
  607. while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
  608. cpu_relax();
  609. #ifdef CONFIG_USB_GADGET_OMAP
  610. if (config->register_dev) {
  611. int status;
  612. udc_device.dev.platform_data = config;
  613. status = platform_device_register(&udc_device);
  614. if (status)
  615. pr_debug("can't register UDC device, %d\n", status);
  616. /* udc driver gates 48MHz by D+ pullup */
  617. }
  618. #endif
  619. #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  620. if (config->register_host) {
  621. int status;
  622. ohci_device.dev.platform_data = config;
  623. status = platform_device_register(&ohci_device);
  624. if (status)
  625. pr_debug("can't register OHCI device, %d\n", status);
  626. /* hcd explicitly gates 48MHz */
  627. }
  628. #endif
  629. }
  630. #else
  631. static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
  632. #endif
  633. /*-------------------------------------------------------------------------*/
  634. void __init omap_usb_init(struct omap_usb_config *pdata)
  635. {
  636. if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
  637. omap_otg_init(pdata);
  638. else if (cpu_is_omap15xx())
  639. omap_1510_usb_init(pdata);
  640. else
  641. printk(KERN_ERR "USB: No init for your chip yet\n");
  642. }