intel_panel.c 8.4 KB

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  1. /*
  2. * Copyright © 2006-2010 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. * Chris Wilson <chris@chris-wilson.co.uk>
  29. */
  30. #include "intel_drv.h"
  31. #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  32. void
  33. intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
  34. struct drm_display_mode *adjusted_mode)
  35. {
  36. adjusted_mode->hdisplay = fixed_mode->hdisplay;
  37. adjusted_mode->hsync_start = fixed_mode->hsync_start;
  38. adjusted_mode->hsync_end = fixed_mode->hsync_end;
  39. adjusted_mode->htotal = fixed_mode->htotal;
  40. adjusted_mode->vdisplay = fixed_mode->vdisplay;
  41. adjusted_mode->vsync_start = fixed_mode->vsync_start;
  42. adjusted_mode->vsync_end = fixed_mode->vsync_end;
  43. adjusted_mode->vtotal = fixed_mode->vtotal;
  44. adjusted_mode->clock = fixed_mode->clock;
  45. drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  46. }
  47. /* adjusted_mode has been preset to be the panel's fixed mode */
  48. void
  49. intel_pch_panel_fitting(struct drm_device *dev,
  50. int fitting_mode,
  51. struct drm_display_mode *mode,
  52. struct drm_display_mode *adjusted_mode)
  53. {
  54. struct drm_i915_private *dev_priv = dev->dev_private;
  55. int x, y, width, height;
  56. x = y = width = height = 0;
  57. /* Native modes don't need fitting */
  58. if (adjusted_mode->hdisplay == mode->hdisplay &&
  59. adjusted_mode->vdisplay == mode->vdisplay)
  60. goto done;
  61. switch (fitting_mode) {
  62. case DRM_MODE_SCALE_CENTER:
  63. width = mode->hdisplay;
  64. height = mode->vdisplay;
  65. x = (adjusted_mode->hdisplay - width + 1)/2;
  66. y = (adjusted_mode->vdisplay - height + 1)/2;
  67. break;
  68. case DRM_MODE_SCALE_ASPECT:
  69. /* Scale but preserve the aspect ratio */
  70. {
  71. u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
  72. u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
  73. if (scaled_width > scaled_height) { /* pillar */
  74. width = scaled_height / mode->vdisplay;
  75. if (width & 1)
  76. width++;
  77. x = (adjusted_mode->hdisplay - width + 1) / 2;
  78. y = 0;
  79. height = adjusted_mode->vdisplay;
  80. } else if (scaled_width < scaled_height) { /* letter */
  81. height = scaled_width / mode->hdisplay;
  82. if (height & 1)
  83. height++;
  84. y = (adjusted_mode->vdisplay - height + 1) / 2;
  85. x = 0;
  86. width = adjusted_mode->hdisplay;
  87. } else {
  88. x = y = 0;
  89. width = adjusted_mode->hdisplay;
  90. height = adjusted_mode->vdisplay;
  91. }
  92. }
  93. break;
  94. default:
  95. case DRM_MODE_SCALE_FULLSCREEN:
  96. x = y = 0;
  97. width = adjusted_mode->hdisplay;
  98. height = adjusted_mode->vdisplay;
  99. break;
  100. }
  101. done:
  102. dev_priv->pch_pf_pos = (x << 16) | y;
  103. dev_priv->pch_pf_size = (width << 16) | height;
  104. }
  105. static int is_backlight_combination_mode(struct drm_device *dev)
  106. {
  107. struct drm_i915_private *dev_priv = dev->dev_private;
  108. if (INTEL_INFO(dev)->gen >= 4)
  109. return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
  110. if (IS_GEN2(dev))
  111. return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
  112. return 0;
  113. }
  114. static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
  115. {
  116. u32 val;
  117. /* Restore the CTL value if it lost, e.g. GPU reset */
  118. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  119. val = I915_READ(BLC_PWM_PCH_CTL2);
  120. if (dev_priv->saveBLC_PWM_CTL2 == 0) {
  121. dev_priv->saveBLC_PWM_CTL2 = val;
  122. } else if (val == 0) {
  123. I915_WRITE(BLC_PWM_PCH_CTL2,
  124. dev_priv->saveBLC_PWM_CTL);
  125. val = dev_priv->saveBLC_PWM_CTL;
  126. }
  127. } else {
  128. val = I915_READ(BLC_PWM_CTL);
  129. if (dev_priv->saveBLC_PWM_CTL == 0) {
  130. dev_priv->saveBLC_PWM_CTL = val;
  131. dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
  132. } else if (val == 0) {
  133. I915_WRITE(BLC_PWM_CTL,
  134. dev_priv->saveBLC_PWM_CTL);
  135. I915_WRITE(BLC_PWM_CTL2,
  136. dev_priv->saveBLC_PWM_CTL2);
  137. val = dev_priv->saveBLC_PWM_CTL;
  138. }
  139. }
  140. return val;
  141. }
  142. u32 intel_panel_get_max_backlight(struct drm_device *dev)
  143. {
  144. struct drm_i915_private *dev_priv = dev->dev_private;
  145. u32 max;
  146. max = i915_read_blc_pwm_ctl(dev_priv);
  147. if (max == 0) {
  148. /* XXX add code here to query mode clock or hardware clock
  149. * and program max PWM appropriately.
  150. */
  151. printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
  152. return 1;
  153. }
  154. if (HAS_PCH_SPLIT(dev)) {
  155. max >>= 16;
  156. } else {
  157. if (IS_PINEVIEW(dev)) {
  158. max >>= 17;
  159. } else {
  160. max >>= 16;
  161. if (INTEL_INFO(dev)->gen < 4)
  162. max &= ~1;
  163. }
  164. if (is_backlight_combination_mode(dev))
  165. max *= 0xff;
  166. }
  167. DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
  168. return max;
  169. }
  170. u32 intel_panel_get_backlight(struct drm_device *dev)
  171. {
  172. struct drm_i915_private *dev_priv = dev->dev_private;
  173. u32 val;
  174. if (HAS_PCH_SPLIT(dev)) {
  175. val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  176. } else {
  177. val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  178. if (IS_PINEVIEW(dev))
  179. val >>= 1;
  180. if (is_backlight_combination_mode(dev)){
  181. u8 lbpc;
  182. val &= ~1;
  183. pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
  184. val *= lbpc;
  185. }
  186. }
  187. DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
  188. return val;
  189. }
  190. static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
  191. {
  192. struct drm_i915_private *dev_priv = dev->dev_private;
  193. u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  194. I915_WRITE(BLC_PWM_CPU_CTL, val | level);
  195. }
  196. void intel_panel_set_backlight(struct drm_device *dev, u32 level)
  197. {
  198. struct drm_i915_private *dev_priv = dev->dev_private;
  199. u32 tmp;
  200. DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
  201. if (HAS_PCH_SPLIT(dev))
  202. return intel_pch_panel_set_backlight(dev, level);
  203. if (is_backlight_combination_mode(dev)){
  204. u32 max = intel_panel_get_max_backlight(dev);
  205. u8 lbpc;
  206. lbpc = level * 0xfe / max + 1;
  207. level /= lbpc;
  208. pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
  209. }
  210. tmp = I915_READ(BLC_PWM_CTL);
  211. if (IS_PINEVIEW(dev)) {
  212. tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
  213. level <<= 1;
  214. } else
  215. tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
  216. I915_WRITE(BLC_PWM_CTL, tmp | level);
  217. }
  218. void intel_panel_disable_backlight(struct drm_device *dev)
  219. {
  220. struct drm_i915_private *dev_priv = dev->dev_private;
  221. if (dev_priv->backlight_enabled) {
  222. dev_priv->backlight_level = intel_panel_get_backlight(dev);
  223. dev_priv->backlight_enabled = false;
  224. }
  225. intel_panel_set_backlight(dev, 0);
  226. }
  227. void intel_panel_enable_backlight(struct drm_device *dev)
  228. {
  229. struct drm_i915_private *dev_priv = dev->dev_private;
  230. if (dev_priv->backlight_level == 0)
  231. dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
  232. intel_panel_set_backlight(dev, dev_priv->backlight_level);
  233. dev_priv->backlight_enabled = true;
  234. }
  235. void intel_panel_setup_backlight(struct drm_device *dev)
  236. {
  237. struct drm_i915_private *dev_priv = dev->dev_private;
  238. dev_priv->backlight_level = intel_panel_get_backlight(dev);
  239. dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
  240. }
  241. enum drm_connector_status
  242. intel_panel_detect(struct drm_device *dev)
  243. {
  244. #if 0
  245. struct drm_i915_private *dev_priv = dev->dev_private;
  246. #endif
  247. if (i915_panel_ignore_lid)
  248. return i915_panel_ignore_lid > 0 ?
  249. connector_status_connected :
  250. connector_status_disconnected;
  251. /* opregion lid state on HP 2540p is wrong at boot up,
  252. * appears to be either the BIOS or Linux ACPI fault */
  253. #if 0
  254. /* Assume that the BIOS does not lie through the OpRegion... */
  255. if (dev_priv->opregion.lid_state)
  256. return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
  257. connector_status_connected :
  258. connector_status_disconnected;
  259. #endif
  260. return connector_status_unknown;
  261. }