devices.c 20 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <mach/udc.h>
  7. #include <mach/pxafb.h>
  8. #include <mach/mmc.h>
  9. #include <mach/irda.h>
  10. #include <mach/ohci.h>
  11. #include <mach/pxa27x_keypad.h>
  12. #include <mach/pxa2xx_spi.h>
  13. #include <mach/camera.h>
  14. #include <mach/audio.h>
  15. #include <mach/hardware.h>
  16. #include <plat/i2c.h>
  17. #include <plat/pxa3xx_nand.h>
  18. #include "devices.h"
  19. #include "generic.h"
  20. void __init pxa_register_device(struct platform_device *dev, void *data)
  21. {
  22. int ret;
  23. dev->dev.platform_data = data;
  24. ret = platform_device_register(dev);
  25. if (ret)
  26. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  27. }
  28. static struct resource pxamci_resources[] = {
  29. [0] = {
  30. .start = 0x41100000,
  31. .end = 0x41100fff,
  32. .flags = IORESOURCE_MEM,
  33. },
  34. [1] = {
  35. .start = IRQ_MMC,
  36. .end = IRQ_MMC,
  37. .flags = IORESOURCE_IRQ,
  38. },
  39. [2] = {
  40. .start = 21,
  41. .end = 21,
  42. .flags = IORESOURCE_DMA,
  43. },
  44. [3] = {
  45. .start = 22,
  46. .end = 22,
  47. .flags = IORESOURCE_DMA,
  48. },
  49. };
  50. static u64 pxamci_dmamask = 0xffffffffUL;
  51. struct platform_device pxa_device_mci = {
  52. .name = "pxa2xx-mci",
  53. .id = 0,
  54. .dev = {
  55. .dma_mask = &pxamci_dmamask,
  56. .coherent_dma_mask = 0xffffffff,
  57. },
  58. .num_resources = ARRAY_SIZE(pxamci_resources),
  59. .resource = pxamci_resources,
  60. };
  61. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  62. {
  63. pxa_register_device(&pxa_device_mci, info);
  64. }
  65. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  66. .gpio_pullup = -1,
  67. .gpio_vbus = -1,
  68. };
  69. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  70. {
  71. memcpy(&pxa_udc_info, info, sizeof *info);
  72. }
  73. static struct resource pxa2xx_udc_resources[] = {
  74. [0] = {
  75. .start = 0x40600000,
  76. .end = 0x4060ffff,
  77. .flags = IORESOURCE_MEM,
  78. },
  79. [1] = {
  80. .start = IRQ_USB,
  81. .end = IRQ_USB,
  82. .flags = IORESOURCE_IRQ,
  83. },
  84. };
  85. static u64 udc_dma_mask = ~(u32)0;
  86. struct platform_device pxa25x_device_udc = {
  87. .name = "pxa25x-udc",
  88. .id = -1,
  89. .resource = pxa2xx_udc_resources,
  90. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  91. .dev = {
  92. .platform_data = &pxa_udc_info,
  93. .dma_mask = &udc_dma_mask,
  94. }
  95. };
  96. struct platform_device pxa27x_device_udc = {
  97. .name = "pxa27x-udc",
  98. .id = -1,
  99. .resource = pxa2xx_udc_resources,
  100. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  101. .dev = {
  102. .platform_data = &pxa_udc_info,
  103. .dma_mask = &udc_dma_mask,
  104. }
  105. };
  106. static struct resource pxafb_resources[] = {
  107. [0] = {
  108. .start = 0x44000000,
  109. .end = 0x4400ffff,
  110. .flags = IORESOURCE_MEM,
  111. },
  112. [1] = {
  113. .start = IRQ_LCD,
  114. .end = IRQ_LCD,
  115. .flags = IORESOURCE_IRQ,
  116. },
  117. };
  118. static u64 fb_dma_mask = ~(u64)0;
  119. struct platform_device pxa_device_fb = {
  120. .name = "pxa2xx-fb",
  121. .id = -1,
  122. .dev = {
  123. .dma_mask = &fb_dma_mask,
  124. .coherent_dma_mask = 0xffffffff,
  125. },
  126. .num_resources = ARRAY_SIZE(pxafb_resources),
  127. .resource = pxafb_resources,
  128. };
  129. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  130. {
  131. pxa_register_device(&pxa_device_fb, info);
  132. }
  133. void __init set_pxa_fb_parent(struct device *parent_dev)
  134. {
  135. pxa_device_fb.dev.parent = parent_dev;
  136. }
  137. static struct resource pxa_resource_ffuart[] = {
  138. {
  139. .start = 0x40100000,
  140. .end = 0x40100023,
  141. .flags = IORESOURCE_MEM,
  142. }, {
  143. .start = IRQ_FFUART,
  144. .end = IRQ_FFUART,
  145. .flags = IORESOURCE_IRQ,
  146. }
  147. };
  148. struct platform_device pxa_device_ffuart = {
  149. .name = "pxa2xx-uart",
  150. .id = 0,
  151. .resource = pxa_resource_ffuart,
  152. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  153. };
  154. void __init pxa_set_ffuart_info(void *info)
  155. {
  156. pxa_register_device(&pxa_device_ffuart, info);
  157. }
  158. static struct resource pxa_resource_btuart[] = {
  159. {
  160. .start = 0x40200000,
  161. .end = 0x40200023,
  162. .flags = IORESOURCE_MEM,
  163. }, {
  164. .start = IRQ_BTUART,
  165. .end = IRQ_BTUART,
  166. .flags = IORESOURCE_IRQ,
  167. }
  168. };
  169. struct platform_device pxa_device_btuart = {
  170. .name = "pxa2xx-uart",
  171. .id = 1,
  172. .resource = pxa_resource_btuart,
  173. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  174. };
  175. void __init pxa_set_btuart_info(void *info)
  176. {
  177. pxa_register_device(&pxa_device_btuart, info);
  178. }
  179. static struct resource pxa_resource_stuart[] = {
  180. {
  181. .start = 0x40700000,
  182. .end = 0x40700023,
  183. .flags = IORESOURCE_MEM,
  184. }, {
  185. .start = IRQ_STUART,
  186. .end = IRQ_STUART,
  187. .flags = IORESOURCE_IRQ,
  188. }
  189. };
  190. struct platform_device pxa_device_stuart = {
  191. .name = "pxa2xx-uart",
  192. .id = 2,
  193. .resource = pxa_resource_stuart,
  194. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  195. };
  196. void __init pxa_set_stuart_info(void *info)
  197. {
  198. pxa_register_device(&pxa_device_stuart, info);
  199. }
  200. static struct resource pxa_resource_hwuart[] = {
  201. {
  202. .start = 0x41600000,
  203. .end = 0x4160002F,
  204. .flags = IORESOURCE_MEM,
  205. }, {
  206. .start = IRQ_HWUART,
  207. .end = IRQ_HWUART,
  208. .flags = IORESOURCE_IRQ,
  209. }
  210. };
  211. struct platform_device pxa_device_hwuart = {
  212. .name = "pxa2xx-uart",
  213. .id = 3,
  214. .resource = pxa_resource_hwuart,
  215. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  216. };
  217. void __init pxa_set_hwuart_info(void *info)
  218. {
  219. if (cpu_is_pxa255())
  220. pxa_register_device(&pxa_device_hwuart, info);
  221. else
  222. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  223. }
  224. static struct resource pxai2c_resources[] = {
  225. {
  226. .start = 0x40301680,
  227. .end = 0x403016a3,
  228. .flags = IORESOURCE_MEM,
  229. }, {
  230. .start = IRQ_I2C,
  231. .end = IRQ_I2C,
  232. .flags = IORESOURCE_IRQ,
  233. },
  234. };
  235. struct platform_device pxa_device_i2c = {
  236. .name = "pxa2xx-i2c",
  237. .id = 0,
  238. .resource = pxai2c_resources,
  239. .num_resources = ARRAY_SIZE(pxai2c_resources),
  240. };
  241. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  242. {
  243. pxa_register_device(&pxa_device_i2c, info);
  244. }
  245. #ifdef CONFIG_PXA27x
  246. static struct resource pxa27x_resources_i2c_power[] = {
  247. {
  248. .start = 0x40f00180,
  249. .end = 0x40f001a3,
  250. .flags = IORESOURCE_MEM,
  251. }, {
  252. .start = IRQ_PWRI2C,
  253. .end = IRQ_PWRI2C,
  254. .flags = IORESOURCE_IRQ,
  255. },
  256. };
  257. struct platform_device pxa27x_device_i2c_power = {
  258. .name = "pxa2xx-i2c",
  259. .id = 1,
  260. .resource = pxa27x_resources_i2c_power,
  261. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  262. };
  263. #endif
  264. #ifdef CONFIG_PXA3xx
  265. static struct resource pxa3xx_resources_i2c_power[] = {
  266. {
  267. .start = 0x40f500c0,
  268. .end = 0x40f500d3,
  269. .flags = IORESOURCE_MEM,
  270. }, {
  271. .start = IRQ_PWRI2C,
  272. .end = IRQ_PWRI2C,
  273. .flags = IORESOURCE_IRQ,
  274. },
  275. };
  276. struct platform_device pxa3xx_device_i2c_power = {
  277. .name = "pxa3xx-pwri2c",
  278. .id = 1,
  279. .resource = pxa3xx_resources_i2c_power,
  280. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  281. };
  282. #endif
  283. static struct resource pxai2s_resources[] = {
  284. {
  285. .start = 0x40400000,
  286. .end = 0x40400083,
  287. .flags = IORESOURCE_MEM,
  288. }, {
  289. .start = IRQ_I2S,
  290. .end = IRQ_I2S,
  291. .flags = IORESOURCE_IRQ,
  292. },
  293. };
  294. struct platform_device pxa_device_i2s = {
  295. .name = "pxa2xx-i2s",
  296. .id = -1,
  297. .resource = pxai2s_resources,
  298. .num_resources = ARRAY_SIZE(pxai2s_resources),
  299. };
  300. struct platform_device pxa_device_asoc_ssp1 = {
  301. .name = "pxa-ssp-dai",
  302. .id = 0,
  303. };
  304. struct platform_device pxa_device_asoc_ssp2= {
  305. .name = "pxa-ssp-dai",
  306. .id = 1,
  307. };
  308. struct platform_device pxa_device_asoc_ssp3 = {
  309. .name = "pxa-ssp-dai",
  310. .id = 2,
  311. };
  312. struct platform_device pxa_device_asoc_ssp4 = {
  313. .name = "pxa-ssp-dai",
  314. .id = 3,
  315. };
  316. struct platform_device pxa_device_asoc_platform = {
  317. .name = "pxa-pcm-audio",
  318. .id = -1,
  319. };
  320. static u64 pxaficp_dmamask = ~(u32)0;
  321. struct platform_device pxa_device_ficp = {
  322. .name = "pxa2xx-ir",
  323. .id = -1,
  324. .dev = {
  325. .dma_mask = &pxaficp_dmamask,
  326. .coherent_dma_mask = 0xffffffff,
  327. },
  328. };
  329. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  330. {
  331. pxa_register_device(&pxa_device_ficp, info);
  332. }
  333. static struct resource pxa_rtc_resources[] = {
  334. [0] = {
  335. .start = 0x40900000,
  336. .end = 0x40900000 + 0x3b,
  337. .flags = IORESOURCE_MEM,
  338. },
  339. [1] = {
  340. .start = IRQ_RTC1Hz,
  341. .end = IRQ_RTC1Hz,
  342. .flags = IORESOURCE_IRQ,
  343. },
  344. [2] = {
  345. .start = IRQ_RTCAlrm,
  346. .end = IRQ_RTCAlrm,
  347. .flags = IORESOURCE_IRQ,
  348. },
  349. };
  350. struct platform_device sa1100_device_rtc = {
  351. .name = "sa1100-rtc",
  352. .id = -1,
  353. };
  354. struct platform_device pxa_device_rtc = {
  355. .name = "pxa-rtc",
  356. .id = -1,
  357. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  358. .resource = pxa_rtc_resources,
  359. };
  360. static struct resource pxa_ac97_resources[] = {
  361. [0] = {
  362. .start = 0x40500000,
  363. .end = 0x40500000 + 0xfff,
  364. .flags = IORESOURCE_MEM,
  365. },
  366. [1] = {
  367. .start = IRQ_AC97,
  368. .end = IRQ_AC97,
  369. .flags = IORESOURCE_IRQ,
  370. },
  371. };
  372. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  373. struct platform_device pxa_device_ac97 = {
  374. .name = "pxa2xx-ac97",
  375. .id = -1,
  376. .dev = {
  377. .dma_mask = &pxa_ac97_dmamask,
  378. .coherent_dma_mask = 0xffffffff,
  379. },
  380. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  381. .resource = pxa_ac97_resources,
  382. };
  383. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  384. {
  385. pxa_register_device(&pxa_device_ac97, ops);
  386. }
  387. #ifdef CONFIG_PXA25x
  388. static struct resource pxa25x_resource_pwm0[] = {
  389. [0] = {
  390. .start = 0x40b00000,
  391. .end = 0x40b0000f,
  392. .flags = IORESOURCE_MEM,
  393. },
  394. };
  395. struct platform_device pxa25x_device_pwm0 = {
  396. .name = "pxa25x-pwm",
  397. .id = 0,
  398. .resource = pxa25x_resource_pwm0,
  399. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  400. };
  401. static struct resource pxa25x_resource_pwm1[] = {
  402. [0] = {
  403. .start = 0x40c00000,
  404. .end = 0x40c0000f,
  405. .flags = IORESOURCE_MEM,
  406. },
  407. };
  408. struct platform_device pxa25x_device_pwm1 = {
  409. .name = "pxa25x-pwm",
  410. .id = 1,
  411. .resource = pxa25x_resource_pwm1,
  412. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  413. };
  414. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  415. static struct resource pxa25x_resource_ssp[] = {
  416. [0] = {
  417. .start = 0x41000000,
  418. .end = 0x4100001f,
  419. .flags = IORESOURCE_MEM,
  420. },
  421. [1] = {
  422. .start = IRQ_SSP,
  423. .end = IRQ_SSP,
  424. .flags = IORESOURCE_IRQ,
  425. },
  426. [2] = {
  427. /* DRCMR for RX */
  428. .start = 13,
  429. .end = 13,
  430. .flags = IORESOURCE_DMA,
  431. },
  432. [3] = {
  433. /* DRCMR for TX */
  434. .start = 14,
  435. .end = 14,
  436. .flags = IORESOURCE_DMA,
  437. },
  438. };
  439. struct platform_device pxa25x_device_ssp = {
  440. .name = "pxa25x-ssp",
  441. .id = 0,
  442. .dev = {
  443. .dma_mask = &pxa25x_ssp_dma_mask,
  444. .coherent_dma_mask = DMA_BIT_MASK(32),
  445. },
  446. .resource = pxa25x_resource_ssp,
  447. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  448. };
  449. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  450. static struct resource pxa25x_resource_nssp[] = {
  451. [0] = {
  452. .start = 0x41400000,
  453. .end = 0x4140002f,
  454. .flags = IORESOURCE_MEM,
  455. },
  456. [1] = {
  457. .start = IRQ_NSSP,
  458. .end = IRQ_NSSP,
  459. .flags = IORESOURCE_IRQ,
  460. },
  461. [2] = {
  462. /* DRCMR for RX */
  463. .start = 15,
  464. .end = 15,
  465. .flags = IORESOURCE_DMA,
  466. },
  467. [3] = {
  468. /* DRCMR for TX */
  469. .start = 16,
  470. .end = 16,
  471. .flags = IORESOURCE_DMA,
  472. },
  473. };
  474. struct platform_device pxa25x_device_nssp = {
  475. .name = "pxa25x-nssp",
  476. .id = 1,
  477. .dev = {
  478. .dma_mask = &pxa25x_nssp_dma_mask,
  479. .coherent_dma_mask = DMA_BIT_MASK(32),
  480. },
  481. .resource = pxa25x_resource_nssp,
  482. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  483. };
  484. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  485. static struct resource pxa25x_resource_assp[] = {
  486. [0] = {
  487. .start = 0x41500000,
  488. .end = 0x4150002f,
  489. .flags = IORESOURCE_MEM,
  490. },
  491. [1] = {
  492. .start = IRQ_ASSP,
  493. .end = IRQ_ASSP,
  494. .flags = IORESOURCE_IRQ,
  495. },
  496. [2] = {
  497. /* DRCMR for RX */
  498. .start = 23,
  499. .end = 23,
  500. .flags = IORESOURCE_DMA,
  501. },
  502. [3] = {
  503. /* DRCMR for TX */
  504. .start = 24,
  505. .end = 24,
  506. .flags = IORESOURCE_DMA,
  507. },
  508. };
  509. struct platform_device pxa25x_device_assp = {
  510. /* ASSP is basically equivalent to NSSP */
  511. .name = "pxa25x-nssp",
  512. .id = 2,
  513. .dev = {
  514. .dma_mask = &pxa25x_assp_dma_mask,
  515. .coherent_dma_mask = DMA_BIT_MASK(32),
  516. },
  517. .resource = pxa25x_resource_assp,
  518. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  519. };
  520. #endif /* CONFIG_PXA25x */
  521. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  522. static struct resource pxa27x_resource_keypad[] = {
  523. [0] = {
  524. .start = 0x41500000,
  525. .end = 0x4150004c,
  526. .flags = IORESOURCE_MEM,
  527. },
  528. [1] = {
  529. .start = IRQ_KEYPAD,
  530. .end = IRQ_KEYPAD,
  531. .flags = IORESOURCE_IRQ,
  532. },
  533. };
  534. struct platform_device pxa27x_device_keypad = {
  535. .name = "pxa27x-keypad",
  536. .id = -1,
  537. .resource = pxa27x_resource_keypad,
  538. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  539. };
  540. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  541. {
  542. pxa_register_device(&pxa27x_device_keypad, info);
  543. }
  544. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  545. static struct resource pxa27x_resource_ohci[] = {
  546. [0] = {
  547. .start = 0x4C000000,
  548. .end = 0x4C00ff6f,
  549. .flags = IORESOURCE_MEM,
  550. },
  551. [1] = {
  552. .start = IRQ_USBH1,
  553. .end = IRQ_USBH1,
  554. .flags = IORESOURCE_IRQ,
  555. },
  556. };
  557. struct platform_device pxa27x_device_ohci = {
  558. .name = "pxa27x-ohci",
  559. .id = -1,
  560. .dev = {
  561. .dma_mask = &pxa27x_ohci_dma_mask,
  562. .coherent_dma_mask = DMA_BIT_MASK(32),
  563. },
  564. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  565. .resource = pxa27x_resource_ohci,
  566. };
  567. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  568. {
  569. pxa_register_device(&pxa27x_device_ohci, info);
  570. }
  571. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  572. static struct resource pxa27x_resource_ssp1[] = {
  573. [0] = {
  574. .start = 0x41000000,
  575. .end = 0x4100003f,
  576. .flags = IORESOURCE_MEM,
  577. },
  578. [1] = {
  579. .start = IRQ_SSP,
  580. .end = IRQ_SSP,
  581. .flags = IORESOURCE_IRQ,
  582. },
  583. [2] = {
  584. /* DRCMR for RX */
  585. .start = 13,
  586. .end = 13,
  587. .flags = IORESOURCE_DMA,
  588. },
  589. [3] = {
  590. /* DRCMR for TX */
  591. .start = 14,
  592. .end = 14,
  593. .flags = IORESOURCE_DMA,
  594. },
  595. };
  596. struct platform_device pxa27x_device_ssp1 = {
  597. .name = "pxa27x-ssp",
  598. .id = 0,
  599. .dev = {
  600. .dma_mask = &pxa27x_ssp1_dma_mask,
  601. .coherent_dma_mask = DMA_BIT_MASK(32),
  602. },
  603. .resource = pxa27x_resource_ssp1,
  604. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  605. };
  606. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  607. static struct resource pxa27x_resource_ssp2[] = {
  608. [0] = {
  609. .start = 0x41700000,
  610. .end = 0x4170003f,
  611. .flags = IORESOURCE_MEM,
  612. },
  613. [1] = {
  614. .start = IRQ_SSP2,
  615. .end = IRQ_SSP2,
  616. .flags = IORESOURCE_IRQ,
  617. },
  618. [2] = {
  619. /* DRCMR for RX */
  620. .start = 15,
  621. .end = 15,
  622. .flags = IORESOURCE_DMA,
  623. },
  624. [3] = {
  625. /* DRCMR for TX */
  626. .start = 16,
  627. .end = 16,
  628. .flags = IORESOURCE_DMA,
  629. },
  630. };
  631. struct platform_device pxa27x_device_ssp2 = {
  632. .name = "pxa27x-ssp",
  633. .id = 1,
  634. .dev = {
  635. .dma_mask = &pxa27x_ssp2_dma_mask,
  636. .coherent_dma_mask = DMA_BIT_MASK(32),
  637. },
  638. .resource = pxa27x_resource_ssp2,
  639. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  640. };
  641. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  642. static struct resource pxa27x_resource_ssp3[] = {
  643. [0] = {
  644. .start = 0x41900000,
  645. .end = 0x4190003f,
  646. .flags = IORESOURCE_MEM,
  647. },
  648. [1] = {
  649. .start = IRQ_SSP3,
  650. .end = IRQ_SSP3,
  651. .flags = IORESOURCE_IRQ,
  652. },
  653. [2] = {
  654. /* DRCMR for RX */
  655. .start = 66,
  656. .end = 66,
  657. .flags = IORESOURCE_DMA,
  658. },
  659. [3] = {
  660. /* DRCMR for TX */
  661. .start = 67,
  662. .end = 67,
  663. .flags = IORESOURCE_DMA,
  664. },
  665. };
  666. struct platform_device pxa27x_device_ssp3 = {
  667. .name = "pxa27x-ssp",
  668. .id = 2,
  669. .dev = {
  670. .dma_mask = &pxa27x_ssp3_dma_mask,
  671. .coherent_dma_mask = DMA_BIT_MASK(32),
  672. },
  673. .resource = pxa27x_resource_ssp3,
  674. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  675. };
  676. static struct resource pxa27x_resource_pwm0[] = {
  677. [0] = {
  678. .start = 0x40b00000,
  679. .end = 0x40b0001f,
  680. .flags = IORESOURCE_MEM,
  681. },
  682. };
  683. struct platform_device pxa27x_device_pwm0 = {
  684. .name = "pxa27x-pwm",
  685. .id = 0,
  686. .resource = pxa27x_resource_pwm0,
  687. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  688. };
  689. static struct resource pxa27x_resource_pwm1[] = {
  690. [0] = {
  691. .start = 0x40c00000,
  692. .end = 0x40c0001f,
  693. .flags = IORESOURCE_MEM,
  694. },
  695. };
  696. struct platform_device pxa27x_device_pwm1 = {
  697. .name = "pxa27x-pwm",
  698. .id = 1,
  699. .resource = pxa27x_resource_pwm1,
  700. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  701. };
  702. static struct resource pxa27x_resource_camera[] = {
  703. [0] = {
  704. .start = 0x50000000,
  705. .end = 0x50000fff,
  706. .flags = IORESOURCE_MEM,
  707. },
  708. [1] = {
  709. .start = IRQ_CAMERA,
  710. .end = IRQ_CAMERA,
  711. .flags = IORESOURCE_IRQ,
  712. },
  713. };
  714. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  715. static struct platform_device pxa27x_device_camera = {
  716. .name = "pxa27x-camera",
  717. .id = 0, /* This is used to put cameras on this interface */
  718. .dev = {
  719. .dma_mask = &pxa27x_dma_mask_camera,
  720. .coherent_dma_mask = 0xffffffff,
  721. },
  722. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  723. .resource = pxa27x_resource_camera,
  724. };
  725. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  726. {
  727. pxa_register_device(&pxa27x_device_camera, info);
  728. }
  729. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  730. #ifdef CONFIG_PXA3xx
  731. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  732. static struct resource pxa3xx_resource_ssp4[] = {
  733. [0] = {
  734. .start = 0x41a00000,
  735. .end = 0x41a0003f,
  736. .flags = IORESOURCE_MEM,
  737. },
  738. [1] = {
  739. .start = IRQ_SSP4,
  740. .end = IRQ_SSP4,
  741. .flags = IORESOURCE_IRQ,
  742. },
  743. [2] = {
  744. /* DRCMR for RX */
  745. .start = 2,
  746. .end = 2,
  747. .flags = IORESOURCE_DMA,
  748. },
  749. [3] = {
  750. /* DRCMR for TX */
  751. .start = 3,
  752. .end = 3,
  753. .flags = IORESOURCE_DMA,
  754. },
  755. };
  756. struct platform_device pxa3xx_device_ssp4 = {
  757. /* PXA3xx SSP is basically equivalent to PXA27x */
  758. .name = "pxa27x-ssp",
  759. .id = 3,
  760. .dev = {
  761. .dma_mask = &pxa3xx_ssp4_dma_mask,
  762. .coherent_dma_mask = DMA_BIT_MASK(32),
  763. },
  764. .resource = pxa3xx_resource_ssp4,
  765. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  766. };
  767. static struct resource pxa3xx_resources_mci2[] = {
  768. [0] = {
  769. .start = 0x42000000,
  770. .end = 0x42000fff,
  771. .flags = IORESOURCE_MEM,
  772. },
  773. [1] = {
  774. .start = IRQ_MMC2,
  775. .end = IRQ_MMC2,
  776. .flags = IORESOURCE_IRQ,
  777. },
  778. [2] = {
  779. .start = 93,
  780. .end = 93,
  781. .flags = IORESOURCE_DMA,
  782. },
  783. [3] = {
  784. .start = 94,
  785. .end = 94,
  786. .flags = IORESOURCE_DMA,
  787. },
  788. };
  789. struct platform_device pxa3xx_device_mci2 = {
  790. .name = "pxa2xx-mci",
  791. .id = 1,
  792. .dev = {
  793. .dma_mask = &pxamci_dmamask,
  794. .coherent_dma_mask = 0xffffffff,
  795. },
  796. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  797. .resource = pxa3xx_resources_mci2,
  798. };
  799. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  800. {
  801. pxa_register_device(&pxa3xx_device_mci2, info);
  802. }
  803. static struct resource pxa3xx_resources_mci3[] = {
  804. [0] = {
  805. .start = 0x42500000,
  806. .end = 0x42500fff,
  807. .flags = IORESOURCE_MEM,
  808. },
  809. [1] = {
  810. .start = IRQ_MMC3,
  811. .end = IRQ_MMC3,
  812. .flags = IORESOURCE_IRQ,
  813. },
  814. [2] = {
  815. .start = 100,
  816. .end = 100,
  817. .flags = IORESOURCE_DMA,
  818. },
  819. [3] = {
  820. .start = 101,
  821. .end = 101,
  822. .flags = IORESOURCE_DMA,
  823. },
  824. };
  825. struct platform_device pxa3xx_device_mci3 = {
  826. .name = "pxa2xx-mci",
  827. .id = 2,
  828. .dev = {
  829. .dma_mask = &pxamci_dmamask,
  830. .coherent_dma_mask = 0xffffffff,
  831. },
  832. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  833. .resource = pxa3xx_resources_mci3,
  834. };
  835. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  836. {
  837. pxa_register_device(&pxa3xx_device_mci3, info);
  838. }
  839. static struct resource pxa3xx_resources_nand[] = {
  840. [0] = {
  841. .start = 0x43100000,
  842. .end = 0x43100053,
  843. .flags = IORESOURCE_MEM,
  844. },
  845. [1] = {
  846. .start = IRQ_NAND,
  847. .end = IRQ_NAND,
  848. .flags = IORESOURCE_IRQ,
  849. },
  850. [2] = {
  851. /* DRCMR for Data DMA */
  852. .start = 97,
  853. .end = 97,
  854. .flags = IORESOURCE_DMA,
  855. },
  856. [3] = {
  857. /* DRCMR for Command DMA */
  858. .start = 99,
  859. .end = 99,
  860. .flags = IORESOURCE_DMA,
  861. },
  862. };
  863. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  864. struct platform_device pxa3xx_device_nand = {
  865. .name = "pxa3xx-nand",
  866. .id = -1,
  867. .dev = {
  868. .dma_mask = &pxa3xx_nand_dma_mask,
  869. .coherent_dma_mask = DMA_BIT_MASK(32),
  870. },
  871. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  872. .resource = pxa3xx_resources_nand,
  873. };
  874. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  875. {
  876. pxa_register_device(&pxa3xx_device_nand, info);
  877. }
  878. static struct resource pxa3xx_resources_gcu[] = {
  879. {
  880. .start = 0x54000000,
  881. .end = 0x54000fff,
  882. .flags = IORESOURCE_MEM,
  883. },
  884. {
  885. .start = IRQ_GCU,
  886. .end = IRQ_GCU,
  887. .flags = IORESOURCE_IRQ,
  888. },
  889. };
  890. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  891. struct platform_device pxa3xx_device_gcu = {
  892. .name = "pxa3xx-gcu",
  893. .id = -1,
  894. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  895. .resource = pxa3xx_resources_gcu,
  896. .dev = {
  897. .dma_mask = &pxa3xx_gcu_dmamask,
  898. .coherent_dma_mask = 0xffffffff,
  899. },
  900. };
  901. #endif /* CONFIG_PXA3xx */
  902. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  903. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  904. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  905. {
  906. struct platform_device *pd;
  907. pd = platform_device_alloc("pxa2xx-spi", id);
  908. if (pd == NULL) {
  909. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  910. id);
  911. return;
  912. }
  913. pd->dev.platform_data = info;
  914. platform_device_add(pd);
  915. }