tx.c 33 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199
  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2009 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/ipv6.h>
  15. #include <linux/slab.h>
  16. #include <net/ipv6.h>
  17. #include <linux/if_ether.h>
  18. #include <linux/highmem.h>
  19. #include "net_driver.h"
  20. #include "efx.h"
  21. #include "nic.h"
  22. #include "workarounds.h"
  23. /*
  24. * TX descriptor ring full threshold
  25. *
  26. * The tx_queue descriptor ring fill-level must fall below this value
  27. * before we restart the netif queue
  28. */
  29. #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u)
  30. /* We need to be able to nest calls to netif_tx_stop_queue(), partly
  31. * because of the 2 hardware queues associated with each core queue,
  32. * but also so that we can inhibit TX for reasons other than a full
  33. * hardware queue. */
  34. void efx_stop_queue(struct efx_channel *channel)
  35. {
  36. struct efx_nic *efx = channel->efx;
  37. struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
  38. if (!tx_queue)
  39. return;
  40. spin_lock_bh(&channel->tx_stop_lock);
  41. netif_vdbg(efx, tx_queued, efx->net_dev, "stop TX queue\n");
  42. atomic_inc(&channel->tx_stop_count);
  43. netif_tx_stop_queue(
  44. netdev_get_tx_queue(efx->net_dev,
  45. tx_queue->queue / EFX_TXQ_TYPES));
  46. spin_unlock_bh(&channel->tx_stop_lock);
  47. }
  48. /* Decrement core TX queue stop count and wake it if the count is 0 */
  49. void efx_wake_queue(struct efx_channel *channel)
  50. {
  51. struct efx_nic *efx = channel->efx;
  52. struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
  53. if (!tx_queue)
  54. return;
  55. local_bh_disable();
  56. if (atomic_dec_and_lock(&channel->tx_stop_count,
  57. &channel->tx_stop_lock)) {
  58. netif_vdbg(efx, tx_queued, efx->net_dev, "waking TX queue\n");
  59. netif_tx_wake_queue(
  60. netdev_get_tx_queue(efx->net_dev,
  61. tx_queue->queue / EFX_TXQ_TYPES));
  62. spin_unlock(&channel->tx_stop_lock);
  63. }
  64. local_bh_enable();
  65. }
  66. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  67. struct efx_tx_buffer *buffer)
  68. {
  69. if (buffer->unmap_len) {
  70. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  71. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  72. buffer->unmap_len);
  73. if (buffer->unmap_single)
  74. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  75. PCI_DMA_TODEVICE);
  76. else
  77. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  78. PCI_DMA_TODEVICE);
  79. buffer->unmap_len = 0;
  80. buffer->unmap_single = false;
  81. }
  82. if (buffer->skb) {
  83. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  84. buffer->skb = NULL;
  85. netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
  86. "TX queue %d transmission id %x complete\n",
  87. tx_queue->queue, tx_queue->read_count);
  88. }
  89. }
  90. /**
  91. * struct efx_tso_header - a DMA mapped buffer for packet headers
  92. * @next: Linked list of free ones.
  93. * The list is protected by the TX queue lock.
  94. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  95. * @dma_addr: The DMA address of the header below.
  96. *
  97. * This controls the memory used for a TSO header. Use TSOH_DATA()
  98. * to find the packet header data. Use TSOH_SIZE() to calculate the
  99. * total size required for a given packet header length. TSO headers
  100. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  101. */
  102. struct efx_tso_header {
  103. union {
  104. struct efx_tso_header *next;
  105. size_t unmap_len;
  106. };
  107. dma_addr_t dma_addr;
  108. };
  109. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  110. struct sk_buff *skb);
  111. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  112. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  113. struct efx_tso_header *tsoh);
  114. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  115. struct efx_tx_buffer *buffer)
  116. {
  117. if (buffer->tsoh) {
  118. if (likely(!buffer->tsoh->unmap_len)) {
  119. buffer->tsoh->next = tx_queue->tso_headers_free;
  120. tx_queue->tso_headers_free = buffer->tsoh;
  121. } else {
  122. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  123. }
  124. buffer->tsoh = NULL;
  125. }
  126. }
  127. static inline unsigned
  128. efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
  129. {
  130. /* Depending on the NIC revision, we can use descriptor
  131. * lengths up to 8K or 8K-1. However, since PCI Express
  132. * devices must split read requests at 4K boundaries, there is
  133. * little benefit from using descriptors that cross those
  134. * boundaries and we keep things simple by not doing so.
  135. */
  136. unsigned len = (~dma_addr & 0xfff) + 1;
  137. /* Work around hardware bug for unaligned buffers. */
  138. if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
  139. len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
  140. return len;
  141. }
  142. /*
  143. * Add a socket buffer to a TX queue
  144. *
  145. * This maps all fragments of a socket buffer for DMA and adds them to
  146. * the TX queue. The queue's insert pointer will be incremented by
  147. * the number of fragments in the socket buffer.
  148. *
  149. * If any DMA mapping fails, any mapped fragments will be unmapped,
  150. * the queue's insert pointer will be restored to its original value.
  151. *
  152. * This function is split out from efx_hard_start_xmit to allow the
  153. * loopback test to direct packets via specific TX queues.
  154. *
  155. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  156. * You must hold netif_tx_lock() to call this function.
  157. */
  158. netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  159. {
  160. struct efx_nic *efx = tx_queue->efx;
  161. struct pci_dev *pci_dev = efx->pci_dev;
  162. struct efx_tx_buffer *buffer;
  163. skb_frag_t *fragment;
  164. struct page *page;
  165. int page_offset;
  166. unsigned int len, unmap_len = 0, fill_level, insert_ptr;
  167. dma_addr_t dma_addr, unmap_addr = 0;
  168. unsigned int dma_len;
  169. bool unmap_single;
  170. int q_space, i = 0;
  171. netdev_tx_t rc = NETDEV_TX_OK;
  172. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  173. if (skb_shinfo(skb)->gso_size)
  174. return efx_enqueue_skb_tso(tx_queue, skb);
  175. /* Get size of the initial fragment */
  176. len = skb_headlen(skb);
  177. /* Pad if necessary */
  178. if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
  179. EFX_BUG_ON_PARANOID(skb->data_len);
  180. len = 32 + 1;
  181. if (skb_pad(skb, len - skb->len))
  182. return NETDEV_TX_OK;
  183. }
  184. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  185. q_space = efx->txq_entries - 1 - fill_level;
  186. /* Map for DMA. Use pci_map_single rather than pci_map_page
  187. * since this is more efficient on machines with sparse
  188. * memory.
  189. */
  190. unmap_single = true;
  191. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  192. /* Process all fragments */
  193. while (1) {
  194. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  195. goto pci_err;
  196. /* Store fields for marking in the per-fragment final
  197. * descriptor */
  198. unmap_len = len;
  199. unmap_addr = dma_addr;
  200. /* Add to TX queue, splitting across DMA boundaries */
  201. do {
  202. if (unlikely(q_space-- <= 0)) {
  203. /* It might be that completions have
  204. * happened since the xmit path last
  205. * checked. Update the xmit path's
  206. * copy of read_count.
  207. */
  208. ++tx_queue->stopped;
  209. /* This memory barrier protects the
  210. * change of stopped from the access
  211. * of read_count. */
  212. smp_mb();
  213. tx_queue->old_read_count =
  214. ACCESS_ONCE(tx_queue->read_count);
  215. fill_level = (tx_queue->insert_count
  216. - tx_queue->old_read_count);
  217. q_space = efx->txq_entries - 1 - fill_level;
  218. if (unlikely(q_space-- <= 0))
  219. goto stop;
  220. smp_mb();
  221. --tx_queue->stopped;
  222. }
  223. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  224. buffer = &tx_queue->buffer[insert_ptr];
  225. efx_tsoh_free(tx_queue, buffer);
  226. EFX_BUG_ON_PARANOID(buffer->tsoh);
  227. EFX_BUG_ON_PARANOID(buffer->skb);
  228. EFX_BUG_ON_PARANOID(buffer->len);
  229. EFX_BUG_ON_PARANOID(!buffer->continuation);
  230. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  231. dma_len = efx_max_tx_len(efx, dma_addr);
  232. if (likely(dma_len >= len))
  233. dma_len = len;
  234. /* Fill out per descriptor fields */
  235. buffer->len = dma_len;
  236. buffer->dma_addr = dma_addr;
  237. len -= dma_len;
  238. dma_addr += dma_len;
  239. ++tx_queue->insert_count;
  240. } while (len);
  241. /* Transfer ownership of the unmapping to the final buffer */
  242. buffer->unmap_single = unmap_single;
  243. buffer->unmap_len = unmap_len;
  244. unmap_len = 0;
  245. /* Get address and size of next fragment */
  246. if (i >= skb_shinfo(skb)->nr_frags)
  247. break;
  248. fragment = &skb_shinfo(skb)->frags[i];
  249. len = fragment->size;
  250. page = fragment->page;
  251. page_offset = fragment->page_offset;
  252. i++;
  253. /* Map for DMA */
  254. unmap_single = false;
  255. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  256. PCI_DMA_TODEVICE);
  257. }
  258. /* Transfer ownership of the skb to the final buffer */
  259. buffer->skb = skb;
  260. buffer->continuation = false;
  261. /* Pass off to hardware */
  262. efx_nic_push_buffers(tx_queue);
  263. return NETDEV_TX_OK;
  264. pci_err:
  265. netif_err(efx, tx_err, efx->net_dev,
  266. " TX queue %d could not map skb with %d bytes %d "
  267. "fragments for DMA\n", tx_queue->queue, skb->len,
  268. skb_shinfo(skb)->nr_frags + 1);
  269. /* Mark the packet as transmitted, and free the SKB ourselves */
  270. dev_kfree_skb_any(skb);
  271. goto unwind;
  272. stop:
  273. rc = NETDEV_TX_BUSY;
  274. if (tx_queue->stopped == 1)
  275. efx_stop_queue(tx_queue->channel);
  276. unwind:
  277. /* Work backwards until we hit the original insert pointer value */
  278. while (tx_queue->insert_count != tx_queue->write_count) {
  279. --tx_queue->insert_count;
  280. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  281. buffer = &tx_queue->buffer[insert_ptr];
  282. efx_dequeue_buffer(tx_queue, buffer);
  283. buffer->len = 0;
  284. }
  285. /* Free the fragment we were mid-way through pushing */
  286. if (unmap_len) {
  287. if (unmap_single)
  288. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  289. PCI_DMA_TODEVICE);
  290. else
  291. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  292. PCI_DMA_TODEVICE);
  293. }
  294. return rc;
  295. }
  296. /* Remove packets from the TX queue
  297. *
  298. * This removes packets from the TX queue, up to and including the
  299. * specified index.
  300. */
  301. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  302. unsigned int index)
  303. {
  304. struct efx_nic *efx = tx_queue->efx;
  305. unsigned int stop_index, read_ptr;
  306. stop_index = (index + 1) & tx_queue->ptr_mask;
  307. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  308. while (read_ptr != stop_index) {
  309. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  310. if (unlikely(buffer->len == 0)) {
  311. netif_err(efx, tx_err, efx->net_dev,
  312. "TX queue %d spurious TX completion id %x\n",
  313. tx_queue->queue, read_ptr);
  314. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  315. return;
  316. }
  317. efx_dequeue_buffer(tx_queue, buffer);
  318. buffer->continuation = true;
  319. buffer->len = 0;
  320. ++tx_queue->read_count;
  321. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  322. }
  323. }
  324. /* Initiate a packet transmission. We use one channel per CPU
  325. * (sharing when we have more CPUs than channels). On Falcon, the TX
  326. * completion events will be directed back to the CPU that transmitted
  327. * the packet, which should be cache-efficient.
  328. *
  329. * Context: non-blocking.
  330. * Note that returning anything other than NETDEV_TX_OK will cause the
  331. * OS to free the skb.
  332. */
  333. netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
  334. struct net_device *net_dev)
  335. {
  336. struct efx_nic *efx = netdev_priv(net_dev);
  337. struct efx_tx_queue *tx_queue;
  338. if (unlikely(efx->port_inhibited))
  339. return NETDEV_TX_BUSY;
  340. tx_queue = efx_get_tx_queue(efx, skb_get_queue_mapping(skb),
  341. skb->ip_summed == CHECKSUM_PARTIAL ?
  342. EFX_TXQ_TYPE_OFFLOAD : 0);
  343. return efx_enqueue_skb(tx_queue, skb);
  344. }
  345. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  346. {
  347. unsigned fill_level;
  348. struct efx_nic *efx = tx_queue->efx;
  349. struct netdev_queue *queue;
  350. EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
  351. efx_dequeue_buffers(tx_queue, index);
  352. /* See if we need to restart the netif queue. This barrier
  353. * separates the update of read_count from the test of
  354. * stopped. */
  355. smp_mb();
  356. if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
  357. fill_level = tx_queue->insert_count - tx_queue->read_count;
  358. if (fill_level < EFX_TXQ_THRESHOLD(efx)) {
  359. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  360. /* Do this under netif_tx_lock(), to avoid racing
  361. * with efx_xmit(). */
  362. queue = netdev_get_tx_queue(
  363. efx->net_dev,
  364. tx_queue->queue / EFX_TXQ_TYPES);
  365. __netif_tx_lock(queue, smp_processor_id());
  366. if (tx_queue->stopped) {
  367. tx_queue->stopped = 0;
  368. efx_wake_queue(tx_queue->channel);
  369. }
  370. __netif_tx_unlock(queue);
  371. }
  372. }
  373. /* Check whether the hardware queue is now empty */
  374. if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
  375. tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count);
  376. if (tx_queue->read_count == tx_queue->old_write_count) {
  377. smp_mb();
  378. tx_queue->empty_read_count =
  379. tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
  380. }
  381. }
  382. }
  383. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  384. {
  385. struct efx_nic *efx = tx_queue->efx;
  386. unsigned int entries;
  387. int i, rc;
  388. /* Create the smallest power-of-two aligned ring */
  389. entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
  390. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  391. tx_queue->ptr_mask = entries - 1;
  392. netif_dbg(efx, probe, efx->net_dev,
  393. "creating TX queue %d size %#x mask %#x\n",
  394. tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
  395. /* Allocate software ring */
  396. tx_queue->buffer = kzalloc(entries * sizeof(*tx_queue->buffer),
  397. GFP_KERNEL);
  398. if (!tx_queue->buffer)
  399. return -ENOMEM;
  400. for (i = 0; i <= tx_queue->ptr_mask; ++i)
  401. tx_queue->buffer[i].continuation = true;
  402. /* Allocate hardware ring */
  403. rc = efx_nic_probe_tx(tx_queue);
  404. if (rc)
  405. goto fail;
  406. return 0;
  407. fail:
  408. kfree(tx_queue->buffer);
  409. tx_queue->buffer = NULL;
  410. return rc;
  411. }
  412. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  413. {
  414. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  415. "initialising TX queue %d\n", tx_queue->queue);
  416. tx_queue->insert_count = 0;
  417. tx_queue->write_count = 0;
  418. tx_queue->old_write_count = 0;
  419. tx_queue->read_count = 0;
  420. tx_queue->old_read_count = 0;
  421. tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
  422. BUG_ON(tx_queue->stopped);
  423. /* Set up TX descriptor ring */
  424. efx_nic_init_tx(tx_queue);
  425. }
  426. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  427. {
  428. struct efx_tx_buffer *buffer;
  429. if (!tx_queue->buffer)
  430. return;
  431. /* Free any buffers left in the ring */
  432. while (tx_queue->read_count != tx_queue->write_count) {
  433. buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
  434. efx_dequeue_buffer(tx_queue, buffer);
  435. buffer->continuation = true;
  436. buffer->len = 0;
  437. ++tx_queue->read_count;
  438. }
  439. }
  440. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  441. {
  442. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  443. "shutting down TX queue %d\n", tx_queue->queue);
  444. /* Flush TX queue, remove descriptor ring */
  445. efx_nic_fini_tx(tx_queue);
  446. efx_release_tx_buffers(tx_queue);
  447. /* Free up TSO header cache */
  448. efx_fini_tso(tx_queue);
  449. /* Release queue's stop on port, if any */
  450. if (tx_queue->stopped) {
  451. tx_queue->stopped = 0;
  452. efx_wake_queue(tx_queue->channel);
  453. }
  454. }
  455. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  456. {
  457. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  458. "destroying TX queue %d\n", tx_queue->queue);
  459. efx_nic_remove_tx(tx_queue);
  460. kfree(tx_queue->buffer);
  461. tx_queue->buffer = NULL;
  462. }
  463. /* Efx TCP segmentation acceleration.
  464. *
  465. * Why? Because by doing it here in the driver we can go significantly
  466. * faster than the GSO.
  467. *
  468. * Requires TX checksum offload support.
  469. */
  470. /* Number of bytes inserted at the start of a TSO header buffer,
  471. * similar to NET_IP_ALIGN.
  472. */
  473. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  474. #define TSOH_OFFSET 0
  475. #else
  476. #define TSOH_OFFSET NET_IP_ALIGN
  477. #endif
  478. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  479. /* Total size of struct efx_tso_header, buffer and padding */
  480. #define TSOH_SIZE(hdr_len) \
  481. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  482. /* Size of blocks on free list. Larger blocks must be allocated from
  483. * the heap.
  484. */
  485. #define TSOH_STD_SIZE 128
  486. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  487. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  488. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  489. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  490. #define SKB_IPV6_OFF(skb) PTR_DIFF(ipv6_hdr(skb), (skb)->data)
  491. /**
  492. * struct tso_state - TSO state for an SKB
  493. * @out_len: Remaining length in current segment
  494. * @seqnum: Current sequence number
  495. * @ipv4_id: Current IPv4 ID, host endian
  496. * @packet_space: Remaining space in current packet
  497. * @dma_addr: DMA address of current position
  498. * @in_len: Remaining length in current SKB fragment
  499. * @unmap_len: Length of SKB fragment
  500. * @unmap_addr: DMA address of SKB fragment
  501. * @unmap_single: DMA single vs page mapping flag
  502. * @protocol: Network protocol (after any VLAN header)
  503. * @header_len: Number of bytes of header
  504. * @full_packet_size: Number of bytes to put in each outgoing segment
  505. *
  506. * The state used during segmentation. It is put into this data structure
  507. * just to make it easy to pass into inline functions.
  508. */
  509. struct tso_state {
  510. /* Output position */
  511. unsigned out_len;
  512. unsigned seqnum;
  513. unsigned ipv4_id;
  514. unsigned packet_space;
  515. /* Input position */
  516. dma_addr_t dma_addr;
  517. unsigned in_len;
  518. unsigned unmap_len;
  519. dma_addr_t unmap_addr;
  520. bool unmap_single;
  521. __be16 protocol;
  522. unsigned header_len;
  523. int full_packet_size;
  524. };
  525. /*
  526. * Verify that our various assumptions about sk_buffs and the conditions
  527. * under which TSO will be attempted hold true. Return the protocol number.
  528. */
  529. static __be16 efx_tso_check_protocol(struct sk_buff *skb)
  530. {
  531. __be16 protocol = skb->protocol;
  532. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  533. protocol);
  534. if (protocol == htons(ETH_P_8021Q)) {
  535. /* Find the encapsulated protocol; reset network header
  536. * and transport header based on that. */
  537. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  538. protocol = veh->h_vlan_encapsulated_proto;
  539. skb_set_network_header(skb, sizeof(*veh));
  540. if (protocol == htons(ETH_P_IP))
  541. skb_set_transport_header(skb, sizeof(*veh) +
  542. 4 * ip_hdr(skb)->ihl);
  543. else if (protocol == htons(ETH_P_IPV6))
  544. skb_set_transport_header(skb, sizeof(*veh) +
  545. sizeof(struct ipv6hdr));
  546. }
  547. if (protocol == htons(ETH_P_IP)) {
  548. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  549. } else {
  550. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
  551. EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
  552. }
  553. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  554. + (tcp_hdr(skb)->doff << 2u)) >
  555. skb_headlen(skb));
  556. return protocol;
  557. }
  558. /*
  559. * Allocate a page worth of efx_tso_header structures, and string them
  560. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  561. */
  562. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  563. {
  564. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  565. struct efx_tso_header *tsoh;
  566. dma_addr_t dma_addr;
  567. u8 *base_kva, *kva;
  568. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  569. if (base_kva == NULL) {
  570. netif_err(tx_queue->efx, tx_err, tx_queue->efx->net_dev,
  571. "Unable to allocate page for TSO headers\n");
  572. return -ENOMEM;
  573. }
  574. /* pci_alloc_consistent() allocates pages. */
  575. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  576. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  577. tsoh = (struct efx_tso_header *)kva;
  578. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  579. tsoh->next = tx_queue->tso_headers_free;
  580. tx_queue->tso_headers_free = tsoh;
  581. }
  582. return 0;
  583. }
  584. /* Free up a TSO header, and all others in the same page. */
  585. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  586. struct efx_tso_header *tsoh,
  587. struct pci_dev *pci_dev)
  588. {
  589. struct efx_tso_header **p;
  590. unsigned long base_kva;
  591. dma_addr_t base_dma;
  592. base_kva = (unsigned long)tsoh & PAGE_MASK;
  593. base_dma = tsoh->dma_addr & PAGE_MASK;
  594. p = &tx_queue->tso_headers_free;
  595. while (*p != NULL) {
  596. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  597. *p = (*p)->next;
  598. else
  599. p = &(*p)->next;
  600. }
  601. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  602. }
  603. static struct efx_tso_header *
  604. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  605. {
  606. struct efx_tso_header *tsoh;
  607. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  608. if (unlikely(!tsoh))
  609. return NULL;
  610. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  611. TSOH_BUFFER(tsoh), header_len,
  612. PCI_DMA_TODEVICE);
  613. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  614. tsoh->dma_addr))) {
  615. kfree(tsoh);
  616. return NULL;
  617. }
  618. tsoh->unmap_len = header_len;
  619. return tsoh;
  620. }
  621. static void
  622. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  623. {
  624. pci_unmap_single(tx_queue->efx->pci_dev,
  625. tsoh->dma_addr, tsoh->unmap_len,
  626. PCI_DMA_TODEVICE);
  627. kfree(tsoh);
  628. }
  629. /**
  630. * efx_tx_queue_insert - push descriptors onto the TX queue
  631. * @tx_queue: Efx TX queue
  632. * @dma_addr: DMA address of fragment
  633. * @len: Length of fragment
  634. * @final_buffer: The final buffer inserted into the queue
  635. *
  636. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  637. * @tx_queue full.
  638. */
  639. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  640. dma_addr_t dma_addr, unsigned len,
  641. struct efx_tx_buffer **final_buffer)
  642. {
  643. struct efx_tx_buffer *buffer;
  644. struct efx_nic *efx = tx_queue->efx;
  645. unsigned dma_len, fill_level, insert_ptr;
  646. int q_space;
  647. EFX_BUG_ON_PARANOID(len <= 0);
  648. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  649. /* -1 as there is no way to represent all descriptors used */
  650. q_space = efx->txq_entries - 1 - fill_level;
  651. while (1) {
  652. if (unlikely(q_space-- <= 0)) {
  653. /* It might be that completions have happened
  654. * since the xmit path last checked. Update
  655. * the xmit path's copy of read_count.
  656. */
  657. ++tx_queue->stopped;
  658. /* This memory barrier protects the change of
  659. * stopped from the access of read_count. */
  660. smp_mb();
  661. tx_queue->old_read_count =
  662. ACCESS_ONCE(tx_queue->read_count);
  663. fill_level = (tx_queue->insert_count
  664. - tx_queue->old_read_count);
  665. q_space = efx->txq_entries - 1 - fill_level;
  666. if (unlikely(q_space-- <= 0)) {
  667. *final_buffer = NULL;
  668. return 1;
  669. }
  670. smp_mb();
  671. --tx_queue->stopped;
  672. }
  673. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  674. buffer = &tx_queue->buffer[insert_ptr];
  675. ++tx_queue->insert_count;
  676. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  677. tx_queue->read_count >=
  678. efx->txq_entries);
  679. efx_tsoh_free(tx_queue, buffer);
  680. EFX_BUG_ON_PARANOID(buffer->len);
  681. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  682. EFX_BUG_ON_PARANOID(buffer->skb);
  683. EFX_BUG_ON_PARANOID(!buffer->continuation);
  684. EFX_BUG_ON_PARANOID(buffer->tsoh);
  685. buffer->dma_addr = dma_addr;
  686. dma_len = efx_max_tx_len(efx, dma_addr);
  687. /* If there is enough space to send then do so */
  688. if (dma_len >= len)
  689. break;
  690. buffer->len = dma_len; /* Don't set the other members */
  691. dma_addr += dma_len;
  692. len -= dma_len;
  693. }
  694. EFX_BUG_ON_PARANOID(!len);
  695. buffer->len = len;
  696. *final_buffer = buffer;
  697. return 0;
  698. }
  699. /*
  700. * Put a TSO header into the TX queue.
  701. *
  702. * This is special-cased because we know that it is small enough to fit in
  703. * a single fragment, and we know it doesn't cross a page boundary. It
  704. * also allows us to not worry about end-of-packet etc.
  705. */
  706. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  707. struct efx_tso_header *tsoh, unsigned len)
  708. {
  709. struct efx_tx_buffer *buffer;
  710. buffer = &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask];
  711. efx_tsoh_free(tx_queue, buffer);
  712. EFX_BUG_ON_PARANOID(buffer->len);
  713. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  714. EFX_BUG_ON_PARANOID(buffer->skb);
  715. EFX_BUG_ON_PARANOID(!buffer->continuation);
  716. EFX_BUG_ON_PARANOID(buffer->tsoh);
  717. buffer->len = len;
  718. buffer->dma_addr = tsoh->dma_addr;
  719. buffer->tsoh = tsoh;
  720. ++tx_queue->insert_count;
  721. }
  722. /* Remove descriptors put into a tx_queue. */
  723. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  724. {
  725. struct efx_tx_buffer *buffer;
  726. dma_addr_t unmap_addr;
  727. /* Work backwards until we hit the original insert pointer value */
  728. while (tx_queue->insert_count != tx_queue->write_count) {
  729. --tx_queue->insert_count;
  730. buffer = &tx_queue->buffer[tx_queue->insert_count &
  731. tx_queue->ptr_mask];
  732. efx_tsoh_free(tx_queue, buffer);
  733. EFX_BUG_ON_PARANOID(buffer->skb);
  734. if (buffer->unmap_len) {
  735. unmap_addr = (buffer->dma_addr + buffer->len -
  736. buffer->unmap_len);
  737. if (buffer->unmap_single)
  738. pci_unmap_single(tx_queue->efx->pci_dev,
  739. unmap_addr, buffer->unmap_len,
  740. PCI_DMA_TODEVICE);
  741. else
  742. pci_unmap_page(tx_queue->efx->pci_dev,
  743. unmap_addr, buffer->unmap_len,
  744. PCI_DMA_TODEVICE);
  745. buffer->unmap_len = 0;
  746. }
  747. buffer->len = 0;
  748. buffer->continuation = true;
  749. }
  750. }
  751. /* Parse the SKB header and initialise state. */
  752. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  753. {
  754. /* All ethernet/IP/TCP headers combined size is TCP header size
  755. * plus offset of TCP header relative to start of packet.
  756. */
  757. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  758. + PTR_DIFF(tcp_hdr(skb), skb->data));
  759. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  760. if (st->protocol == htons(ETH_P_IP))
  761. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  762. else
  763. st->ipv4_id = 0;
  764. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  765. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  766. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  767. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  768. st->packet_space = st->full_packet_size;
  769. st->out_len = skb->len - st->header_len;
  770. st->unmap_len = 0;
  771. st->unmap_single = false;
  772. }
  773. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  774. skb_frag_t *frag)
  775. {
  776. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  777. frag->page_offset, frag->size,
  778. PCI_DMA_TODEVICE);
  779. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  780. st->unmap_single = false;
  781. st->unmap_len = frag->size;
  782. st->in_len = frag->size;
  783. st->dma_addr = st->unmap_addr;
  784. return 0;
  785. }
  786. return -ENOMEM;
  787. }
  788. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  789. const struct sk_buff *skb)
  790. {
  791. int hl = st->header_len;
  792. int len = skb_headlen(skb) - hl;
  793. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  794. len, PCI_DMA_TODEVICE);
  795. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  796. st->unmap_single = true;
  797. st->unmap_len = len;
  798. st->in_len = len;
  799. st->dma_addr = st->unmap_addr;
  800. return 0;
  801. }
  802. return -ENOMEM;
  803. }
  804. /**
  805. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  806. * @tx_queue: Efx TX queue
  807. * @skb: Socket buffer
  808. * @st: TSO state
  809. *
  810. * Form descriptors for the current fragment, until we reach the end
  811. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  812. * space in @tx_queue.
  813. */
  814. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  815. const struct sk_buff *skb,
  816. struct tso_state *st)
  817. {
  818. struct efx_tx_buffer *buffer;
  819. int n, end_of_packet, rc;
  820. if (st->in_len == 0)
  821. return 0;
  822. if (st->packet_space == 0)
  823. return 0;
  824. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  825. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  826. n = min(st->in_len, st->packet_space);
  827. st->packet_space -= n;
  828. st->out_len -= n;
  829. st->in_len -= n;
  830. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  831. if (likely(rc == 0)) {
  832. if (st->out_len == 0)
  833. /* Transfer ownership of the skb */
  834. buffer->skb = skb;
  835. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  836. buffer->continuation = !end_of_packet;
  837. if (st->in_len == 0) {
  838. /* Transfer ownership of the pci mapping */
  839. buffer->unmap_len = st->unmap_len;
  840. buffer->unmap_single = st->unmap_single;
  841. st->unmap_len = 0;
  842. }
  843. }
  844. st->dma_addr += n;
  845. return rc;
  846. }
  847. /**
  848. * tso_start_new_packet - generate a new header and prepare for the new packet
  849. * @tx_queue: Efx TX queue
  850. * @skb: Socket buffer
  851. * @st: TSO state
  852. *
  853. * Generate a new header and prepare for the new packet. Return 0 on
  854. * success, or -1 if failed to alloc header.
  855. */
  856. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  857. const struct sk_buff *skb,
  858. struct tso_state *st)
  859. {
  860. struct efx_tso_header *tsoh;
  861. struct tcphdr *tsoh_th;
  862. unsigned ip_length;
  863. u8 *header;
  864. /* Allocate a DMA-mapped header buffer. */
  865. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  866. if (tx_queue->tso_headers_free == NULL) {
  867. if (efx_tsoh_block_alloc(tx_queue))
  868. return -1;
  869. }
  870. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  871. tsoh = tx_queue->tso_headers_free;
  872. tx_queue->tso_headers_free = tsoh->next;
  873. tsoh->unmap_len = 0;
  874. } else {
  875. tx_queue->tso_long_headers++;
  876. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  877. if (unlikely(!tsoh))
  878. return -1;
  879. }
  880. header = TSOH_BUFFER(tsoh);
  881. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  882. /* Copy and update the headers. */
  883. memcpy(header, skb->data, st->header_len);
  884. tsoh_th->seq = htonl(st->seqnum);
  885. st->seqnum += skb_shinfo(skb)->gso_size;
  886. if (st->out_len > skb_shinfo(skb)->gso_size) {
  887. /* This packet will not finish the TSO burst. */
  888. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  889. tsoh_th->fin = 0;
  890. tsoh_th->psh = 0;
  891. } else {
  892. /* This packet will be the last in the TSO burst. */
  893. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  894. tsoh_th->fin = tcp_hdr(skb)->fin;
  895. tsoh_th->psh = tcp_hdr(skb)->psh;
  896. }
  897. if (st->protocol == htons(ETH_P_IP)) {
  898. struct iphdr *tsoh_iph =
  899. (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  900. tsoh_iph->tot_len = htons(ip_length);
  901. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  902. tsoh_iph->id = htons(st->ipv4_id);
  903. st->ipv4_id++;
  904. } else {
  905. struct ipv6hdr *tsoh_iph =
  906. (struct ipv6hdr *)(header + SKB_IPV6_OFF(skb));
  907. tsoh_iph->payload_len = htons(ip_length - sizeof(*tsoh_iph));
  908. }
  909. st->packet_space = skb_shinfo(skb)->gso_size;
  910. ++tx_queue->tso_packets;
  911. /* Form a descriptor for this header. */
  912. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  913. return 0;
  914. }
  915. /**
  916. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  917. * @tx_queue: Efx TX queue
  918. * @skb: Socket buffer
  919. *
  920. * Context: You must hold netif_tx_lock() to call this function.
  921. *
  922. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  923. * @skb was not enqueued. In all cases @skb is consumed. Return
  924. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  925. */
  926. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  927. struct sk_buff *skb)
  928. {
  929. struct efx_nic *efx = tx_queue->efx;
  930. int frag_i, rc, rc2 = NETDEV_TX_OK;
  931. struct tso_state state;
  932. /* Find the packet protocol and sanity-check it */
  933. state.protocol = efx_tso_check_protocol(skb);
  934. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  935. tso_start(&state, skb);
  936. /* Assume that skb header area contains exactly the headers, and
  937. * all payload is in the frag list.
  938. */
  939. if (skb_headlen(skb) == state.header_len) {
  940. /* Grab the first payload fragment. */
  941. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  942. frag_i = 0;
  943. rc = tso_get_fragment(&state, efx,
  944. skb_shinfo(skb)->frags + frag_i);
  945. if (rc)
  946. goto mem_err;
  947. } else {
  948. rc = tso_get_head_fragment(&state, efx, skb);
  949. if (rc)
  950. goto mem_err;
  951. frag_i = -1;
  952. }
  953. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  954. goto mem_err;
  955. while (1) {
  956. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  957. if (unlikely(rc))
  958. goto stop;
  959. /* Move onto the next fragment? */
  960. if (state.in_len == 0) {
  961. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  962. /* End of payload reached. */
  963. break;
  964. rc = tso_get_fragment(&state, efx,
  965. skb_shinfo(skb)->frags + frag_i);
  966. if (rc)
  967. goto mem_err;
  968. }
  969. /* Start at new packet? */
  970. if (state.packet_space == 0 &&
  971. tso_start_new_packet(tx_queue, skb, &state) < 0)
  972. goto mem_err;
  973. }
  974. /* Pass off to hardware */
  975. efx_nic_push_buffers(tx_queue);
  976. tx_queue->tso_bursts++;
  977. return NETDEV_TX_OK;
  978. mem_err:
  979. netif_err(efx, tx_err, efx->net_dev,
  980. "Out of memory for TSO headers, or PCI mapping error\n");
  981. dev_kfree_skb_any(skb);
  982. goto unwind;
  983. stop:
  984. rc2 = NETDEV_TX_BUSY;
  985. /* Stop the queue if it wasn't stopped before. */
  986. if (tx_queue->stopped == 1)
  987. efx_stop_queue(tx_queue->channel);
  988. unwind:
  989. /* Free the DMA mapping we were in the process of writing out */
  990. if (state.unmap_len) {
  991. if (state.unmap_single)
  992. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  993. state.unmap_len, PCI_DMA_TODEVICE);
  994. else
  995. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  996. state.unmap_len, PCI_DMA_TODEVICE);
  997. }
  998. efx_enqueue_unwind(tx_queue);
  999. return rc2;
  1000. }
  1001. /*
  1002. * Free up all TSO datastructures associated with tx_queue. This
  1003. * routine should be called only once the tx_queue is both empty and
  1004. * will no longer be used.
  1005. */
  1006. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  1007. {
  1008. unsigned i;
  1009. if (tx_queue->buffer) {
  1010. for (i = 0; i <= tx_queue->ptr_mask; ++i)
  1011. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  1012. }
  1013. while (tx_queue->tso_headers_free != NULL)
  1014. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  1015. tx_queue->efx->pci_dev);
  1016. }