tegra20-ventana.dts 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591
  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra2 Ventana evaluation board";
  5. compatible = "nvidia,ventana", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata";
  15. nvidia,function = "ide";
  16. };
  17. atb {
  18. nvidia,pins = "atb", "gma", "gme";
  19. nvidia,function = "sdio4";
  20. };
  21. atc {
  22. nvidia,pins = "atc";
  23. nvidia,function = "nand";
  24. };
  25. atd {
  26. nvidia,pins = "atd", "ate", "gmb", "spia",
  27. "spib", "spic";
  28. nvidia,function = "gmi";
  29. };
  30. cdev1 {
  31. nvidia,pins = "cdev1";
  32. nvidia,function = "plla_out";
  33. };
  34. cdev2 {
  35. nvidia,pins = "cdev2";
  36. nvidia,function = "pllp_out4";
  37. };
  38. crtp {
  39. nvidia,pins = "crtp", "lm1";
  40. nvidia,function = "crt";
  41. };
  42. csus {
  43. nvidia,pins = "csus";
  44. nvidia,function = "vi_sensor_clk";
  45. };
  46. dap1 {
  47. nvidia,pins = "dap1";
  48. nvidia,function = "dap1";
  49. };
  50. dap2 {
  51. nvidia,pins = "dap2";
  52. nvidia,function = "dap2";
  53. };
  54. dap3 {
  55. nvidia,pins = "dap3";
  56. nvidia,function = "dap3";
  57. };
  58. dap4 {
  59. nvidia,pins = "dap4";
  60. nvidia,function = "dap4";
  61. };
  62. dta {
  63. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  64. nvidia,function = "vi";
  65. };
  66. dtf {
  67. nvidia,pins = "dtf";
  68. nvidia,function = "i2c3";
  69. };
  70. gmc {
  71. nvidia,pins = "gmc";
  72. nvidia,function = "uartd";
  73. };
  74. gmd {
  75. nvidia,pins = "gmd";
  76. nvidia,function = "sflash";
  77. };
  78. gpu {
  79. nvidia,pins = "gpu";
  80. nvidia,function = "pwm";
  81. };
  82. gpu7 {
  83. nvidia,pins = "gpu7";
  84. nvidia,function = "rtck";
  85. };
  86. gpv {
  87. nvidia,pins = "gpv", "slxa", "slxk";
  88. nvidia,function = "pcie";
  89. };
  90. hdint {
  91. nvidia,pins = "hdint";
  92. nvidia,function = "hdmi";
  93. };
  94. i2cp {
  95. nvidia,pins = "i2cp";
  96. nvidia,function = "i2cp";
  97. };
  98. irrx {
  99. nvidia,pins = "irrx", "irtx";
  100. nvidia,function = "uartb";
  101. };
  102. kbca {
  103. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  104. "kbce", "kbcf";
  105. nvidia,function = "kbc";
  106. };
  107. lcsn {
  108. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  109. "lsdi", "lvp0";
  110. nvidia,function = "rsvd4";
  111. };
  112. ld0 {
  113. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  114. "ld5", "ld6", "ld7", "ld8", "ld9",
  115. "ld10", "ld11", "ld12", "ld13", "ld14",
  116. "ld15", "ld16", "ld17", "ldi", "lhp0",
  117. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  118. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  119. "lspi", "lvp1", "lvs";
  120. nvidia,function = "displaya";
  121. };
  122. owc {
  123. nvidia,pins = "owc", "spdi", "spdo", "uac";
  124. nvidia,function = "rsvd2";
  125. };
  126. pmc {
  127. nvidia,pins = "pmc";
  128. nvidia,function = "pwr_on";
  129. };
  130. rm {
  131. nvidia,pins = "rm";
  132. nvidia,function = "i2c1";
  133. };
  134. sdb {
  135. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  136. nvidia,function = "sdio3";
  137. };
  138. sdio1 {
  139. nvidia,pins = "sdio1";
  140. nvidia,function = "sdio1";
  141. };
  142. slxd {
  143. nvidia,pins = "slxd";
  144. nvidia,function = "spdif";
  145. };
  146. spid {
  147. nvidia,pins = "spid", "spie", "spif";
  148. nvidia,function = "spi1";
  149. };
  150. spig {
  151. nvidia,pins = "spig", "spih";
  152. nvidia,function = "spi2_alt";
  153. };
  154. uaa {
  155. nvidia,pins = "uaa", "uab", "uda";
  156. nvidia,function = "ulpi";
  157. };
  158. uad {
  159. nvidia,pins = "uad";
  160. nvidia,function = "irda";
  161. };
  162. uca {
  163. nvidia,pins = "uca", "ucb";
  164. nvidia,function = "uartc";
  165. };
  166. conf_ata {
  167. nvidia,pins = "ata", "atb", "atc", "atd",
  168. "cdev1", "cdev2", "dap1", "dap2",
  169. "dap4", "ddc", "dtf", "gma", "gmc",
  170. "gme", "gpu", "gpu7", "i2cp", "irrx",
  171. "irtx", "pta", "rm", "sdc", "sdd",
  172. "slxc", "slxd", "slxk", "spdi", "spdo",
  173. "uac", "uad", "uca", "ucb", "uda";
  174. nvidia,pull = <0>;
  175. nvidia,tristate = <0>;
  176. };
  177. conf_ate {
  178. nvidia,pins = "ate", "csus", "dap3", "gmd",
  179. "gpv", "owc", "spia", "spib", "spic",
  180. "spid", "spie", "spig";
  181. nvidia,pull = <0>;
  182. nvidia,tristate = <1>;
  183. };
  184. conf_ck32 {
  185. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  186. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  187. nvidia,pull = <0>;
  188. };
  189. conf_crtp {
  190. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  191. nvidia,pull = <2>;
  192. nvidia,tristate = <1>;
  193. };
  194. conf_dta {
  195. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  196. nvidia,pull = <1>;
  197. nvidia,tristate = <0>;
  198. };
  199. conf_dte {
  200. nvidia,pins = "dte", "spif";
  201. nvidia,pull = <1>;
  202. nvidia,tristate = <1>;
  203. };
  204. conf_hdint {
  205. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  206. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  207. nvidia,tristate = <1>;
  208. };
  209. conf_kbca {
  210. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  211. "kbce", "kbcf", "sdio1", "uaa", "uab";
  212. nvidia,pull = <2>;
  213. nvidia,tristate = <0>;
  214. };
  215. conf_lc {
  216. nvidia,pins = "lc", "ls";
  217. nvidia,pull = <2>;
  218. };
  219. conf_ld0 {
  220. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  221. "ld5", "ld6", "ld7", "ld8", "ld9",
  222. "ld10", "ld11", "ld12", "ld13", "ld14",
  223. "ld15", "ld16", "ld17", "ldi", "lhp0",
  224. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  225. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  226. "lvp1", "lvs", "pmc", "sdb";
  227. nvidia,tristate = <0>;
  228. };
  229. conf_ld17_0 {
  230. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  231. "ld23_22";
  232. nvidia,pull = <1>;
  233. };
  234. drive_sdio1 {
  235. nvidia,pins = "drive_sdio1";
  236. nvidia,high-speed-mode = <0>;
  237. nvidia,schmitt = <1>;
  238. nvidia,low-power-mode = <3>;
  239. nvidia,pull-down-strength = <31>;
  240. nvidia,pull-up-strength = <31>;
  241. nvidia,slew-rate-rising = <3>;
  242. nvidia,slew-rate-falling = <3>;
  243. };
  244. };
  245. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  246. ddc {
  247. nvidia,pins = "ddc";
  248. nvidia,function = "i2c2";
  249. };
  250. pta {
  251. nvidia,pins = "pta";
  252. nvidia,function = "rsvd4";
  253. };
  254. };
  255. state_i2cmux_pta: pinmux_i2cmux_pta {
  256. ddc {
  257. nvidia,pins = "ddc";
  258. nvidia,function = "rsvd4";
  259. };
  260. pta {
  261. nvidia,pins = "pta";
  262. nvidia,function = "i2c2";
  263. };
  264. };
  265. state_i2cmux_idle: pinmux_i2cmux_idle {
  266. ddc {
  267. nvidia,pins = "ddc";
  268. nvidia,function = "rsvd4";
  269. };
  270. pta {
  271. nvidia,pins = "pta";
  272. nvidia,function = "rsvd4";
  273. };
  274. };
  275. };
  276. i2s@70002800 {
  277. status = "okay";
  278. };
  279. serial@70006300 {
  280. status = "okay";
  281. clock-frequency = <216000000>;
  282. };
  283. i2c@7000c000 {
  284. status = "okay";
  285. clock-frequency = <400000>;
  286. wm8903: wm8903@1a {
  287. compatible = "wlf,wm8903";
  288. reg = <0x1a>;
  289. interrupt-parent = <&gpio>;
  290. interrupts = <187 0x04>;
  291. gpio-controller;
  292. #gpio-cells = <2>;
  293. micdet-cfg = <0>;
  294. micdet-delay = <100>;
  295. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  296. };
  297. /* ALS and proximity sensor */
  298. isl29018@44 {
  299. compatible = "isil,isl29018";
  300. reg = <0x44>;
  301. interrupt-parent = <&gpio>;
  302. interrupts = <202 0x04>; /*gpio PZ2 */
  303. };
  304. };
  305. i2c@7000c400 {
  306. status = "okay";
  307. clock-frequency = <400000>;
  308. };
  309. i2cmux {
  310. compatible = "i2c-mux-pinctrl";
  311. #address-cells = <1>;
  312. #size-cells = <0>;
  313. i2c-parent = <&{/i2c@7000c400}>;
  314. pinctrl-names = "ddc", "pta", "idle";
  315. pinctrl-0 = <&state_i2cmux_ddc>;
  316. pinctrl-1 = <&state_i2cmux_pta>;
  317. pinctrl-2 = <&state_i2cmux_idle>;
  318. i2c@0 {
  319. reg = <0>;
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. };
  323. i2c@1 {
  324. reg = <1>;
  325. #address-cells = <1>;
  326. #size-cells = <0>;
  327. };
  328. };
  329. i2c@7000c500 {
  330. status = "okay";
  331. clock-frequency = <400000>;
  332. };
  333. i2c@7000d000 {
  334. status = "okay";
  335. clock-frequency = <400000>;
  336. pmic: tps6586x@34 {
  337. compatible = "ti,tps6586x";
  338. reg = <0x34>;
  339. interrupts = <0 86 0x4>;
  340. ti,system-power-controller;
  341. #gpio-cells = <2>;
  342. gpio-controller;
  343. sys-supply = <&vdd_5v0_reg>;
  344. vin-sm0-supply = <&sys_reg>;
  345. vin-sm1-supply = <&sys_reg>;
  346. vin-sm2-supply = <&sys_reg>;
  347. vinldo01-supply = <&sm2_reg>;
  348. vinldo23-supply = <&sm2_reg>;
  349. vinldo4-supply = <&sm2_reg>;
  350. vinldo678-supply = <&sm2_reg>;
  351. vinldo9-supply = <&sm2_reg>;
  352. regulators {
  353. sys_reg: sys {
  354. regulator-name = "vdd_sys";
  355. regulator-always-on;
  356. };
  357. sm0 {
  358. regulator-name = "vdd_sm0,vdd_core";
  359. regulator-min-microvolt = <1200000>;
  360. regulator-max-microvolt = <1200000>;
  361. regulator-always-on;
  362. };
  363. sm1 {
  364. regulator-name = "vdd_sm1,vdd_cpu";
  365. regulator-min-microvolt = <1000000>;
  366. regulator-max-microvolt = <1000000>;
  367. regulator-always-on;
  368. };
  369. sm2_reg: sm2 {
  370. regulator-name = "vdd_sm2,vin_ldo*";
  371. regulator-min-microvolt = <3700000>;
  372. regulator-max-microvolt = <3700000>;
  373. regulator-always-on;
  374. };
  375. /* LDO0 is not connected to anything */
  376. ldo1 {
  377. regulator-name = "vdd_ldo1,avdd_pll*";
  378. regulator-min-microvolt = <1100000>;
  379. regulator-max-microvolt = <1100000>;
  380. regulator-always-on;
  381. };
  382. ldo2 {
  383. regulator-name = "vdd_ldo2,vdd_rtc";
  384. regulator-min-microvolt = <1200000>;
  385. regulator-max-microvolt = <1200000>;
  386. };
  387. ldo3 {
  388. regulator-name = "vdd_ldo3,avdd_usb*";
  389. regulator-min-microvolt = <3300000>;
  390. regulator-max-microvolt = <3300000>;
  391. regulator-always-on;
  392. };
  393. ldo4 {
  394. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  395. regulator-min-microvolt = <1800000>;
  396. regulator-max-microvolt = <1800000>;
  397. regulator-always-on;
  398. };
  399. ldo5 {
  400. regulator-name = "vdd_ldo5,vcore_mmc";
  401. regulator-min-microvolt = <2850000>;
  402. regulator-max-microvolt = <2850000>;
  403. regulator-always-on;
  404. };
  405. ldo6 {
  406. regulator-name = "vdd_ldo6,avdd_vdac";
  407. regulator-min-microvolt = <1800000>;
  408. regulator-max-microvolt = <1800000>;
  409. };
  410. ldo7 {
  411. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  412. regulator-min-microvolt = <3300000>;
  413. regulator-max-microvolt = <3300000>;
  414. };
  415. ldo8 {
  416. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  417. regulator-min-microvolt = <1800000>;
  418. regulator-max-microvolt = <1800000>;
  419. };
  420. ldo9 {
  421. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  422. regulator-min-microvolt = <2850000>;
  423. regulator-max-microvolt = <2850000>;
  424. regulator-always-on;
  425. };
  426. ldo_rtc {
  427. regulator-name = "vdd_rtc_out,vdd_cell";
  428. regulator-min-microvolt = <3300000>;
  429. regulator-max-microvolt = <3300000>;
  430. regulator-always-on;
  431. };
  432. };
  433. };
  434. };
  435. pmc {
  436. nvidia,invert-interrupt;
  437. };
  438. usb@c5000000 {
  439. status = "okay";
  440. };
  441. usb@c5004000 {
  442. status = "okay";
  443. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  444. };
  445. usb@c5008000 {
  446. status = "okay";
  447. };
  448. sdhci@c8000000 {
  449. status = "okay";
  450. power-gpios = <&gpio 86 0>; /* gpio PK6 */
  451. bus-width = <4>;
  452. };
  453. sdhci@c8000400 {
  454. status = "okay";
  455. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  456. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  457. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  458. bus-width = <4>;
  459. };
  460. sdhci@c8000600 {
  461. status = "okay";
  462. bus-width = <8>;
  463. };
  464. regulators {
  465. compatible = "simple-bus";
  466. #address-cells = <1>;
  467. #size-cells = <0>;
  468. vdd_5v0_reg: regulator@0 {
  469. compatible = "regulator-fixed";
  470. reg = <0>;
  471. regulator-name = "vdd_5v0";
  472. regulator-min-microvolt = <5000000>;
  473. regulator-max-microvolt = <5000000>;
  474. regulator-always-on;
  475. };
  476. regulator@1 {
  477. compatible = "regulator-fixed";
  478. reg = <1>;
  479. regulator-name = "vdd_1v5";
  480. regulator-min-microvolt = <1500000>;
  481. regulator-max-microvolt = <1500000>;
  482. gpio = <&pmic 0 0>;
  483. };
  484. regulator@2 {
  485. compatible = "regulator-fixed";
  486. reg = <2>;
  487. regulator-name = "vdd_1v2";
  488. regulator-min-microvolt = <1200000>;
  489. regulator-max-microvolt = <1200000>;
  490. gpio = <&pmic 1 0>;
  491. enable-active-high;
  492. };
  493. regulator@3 {
  494. compatible = "regulator-fixed";
  495. reg = <3>;
  496. regulator-name = "vdd_pnl";
  497. regulator-min-microvolt = <2800000>;
  498. regulator-max-microvolt = <2800000>;
  499. gpio = <&gpio 22 0>; /* gpio PC6 */
  500. enable-active-high;
  501. };
  502. regulator@4 {
  503. compatible = "regulator-fixed";
  504. reg = <4>;
  505. regulator-name = "vdd_bl";
  506. regulator-min-microvolt = <2800000>;
  507. regulator-max-microvolt = <2800000>;
  508. gpio = <&gpio 176 0>; /* gpio PW0 */
  509. enable-active-high;
  510. };
  511. };
  512. sound {
  513. compatible = "nvidia,tegra-audio-wm8903-ventana",
  514. "nvidia,tegra-audio-wm8903";
  515. nvidia,model = "NVIDIA Tegra Ventana";
  516. nvidia,audio-routing =
  517. "Headphone Jack", "HPOUTR",
  518. "Headphone Jack", "HPOUTL",
  519. "Int Spk", "ROP",
  520. "Int Spk", "RON",
  521. "Int Spk", "LOP",
  522. "Int Spk", "LON",
  523. "Mic Jack", "MICBIAS",
  524. "IN1L", "Mic Jack";
  525. nvidia,i2s-controller = <&tegra_i2s1>;
  526. nvidia,audio-codec = <&wm8903>;
  527. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  528. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  529. nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
  530. nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
  531. };
  532. };