aaci.c 27 KB

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  1. /*
  2. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Documentation: ARM DDI 0173B
  11. */
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/ioport.h>
  16. #include <linux/device.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/err.h>
  20. #include <linux/amba/bus.h>
  21. #include <linux/io.h>
  22. #include <sound/core.h>
  23. #include <sound/initval.h>
  24. #include <sound/ac97_codec.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include "aaci.h"
  28. #include "devdma.h"
  29. #define DRIVER_NAME "aaci-pl041"
  30. /*
  31. * PM support is not complete. Turn it off.
  32. */
  33. #undef CONFIG_PM
  34. static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
  35. {
  36. u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  37. /*
  38. * Ensure that the slot 1/2 RX registers are empty.
  39. */
  40. v = readl(aaci->base + AACI_SLFR);
  41. if (v & SLFR_2RXV)
  42. readl(aaci->base + AACI_SL2RX);
  43. if (v & SLFR_1RXV)
  44. readl(aaci->base + AACI_SL1RX);
  45. writel(maincr, aaci->base + AACI_MAINCR);
  46. }
  47. /*
  48. * P29:
  49. * The recommended use of programming the external codec through slot 1
  50. * and slot 2 data is to use the channels during setup routines and the
  51. * slot register at any other time. The data written into slot 1, slot 2
  52. * and slot 12 registers is transmitted only when their corresponding
  53. * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  54. * register.
  55. */
  56. static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  57. unsigned short val)
  58. {
  59. struct aaci *aaci = ac97->private_data;
  60. u32 v;
  61. int timeout = 5000;
  62. if (ac97->num >= 4)
  63. return;
  64. mutex_lock(&aaci->ac97_sem);
  65. aaci_ac97_select_codec(aaci, ac97);
  66. /*
  67. * P54: You must ensure that AACI_SL2TX is always written
  68. * to, if required, before data is written to AACI_SL1TX.
  69. */
  70. writel(val << 4, aaci->base + AACI_SL2TX);
  71. writel(reg << 12, aaci->base + AACI_SL1TX);
  72. /*
  73. * Wait for the transmission of both slots to complete.
  74. */
  75. do {
  76. v = readl(aaci->base + AACI_SLFR);
  77. } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
  78. if (!timeout)
  79. dev_err(&aaci->dev->dev,
  80. "timeout waiting for write to complete\n");
  81. mutex_unlock(&aaci->ac97_sem);
  82. }
  83. /*
  84. * Read an AC'97 register.
  85. */
  86. static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  87. {
  88. struct aaci *aaci = ac97->private_data;
  89. u32 v;
  90. int timeout = 5000;
  91. int retries = 10;
  92. if (ac97->num >= 4)
  93. return ~0;
  94. mutex_lock(&aaci->ac97_sem);
  95. aaci_ac97_select_codec(aaci, ac97);
  96. /*
  97. * Write the register address to slot 1.
  98. */
  99. writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
  100. /*
  101. * Wait for the transmission to complete.
  102. */
  103. do {
  104. v = readl(aaci->base + AACI_SLFR);
  105. } while ((v & SLFR_1TXB) && --timeout);
  106. if (!timeout) {
  107. dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
  108. v = ~0;
  109. goto out;
  110. }
  111. /*
  112. * Give the AC'97 codec more than enough time
  113. * to respond. (42us = ~2 frames at 48kHz.)
  114. */
  115. udelay(42);
  116. /*
  117. * Wait for slot 2 to indicate data.
  118. */
  119. timeout = 5000;
  120. do {
  121. cond_resched();
  122. v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
  123. } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
  124. if (!timeout) {
  125. dev_err(&aaci->dev->dev, "timeout on RX valid\n");
  126. v = ~0;
  127. goto out;
  128. }
  129. do {
  130. v = readl(aaci->base + AACI_SL1RX) >> 12;
  131. if (v == reg) {
  132. v = readl(aaci->base + AACI_SL2RX) >> 4;
  133. break;
  134. } else if (--retries) {
  135. dev_warn(&aaci->dev->dev,
  136. "ac97 read back fail. retry\n");
  137. continue;
  138. } else {
  139. dev_warn(&aaci->dev->dev,
  140. "wrong ac97 register read back (%x != %x)\n",
  141. v, reg);
  142. v = ~0;
  143. }
  144. } while (retries);
  145. out:
  146. mutex_unlock(&aaci->ac97_sem);
  147. return v;
  148. }
  149. static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
  150. {
  151. u32 val;
  152. int timeout = 5000;
  153. do {
  154. val = readl(aacirun->base + AACI_SR);
  155. } while (val & (SR_TXB|SR_RXB) && timeout--);
  156. }
  157. /*
  158. * Interrupt support.
  159. */
  160. static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
  161. {
  162. if (mask & ISR_ORINTR) {
  163. dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
  164. writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
  165. }
  166. if (mask & ISR_RXTOINTR) {
  167. dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
  168. writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
  169. }
  170. if (mask & ISR_RXINTR) {
  171. struct aaci_runtime *aacirun = &aaci->capture;
  172. void *ptr;
  173. if (!aacirun->substream || !aacirun->start) {
  174. dev_warn(&aaci->dev->dev, "RX interrupt???\n");
  175. writel(0, aacirun->base + AACI_IE);
  176. return;
  177. }
  178. ptr = aacirun->ptr;
  179. do {
  180. unsigned int len = aacirun->fifosz;
  181. u32 val;
  182. if (aacirun->bytes <= 0) {
  183. aacirun->bytes += aacirun->period;
  184. aacirun->ptr = ptr;
  185. spin_unlock(&aaci->lock);
  186. snd_pcm_period_elapsed(aacirun->substream);
  187. spin_lock(&aaci->lock);
  188. }
  189. if (!(aacirun->cr & CR_EN))
  190. break;
  191. val = readl(aacirun->base + AACI_SR);
  192. if (!(val & SR_RXHF))
  193. break;
  194. if (!(val & SR_RXFF))
  195. len >>= 1;
  196. aacirun->bytes -= len;
  197. /* reading 16 bytes at a time */
  198. for( ; len > 0; len -= 16) {
  199. asm(
  200. "ldmia %1, {r0, r1, r2, r3}\n\t"
  201. "stmia %0!, {r0, r1, r2, r3}"
  202. : "+r" (ptr)
  203. : "r" (aacirun->fifo)
  204. : "r0", "r1", "r2", "r3", "cc");
  205. if (ptr >= aacirun->end)
  206. ptr = aacirun->start;
  207. }
  208. } while(1);
  209. aacirun->ptr = ptr;
  210. }
  211. if (mask & ISR_URINTR) {
  212. dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
  213. writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
  214. }
  215. if (mask & ISR_TXINTR) {
  216. struct aaci_runtime *aacirun = &aaci->playback;
  217. void *ptr;
  218. if (!aacirun->substream || !aacirun->start) {
  219. dev_warn(&aaci->dev->dev, "TX interrupt???\n");
  220. writel(0, aacirun->base + AACI_IE);
  221. return;
  222. }
  223. ptr = aacirun->ptr;
  224. do {
  225. unsigned int len = aacirun->fifosz;
  226. u32 val;
  227. if (aacirun->bytes <= 0) {
  228. aacirun->bytes += aacirun->period;
  229. aacirun->ptr = ptr;
  230. spin_unlock(&aaci->lock);
  231. snd_pcm_period_elapsed(aacirun->substream);
  232. spin_lock(&aaci->lock);
  233. }
  234. if (!(aacirun->cr & CR_EN))
  235. break;
  236. val = readl(aacirun->base + AACI_SR);
  237. if (!(val & SR_TXHE))
  238. break;
  239. if (!(val & SR_TXFE))
  240. len >>= 1;
  241. aacirun->bytes -= len;
  242. /* writing 16 bytes at a time */
  243. for ( ; len > 0; len -= 16) {
  244. asm(
  245. "ldmia %0!, {r0, r1, r2, r3}\n\t"
  246. "stmia %1, {r0, r1, r2, r3}"
  247. : "+r" (ptr)
  248. : "r" (aacirun->fifo)
  249. : "r0", "r1", "r2", "r3", "cc");
  250. if (ptr >= aacirun->end)
  251. ptr = aacirun->start;
  252. }
  253. } while (1);
  254. aacirun->ptr = ptr;
  255. }
  256. }
  257. static irqreturn_t aaci_irq(int irq, void *devid)
  258. {
  259. struct aaci *aaci = devid;
  260. u32 mask;
  261. int i;
  262. spin_lock(&aaci->lock);
  263. mask = readl(aaci->base + AACI_ALLINTS);
  264. if (mask) {
  265. u32 m = mask;
  266. for (i = 0; i < 4; i++, m >>= 7) {
  267. if (m & 0x7f) {
  268. aaci_fifo_irq(aaci, i, m);
  269. }
  270. }
  271. }
  272. spin_unlock(&aaci->lock);
  273. return mask ? IRQ_HANDLED : IRQ_NONE;
  274. }
  275. /*
  276. * ALSA support.
  277. */
  278. struct aaci_stream {
  279. unsigned char codec_idx;
  280. unsigned char rate_idx;
  281. };
  282. static struct aaci_stream aaci_streams[] = {
  283. [ACSTREAM_FRONT] = {
  284. .codec_idx = 0,
  285. .rate_idx = AC97_RATES_FRONT_DAC,
  286. },
  287. [ACSTREAM_SURROUND] = {
  288. .codec_idx = 0,
  289. .rate_idx = AC97_RATES_SURR_DAC,
  290. },
  291. [ACSTREAM_LFE] = {
  292. .codec_idx = 0,
  293. .rate_idx = AC97_RATES_LFE_DAC,
  294. },
  295. };
  296. static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
  297. {
  298. struct aaci_stream *s = aaci_streams + streamid;
  299. return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
  300. }
  301. static unsigned int rate_list[] = {
  302. 5512, 8000, 11025, 16000, 22050, 32000, 44100,
  303. 48000, 64000, 88200, 96000, 176400, 192000
  304. };
  305. /*
  306. * Double-rate rule: we can support double rate iff channels == 2
  307. * (unimplemented)
  308. */
  309. static int
  310. aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  311. {
  312. struct aaci *aaci = rule->private;
  313. unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
  314. struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
  315. switch (c->max) {
  316. case 6:
  317. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
  318. case 4:
  319. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
  320. case 2:
  321. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
  322. }
  323. return snd_interval_list(hw_param_interval(p, rule->var),
  324. ARRAY_SIZE(rate_list), rate_list,
  325. rate_mask);
  326. }
  327. static struct snd_pcm_hardware aaci_hw_info = {
  328. .info = SNDRV_PCM_INFO_MMAP |
  329. SNDRV_PCM_INFO_MMAP_VALID |
  330. SNDRV_PCM_INFO_INTERLEAVED |
  331. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  332. SNDRV_PCM_INFO_RESUME,
  333. /*
  334. * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
  335. * words. It also doesn't support 12-bit at all.
  336. */
  337. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  338. /* should this be continuous or knot? */
  339. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  340. .rate_max = 48000,
  341. .rate_min = 4000,
  342. .channels_min = 2,
  343. .channels_max = 6,
  344. .buffer_bytes_max = 64 * 1024,
  345. .period_bytes_min = 256,
  346. .period_bytes_max = PAGE_SIZE,
  347. .periods_min = 4,
  348. .periods_max = PAGE_SIZE / 16,
  349. };
  350. static int __aaci_pcm_open(struct aaci *aaci,
  351. struct snd_pcm_substream *substream,
  352. struct aaci_runtime *aacirun)
  353. {
  354. struct snd_pcm_runtime *runtime = substream->runtime;
  355. int ret;
  356. aacirun->substream = substream;
  357. runtime->private_data = aacirun;
  358. runtime->hw = aaci_hw_info;
  359. /*
  360. * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
  361. * mode, each 32-bit word contains one sample. If we're in
  362. * compact mode, each 32-bit word contains two samples, effectively
  363. * halving the FIFO size. However, we don't know for sure which
  364. * we'll be using at this point. We set this to the lower limit.
  365. */
  366. runtime->hw.fifo_size = aaci->fifosize * 2;
  367. /*
  368. * Add rule describing hardware rate dependency
  369. * on the number of channels.
  370. */
  371. ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  372. aaci_rule_rate_by_channels, aaci,
  373. SNDRV_PCM_HW_PARAM_CHANNELS,
  374. SNDRV_PCM_HW_PARAM_RATE, -1);
  375. if (ret)
  376. goto out;
  377. ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
  378. DRIVER_NAME, aaci);
  379. if (ret)
  380. goto out;
  381. return 0;
  382. out:
  383. return ret;
  384. }
  385. /*
  386. * Common ALSA stuff
  387. */
  388. static int aaci_pcm_close(struct snd_pcm_substream *substream)
  389. {
  390. struct aaci *aaci = substream->private_data;
  391. struct aaci_runtime *aacirun = substream->runtime->private_data;
  392. WARN_ON(aacirun->cr & CR_EN);
  393. aacirun->substream = NULL;
  394. free_irq(aaci->dev->irq[0], aaci);
  395. return 0;
  396. }
  397. static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
  398. {
  399. struct aaci_runtime *aacirun = substream->runtime->private_data;
  400. /*
  401. * This must not be called with the device enabled.
  402. */
  403. WARN_ON(aacirun->cr & CR_EN);
  404. if (aacirun->pcm_open)
  405. snd_ac97_pcm_close(aacirun->pcm);
  406. aacirun->pcm_open = 0;
  407. /*
  408. * Clear out the DMA and any allocated buffers.
  409. */
  410. devdma_hw_free(NULL, substream);
  411. return 0;
  412. }
  413. static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
  414. struct aaci_runtime *aacirun,
  415. struct snd_pcm_hw_params *params)
  416. {
  417. int err;
  418. aaci_pcm_hw_free(substream);
  419. if (aacirun->pcm_open) {
  420. snd_ac97_pcm_close(aacirun->pcm);
  421. aacirun->pcm_open = 0;
  422. }
  423. err = devdma_hw_alloc(NULL, substream,
  424. params_buffer_bytes(params));
  425. if (err < 0)
  426. goto out;
  427. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  428. params_channels(params),
  429. aacirun->pcm->r[0].slots);
  430. if (err)
  431. goto out;
  432. aacirun->pcm_open = 1;
  433. out:
  434. return err;
  435. }
  436. static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
  437. {
  438. struct snd_pcm_runtime *runtime = substream->runtime;
  439. struct aaci_runtime *aacirun = runtime->private_data;
  440. aacirun->start = (void *)runtime->dma_area;
  441. aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
  442. aacirun->ptr = aacirun->start;
  443. aacirun->period =
  444. aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
  445. return 0;
  446. }
  447. static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
  448. {
  449. struct snd_pcm_runtime *runtime = substream->runtime;
  450. struct aaci_runtime *aacirun = runtime->private_data;
  451. ssize_t bytes = aacirun->ptr - aacirun->start;
  452. return bytes_to_frames(runtime, bytes);
  453. }
  454. static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
  455. {
  456. return devdma_mmap(NULL, substream, vma);
  457. }
  458. /*
  459. * Playback specific ALSA stuff
  460. */
  461. static const u32 channels_to_txmask[] = {
  462. [2] = CR_SL3 | CR_SL4,
  463. [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
  464. [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
  465. };
  466. /*
  467. * We can support two and four channel audio. Unfortunately
  468. * six channel audio requires a non-standard channel ordering:
  469. * 2 -> FL(3), FR(4)
  470. * 4 -> FL(3), FR(4), SL(7), SR(8)
  471. * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
  472. * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
  473. * This requires an ALSA configuration file to correct.
  474. */
  475. static unsigned int channel_list[] = { 2, 4, 6 };
  476. static int
  477. aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  478. {
  479. struct aaci *aaci = rule->private;
  480. unsigned int chan_mask = 1 << 0, slots;
  481. /*
  482. * pcms[0] is the our 5.1 PCM instance.
  483. */
  484. slots = aaci->ac97_bus->pcms[0].r[0].slots;
  485. if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  486. chan_mask |= 1 << 1;
  487. if (slots & (1 << AC97_SLOT_LFE))
  488. chan_mask |= 1 << 2;
  489. }
  490. return snd_interval_list(hw_param_interval(p, rule->var),
  491. ARRAY_SIZE(channel_list), channel_list,
  492. chan_mask);
  493. }
  494. static int aaci_pcm_open(struct snd_pcm_substream *substream)
  495. {
  496. struct aaci *aaci = substream->private_data;
  497. int ret;
  498. /*
  499. * Add rule describing channel dependency.
  500. */
  501. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  502. SNDRV_PCM_HW_PARAM_CHANNELS,
  503. aaci_rule_channels, aaci,
  504. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  505. if (ret)
  506. return ret;
  507. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  508. ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
  509. } else {
  510. ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
  511. }
  512. return ret;
  513. }
  514. static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
  515. struct snd_pcm_hw_params *params)
  516. {
  517. struct aaci *aaci = substream->private_data;
  518. struct aaci_runtime *aacirun = substream->runtime->private_data;
  519. unsigned int channels = params_channels(params);
  520. int ret;
  521. WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
  522. !channels_to_txmask[channels]);
  523. ret = aaci_pcm_hw_params(substream, aacirun, params);
  524. /*
  525. * Enable FIFO, compact mode, 16 bits per sample.
  526. * FIXME: double rate slots?
  527. */
  528. if (ret >= 0) {
  529. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  530. aacirun->cr |= channels_to_txmask[channels];
  531. aacirun->fifosz = aaci->fifosize * 4;
  532. if (aacirun->cr & CR_COMPACT)
  533. aacirun->fifosz >>= 1;
  534. }
  535. return ret;
  536. }
  537. static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
  538. {
  539. u32 ie;
  540. ie = readl(aacirun->base + AACI_IE);
  541. ie &= ~(IE_URIE|IE_TXIE);
  542. writel(ie, aacirun->base + AACI_IE);
  543. aacirun->cr &= ~CR_EN;
  544. aaci_chan_wait_ready(aacirun);
  545. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  546. }
  547. static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
  548. {
  549. u32 ie;
  550. aaci_chan_wait_ready(aacirun);
  551. aacirun->cr |= CR_EN;
  552. ie = readl(aacirun->base + AACI_IE);
  553. ie |= IE_URIE | IE_TXIE;
  554. writel(ie, aacirun->base + AACI_IE);
  555. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  556. }
  557. static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  558. {
  559. struct aaci *aaci = substream->private_data;
  560. struct aaci_runtime *aacirun = substream->runtime->private_data;
  561. unsigned long flags;
  562. int ret = 0;
  563. spin_lock_irqsave(&aaci->lock, flags);
  564. switch (cmd) {
  565. case SNDRV_PCM_TRIGGER_START:
  566. aaci_pcm_playback_start(aacirun);
  567. break;
  568. case SNDRV_PCM_TRIGGER_RESUME:
  569. aaci_pcm_playback_start(aacirun);
  570. break;
  571. case SNDRV_PCM_TRIGGER_STOP:
  572. aaci_pcm_playback_stop(aacirun);
  573. break;
  574. case SNDRV_PCM_TRIGGER_SUSPEND:
  575. aaci_pcm_playback_stop(aacirun);
  576. break;
  577. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  578. break;
  579. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  580. break;
  581. default:
  582. ret = -EINVAL;
  583. }
  584. spin_unlock_irqrestore(&aaci->lock, flags);
  585. return ret;
  586. }
  587. static struct snd_pcm_ops aaci_playback_ops = {
  588. .open = aaci_pcm_open,
  589. .close = aaci_pcm_close,
  590. .ioctl = snd_pcm_lib_ioctl,
  591. .hw_params = aaci_pcm_playback_hw_params,
  592. .hw_free = aaci_pcm_hw_free,
  593. .prepare = aaci_pcm_prepare,
  594. .trigger = aaci_pcm_playback_trigger,
  595. .pointer = aaci_pcm_pointer,
  596. .mmap = aaci_pcm_mmap,
  597. };
  598. static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
  599. struct snd_pcm_hw_params *params)
  600. {
  601. struct aaci *aaci = substream->private_data;
  602. struct aaci_runtime *aacirun = substream->runtime->private_data;
  603. int ret;
  604. ret = aaci_pcm_hw_params(substream, aacirun, params);
  605. if (ret >= 0) {
  606. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  607. /* Line in record: slot 3 and 4 */
  608. aacirun->cr |= CR_SL3 | CR_SL4;
  609. aacirun->fifosz = aaci->fifosize * 4;
  610. if (aacirun->cr & CR_COMPACT)
  611. aacirun->fifosz >>= 1;
  612. }
  613. return ret;
  614. }
  615. static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
  616. {
  617. u32 ie;
  618. aaci_chan_wait_ready(aacirun);
  619. ie = readl(aacirun->base + AACI_IE);
  620. ie &= ~(IE_ORIE | IE_RXIE);
  621. writel(ie, aacirun->base+AACI_IE);
  622. aacirun->cr &= ~CR_EN;
  623. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  624. }
  625. static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
  626. {
  627. u32 ie;
  628. aaci_chan_wait_ready(aacirun);
  629. #ifdef DEBUG
  630. /* RX Timeout value: bits 28:17 in RXCR */
  631. aacirun->cr |= 0xf << 17;
  632. #endif
  633. aacirun->cr |= CR_EN;
  634. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  635. ie = readl(aacirun->base + AACI_IE);
  636. ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
  637. writel(ie, aacirun->base + AACI_IE);
  638. }
  639. static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  640. {
  641. struct aaci *aaci = substream->private_data;
  642. struct aaci_runtime *aacirun = substream->runtime->private_data;
  643. unsigned long flags;
  644. int ret = 0;
  645. spin_lock_irqsave(&aaci->lock, flags);
  646. switch (cmd) {
  647. case SNDRV_PCM_TRIGGER_START:
  648. aaci_pcm_capture_start(aacirun);
  649. break;
  650. case SNDRV_PCM_TRIGGER_RESUME:
  651. aaci_pcm_capture_start(aacirun);
  652. break;
  653. case SNDRV_PCM_TRIGGER_STOP:
  654. aaci_pcm_capture_stop(aacirun);
  655. break;
  656. case SNDRV_PCM_TRIGGER_SUSPEND:
  657. aaci_pcm_capture_stop(aacirun);
  658. break;
  659. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  660. break;
  661. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  662. break;
  663. default:
  664. ret = -EINVAL;
  665. }
  666. spin_unlock_irqrestore(&aaci->lock, flags);
  667. return ret;
  668. }
  669. static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
  670. {
  671. struct snd_pcm_runtime *runtime = substream->runtime;
  672. struct aaci *aaci = substream->private_data;
  673. aaci_pcm_prepare(substream);
  674. /* allow changing of sample rate */
  675. aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
  676. aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  677. aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
  678. /* Record select: Mic: 0, Aux: 3, Line: 4 */
  679. aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
  680. return 0;
  681. }
  682. static struct snd_pcm_ops aaci_capture_ops = {
  683. .open = aaci_pcm_open,
  684. .close = aaci_pcm_close,
  685. .ioctl = snd_pcm_lib_ioctl,
  686. .hw_params = aaci_pcm_capture_hw_params,
  687. .hw_free = aaci_pcm_hw_free,
  688. .prepare = aaci_pcm_capture_prepare,
  689. .trigger = aaci_pcm_capture_trigger,
  690. .pointer = aaci_pcm_pointer,
  691. .mmap = aaci_pcm_mmap,
  692. };
  693. /*
  694. * Power Management.
  695. */
  696. #ifdef CONFIG_PM
  697. static int aaci_do_suspend(struct snd_card *card, unsigned int state)
  698. {
  699. struct aaci *aaci = card->private_data;
  700. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  701. snd_pcm_suspend_all(aaci->pcm);
  702. return 0;
  703. }
  704. static int aaci_do_resume(struct snd_card *card, unsigned int state)
  705. {
  706. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  707. return 0;
  708. }
  709. static int aaci_suspend(struct amba_device *dev, pm_message_t state)
  710. {
  711. struct snd_card *card = amba_get_drvdata(dev);
  712. return card ? aaci_do_suspend(card) : 0;
  713. }
  714. static int aaci_resume(struct amba_device *dev)
  715. {
  716. struct snd_card *card = amba_get_drvdata(dev);
  717. return card ? aaci_do_resume(card) : 0;
  718. }
  719. #else
  720. #define aaci_do_suspend NULL
  721. #define aaci_do_resume NULL
  722. #define aaci_suspend NULL
  723. #define aaci_resume NULL
  724. #endif
  725. static struct ac97_pcm ac97_defs[] __devinitdata = {
  726. [0] = { /* Front PCM */
  727. .exclusive = 1,
  728. .r = {
  729. [0] = {
  730. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  731. (1 << AC97_SLOT_PCM_RIGHT) |
  732. (1 << AC97_SLOT_PCM_CENTER) |
  733. (1 << AC97_SLOT_PCM_SLEFT) |
  734. (1 << AC97_SLOT_PCM_SRIGHT) |
  735. (1 << AC97_SLOT_LFE),
  736. },
  737. },
  738. },
  739. [1] = { /* PCM in */
  740. .stream = 1,
  741. .exclusive = 1,
  742. .r = {
  743. [0] = {
  744. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  745. (1 << AC97_SLOT_PCM_RIGHT),
  746. },
  747. },
  748. },
  749. [2] = { /* Mic in */
  750. .stream = 1,
  751. .exclusive = 1,
  752. .r = {
  753. [0] = {
  754. .slots = (1 << AC97_SLOT_MIC),
  755. },
  756. },
  757. }
  758. };
  759. static struct snd_ac97_bus_ops aaci_bus_ops = {
  760. .write = aaci_ac97_write,
  761. .read = aaci_ac97_read,
  762. };
  763. static int __devinit aaci_probe_ac97(struct aaci *aaci)
  764. {
  765. struct snd_ac97_template ac97_template;
  766. struct snd_ac97_bus *ac97_bus;
  767. struct snd_ac97 *ac97;
  768. int ret;
  769. writel(0, aaci->base + AC97_POWERDOWN);
  770. /*
  771. * Assert AACIRESET for 2us
  772. */
  773. writel(0, aaci->base + AACI_RESET);
  774. udelay(2);
  775. writel(RESET_NRST, aaci->base + AACI_RESET);
  776. /*
  777. * Give the AC'97 codec more than enough time
  778. * to wake up. (42us = ~2 frames at 48kHz.)
  779. */
  780. udelay(42);
  781. ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
  782. if (ret)
  783. goto out;
  784. ac97_bus->clock = 48000;
  785. aaci->ac97_bus = ac97_bus;
  786. memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
  787. ac97_template.private_data = aaci;
  788. ac97_template.num = 0;
  789. ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
  790. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
  791. if (ret)
  792. goto out;
  793. aaci->ac97 = ac97;
  794. /*
  795. * Disable AC97 PC Beep input on audio codecs.
  796. */
  797. if (ac97_is_audio(ac97))
  798. snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
  799. ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
  800. if (ret)
  801. goto out;
  802. aaci->playback.pcm = &ac97_bus->pcms[0];
  803. aaci->capture.pcm = &ac97_bus->pcms[1];
  804. out:
  805. return ret;
  806. }
  807. static void aaci_free_card(struct snd_card *card)
  808. {
  809. struct aaci *aaci = card->private_data;
  810. if (aaci->base)
  811. iounmap(aaci->base);
  812. }
  813. static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
  814. {
  815. struct aaci *aaci;
  816. struct snd_card *card;
  817. int err;
  818. err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  819. THIS_MODULE, sizeof(struct aaci), &card);
  820. if (err < 0)
  821. return NULL;
  822. card->private_free = aaci_free_card;
  823. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  824. strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
  825. snprintf(card->longname, sizeof(card->longname),
  826. "%s at 0x%016llx, irq %d",
  827. card->shortname, (unsigned long long)dev->res.start,
  828. dev->irq[0]);
  829. aaci = card->private_data;
  830. mutex_init(&aaci->ac97_sem);
  831. spin_lock_init(&aaci->lock);
  832. aaci->card = card;
  833. aaci->dev = dev;
  834. /* Set MAINCR to allow slot 1 and 2 data IO */
  835. aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
  836. MAINCR_SL2RXEN | MAINCR_SL2TXEN;
  837. return aaci;
  838. }
  839. static int __devinit aaci_init_pcm(struct aaci *aaci)
  840. {
  841. struct snd_pcm *pcm;
  842. int ret;
  843. ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
  844. if (ret == 0) {
  845. aaci->pcm = pcm;
  846. pcm->private_data = aaci;
  847. pcm->info_flags = 0;
  848. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  849. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
  850. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
  851. }
  852. return ret;
  853. }
  854. static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
  855. {
  856. struct aaci_runtime *aacirun = &aaci->playback;
  857. int i;
  858. writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
  859. for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
  860. writel(0, aacirun->fifo);
  861. writel(0, aacirun->base + AACI_TXCR);
  862. /*
  863. * Re-initialise the AACI after the FIFO depth test, to
  864. * ensure that the FIFOs are empty. Unfortunately, merely
  865. * disabling the channel doesn't clear the FIFO.
  866. */
  867. writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
  868. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  869. /*
  870. * If we hit 4096, we failed. Go back to the specified
  871. * fifo depth.
  872. */
  873. if (i == 4096)
  874. i = 8;
  875. return i;
  876. }
  877. static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id)
  878. {
  879. struct aaci *aaci;
  880. int ret, i;
  881. ret = amba_request_regions(dev, NULL);
  882. if (ret)
  883. return ret;
  884. aaci = aaci_init_card(dev);
  885. if (!aaci) {
  886. ret = -ENOMEM;
  887. goto out;
  888. }
  889. aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
  890. if (!aaci->base) {
  891. ret = -ENOMEM;
  892. goto out;
  893. }
  894. /*
  895. * Playback uses AACI channel 0
  896. */
  897. aaci->playback.base = aaci->base + AACI_CSCH1;
  898. aaci->playback.fifo = aaci->base + AACI_DR1;
  899. /*
  900. * Capture uses AACI channel 0
  901. */
  902. aaci->capture.base = aaci->base + AACI_CSCH1;
  903. aaci->capture.fifo = aaci->base + AACI_DR1;
  904. for (i = 0; i < 4; i++) {
  905. void __iomem *base = aaci->base + i * 0x14;
  906. writel(0, base + AACI_IE);
  907. writel(0, base + AACI_TXCR);
  908. writel(0, base + AACI_RXCR);
  909. }
  910. writel(0x1fff, aaci->base + AACI_INTCLR);
  911. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  912. ret = aaci_probe_ac97(aaci);
  913. if (ret)
  914. goto out;
  915. /*
  916. * Size the FIFOs (must be multiple of 16).
  917. */
  918. aaci->fifosize = aaci_size_fifo(aaci);
  919. if (aaci->fifosize & 15) {
  920. printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
  921. aaci->fifosize);
  922. ret = -ENODEV;
  923. goto out;
  924. }
  925. ret = aaci_init_pcm(aaci);
  926. if (ret)
  927. goto out;
  928. snd_card_set_dev(aaci->card, &dev->dev);
  929. ret = snd_card_register(aaci->card);
  930. if (ret == 0) {
  931. dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
  932. aaci->fifosize);
  933. amba_set_drvdata(dev, aaci->card);
  934. return ret;
  935. }
  936. out:
  937. if (aaci)
  938. snd_card_free(aaci->card);
  939. amba_release_regions(dev);
  940. return ret;
  941. }
  942. static int __devexit aaci_remove(struct amba_device *dev)
  943. {
  944. struct snd_card *card = amba_get_drvdata(dev);
  945. amba_set_drvdata(dev, NULL);
  946. if (card) {
  947. struct aaci *aaci = card->private_data;
  948. writel(0, aaci->base + AACI_MAINCR);
  949. snd_card_free(card);
  950. amba_release_regions(dev);
  951. }
  952. return 0;
  953. }
  954. static struct amba_id aaci_ids[] = {
  955. {
  956. .id = 0x00041041,
  957. .mask = 0x000fffff,
  958. },
  959. { 0, 0 },
  960. };
  961. static struct amba_driver aaci_driver = {
  962. .drv = {
  963. .name = DRIVER_NAME,
  964. },
  965. .probe = aaci_probe,
  966. .remove = __devexit_p(aaci_remove),
  967. .suspend = aaci_suspend,
  968. .resume = aaci_resume,
  969. .id_table = aaci_ids,
  970. };
  971. static int __init aaci_init(void)
  972. {
  973. return amba_driver_register(&aaci_driver);
  974. }
  975. static void __exit aaci_exit(void)
  976. {
  977. amba_driver_unregister(&aaci_driver);
  978. }
  979. module_init(aaci_init);
  980. module_exit(aaci_exit);
  981. MODULE_LICENSE("GPL");
  982. MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");