be_main.c 63 KB

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  1. /*
  2. * Copyright (C) 2005 - 2009 ServerEngines
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@serverengines.com
  12. *
  13. * ServerEngines
  14. * 209 N. Fair Oaks Ave
  15. * Sunnyvale, CA 94085
  16. */
  17. #include "be.h"
  18. #include "be_cmds.h"
  19. #include <asm/div64.h>
  20. MODULE_VERSION(DRV_VER);
  21. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  22. MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
  23. MODULE_AUTHOR("ServerEngines Corporation");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int rx_frag_size = 2048;
  26. module_param(rx_frag_size, uint, S_IRUGO);
  27. MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
  28. static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
  29. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  30. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  31. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  32. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  33. { 0 }
  34. };
  35. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  36. static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
  37. {
  38. struct be_dma_mem *mem = &q->dma_mem;
  39. if (mem->va)
  40. pci_free_consistent(adapter->pdev, mem->size,
  41. mem->va, mem->dma);
  42. }
  43. static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
  44. u16 len, u16 entry_size)
  45. {
  46. struct be_dma_mem *mem = &q->dma_mem;
  47. memset(q, 0, sizeof(*q));
  48. q->len = len;
  49. q->entry_size = entry_size;
  50. mem->size = len * entry_size;
  51. mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
  52. if (!mem->va)
  53. return -1;
  54. memset(mem->va, 0, mem->size);
  55. return 0;
  56. }
  57. static void be_intr_set(struct be_adapter *adapter, bool enable)
  58. {
  59. u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  60. u32 reg = ioread32(addr);
  61. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  62. if (adapter->eeh_err)
  63. return;
  64. if (!enabled && enable)
  65. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  66. else if (enabled && !enable)
  67. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  68. else
  69. return;
  70. iowrite32(reg, addr);
  71. }
  72. static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  73. {
  74. u32 val = 0;
  75. val |= qid & DB_RQ_RING_ID_MASK;
  76. val |= posted << DB_RQ_NUM_POSTED_SHIFT;
  77. iowrite32(val, adapter->db + DB_RQ_OFFSET);
  78. }
  79. static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  80. {
  81. u32 val = 0;
  82. val |= qid & DB_TXULP_RING_ID_MASK;
  83. val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
  84. iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
  85. }
  86. static void be_eq_notify(struct be_adapter *adapter, u16 qid,
  87. bool arm, bool clear_int, u16 num_popped)
  88. {
  89. u32 val = 0;
  90. val |= qid & DB_EQ_RING_ID_MASK;
  91. if (adapter->eeh_err)
  92. return;
  93. if (arm)
  94. val |= 1 << DB_EQ_REARM_SHIFT;
  95. if (clear_int)
  96. val |= 1 << DB_EQ_CLR_SHIFT;
  97. val |= 1 << DB_EQ_EVNT_SHIFT;
  98. val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
  99. iowrite32(val, adapter->db + DB_EQ_OFFSET);
  100. }
  101. void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
  102. {
  103. u32 val = 0;
  104. val |= qid & DB_CQ_RING_ID_MASK;
  105. if (adapter->eeh_err)
  106. return;
  107. if (arm)
  108. val |= 1 << DB_CQ_REARM_SHIFT;
  109. val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
  110. iowrite32(val, adapter->db + DB_CQ_OFFSET);
  111. }
  112. static int be_mac_addr_set(struct net_device *netdev, void *p)
  113. {
  114. struct be_adapter *adapter = netdev_priv(netdev);
  115. struct sockaddr *addr = p;
  116. int status = 0;
  117. if (!is_valid_ether_addr(addr->sa_data))
  118. return -EADDRNOTAVAIL;
  119. status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
  120. if (status)
  121. return status;
  122. status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
  123. adapter->if_handle, &adapter->pmac_id);
  124. if (!status)
  125. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  126. return status;
  127. }
  128. void netdev_stats_update(struct be_adapter *adapter)
  129. {
  130. struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
  131. struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
  132. struct be_port_rxf_stats *port_stats =
  133. &rxf_stats->port[adapter->port_num];
  134. struct net_device_stats *dev_stats = &adapter->netdev->stats;
  135. struct be_erx_stats *erx_stats = &hw_stats->erx;
  136. dev_stats->rx_packets = port_stats->rx_total_frames;
  137. dev_stats->tx_packets = port_stats->tx_unicastframes +
  138. port_stats->tx_multicastframes + port_stats->tx_broadcastframes;
  139. dev_stats->rx_bytes = (u64) port_stats->rx_bytes_msd << 32 |
  140. (u64) port_stats->rx_bytes_lsd;
  141. dev_stats->tx_bytes = (u64) port_stats->tx_bytes_msd << 32 |
  142. (u64) port_stats->tx_bytes_lsd;
  143. /* bad pkts received */
  144. dev_stats->rx_errors = port_stats->rx_crc_errors +
  145. port_stats->rx_alignment_symbol_errors +
  146. port_stats->rx_in_range_errors +
  147. port_stats->rx_out_range_errors +
  148. port_stats->rx_frame_too_long +
  149. port_stats->rx_dropped_too_small +
  150. port_stats->rx_dropped_too_short +
  151. port_stats->rx_dropped_header_too_small +
  152. port_stats->rx_dropped_tcp_length +
  153. port_stats->rx_dropped_runt +
  154. port_stats->rx_tcp_checksum_errs +
  155. port_stats->rx_ip_checksum_errs +
  156. port_stats->rx_udp_checksum_errs;
  157. /* no space in linux buffers: best possible approximation */
  158. dev_stats->rx_dropped =
  159. erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
  160. /* detailed rx errors */
  161. dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
  162. port_stats->rx_out_range_errors +
  163. port_stats->rx_frame_too_long;
  164. /* receive ring buffer overflow */
  165. dev_stats->rx_over_errors = 0;
  166. dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
  167. /* frame alignment errors */
  168. dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
  169. /* receiver fifo overrun */
  170. /* drops_no_pbuf is no per i/f, it's per BE card */
  171. dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
  172. port_stats->rx_input_fifo_overflow +
  173. rxf_stats->rx_drops_no_pbuf;
  174. /* receiver missed packetd */
  175. dev_stats->rx_missed_errors = 0;
  176. /* packet transmit problems */
  177. dev_stats->tx_errors = 0;
  178. /* no space available in linux */
  179. dev_stats->tx_dropped = 0;
  180. dev_stats->multicast = port_stats->rx_multicast_frames;
  181. dev_stats->collisions = 0;
  182. /* detailed tx_errors */
  183. dev_stats->tx_aborted_errors = 0;
  184. dev_stats->tx_carrier_errors = 0;
  185. dev_stats->tx_fifo_errors = 0;
  186. dev_stats->tx_heartbeat_errors = 0;
  187. dev_stats->tx_window_errors = 0;
  188. }
  189. void be_link_status_update(struct be_adapter *adapter, bool link_up)
  190. {
  191. struct net_device *netdev = adapter->netdev;
  192. /* If link came up or went down */
  193. if (adapter->link_up != link_up) {
  194. adapter->link_speed = -1;
  195. if (link_up) {
  196. netif_start_queue(netdev);
  197. netif_carrier_on(netdev);
  198. printk(KERN_INFO "%s: Link up\n", netdev->name);
  199. } else {
  200. netif_stop_queue(netdev);
  201. netif_carrier_off(netdev);
  202. printk(KERN_INFO "%s: Link down\n", netdev->name);
  203. }
  204. adapter->link_up = link_up;
  205. }
  206. }
  207. /* Update the EQ delay n BE based on the RX frags consumed / sec */
  208. static void be_rx_eqd_update(struct be_adapter *adapter)
  209. {
  210. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  211. struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
  212. ulong now = jiffies;
  213. u32 eqd;
  214. if (!rx_eq->enable_aic)
  215. return;
  216. /* Wrapped around */
  217. if (time_before(now, stats->rx_fps_jiffies)) {
  218. stats->rx_fps_jiffies = now;
  219. return;
  220. }
  221. /* Update once a second */
  222. if ((now - stats->rx_fps_jiffies) < HZ)
  223. return;
  224. stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
  225. ((now - stats->rx_fps_jiffies) / HZ);
  226. stats->rx_fps_jiffies = now;
  227. stats->be_prev_rx_frags = stats->be_rx_frags;
  228. eqd = stats->be_rx_fps / 110000;
  229. eqd = eqd << 3;
  230. if (eqd > rx_eq->max_eqd)
  231. eqd = rx_eq->max_eqd;
  232. if (eqd < rx_eq->min_eqd)
  233. eqd = rx_eq->min_eqd;
  234. if (eqd < 10)
  235. eqd = 0;
  236. if (eqd != rx_eq->cur_eqd)
  237. be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
  238. rx_eq->cur_eqd = eqd;
  239. }
  240. static struct net_device_stats *be_get_stats(struct net_device *dev)
  241. {
  242. return &dev->stats;
  243. }
  244. static u32 be_calc_rate(u64 bytes, unsigned long ticks)
  245. {
  246. u64 rate = bytes;
  247. do_div(rate, ticks / HZ);
  248. rate <<= 3; /* bytes/sec -> bits/sec */
  249. do_div(rate, 1000000ul); /* MB/Sec */
  250. return rate;
  251. }
  252. static void be_tx_rate_update(struct be_adapter *adapter)
  253. {
  254. struct be_drvr_stats *stats = drvr_stats(adapter);
  255. ulong now = jiffies;
  256. /* Wrapped around? */
  257. if (time_before(now, stats->be_tx_jiffies)) {
  258. stats->be_tx_jiffies = now;
  259. return;
  260. }
  261. /* Update tx rate once in two seconds */
  262. if ((now - stats->be_tx_jiffies) > 2 * HZ) {
  263. stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
  264. - stats->be_tx_bytes_prev,
  265. now - stats->be_tx_jiffies);
  266. stats->be_tx_jiffies = now;
  267. stats->be_tx_bytes_prev = stats->be_tx_bytes;
  268. }
  269. }
  270. static void be_tx_stats_update(struct be_adapter *adapter,
  271. u32 wrb_cnt, u32 copied, bool stopped)
  272. {
  273. struct be_drvr_stats *stats = drvr_stats(adapter);
  274. stats->be_tx_reqs++;
  275. stats->be_tx_wrbs += wrb_cnt;
  276. stats->be_tx_bytes += copied;
  277. if (stopped)
  278. stats->be_tx_stops++;
  279. }
  280. /* Determine number of WRB entries needed to xmit data in an skb */
  281. static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
  282. {
  283. int cnt = (skb->len > skb->data_len);
  284. cnt += skb_shinfo(skb)->nr_frags;
  285. /* to account for hdr wrb */
  286. cnt++;
  287. if (cnt & 1) {
  288. /* add a dummy to make it an even num */
  289. cnt++;
  290. *dummy = true;
  291. } else
  292. *dummy = false;
  293. BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
  294. return cnt;
  295. }
  296. static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
  297. {
  298. wrb->frag_pa_hi = upper_32_bits(addr);
  299. wrb->frag_pa_lo = addr & 0xFFFFFFFF;
  300. wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
  301. }
  302. static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
  303. bool vlan, u32 wrb_cnt, u32 len)
  304. {
  305. memset(hdr, 0, sizeof(*hdr));
  306. AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
  307. if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
  308. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
  309. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
  310. hdr, skb_shinfo(skb)->gso_size);
  311. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  312. if (is_tcp_pkt(skb))
  313. AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
  314. else if (is_udp_pkt(skb))
  315. AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
  316. }
  317. if (vlan && vlan_tx_tag_present(skb)) {
  318. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
  319. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
  320. hdr, vlan_tx_tag_get(skb));
  321. }
  322. AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
  323. AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
  324. AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
  325. AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
  326. }
  327. static int make_tx_wrbs(struct be_adapter *adapter,
  328. struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
  329. {
  330. u64 busaddr;
  331. u32 i, copied = 0;
  332. struct pci_dev *pdev = adapter->pdev;
  333. struct sk_buff *first_skb = skb;
  334. struct be_queue_info *txq = &adapter->tx_obj.q;
  335. struct be_eth_wrb *wrb;
  336. struct be_eth_hdr_wrb *hdr;
  337. hdr = queue_head_node(txq);
  338. atomic_add(wrb_cnt, &txq->used);
  339. queue_head_inc(txq);
  340. if (skb->len > skb->data_len) {
  341. int len = skb->len - skb->data_len;
  342. busaddr = pci_map_single(pdev, skb->data, len,
  343. PCI_DMA_TODEVICE);
  344. wrb = queue_head_node(txq);
  345. wrb_fill(wrb, busaddr, len);
  346. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  347. queue_head_inc(txq);
  348. copied += len;
  349. }
  350. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  351. struct skb_frag_struct *frag =
  352. &skb_shinfo(skb)->frags[i];
  353. busaddr = pci_map_page(pdev, frag->page,
  354. frag->page_offset,
  355. frag->size, PCI_DMA_TODEVICE);
  356. wrb = queue_head_node(txq);
  357. wrb_fill(wrb, busaddr, frag->size);
  358. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  359. queue_head_inc(txq);
  360. copied += frag->size;
  361. }
  362. if (dummy_wrb) {
  363. wrb = queue_head_node(txq);
  364. wrb_fill(wrb, 0, 0);
  365. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  366. queue_head_inc(txq);
  367. }
  368. wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
  369. wrb_cnt, copied);
  370. be_dws_cpu_to_le(hdr, sizeof(*hdr));
  371. return copied;
  372. }
  373. static netdev_tx_t be_xmit(struct sk_buff *skb,
  374. struct net_device *netdev)
  375. {
  376. struct be_adapter *adapter = netdev_priv(netdev);
  377. struct be_tx_obj *tx_obj = &adapter->tx_obj;
  378. struct be_queue_info *txq = &tx_obj->q;
  379. u32 wrb_cnt = 0, copied = 0;
  380. u32 start = txq->head;
  381. bool dummy_wrb, stopped = false;
  382. wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
  383. copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
  384. if (copied) {
  385. /* record the sent skb in the sent_skb table */
  386. BUG_ON(tx_obj->sent_skb_list[start]);
  387. tx_obj->sent_skb_list[start] = skb;
  388. /* Ensure txq has space for the next skb; Else stop the queue
  389. * *BEFORE* ringing the tx doorbell, so that we serialze the
  390. * tx compls of the current transmit which'll wake up the queue
  391. */
  392. if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
  393. txq->len) {
  394. netif_stop_queue(netdev);
  395. stopped = true;
  396. }
  397. be_txq_notify(adapter, txq->id, wrb_cnt);
  398. be_tx_stats_update(adapter, wrb_cnt, copied, stopped);
  399. } else {
  400. txq->head = start;
  401. dev_kfree_skb_any(skb);
  402. }
  403. return NETDEV_TX_OK;
  404. }
  405. static int be_change_mtu(struct net_device *netdev, int new_mtu)
  406. {
  407. struct be_adapter *adapter = netdev_priv(netdev);
  408. if (new_mtu < BE_MIN_MTU ||
  409. new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
  410. (ETH_HLEN + ETH_FCS_LEN))) {
  411. dev_info(&adapter->pdev->dev,
  412. "MTU must be between %d and %d bytes\n",
  413. BE_MIN_MTU,
  414. (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
  415. return -EINVAL;
  416. }
  417. dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
  418. netdev->mtu, new_mtu);
  419. netdev->mtu = new_mtu;
  420. return 0;
  421. }
  422. /*
  423. * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
  424. * If the user configures more, place BE in vlan promiscuous mode.
  425. */
  426. static int be_vid_config(struct be_adapter *adapter)
  427. {
  428. u16 vtag[BE_NUM_VLANS_SUPPORTED];
  429. u16 ntags = 0, i;
  430. int status = 0;
  431. if (adapter->vlans_added <= adapter->max_vlans) {
  432. /* Construct VLAN Table to give to HW */
  433. for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
  434. if (adapter->vlan_tag[i]) {
  435. vtag[ntags] = cpu_to_le16(i);
  436. ntags++;
  437. }
  438. }
  439. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  440. vtag, ntags, 1, 0);
  441. } else {
  442. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  443. NULL, 0, 1, 1);
  444. }
  445. return status;
  446. }
  447. static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
  448. {
  449. struct be_adapter *adapter = netdev_priv(netdev);
  450. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  451. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  452. be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
  453. be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
  454. adapter->vlan_grp = grp;
  455. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  456. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  457. }
  458. static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
  459. {
  460. struct be_adapter *adapter = netdev_priv(netdev);
  461. adapter->vlan_tag[vid] = 1;
  462. adapter->vlans_added++;
  463. if (adapter->vlans_added <= (adapter->max_vlans + 1))
  464. be_vid_config(adapter);
  465. }
  466. static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
  467. {
  468. struct be_adapter *adapter = netdev_priv(netdev);
  469. adapter->vlan_tag[vid] = 0;
  470. vlan_group_set_device(adapter->vlan_grp, vid, NULL);
  471. adapter->vlans_added--;
  472. if (adapter->vlans_added <= adapter->max_vlans)
  473. be_vid_config(adapter);
  474. }
  475. static void be_set_multicast_list(struct net_device *netdev)
  476. {
  477. struct be_adapter *adapter = netdev_priv(netdev);
  478. if (netdev->flags & IFF_PROMISC) {
  479. be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
  480. adapter->promiscuous = true;
  481. goto done;
  482. }
  483. /* BE was previously in promiscous mode; disable it */
  484. if (adapter->promiscuous) {
  485. adapter->promiscuous = false;
  486. be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
  487. }
  488. /* Enable multicast promisc if num configured exceeds what we support */
  489. if (netdev->flags & IFF_ALLMULTI ||
  490. netdev_mc_count(netdev) > BE_MAX_MC) {
  491. be_cmd_multicast_set(adapter, adapter->if_handle, NULL, 0,
  492. &adapter->mc_cmd_mem);
  493. goto done;
  494. }
  495. be_cmd_multicast_set(adapter, adapter->if_handle, netdev->mc_list,
  496. netdev_mc_count(netdev), &adapter->mc_cmd_mem);
  497. done:
  498. return;
  499. }
  500. static void be_rx_rate_update(struct be_adapter *adapter)
  501. {
  502. struct be_drvr_stats *stats = drvr_stats(adapter);
  503. ulong now = jiffies;
  504. /* Wrapped around */
  505. if (time_before(now, stats->be_rx_jiffies)) {
  506. stats->be_rx_jiffies = now;
  507. return;
  508. }
  509. /* Update the rate once in two seconds */
  510. if ((now - stats->be_rx_jiffies) < 2 * HZ)
  511. return;
  512. stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
  513. - stats->be_rx_bytes_prev,
  514. now - stats->be_rx_jiffies);
  515. stats->be_rx_jiffies = now;
  516. stats->be_rx_bytes_prev = stats->be_rx_bytes;
  517. }
  518. static void be_rx_stats_update(struct be_adapter *adapter,
  519. u32 pktsize, u16 numfrags)
  520. {
  521. struct be_drvr_stats *stats = drvr_stats(adapter);
  522. stats->be_rx_compl++;
  523. stats->be_rx_frags += numfrags;
  524. stats->be_rx_bytes += pktsize;
  525. }
  526. static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
  527. {
  528. u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
  529. l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
  530. ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
  531. ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
  532. if (ip_version) {
  533. tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  534. udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
  535. }
  536. ipv6_chk = (ip_version && (tcpf || udpf));
  537. return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
  538. }
  539. static struct be_rx_page_info *
  540. get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
  541. {
  542. struct be_rx_page_info *rx_page_info;
  543. struct be_queue_info *rxq = &adapter->rx_obj.q;
  544. rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
  545. BUG_ON(!rx_page_info->page);
  546. if (rx_page_info->last_page_user) {
  547. pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus),
  548. adapter->big_page_size, PCI_DMA_FROMDEVICE);
  549. rx_page_info->last_page_user = false;
  550. }
  551. atomic_dec(&rxq->used);
  552. return rx_page_info;
  553. }
  554. /* Throwaway the data in the Rx completion */
  555. static void be_rx_compl_discard(struct be_adapter *adapter,
  556. struct be_eth_rx_compl *rxcp)
  557. {
  558. struct be_queue_info *rxq = &adapter->rx_obj.q;
  559. struct be_rx_page_info *page_info;
  560. u16 rxq_idx, i, num_rcvd;
  561. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  562. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  563. for (i = 0; i < num_rcvd; i++) {
  564. page_info = get_rx_page_info(adapter, rxq_idx);
  565. put_page(page_info->page);
  566. memset(page_info, 0, sizeof(*page_info));
  567. index_inc(&rxq_idx, rxq->len);
  568. }
  569. }
  570. /*
  571. * skb_fill_rx_data forms a complete skb for an ether frame
  572. * indicated by rxcp.
  573. */
  574. static void skb_fill_rx_data(struct be_adapter *adapter,
  575. struct sk_buff *skb, struct be_eth_rx_compl *rxcp)
  576. {
  577. struct be_queue_info *rxq = &adapter->rx_obj.q;
  578. struct be_rx_page_info *page_info;
  579. u16 rxq_idx, i, num_rcvd, j;
  580. u32 pktsize, hdr_len, curr_frag_len, size;
  581. u8 *start;
  582. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  583. pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  584. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  585. page_info = get_rx_page_info(adapter, rxq_idx);
  586. start = page_address(page_info->page) + page_info->page_offset;
  587. prefetch(start);
  588. /* Copy data in the first descriptor of this completion */
  589. curr_frag_len = min(pktsize, rx_frag_size);
  590. /* Copy the header portion into skb_data */
  591. hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
  592. memcpy(skb->data, start, hdr_len);
  593. skb->len = curr_frag_len;
  594. if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
  595. /* Complete packet has now been moved to data */
  596. put_page(page_info->page);
  597. skb->data_len = 0;
  598. skb->tail += curr_frag_len;
  599. } else {
  600. skb_shinfo(skb)->nr_frags = 1;
  601. skb_shinfo(skb)->frags[0].page = page_info->page;
  602. skb_shinfo(skb)->frags[0].page_offset =
  603. page_info->page_offset + hdr_len;
  604. skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
  605. skb->data_len = curr_frag_len - hdr_len;
  606. skb->tail += hdr_len;
  607. }
  608. page_info->page = NULL;
  609. if (pktsize <= rx_frag_size) {
  610. BUG_ON(num_rcvd != 1);
  611. goto done;
  612. }
  613. /* More frags present for this completion */
  614. size = pktsize;
  615. for (i = 1, j = 0; i < num_rcvd; i++) {
  616. size -= curr_frag_len;
  617. index_inc(&rxq_idx, rxq->len);
  618. page_info = get_rx_page_info(adapter, rxq_idx);
  619. curr_frag_len = min(size, rx_frag_size);
  620. /* Coalesce all frags from the same physical page in one slot */
  621. if (page_info->page_offset == 0) {
  622. /* Fresh page */
  623. j++;
  624. skb_shinfo(skb)->frags[j].page = page_info->page;
  625. skb_shinfo(skb)->frags[j].page_offset =
  626. page_info->page_offset;
  627. skb_shinfo(skb)->frags[j].size = 0;
  628. skb_shinfo(skb)->nr_frags++;
  629. } else {
  630. put_page(page_info->page);
  631. }
  632. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  633. skb->len += curr_frag_len;
  634. skb->data_len += curr_frag_len;
  635. page_info->page = NULL;
  636. }
  637. BUG_ON(j > MAX_SKB_FRAGS);
  638. done:
  639. be_rx_stats_update(adapter, pktsize, num_rcvd);
  640. return;
  641. }
  642. /* Process the RX completion indicated by rxcp when GRO is disabled */
  643. static void be_rx_compl_process(struct be_adapter *adapter,
  644. struct be_eth_rx_compl *rxcp)
  645. {
  646. struct sk_buff *skb;
  647. u32 vlanf, vid;
  648. u8 vtm;
  649. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  650. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  651. /* vlanf could be wrongly set in some cards.
  652. * ignore if vtm is not set */
  653. if ((adapter->cap & 0x400) && !vtm)
  654. vlanf = 0;
  655. skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
  656. if (!skb) {
  657. if (net_ratelimit())
  658. dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
  659. be_rx_compl_discard(adapter, rxcp);
  660. return;
  661. }
  662. skb_fill_rx_data(adapter, skb, rxcp);
  663. if (do_pkt_csum(rxcp, adapter->rx_csum))
  664. skb->ip_summed = CHECKSUM_NONE;
  665. else
  666. skb->ip_summed = CHECKSUM_UNNECESSARY;
  667. skb->truesize = skb->len + sizeof(struct sk_buff);
  668. skb->protocol = eth_type_trans(skb, adapter->netdev);
  669. skb->dev = adapter->netdev;
  670. if (vlanf) {
  671. if (!adapter->vlan_grp || adapter->vlans_added == 0) {
  672. kfree_skb(skb);
  673. return;
  674. }
  675. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  676. vid = be16_to_cpu(vid);
  677. vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
  678. } else {
  679. netif_receive_skb(skb);
  680. }
  681. return;
  682. }
  683. /* Process the RX completion indicated by rxcp when GRO is enabled */
  684. static void be_rx_compl_process_gro(struct be_adapter *adapter,
  685. struct be_eth_rx_compl *rxcp)
  686. {
  687. struct be_rx_page_info *page_info;
  688. struct sk_buff *skb = NULL;
  689. struct be_queue_info *rxq = &adapter->rx_obj.q;
  690. struct be_eq_obj *eq_obj = &adapter->rx_eq;
  691. u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
  692. u16 i, rxq_idx = 0, vid, j;
  693. u8 vtm;
  694. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  695. pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  696. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  697. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  698. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  699. /* vlanf could be wrongly set in some cards.
  700. * ignore if vtm is not set */
  701. if ((adapter->cap & 0x400) && !vtm)
  702. vlanf = 0;
  703. skb = napi_get_frags(&eq_obj->napi);
  704. if (!skb) {
  705. be_rx_compl_discard(adapter, rxcp);
  706. return;
  707. }
  708. remaining = pkt_size;
  709. for (i = 0, j = -1; i < num_rcvd; i++) {
  710. page_info = get_rx_page_info(adapter, rxq_idx);
  711. curr_frag_len = min(remaining, rx_frag_size);
  712. /* Coalesce all frags from the same physical page in one slot */
  713. if (i == 0 || page_info->page_offset == 0) {
  714. /* First frag or Fresh page */
  715. j++;
  716. skb_shinfo(skb)->frags[j].page = page_info->page;
  717. skb_shinfo(skb)->frags[j].page_offset =
  718. page_info->page_offset;
  719. skb_shinfo(skb)->frags[j].size = 0;
  720. } else {
  721. put_page(page_info->page);
  722. }
  723. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  724. remaining -= curr_frag_len;
  725. index_inc(&rxq_idx, rxq->len);
  726. memset(page_info, 0, sizeof(*page_info));
  727. }
  728. BUG_ON(j > MAX_SKB_FRAGS);
  729. skb_shinfo(skb)->nr_frags = j + 1;
  730. skb->len = pkt_size;
  731. skb->data_len = pkt_size;
  732. skb->truesize += pkt_size;
  733. skb->ip_summed = CHECKSUM_UNNECESSARY;
  734. if (likely(!vlanf)) {
  735. napi_gro_frags(&eq_obj->napi);
  736. } else {
  737. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  738. vid = be16_to_cpu(vid);
  739. if (!adapter->vlan_grp || adapter->vlans_added == 0)
  740. return;
  741. vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
  742. }
  743. be_rx_stats_update(adapter, pkt_size, num_rcvd);
  744. return;
  745. }
  746. static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
  747. {
  748. struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
  749. if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
  750. return NULL;
  751. be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
  752. queue_tail_inc(&adapter->rx_obj.cq);
  753. return rxcp;
  754. }
  755. /* To reset the valid bit, we need to reset the whole word as
  756. * when walking the queue the valid entries are little-endian
  757. * and invalid entries are host endian
  758. */
  759. static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
  760. {
  761. rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
  762. }
  763. static inline struct page *be_alloc_pages(u32 size)
  764. {
  765. gfp_t alloc_flags = GFP_ATOMIC;
  766. u32 order = get_order(size);
  767. if (order > 0)
  768. alloc_flags |= __GFP_COMP;
  769. return alloc_pages(alloc_flags, order);
  770. }
  771. /*
  772. * Allocate a page, split it to fragments of size rx_frag_size and post as
  773. * receive buffers to BE
  774. */
  775. static void be_post_rx_frags(struct be_adapter *adapter)
  776. {
  777. struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
  778. struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
  779. struct be_queue_info *rxq = &adapter->rx_obj.q;
  780. struct page *pagep = NULL;
  781. struct be_eth_rx_d *rxd;
  782. u64 page_dmaaddr = 0, frag_dmaaddr;
  783. u32 posted, page_offset = 0;
  784. page_info = &page_info_tbl[rxq->head];
  785. for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
  786. if (!pagep) {
  787. pagep = be_alloc_pages(adapter->big_page_size);
  788. if (unlikely(!pagep)) {
  789. drvr_stats(adapter)->be_ethrx_post_fail++;
  790. break;
  791. }
  792. page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
  793. adapter->big_page_size,
  794. PCI_DMA_FROMDEVICE);
  795. page_info->page_offset = 0;
  796. } else {
  797. get_page(pagep);
  798. page_info->page_offset = page_offset + rx_frag_size;
  799. }
  800. page_offset = page_info->page_offset;
  801. page_info->page = pagep;
  802. pci_unmap_addr_set(page_info, bus, page_dmaaddr);
  803. frag_dmaaddr = page_dmaaddr + page_info->page_offset;
  804. rxd = queue_head_node(rxq);
  805. rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
  806. rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
  807. /* Any space left in the current big page for another frag? */
  808. if ((page_offset + rx_frag_size + rx_frag_size) >
  809. adapter->big_page_size) {
  810. pagep = NULL;
  811. page_info->last_page_user = true;
  812. }
  813. prev_page_info = page_info;
  814. queue_head_inc(rxq);
  815. page_info = &page_info_tbl[rxq->head];
  816. }
  817. if (pagep)
  818. prev_page_info->last_page_user = true;
  819. if (posted) {
  820. atomic_add(posted, &rxq->used);
  821. be_rxq_notify(adapter, rxq->id, posted);
  822. } else if (atomic_read(&rxq->used) == 0) {
  823. /* Let be_worker replenish when memory is available */
  824. adapter->rx_post_starved = true;
  825. }
  826. return;
  827. }
  828. static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
  829. {
  830. struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
  831. if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
  832. return NULL;
  833. be_dws_le_to_cpu(txcp, sizeof(*txcp));
  834. txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
  835. queue_tail_inc(tx_cq);
  836. return txcp;
  837. }
  838. static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
  839. {
  840. struct be_queue_info *txq = &adapter->tx_obj.q;
  841. struct be_eth_wrb *wrb;
  842. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  843. struct sk_buff *sent_skb;
  844. u64 busaddr;
  845. u16 cur_index, num_wrbs = 0;
  846. cur_index = txq->tail;
  847. sent_skb = sent_skbs[cur_index];
  848. BUG_ON(!sent_skb);
  849. sent_skbs[cur_index] = NULL;
  850. wrb = queue_tail_node(txq);
  851. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  852. busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
  853. if (busaddr != 0) {
  854. pci_unmap_single(adapter->pdev, busaddr,
  855. wrb->frag_len, PCI_DMA_TODEVICE);
  856. }
  857. num_wrbs++;
  858. queue_tail_inc(txq);
  859. while (cur_index != last_index) {
  860. cur_index = txq->tail;
  861. wrb = queue_tail_node(txq);
  862. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  863. busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
  864. if (busaddr != 0) {
  865. pci_unmap_page(adapter->pdev, busaddr,
  866. wrb->frag_len, PCI_DMA_TODEVICE);
  867. }
  868. num_wrbs++;
  869. queue_tail_inc(txq);
  870. }
  871. atomic_sub(num_wrbs, &txq->used);
  872. kfree_skb(sent_skb);
  873. }
  874. static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
  875. {
  876. struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
  877. if (!eqe->evt)
  878. return NULL;
  879. eqe->evt = le32_to_cpu(eqe->evt);
  880. queue_tail_inc(&eq_obj->q);
  881. return eqe;
  882. }
  883. static int event_handle(struct be_adapter *adapter,
  884. struct be_eq_obj *eq_obj)
  885. {
  886. struct be_eq_entry *eqe;
  887. u16 num = 0;
  888. while ((eqe = event_get(eq_obj)) != NULL) {
  889. eqe->evt = 0;
  890. num++;
  891. }
  892. /* Deal with any spurious interrupts that come
  893. * without events
  894. */
  895. be_eq_notify(adapter, eq_obj->q.id, true, true, num);
  896. if (num)
  897. napi_schedule(&eq_obj->napi);
  898. return num;
  899. }
  900. /* Just read and notify events without processing them.
  901. * Used at the time of destroying event queues */
  902. static void be_eq_clean(struct be_adapter *adapter,
  903. struct be_eq_obj *eq_obj)
  904. {
  905. struct be_eq_entry *eqe;
  906. u16 num = 0;
  907. while ((eqe = event_get(eq_obj)) != NULL) {
  908. eqe->evt = 0;
  909. num++;
  910. }
  911. if (num)
  912. be_eq_notify(adapter, eq_obj->q.id, false, true, num);
  913. }
  914. static void be_rx_q_clean(struct be_adapter *adapter)
  915. {
  916. struct be_rx_page_info *page_info;
  917. struct be_queue_info *rxq = &adapter->rx_obj.q;
  918. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  919. struct be_eth_rx_compl *rxcp;
  920. u16 tail;
  921. /* First cleanup pending rx completions */
  922. while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
  923. be_rx_compl_discard(adapter, rxcp);
  924. be_rx_compl_reset(rxcp);
  925. be_cq_notify(adapter, rx_cq->id, true, 1);
  926. }
  927. /* Then free posted rx buffer that were not used */
  928. tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
  929. for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
  930. page_info = get_rx_page_info(adapter, tail);
  931. put_page(page_info->page);
  932. memset(page_info, 0, sizeof(*page_info));
  933. }
  934. BUG_ON(atomic_read(&rxq->used));
  935. }
  936. static void be_tx_compl_clean(struct be_adapter *adapter)
  937. {
  938. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  939. struct be_queue_info *txq = &adapter->tx_obj.q;
  940. struct be_eth_tx_compl *txcp;
  941. u16 end_idx, cmpl = 0, timeo = 0;
  942. /* Wait for a max of 200ms for all the tx-completions to arrive. */
  943. do {
  944. while ((txcp = be_tx_compl_get(tx_cq))) {
  945. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  946. wrb_index, txcp);
  947. be_tx_compl_process(adapter, end_idx);
  948. cmpl++;
  949. }
  950. if (cmpl) {
  951. be_cq_notify(adapter, tx_cq->id, false, cmpl);
  952. cmpl = 0;
  953. }
  954. if (atomic_read(&txq->used) == 0 || ++timeo > 200)
  955. break;
  956. mdelay(1);
  957. } while (true);
  958. if (atomic_read(&txq->used))
  959. dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
  960. atomic_read(&txq->used));
  961. }
  962. static void be_mcc_queues_destroy(struct be_adapter *adapter)
  963. {
  964. struct be_queue_info *q;
  965. q = &adapter->mcc_obj.q;
  966. if (q->created)
  967. be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
  968. be_queue_free(adapter, q);
  969. q = &adapter->mcc_obj.cq;
  970. if (q->created)
  971. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  972. be_queue_free(adapter, q);
  973. }
  974. /* Must be called only after TX qs are created as MCC shares TX EQ */
  975. static int be_mcc_queues_create(struct be_adapter *adapter)
  976. {
  977. struct be_queue_info *q, *cq;
  978. /* Alloc MCC compl queue */
  979. cq = &adapter->mcc_obj.cq;
  980. if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
  981. sizeof(struct be_mcc_compl)))
  982. goto err;
  983. /* Ask BE to create MCC compl queue; share TX's eq */
  984. if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
  985. goto mcc_cq_free;
  986. /* Alloc MCC queue */
  987. q = &adapter->mcc_obj.q;
  988. if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  989. goto mcc_cq_destroy;
  990. /* Ask BE to create MCC queue */
  991. if (be_cmd_mccq_create(adapter, q, cq))
  992. goto mcc_q_free;
  993. return 0;
  994. mcc_q_free:
  995. be_queue_free(adapter, q);
  996. mcc_cq_destroy:
  997. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  998. mcc_cq_free:
  999. be_queue_free(adapter, cq);
  1000. err:
  1001. return -1;
  1002. }
  1003. static void be_tx_queues_destroy(struct be_adapter *adapter)
  1004. {
  1005. struct be_queue_info *q;
  1006. q = &adapter->tx_obj.q;
  1007. if (q->created)
  1008. be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
  1009. be_queue_free(adapter, q);
  1010. q = &adapter->tx_obj.cq;
  1011. if (q->created)
  1012. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1013. be_queue_free(adapter, q);
  1014. /* Clear any residual events */
  1015. be_eq_clean(adapter, &adapter->tx_eq);
  1016. q = &adapter->tx_eq.q;
  1017. if (q->created)
  1018. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1019. be_queue_free(adapter, q);
  1020. }
  1021. static int be_tx_queues_create(struct be_adapter *adapter)
  1022. {
  1023. struct be_queue_info *eq, *q, *cq;
  1024. adapter->tx_eq.max_eqd = 0;
  1025. adapter->tx_eq.min_eqd = 0;
  1026. adapter->tx_eq.cur_eqd = 96;
  1027. adapter->tx_eq.enable_aic = false;
  1028. /* Alloc Tx Event queue */
  1029. eq = &adapter->tx_eq.q;
  1030. if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
  1031. return -1;
  1032. /* Ask BE to create Tx Event queue */
  1033. if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
  1034. goto tx_eq_free;
  1035. /* Alloc TX eth compl queue */
  1036. cq = &adapter->tx_obj.cq;
  1037. if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
  1038. sizeof(struct be_eth_tx_compl)))
  1039. goto tx_eq_destroy;
  1040. /* Ask BE to create Tx eth compl queue */
  1041. if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
  1042. goto tx_cq_free;
  1043. /* Alloc TX eth queue */
  1044. q = &adapter->tx_obj.q;
  1045. if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
  1046. goto tx_cq_destroy;
  1047. /* Ask BE to create Tx eth queue */
  1048. if (be_cmd_txq_create(adapter, q, cq))
  1049. goto tx_q_free;
  1050. return 0;
  1051. tx_q_free:
  1052. be_queue_free(adapter, q);
  1053. tx_cq_destroy:
  1054. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1055. tx_cq_free:
  1056. be_queue_free(adapter, cq);
  1057. tx_eq_destroy:
  1058. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1059. tx_eq_free:
  1060. be_queue_free(adapter, eq);
  1061. return -1;
  1062. }
  1063. static void be_rx_queues_destroy(struct be_adapter *adapter)
  1064. {
  1065. struct be_queue_info *q;
  1066. q = &adapter->rx_obj.q;
  1067. if (q->created) {
  1068. be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
  1069. be_rx_q_clean(adapter);
  1070. }
  1071. be_queue_free(adapter, q);
  1072. q = &adapter->rx_obj.cq;
  1073. if (q->created)
  1074. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1075. be_queue_free(adapter, q);
  1076. /* Clear any residual events */
  1077. be_eq_clean(adapter, &adapter->rx_eq);
  1078. q = &adapter->rx_eq.q;
  1079. if (q->created)
  1080. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1081. be_queue_free(adapter, q);
  1082. }
  1083. static int be_rx_queues_create(struct be_adapter *adapter)
  1084. {
  1085. struct be_queue_info *eq, *q, *cq;
  1086. int rc;
  1087. adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
  1088. adapter->rx_eq.max_eqd = BE_MAX_EQD;
  1089. adapter->rx_eq.min_eqd = 0;
  1090. adapter->rx_eq.cur_eqd = 0;
  1091. adapter->rx_eq.enable_aic = true;
  1092. /* Alloc Rx Event queue */
  1093. eq = &adapter->rx_eq.q;
  1094. rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
  1095. sizeof(struct be_eq_entry));
  1096. if (rc)
  1097. return rc;
  1098. /* Ask BE to create Rx Event queue */
  1099. rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
  1100. if (rc)
  1101. goto rx_eq_free;
  1102. /* Alloc RX eth compl queue */
  1103. cq = &adapter->rx_obj.cq;
  1104. rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
  1105. sizeof(struct be_eth_rx_compl));
  1106. if (rc)
  1107. goto rx_eq_destroy;
  1108. /* Ask BE to create Rx eth compl queue */
  1109. rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
  1110. if (rc)
  1111. goto rx_cq_free;
  1112. /* Alloc RX eth queue */
  1113. q = &adapter->rx_obj.q;
  1114. rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
  1115. if (rc)
  1116. goto rx_cq_destroy;
  1117. /* Ask BE to create Rx eth queue */
  1118. rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
  1119. BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
  1120. if (rc)
  1121. goto rx_q_free;
  1122. return 0;
  1123. rx_q_free:
  1124. be_queue_free(adapter, q);
  1125. rx_cq_destroy:
  1126. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1127. rx_cq_free:
  1128. be_queue_free(adapter, cq);
  1129. rx_eq_destroy:
  1130. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1131. rx_eq_free:
  1132. be_queue_free(adapter, eq);
  1133. return rc;
  1134. }
  1135. /* There are 8 evt ids per func. Retruns the evt id's bit number */
  1136. static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
  1137. {
  1138. return eq_id - 8 * be_pci_func(adapter);
  1139. }
  1140. static irqreturn_t be_intx(int irq, void *dev)
  1141. {
  1142. struct be_adapter *adapter = dev;
  1143. int isr;
  1144. isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
  1145. (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
  1146. if (!isr)
  1147. return IRQ_NONE;
  1148. event_handle(adapter, &adapter->tx_eq);
  1149. event_handle(adapter, &adapter->rx_eq);
  1150. return IRQ_HANDLED;
  1151. }
  1152. static irqreturn_t be_msix_rx(int irq, void *dev)
  1153. {
  1154. struct be_adapter *adapter = dev;
  1155. event_handle(adapter, &adapter->rx_eq);
  1156. return IRQ_HANDLED;
  1157. }
  1158. static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
  1159. {
  1160. struct be_adapter *adapter = dev;
  1161. event_handle(adapter, &adapter->tx_eq);
  1162. return IRQ_HANDLED;
  1163. }
  1164. static inline bool do_gro(struct be_adapter *adapter,
  1165. struct be_eth_rx_compl *rxcp)
  1166. {
  1167. int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
  1168. int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  1169. if (err)
  1170. drvr_stats(adapter)->be_rxcp_err++;
  1171. return (tcp_frame && !err) ? true : false;
  1172. }
  1173. int be_poll_rx(struct napi_struct *napi, int budget)
  1174. {
  1175. struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
  1176. struct be_adapter *adapter =
  1177. container_of(rx_eq, struct be_adapter, rx_eq);
  1178. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  1179. struct be_eth_rx_compl *rxcp;
  1180. u32 work_done;
  1181. adapter->stats.drvr_stats.be_rx_polls++;
  1182. for (work_done = 0; work_done < budget; work_done++) {
  1183. rxcp = be_rx_compl_get(adapter);
  1184. if (!rxcp)
  1185. break;
  1186. if (do_gro(adapter, rxcp))
  1187. be_rx_compl_process_gro(adapter, rxcp);
  1188. else
  1189. be_rx_compl_process(adapter, rxcp);
  1190. be_rx_compl_reset(rxcp);
  1191. }
  1192. /* Refill the queue */
  1193. if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
  1194. be_post_rx_frags(adapter);
  1195. /* All consumed */
  1196. if (work_done < budget) {
  1197. napi_complete(napi);
  1198. be_cq_notify(adapter, rx_cq->id, true, work_done);
  1199. } else {
  1200. /* More to be consumed; continue with interrupts disabled */
  1201. be_cq_notify(adapter, rx_cq->id, false, work_done);
  1202. }
  1203. return work_done;
  1204. }
  1205. void be_process_tx(struct be_adapter *adapter)
  1206. {
  1207. struct be_queue_info *txq = &adapter->tx_obj.q;
  1208. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1209. struct be_eth_tx_compl *txcp;
  1210. u32 num_cmpl = 0;
  1211. u16 end_idx;
  1212. while ((txcp = be_tx_compl_get(tx_cq))) {
  1213. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1214. wrb_index, txcp);
  1215. be_tx_compl_process(adapter, end_idx);
  1216. num_cmpl++;
  1217. }
  1218. if (num_cmpl) {
  1219. be_cq_notify(adapter, tx_cq->id, true, num_cmpl);
  1220. /* As Tx wrbs have been freed up, wake up netdev queue if
  1221. * it was stopped due to lack of tx wrbs.
  1222. */
  1223. if (netif_queue_stopped(adapter->netdev) &&
  1224. atomic_read(&txq->used) < txq->len / 2) {
  1225. netif_wake_queue(adapter->netdev);
  1226. }
  1227. drvr_stats(adapter)->be_tx_events++;
  1228. drvr_stats(adapter)->be_tx_compl += num_cmpl;
  1229. }
  1230. }
  1231. /* As TX and MCC share the same EQ check for both TX and MCC completions.
  1232. * For TX/MCC we don't honour budget; consume everything
  1233. */
  1234. static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
  1235. {
  1236. struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
  1237. struct be_adapter *adapter =
  1238. container_of(tx_eq, struct be_adapter, tx_eq);
  1239. napi_complete(napi);
  1240. be_process_tx(adapter);
  1241. be_process_mcc(adapter);
  1242. return 1;
  1243. }
  1244. static void be_worker(struct work_struct *work)
  1245. {
  1246. struct be_adapter *adapter =
  1247. container_of(work, struct be_adapter, work.work);
  1248. be_cmd_get_stats(adapter, &adapter->stats.cmd);
  1249. /* Set EQ delay */
  1250. be_rx_eqd_update(adapter);
  1251. be_tx_rate_update(adapter);
  1252. be_rx_rate_update(adapter);
  1253. if (adapter->rx_post_starved) {
  1254. adapter->rx_post_starved = false;
  1255. be_post_rx_frags(adapter);
  1256. }
  1257. schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
  1258. }
  1259. static void be_msix_disable(struct be_adapter *adapter)
  1260. {
  1261. if (adapter->msix_enabled) {
  1262. pci_disable_msix(adapter->pdev);
  1263. adapter->msix_enabled = false;
  1264. }
  1265. }
  1266. static void be_msix_enable(struct be_adapter *adapter)
  1267. {
  1268. int i, status;
  1269. for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
  1270. adapter->msix_entries[i].entry = i;
  1271. status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
  1272. BE_NUM_MSIX_VECTORS);
  1273. if (status == 0)
  1274. adapter->msix_enabled = true;
  1275. return;
  1276. }
  1277. static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
  1278. {
  1279. return adapter->msix_entries[
  1280. be_evt_bit_get(adapter, eq_id)].vector;
  1281. }
  1282. static int be_request_irq(struct be_adapter *adapter,
  1283. struct be_eq_obj *eq_obj,
  1284. void *handler, char *desc)
  1285. {
  1286. struct net_device *netdev = adapter->netdev;
  1287. int vec;
  1288. sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
  1289. vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1290. return request_irq(vec, handler, 0, eq_obj->desc, adapter);
  1291. }
  1292. static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
  1293. {
  1294. int vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1295. free_irq(vec, adapter);
  1296. }
  1297. static int be_msix_register(struct be_adapter *adapter)
  1298. {
  1299. int status;
  1300. status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
  1301. if (status)
  1302. goto err;
  1303. status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
  1304. if (status)
  1305. goto free_tx_irq;
  1306. return 0;
  1307. free_tx_irq:
  1308. be_free_irq(adapter, &adapter->tx_eq);
  1309. err:
  1310. dev_warn(&adapter->pdev->dev,
  1311. "MSIX Request IRQ failed - err %d\n", status);
  1312. pci_disable_msix(adapter->pdev);
  1313. adapter->msix_enabled = false;
  1314. return status;
  1315. }
  1316. static int be_irq_register(struct be_adapter *adapter)
  1317. {
  1318. struct net_device *netdev = adapter->netdev;
  1319. int status;
  1320. if (adapter->msix_enabled) {
  1321. status = be_msix_register(adapter);
  1322. if (status == 0)
  1323. goto done;
  1324. }
  1325. /* INTx */
  1326. netdev->irq = adapter->pdev->irq;
  1327. status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
  1328. adapter);
  1329. if (status) {
  1330. dev_err(&adapter->pdev->dev,
  1331. "INTx request IRQ failed - err %d\n", status);
  1332. return status;
  1333. }
  1334. done:
  1335. adapter->isr_registered = true;
  1336. return 0;
  1337. }
  1338. static void be_irq_unregister(struct be_adapter *adapter)
  1339. {
  1340. struct net_device *netdev = adapter->netdev;
  1341. if (!adapter->isr_registered)
  1342. return;
  1343. /* INTx */
  1344. if (!adapter->msix_enabled) {
  1345. free_irq(netdev->irq, adapter);
  1346. goto done;
  1347. }
  1348. /* MSIx */
  1349. be_free_irq(adapter, &adapter->tx_eq);
  1350. be_free_irq(adapter, &adapter->rx_eq);
  1351. done:
  1352. adapter->isr_registered = false;
  1353. return;
  1354. }
  1355. static int be_open(struct net_device *netdev)
  1356. {
  1357. struct be_adapter *adapter = netdev_priv(netdev);
  1358. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1359. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1360. bool link_up;
  1361. int status;
  1362. u8 mac_speed;
  1363. u16 link_speed;
  1364. /* First time posting */
  1365. be_post_rx_frags(adapter);
  1366. napi_enable(&rx_eq->napi);
  1367. napi_enable(&tx_eq->napi);
  1368. be_irq_register(adapter);
  1369. be_intr_set(adapter, true);
  1370. /* The evt queues are created in unarmed state; arm them */
  1371. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  1372. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  1373. /* Rx compl queue may be in unarmed state; rearm it */
  1374. be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
  1375. status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
  1376. &link_speed);
  1377. if (status)
  1378. goto ret_sts;
  1379. be_link_status_update(adapter, link_up);
  1380. status = be_vid_config(adapter);
  1381. if (status)
  1382. goto ret_sts;
  1383. status = be_cmd_set_flow_control(adapter,
  1384. adapter->tx_fc, adapter->rx_fc);
  1385. if (status)
  1386. goto ret_sts;
  1387. schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
  1388. ret_sts:
  1389. return status;
  1390. }
  1391. static int be_setup_wol(struct be_adapter *adapter, bool enable)
  1392. {
  1393. struct be_dma_mem cmd;
  1394. int status = 0;
  1395. u8 mac[ETH_ALEN];
  1396. memset(mac, 0, ETH_ALEN);
  1397. cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
  1398. cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
  1399. if (cmd.va == NULL)
  1400. return -1;
  1401. memset(cmd.va, 0, cmd.size);
  1402. if (enable) {
  1403. status = pci_write_config_dword(adapter->pdev,
  1404. PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
  1405. if (status) {
  1406. dev_err(&adapter->pdev->dev,
  1407. "Could not enable Wake-on-lan \n");
  1408. pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
  1409. cmd.dma);
  1410. return status;
  1411. }
  1412. status = be_cmd_enable_magic_wol(adapter,
  1413. adapter->netdev->dev_addr, &cmd);
  1414. pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
  1415. pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
  1416. } else {
  1417. status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
  1418. pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
  1419. pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
  1420. }
  1421. pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
  1422. return status;
  1423. }
  1424. static int be_setup(struct be_adapter *adapter)
  1425. {
  1426. struct net_device *netdev = adapter->netdev;
  1427. u32 cap_flags, en_flags;
  1428. int status;
  1429. cap_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
  1430. BE_IF_FLAGS_MCAST_PROMISCUOUS |
  1431. BE_IF_FLAGS_PROMISCUOUS |
  1432. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1433. en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
  1434. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1435. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1436. netdev->dev_addr, false/* pmac_invalid */,
  1437. &adapter->if_handle, &adapter->pmac_id);
  1438. if (status != 0)
  1439. goto do_none;
  1440. status = be_tx_queues_create(adapter);
  1441. if (status != 0)
  1442. goto if_destroy;
  1443. status = be_rx_queues_create(adapter);
  1444. if (status != 0)
  1445. goto tx_qs_destroy;
  1446. status = be_mcc_queues_create(adapter);
  1447. if (status != 0)
  1448. goto rx_qs_destroy;
  1449. adapter->link_speed = -1;
  1450. return 0;
  1451. rx_qs_destroy:
  1452. be_rx_queues_destroy(adapter);
  1453. tx_qs_destroy:
  1454. be_tx_queues_destroy(adapter);
  1455. if_destroy:
  1456. be_cmd_if_destroy(adapter, adapter->if_handle);
  1457. do_none:
  1458. return status;
  1459. }
  1460. static int be_clear(struct be_adapter *adapter)
  1461. {
  1462. be_mcc_queues_destroy(adapter);
  1463. be_rx_queues_destroy(adapter);
  1464. be_tx_queues_destroy(adapter);
  1465. be_cmd_if_destroy(adapter, adapter->if_handle);
  1466. /* tell fw we're done with firing cmds */
  1467. be_cmd_fw_clean(adapter);
  1468. return 0;
  1469. }
  1470. static int be_close(struct net_device *netdev)
  1471. {
  1472. struct be_adapter *adapter = netdev_priv(netdev);
  1473. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1474. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1475. int vec;
  1476. cancel_delayed_work_sync(&adapter->work);
  1477. netif_stop_queue(netdev);
  1478. netif_carrier_off(netdev);
  1479. adapter->link_up = false;
  1480. be_intr_set(adapter, false);
  1481. if (adapter->msix_enabled) {
  1482. vec = be_msix_vec_get(adapter, tx_eq->q.id);
  1483. synchronize_irq(vec);
  1484. vec = be_msix_vec_get(adapter, rx_eq->q.id);
  1485. synchronize_irq(vec);
  1486. } else {
  1487. synchronize_irq(netdev->irq);
  1488. }
  1489. be_irq_unregister(adapter);
  1490. napi_disable(&rx_eq->napi);
  1491. napi_disable(&tx_eq->napi);
  1492. /* Wait for all pending tx completions to arrive so that
  1493. * all tx skbs are freed.
  1494. */
  1495. be_tx_compl_clean(adapter);
  1496. return 0;
  1497. }
  1498. #define FW_FILE_HDR_SIGN "ServerEngines Corp. "
  1499. char flash_cookie[2][16] = {"*** SE FLAS",
  1500. "H DIRECTORY *** "};
  1501. static bool be_flash_redboot(struct be_adapter *adapter,
  1502. const u8 *p, u32 img_start, int image_size,
  1503. int hdr_size)
  1504. {
  1505. u32 crc_offset;
  1506. u8 flashed_crc[4];
  1507. int status;
  1508. crc_offset = hdr_size + img_start + image_size - 4;
  1509. p += crc_offset;
  1510. status = be_cmd_get_flash_crc(adapter, flashed_crc,
  1511. (img_start + image_size - 4));
  1512. if (status) {
  1513. dev_err(&adapter->pdev->dev,
  1514. "could not get crc from flash, not flashing redboot\n");
  1515. return false;
  1516. }
  1517. /*update redboot only if crc does not match*/
  1518. if (!memcmp(flashed_crc, p, 4))
  1519. return false;
  1520. else
  1521. return true;
  1522. }
  1523. static int be_flash_data(struct be_adapter *adapter,
  1524. const struct firmware *fw,
  1525. struct be_dma_mem *flash_cmd, int num_of_images)
  1526. {
  1527. int status = 0, i, filehdr_size = 0;
  1528. u32 total_bytes = 0, flash_op;
  1529. int num_bytes;
  1530. const u8 *p = fw->data;
  1531. struct be_cmd_write_flashrom *req = flash_cmd->va;
  1532. struct flash_comp *pflashcomp;
  1533. struct flash_comp gen3_flash_types[8] = {
  1534. { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
  1535. FLASH_IMAGE_MAX_SIZE_g3},
  1536. { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
  1537. FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
  1538. { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
  1539. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1540. { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
  1541. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1542. { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
  1543. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1544. { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
  1545. FLASH_IMAGE_MAX_SIZE_g3},
  1546. { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
  1547. FLASH_IMAGE_MAX_SIZE_g3},
  1548. { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
  1549. FLASH_IMAGE_MAX_SIZE_g3}
  1550. };
  1551. struct flash_comp gen2_flash_types[8] = {
  1552. { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
  1553. FLASH_IMAGE_MAX_SIZE_g2},
  1554. { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
  1555. FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
  1556. { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
  1557. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1558. { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
  1559. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1560. { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
  1561. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1562. { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
  1563. FLASH_IMAGE_MAX_SIZE_g2},
  1564. { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
  1565. FLASH_IMAGE_MAX_SIZE_g2},
  1566. { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
  1567. FLASH_IMAGE_MAX_SIZE_g2}
  1568. };
  1569. if (adapter->generation == BE_GEN3) {
  1570. pflashcomp = gen3_flash_types;
  1571. filehdr_size = sizeof(struct flash_file_hdr_g3);
  1572. } else {
  1573. pflashcomp = gen2_flash_types;
  1574. filehdr_size = sizeof(struct flash_file_hdr_g2);
  1575. }
  1576. for (i = 0; i < 8; i++) {
  1577. if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
  1578. (!be_flash_redboot(adapter, fw->data,
  1579. pflashcomp[i].offset, pflashcomp[i].size,
  1580. filehdr_size)))
  1581. continue;
  1582. p = fw->data;
  1583. p += filehdr_size + pflashcomp[i].offset
  1584. + (num_of_images * sizeof(struct image_hdr));
  1585. if (p + pflashcomp[i].size > fw->data + fw->size)
  1586. return -1;
  1587. total_bytes = pflashcomp[i].size;
  1588. while (total_bytes) {
  1589. if (total_bytes > 32*1024)
  1590. num_bytes = 32*1024;
  1591. else
  1592. num_bytes = total_bytes;
  1593. total_bytes -= num_bytes;
  1594. if (!total_bytes)
  1595. flash_op = FLASHROM_OPER_FLASH;
  1596. else
  1597. flash_op = FLASHROM_OPER_SAVE;
  1598. memcpy(req->params.data_buf, p, num_bytes);
  1599. p += num_bytes;
  1600. status = be_cmd_write_flashrom(adapter, flash_cmd,
  1601. pflashcomp[i].optype, flash_op, num_bytes);
  1602. if (status) {
  1603. dev_err(&adapter->pdev->dev,
  1604. "cmd to write to flash rom failed.\n");
  1605. return -1;
  1606. }
  1607. yield();
  1608. }
  1609. }
  1610. return 0;
  1611. }
  1612. static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
  1613. {
  1614. if (fhdr == NULL)
  1615. return 0;
  1616. if (fhdr->build[0] == '3')
  1617. return BE_GEN3;
  1618. else if (fhdr->build[0] == '2')
  1619. return BE_GEN2;
  1620. else
  1621. return 0;
  1622. }
  1623. int be_load_fw(struct be_adapter *adapter, u8 *func)
  1624. {
  1625. char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
  1626. const struct firmware *fw;
  1627. struct flash_file_hdr_g2 *fhdr;
  1628. struct flash_file_hdr_g3 *fhdr3;
  1629. struct image_hdr *img_hdr_ptr = NULL;
  1630. struct be_dma_mem flash_cmd;
  1631. int status, i = 0;
  1632. const u8 *p;
  1633. char fw_ver[FW_VER_LEN];
  1634. char fw_cfg;
  1635. status = be_cmd_get_fw_ver(adapter, fw_ver);
  1636. if (status)
  1637. return status;
  1638. fw_cfg = *(fw_ver + 2);
  1639. if (fw_cfg == '0')
  1640. fw_cfg = '1';
  1641. strcpy(fw_file, func);
  1642. status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
  1643. if (status)
  1644. goto fw_exit;
  1645. p = fw->data;
  1646. fhdr = (struct flash_file_hdr_g2 *) p;
  1647. dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
  1648. flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
  1649. flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
  1650. &flash_cmd.dma);
  1651. if (!flash_cmd.va) {
  1652. status = -ENOMEM;
  1653. dev_err(&adapter->pdev->dev,
  1654. "Memory allocation failure while flashing\n");
  1655. goto fw_exit;
  1656. }
  1657. if ((adapter->generation == BE_GEN3) &&
  1658. (get_ufigen_type(fhdr) == BE_GEN3)) {
  1659. fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
  1660. for (i = 0; i < fhdr3->num_imgs; i++) {
  1661. img_hdr_ptr = (struct image_hdr *) (fw->data +
  1662. (sizeof(struct flash_file_hdr_g3) +
  1663. i * sizeof(struct image_hdr)));
  1664. if (img_hdr_ptr->imageid == 1) {
  1665. status = be_flash_data(adapter, fw,
  1666. &flash_cmd, fhdr3->num_imgs);
  1667. }
  1668. }
  1669. } else if ((adapter->generation == BE_GEN2) &&
  1670. (get_ufigen_type(fhdr) == BE_GEN2)) {
  1671. status = be_flash_data(adapter, fw, &flash_cmd, 0);
  1672. } else {
  1673. dev_err(&adapter->pdev->dev,
  1674. "UFI and Interface are not compatible for flashing\n");
  1675. status = -1;
  1676. }
  1677. pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
  1678. flash_cmd.dma);
  1679. if (status) {
  1680. dev_err(&adapter->pdev->dev, "Firmware load error\n");
  1681. goto fw_exit;
  1682. }
  1683. dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
  1684. fw_exit:
  1685. release_firmware(fw);
  1686. return status;
  1687. }
  1688. static struct net_device_ops be_netdev_ops = {
  1689. .ndo_open = be_open,
  1690. .ndo_stop = be_close,
  1691. .ndo_start_xmit = be_xmit,
  1692. .ndo_get_stats = be_get_stats,
  1693. .ndo_set_rx_mode = be_set_multicast_list,
  1694. .ndo_set_mac_address = be_mac_addr_set,
  1695. .ndo_change_mtu = be_change_mtu,
  1696. .ndo_validate_addr = eth_validate_addr,
  1697. .ndo_vlan_rx_register = be_vlan_register,
  1698. .ndo_vlan_rx_add_vid = be_vlan_add_vid,
  1699. .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
  1700. };
  1701. static void be_netdev_init(struct net_device *netdev)
  1702. {
  1703. struct be_adapter *adapter = netdev_priv(netdev);
  1704. netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
  1705. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
  1706. NETIF_F_GRO;
  1707. netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
  1708. netdev->flags |= IFF_MULTICAST;
  1709. adapter->rx_csum = true;
  1710. /* Default settings for Rx and Tx flow control */
  1711. adapter->rx_fc = true;
  1712. adapter->tx_fc = true;
  1713. netif_set_gso_max_size(netdev, 65535);
  1714. BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
  1715. SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
  1716. netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
  1717. BE_NAPI_WEIGHT);
  1718. netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
  1719. BE_NAPI_WEIGHT);
  1720. netif_carrier_off(netdev);
  1721. netif_stop_queue(netdev);
  1722. }
  1723. static void be_unmap_pci_bars(struct be_adapter *adapter)
  1724. {
  1725. if (adapter->csr)
  1726. iounmap(adapter->csr);
  1727. if (adapter->db)
  1728. iounmap(adapter->db);
  1729. if (adapter->pcicfg)
  1730. iounmap(adapter->pcicfg);
  1731. }
  1732. static int be_map_pci_bars(struct be_adapter *adapter)
  1733. {
  1734. u8 __iomem *addr;
  1735. int pcicfg_reg;
  1736. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
  1737. pci_resource_len(adapter->pdev, 2));
  1738. if (addr == NULL)
  1739. return -ENOMEM;
  1740. adapter->csr = addr;
  1741. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4),
  1742. 128 * 1024);
  1743. if (addr == NULL)
  1744. goto pci_map_err;
  1745. adapter->db = addr;
  1746. if (adapter->generation == BE_GEN2)
  1747. pcicfg_reg = 1;
  1748. else
  1749. pcicfg_reg = 0;
  1750. addr = ioremap_nocache(pci_resource_start(adapter->pdev, pcicfg_reg),
  1751. pci_resource_len(adapter->pdev, pcicfg_reg));
  1752. if (addr == NULL)
  1753. goto pci_map_err;
  1754. adapter->pcicfg = addr;
  1755. return 0;
  1756. pci_map_err:
  1757. be_unmap_pci_bars(adapter);
  1758. return -ENOMEM;
  1759. }
  1760. static void be_ctrl_cleanup(struct be_adapter *adapter)
  1761. {
  1762. struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
  1763. be_unmap_pci_bars(adapter);
  1764. if (mem->va)
  1765. pci_free_consistent(adapter->pdev, mem->size,
  1766. mem->va, mem->dma);
  1767. mem = &adapter->mc_cmd_mem;
  1768. if (mem->va)
  1769. pci_free_consistent(adapter->pdev, mem->size,
  1770. mem->va, mem->dma);
  1771. }
  1772. static int be_ctrl_init(struct be_adapter *adapter)
  1773. {
  1774. struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
  1775. struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
  1776. struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
  1777. int status;
  1778. status = be_map_pci_bars(adapter);
  1779. if (status)
  1780. goto done;
  1781. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  1782. mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
  1783. mbox_mem_alloc->size, &mbox_mem_alloc->dma);
  1784. if (!mbox_mem_alloc->va) {
  1785. status = -ENOMEM;
  1786. goto unmap_pci_bars;
  1787. }
  1788. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  1789. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  1790. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  1791. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  1792. mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
  1793. mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
  1794. &mc_cmd_mem->dma);
  1795. if (mc_cmd_mem->va == NULL) {
  1796. status = -ENOMEM;
  1797. goto free_mbox;
  1798. }
  1799. memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
  1800. spin_lock_init(&adapter->mbox_lock);
  1801. spin_lock_init(&adapter->mcc_lock);
  1802. spin_lock_init(&adapter->mcc_cq_lock);
  1803. pci_save_state(adapter->pdev);
  1804. return 0;
  1805. free_mbox:
  1806. pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
  1807. mbox_mem_alloc->va, mbox_mem_alloc->dma);
  1808. unmap_pci_bars:
  1809. be_unmap_pci_bars(adapter);
  1810. done:
  1811. return status;
  1812. }
  1813. static void be_stats_cleanup(struct be_adapter *adapter)
  1814. {
  1815. struct be_stats_obj *stats = &adapter->stats;
  1816. struct be_dma_mem *cmd = &stats->cmd;
  1817. if (cmd->va)
  1818. pci_free_consistent(adapter->pdev, cmd->size,
  1819. cmd->va, cmd->dma);
  1820. }
  1821. static int be_stats_init(struct be_adapter *adapter)
  1822. {
  1823. struct be_stats_obj *stats = &adapter->stats;
  1824. struct be_dma_mem *cmd = &stats->cmd;
  1825. cmd->size = sizeof(struct be_cmd_req_get_stats);
  1826. cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
  1827. if (cmd->va == NULL)
  1828. return -1;
  1829. memset(cmd->va, 0, cmd->size);
  1830. return 0;
  1831. }
  1832. static void __devexit be_remove(struct pci_dev *pdev)
  1833. {
  1834. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1835. if (!adapter)
  1836. return;
  1837. unregister_netdev(adapter->netdev);
  1838. be_clear(adapter);
  1839. be_stats_cleanup(adapter);
  1840. be_ctrl_cleanup(adapter);
  1841. be_msix_disable(adapter);
  1842. pci_set_drvdata(pdev, NULL);
  1843. pci_release_regions(pdev);
  1844. pci_disable_device(pdev);
  1845. free_netdev(adapter->netdev);
  1846. }
  1847. static int be_get_config(struct be_adapter *adapter)
  1848. {
  1849. int status;
  1850. u8 mac[ETH_ALEN];
  1851. status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
  1852. if (status)
  1853. return status;
  1854. status = be_cmd_query_fw_cfg(adapter,
  1855. &adapter->port_num, &adapter->cap);
  1856. if (status)
  1857. return status;
  1858. memset(mac, 0, ETH_ALEN);
  1859. status = be_cmd_mac_addr_query(adapter, mac,
  1860. MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
  1861. if (status)
  1862. return status;
  1863. if (!is_valid_ether_addr(mac))
  1864. return -EADDRNOTAVAIL;
  1865. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  1866. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  1867. if (adapter->cap & 0x400)
  1868. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
  1869. else
  1870. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
  1871. return 0;
  1872. }
  1873. static int __devinit be_probe(struct pci_dev *pdev,
  1874. const struct pci_device_id *pdev_id)
  1875. {
  1876. int status = 0;
  1877. struct be_adapter *adapter;
  1878. struct net_device *netdev;
  1879. status = pci_enable_device(pdev);
  1880. if (status)
  1881. goto do_none;
  1882. status = pci_request_regions(pdev, DRV_NAME);
  1883. if (status)
  1884. goto disable_dev;
  1885. pci_set_master(pdev);
  1886. netdev = alloc_etherdev(sizeof(struct be_adapter));
  1887. if (netdev == NULL) {
  1888. status = -ENOMEM;
  1889. goto rel_reg;
  1890. }
  1891. adapter = netdev_priv(netdev);
  1892. switch (pdev->device) {
  1893. case BE_DEVICE_ID1:
  1894. case OC_DEVICE_ID1:
  1895. adapter->generation = BE_GEN2;
  1896. break;
  1897. case BE_DEVICE_ID2:
  1898. case OC_DEVICE_ID2:
  1899. adapter->generation = BE_GEN3;
  1900. break;
  1901. default:
  1902. adapter->generation = 0;
  1903. }
  1904. adapter->pdev = pdev;
  1905. pci_set_drvdata(pdev, adapter);
  1906. adapter->netdev = netdev;
  1907. be_netdev_init(netdev);
  1908. SET_NETDEV_DEV(netdev, &pdev->dev);
  1909. be_msix_enable(adapter);
  1910. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  1911. if (!status) {
  1912. netdev->features |= NETIF_F_HIGHDMA;
  1913. } else {
  1914. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1915. if (status) {
  1916. dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
  1917. goto free_netdev;
  1918. }
  1919. }
  1920. status = be_ctrl_init(adapter);
  1921. if (status)
  1922. goto free_netdev;
  1923. /* sync up with fw's ready state */
  1924. status = be_cmd_POST(adapter);
  1925. if (status)
  1926. goto ctrl_clean;
  1927. /* tell fw we're ready to fire cmds */
  1928. status = be_cmd_fw_init(adapter);
  1929. if (status)
  1930. goto ctrl_clean;
  1931. status = be_cmd_reset_function(adapter);
  1932. if (status)
  1933. goto ctrl_clean;
  1934. status = be_stats_init(adapter);
  1935. if (status)
  1936. goto ctrl_clean;
  1937. status = be_get_config(adapter);
  1938. if (status)
  1939. goto stats_clean;
  1940. INIT_DELAYED_WORK(&adapter->work, be_worker);
  1941. status = be_setup(adapter);
  1942. if (status)
  1943. goto stats_clean;
  1944. status = register_netdev(netdev);
  1945. if (status != 0)
  1946. goto unsetup;
  1947. dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
  1948. return 0;
  1949. unsetup:
  1950. be_clear(adapter);
  1951. stats_clean:
  1952. be_stats_cleanup(adapter);
  1953. ctrl_clean:
  1954. be_ctrl_cleanup(adapter);
  1955. free_netdev:
  1956. be_msix_disable(adapter);
  1957. free_netdev(adapter->netdev);
  1958. pci_set_drvdata(pdev, NULL);
  1959. rel_reg:
  1960. pci_release_regions(pdev);
  1961. disable_dev:
  1962. pci_disable_device(pdev);
  1963. do_none:
  1964. dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
  1965. return status;
  1966. }
  1967. static int be_suspend(struct pci_dev *pdev, pm_message_t state)
  1968. {
  1969. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1970. struct net_device *netdev = adapter->netdev;
  1971. if (adapter->wol)
  1972. be_setup_wol(adapter, true);
  1973. netif_device_detach(netdev);
  1974. if (netif_running(netdev)) {
  1975. rtnl_lock();
  1976. be_close(netdev);
  1977. rtnl_unlock();
  1978. }
  1979. be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
  1980. be_clear(adapter);
  1981. pci_save_state(pdev);
  1982. pci_disable_device(pdev);
  1983. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  1984. return 0;
  1985. }
  1986. static int be_resume(struct pci_dev *pdev)
  1987. {
  1988. int status = 0;
  1989. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1990. struct net_device *netdev = adapter->netdev;
  1991. netif_device_detach(netdev);
  1992. status = pci_enable_device(pdev);
  1993. if (status)
  1994. return status;
  1995. pci_set_power_state(pdev, 0);
  1996. pci_restore_state(pdev);
  1997. /* tell fw we're ready to fire cmds */
  1998. status = be_cmd_fw_init(adapter);
  1999. if (status)
  2000. return status;
  2001. be_setup(adapter);
  2002. if (netif_running(netdev)) {
  2003. rtnl_lock();
  2004. be_open(netdev);
  2005. rtnl_unlock();
  2006. }
  2007. netif_device_attach(netdev);
  2008. if (adapter->wol)
  2009. be_setup_wol(adapter, false);
  2010. return 0;
  2011. }
  2012. static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
  2013. pci_channel_state_t state)
  2014. {
  2015. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2016. struct net_device *netdev = adapter->netdev;
  2017. dev_err(&adapter->pdev->dev, "EEH error detected\n");
  2018. adapter->eeh_err = true;
  2019. netif_device_detach(netdev);
  2020. if (netif_running(netdev)) {
  2021. rtnl_lock();
  2022. be_close(netdev);
  2023. rtnl_unlock();
  2024. }
  2025. be_clear(adapter);
  2026. if (state == pci_channel_io_perm_failure)
  2027. return PCI_ERS_RESULT_DISCONNECT;
  2028. pci_disable_device(pdev);
  2029. return PCI_ERS_RESULT_NEED_RESET;
  2030. }
  2031. static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
  2032. {
  2033. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2034. int status;
  2035. dev_info(&adapter->pdev->dev, "EEH reset\n");
  2036. adapter->eeh_err = false;
  2037. status = pci_enable_device(pdev);
  2038. if (status)
  2039. return PCI_ERS_RESULT_DISCONNECT;
  2040. pci_set_master(pdev);
  2041. pci_set_power_state(pdev, 0);
  2042. pci_restore_state(pdev);
  2043. /* Check if card is ok and fw is ready */
  2044. status = be_cmd_POST(adapter);
  2045. if (status)
  2046. return PCI_ERS_RESULT_DISCONNECT;
  2047. return PCI_ERS_RESULT_RECOVERED;
  2048. }
  2049. static void be_eeh_resume(struct pci_dev *pdev)
  2050. {
  2051. int status = 0;
  2052. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2053. struct net_device *netdev = adapter->netdev;
  2054. dev_info(&adapter->pdev->dev, "EEH resume\n");
  2055. pci_save_state(pdev);
  2056. /* tell fw we're ready to fire cmds */
  2057. status = be_cmd_fw_init(adapter);
  2058. if (status)
  2059. goto err;
  2060. status = be_setup(adapter);
  2061. if (status)
  2062. goto err;
  2063. if (netif_running(netdev)) {
  2064. status = be_open(netdev);
  2065. if (status)
  2066. goto err;
  2067. }
  2068. netif_device_attach(netdev);
  2069. return;
  2070. err:
  2071. dev_err(&adapter->pdev->dev, "EEH resume failed\n");
  2072. return;
  2073. }
  2074. static struct pci_error_handlers be_eeh_handlers = {
  2075. .error_detected = be_eeh_err_detected,
  2076. .slot_reset = be_eeh_reset,
  2077. .resume = be_eeh_resume,
  2078. };
  2079. static struct pci_driver be_driver = {
  2080. .name = DRV_NAME,
  2081. .id_table = be_dev_ids,
  2082. .probe = be_probe,
  2083. .remove = be_remove,
  2084. .suspend = be_suspend,
  2085. .resume = be_resume,
  2086. .err_handler = &be_eeh_handlers
  2087. };
  2088. static int __init be_init_module(void)
  2089. {
  2090. if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
  2091. rx_frag_size != 2048) {
  2092. printk(KERN_WARNING DRV_NAME
  2093. " : Module param rx_frag_size must be 2048/4096/8192."
  2094. " Using 2048\n");
  2095. rx_frag_size = 2048;
  2096. }
  2097. return pci_register_driver(&be_driver);
  2098. }
  2099. module_init(be_init_module);
  2100. static void __exit be_exit_module(void)
  2101. {
  2102. pci_unregister_driver(&be_driver);
  2103. }
  2104. module_exit(be_exit_module);