ci13xxx_udc.c 72 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/platform_device.h>
  58. #include <linux/module.h>
  59. #include <linux/interrupt.h>
  60. #include <linux/io.h>
  61. #include <linux/irq.h>
  62. #include <linux/kernel.h>
  63. #include <linux/slab.h>
  64. #include <linux/pm_runtime.h>
  65. #include <linux/usb/ch9.h>
  66. #include <linux/usb/gadget.h>
  67. #include <linux/usb/otg.h>
  68. #include "ci13xxx_udc.h"
  69. /******************************************************************************
  70. * DEFINE
  71. *****************************************************************************/
  72. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* Interrupt statistics */
  91. #define ISR_MASK 0x1F
  92. static struct {
  93. u32 test;
  94. u32 ui;
  95. u32 uei;
  96. u32 pci;
  97. u32 uri;
  98. u32 sli;
  99. u32 none;
  100. struct {
  101. u32 cnt;
  102. u32 buf[ISR_MASK+1];
  103. u32 idx;
  104. } hndl;
  105. } isr_statistics;
  106. /**
  107. * ffs_nr: find first (least significant) bit set
  108. * @x: the word to search
  109. *
  110. * This function returns bit number (instead of position)
  111. */
  112. static int ffs_nr(u32 x)
  113. {
  114. int n = ffs(x);
  115. return n ? n-1 : 32;
  116. }
  117. /******************************************************************************
  118. * HW block
  119. *****************************************************************************/
  120. /* MSM specific */
  121. #define ABS_AHBBURST (0x0090UL)
  122. #define ABS_AHBMODE (0x0098UL)
  123. /* UDC register map */
  124. static uintptr_t ci_regs_nolpm[] = {
  125. [CAP_CAPLENGTH] = 0x000UL,
  126. [CAP_HCCPARAMS] = 0x008UL,
  127. [CAP_DCCPARAMS] = 0x024UL,
  128. [CAP_TESTMODE] = 0x038UL,
  129. [OP_USBCMD] = 0x000UL,
  130. [OP_USBSTS] = 0x004UL,
  131. [OP_USBINTR] = 0x008UL,
  132. [OP_DEVICEADDR] = 0x014UL,
  133. [OP_ENDPTLISTADDR] = 0x018UL,
  134. [OP_PORTSC] = 0x044UL,
  135. [OP_DEVLC] = 0x084UL,
  136. [OP_USBMODE] = 0x068UL,
  137. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  138. [OP_ENDPTPRIME] = 0x070UL,
  139. [OP_ENDPTFLUSH] = 0x074UL,
  140. [OP_ENDPTSTAT] = 0x078UL,
  141. [OP_ENDPTCOMPLETE] = 0x07CUL,
  142. [OP_ENDPTCTRL] = 0x080UL,
  143. };
  144. static uintptr_t ci_regs_lpm[] = {
  145. [CAP_CAPLENGTH] = 0x000UL,
  146. [CAP_HCCPARAMS] = 0x008UL,
  147. [CAP_DCCPARAMS] = 0x024UL,
  148. [CAP_TESTMODE] = 0x0FCUL,
  149. [OP_USBCMD] = 0x000UL,
  150. [OP_USBSTS] = 0x004UL,
  151. [OP_USBINTR] = 0x008UL,
  152. [OP_DEVICEADDR] = 0x014UL,
  153. [OP_ENDPTLISTADDR] = 0x018UL,
  154. [OP_PORTSC] = 0x044UL,
  155. [OP_DEVLC] = 0x084UL,
  156. [OP_USBMODE] = 0x0C8UL,
  157. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  158. [OP_ENDPTPRIME] = 0x0DCUL,
  159. [OP_ENDPTFLUSH] = 0x0E0UL,
  160. [OP_ENDPTSTAT] = 0x0E4UL,
  161. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  162. [OP_ENDPTCTRL] = 0x0ECUL,
  163. };
  164. static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
  165. {
  166. int i;
  167. kfree(udc->hw_bank.regmap);
  168. udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  169. GFP_KERNEL);
  170. if (!udc->hw_bank.regmap)
  171. return -ENOMEM;
  172. for (i = 0; i < OP_ENDPTCTRL; i++)
  173. udc->hw_bank.regmap[i] =
  174. (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
  175. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  176. for (; i <= OP_LAST; i++)
  177. udc->hw_bank.regmap[i] = udc->hw_bank.op +
  178. 4 * (i - OP_ENDPTCTRL) +
  179. (is_lpm
  180. ? ci_regs_lpm[OP_ENDPTCTRL]
  181. : ci_regs_nolpm[OP_ENDPTCTRL]);
  182. return 0;
  183. }
  184. /**
  185. * hw_ep_bit: calculates the bit number
  186. * @num: endpoint number
  187. * @dir: endpoint direction
  188. *
  189. * This function returns bit number
  190. */
  191. static inline int hw_ep_bit(int num, int dir)
  192. {
  193. return num + (dir ? 16 : 0);
  194. }
  195. static int ep_to_bit(struct ci13xxx *udc, int n)
  196. {
  197. int fill = 16 - udc->hw_ep_max / 2;
  198. if (n >= udc->hw_ep_max / 2)
  199. n += fill;
  200. return n;
  201. }
  202. /**
  203. * hw_read: reads from a hw register
  204. * @reg: register index
  205. * @mask: bitfield mask
  206. *
  207. * This function returns register contents
  208. */
  209. static u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
  210. {
  211. return ioread32(udc->hw_bank.regmap[reg]) & mask;
  212. }
  213. /**
  214. * hw_write: writes to a hw register
  215. * @reg: register index
  216. * @mask: bitfield mask
  217. * @data: new value
  218. */
  219. static void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask,
  220. u32 data)
  221. {
  222. if (~mask)
  223. data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
  224. | (data & mask);
  225. iowrite32(data, udc->hw_bank.regmap[reg]);
  226. }
  227. /**
  228. * hw_test_and_clear: tests & clears a hw register
  229. * @reg: register index
  230. * @mask: bitfield mask
  231. *
  232. * This function returns register contents
  233. */
  234. static u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
  235. u32 mask)
  236. {
  237. u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
  238. iowrite32(val, udc->hw_bank.regmap[reg]);
  239. return val;
  240. }
  241. /**
  242. * hw_test_and_write: tests & writes a hw register
  243. * @reg: register index
  244. * @mask: bitfield mask
  245. * @data: new value
  246. *
  247. * This function returns register contents
  248. */
  249. static u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
  250. u32 mask, u32 data)
  251. {
  252. u32 val = hw_read(udc, reg, ~0);
  253. hw_write(udc, reg, mask, data);
  254. return (val & mask) >> ffs_nr(mask);
  255. }
  256. static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
  257. uintptr_t cap_offset)
  258. {
  259. u32 reg;
  260. /* bank is a module variable */
  261. udc->hw_bank.abs = base;
  262. udc->hw_bank.cap = udc->hw_bank.abs;
  263. udc->hw_bank.cap += cap_offset;
  264. udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
  265. hw_alloc_regmap(udc, false);
  266. reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  267. ffs_nr(HCCPARAMS_LEN);
  268. udc->hw_bank.lpm = reg;
  269. hw_alloc_regmap(udc, !!reg);
  270. udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
  271. udc->hw_bank.size += OP_LAST;
  272. udc->hw_bank.size /= sizeof(u32);
  273. reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  274. ffs_nr(DCCPARAMS_DEN);
  275. udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  276. if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX)
  277. return -ENODEV;
  278. dev_dbg(udc->dev, "ChipIdea UDC found, lpm: %d; cap: %p op: %p\n",
  279. udc->hw_bank.lpm, udc->hw_bank.cap, udc->hw_bank.op);
  280. /* setup lock mode ? */
  281. /* ENDPTSETUPSTAT is '0' by default */
  282. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  283. return 0;
  284. }
  285. /**
  286. * hw_device_reset: resets chip (execute without interruption)
  287. * @base: register base address
  288. *
  289. * This function returns an error code
  290. */
  291. static int hw_device_reset(struct ci13xxx *udc)
  292. {
  293. /* should flush & stop before reset */
  294. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  295. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  296. hw_write(udc, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  297. while (hw_read(udc, OP_USBCMD, USBCMD_RST))
  298. udelay(10); /* not RTOS friendly */
  299. if (udc->udc_driver->notify_event)
  300. udc->udc_driver->notify_event(udc,
  301. CI13XXX_CONTROLLER_RESET_EVENT);
  302. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  303. hw_write(udc, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  304. /* USBMODE should be configured step by step */
  305. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  306. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  307. /* HW >= 2.3 */
  308. hw_write(udc, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  309. if (hw_read(udc, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  310. pr_err("cannot enter in device mode");
  311. pr_err("lpm = %i", udc->hw_bank.lpm);
  312. return -ENODEV;
  313. }
  314. return 0;
  315. }
  316. /**
  317. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  318. * without interruption)
  319. * @dma: 0 => disable, !0 => enable and set dma engine
  320. *
  321. * This function returns an error code
  322. */
  323. static int hw_device_state(struct ci13xxx *udc, u32 dma)
  324. {
  325. if (dma) {
  326. hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
  327. /* interrupt, error, port change, reset, sleep/suspend */
  328. hw_write(udc, OP_USBINTR, ~0,
  329. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  330. hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  331. } else {
  332. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  333. hw_write(udc, OP_USBINTR, ~0, 0);
  334. }
  335. return 0;
  336. }
  337. /**
  338. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  339. * @num: endpoint number
  340. * @dir: endpoint direction
  341. *
  342. * This function returns an error code
  343. */
  344. static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
  345. {
  346. int n = hw_ep_bit(num, dir);
  347. do {
  348. /* flush any pending transfer */
  349. hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
  350. while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
  351. cpu_relax();
  352. } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
  353. return 0;
  354. }
  355. /**
  356. * hw_ep_disable: disables endpoint (execute without interruption)
  357. * @num: endpoint number
  358. * @dir: endpoint direction
  359. *
  360. * This function returns an error code
  361. */
  362. static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
  363. {
  364. hw_ep_flush(udc, num, dir);
  365. hw_write(udc, OP_ENDPTCTRL + num,
  366. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  367. return 0;
  368. }
  369. /**
  370. * hw_ep_enable: enables endpoint (execute without interruption)
  371. * @num: endpoint number
  372. * @dir: endpoint direction
  373. * @type: endpoint type
  374. *
  375. * This function returns an error code
  376. */
  377. static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
  378. {
  379. u32 mask, data;
  380. if (dir) {
  381. mask = ENDPTCTRL_TXT; /* type */
  382. data = type << ffs_nr(mask);
  383. mask |= ENDPTCTRL_TXS; /* unstall */
  384. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  385. data |= ENDPTCTRL_TXR;
  386. mask |= ENDPTCTRL_TXE; /* enable */
  387. data |= ENDPTCTRL_TXE;
  388. } else {
  389. mask = ENDPTCTRL_RXT; /* type */
  390. data = type << ffs_nr(mask);
  391. mask |= ENDPTCTRL_RXS; /* unstall */
  392. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  393. data |= ENDPTCTRL_RXR;
  394. mask |= ENDPTCTRL_RXE; /* enable */
  395. data |= ENDPTCTRL_RXE;
  396. }
  397. hw_write(udc, OP_ENDPTCTRL + num, mask, data);
  398. return 0;
  399. }
  400. /**
  401. * hw_ep_get_halt: return endpoint halt status
  402. * @num: endpoint number
  403. * @dir: endpoint direction
  404. *
  405. * This function returns 1 if endpoint halted
  406. */
  407. static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
  408. {
  409. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  410. return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  411. }
  412. /**
  413. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  414. * interruption)
  415. * @n: endpoint number
  416. *
  417. * This function returns setup status
  418. */
  419. static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
  420. {
  421. n = ep_to_bit(udc, n);
  422. return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
  423. }
  424. /**
  425. * hw_ep_prime: primes endpoint (execute without interruption)
  426. * @num: endpoint number
  427. * @dir: endpoint direction
  428. * @is_ctrl: true if control endpoint
  429. *
  430. * This function returns an error code
  431. */
  432. static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
  433. {
  434. int n = hw_ep_bit(num, dir);
  435. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  436. return -EAGAIN;
  437. hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
  438. while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  439. cpu_relax();
  440. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  441. return -EAGAIN;
  442. /* status shoult be tested according with manual but it doesn't work */
  443. return 0;
  444. }
  445. /**
  446. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  447. * without interruption)
  448. * @num: endpoint number
  449. * @dir: endpoint direction
  450. * @value: true => stall, false => unstall
  451. *
  452. * This function returns an error code
  453. */
  454. static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
  455. {
  456. if (value != 0 && value != 1)
  457. return -EINVAL;
  458. do {
  459. enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
  460. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  461. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  462. /* data toggle - reserved for EP0 but it's in ESS */
  463. hw_write(udc, reg, mask_xs|mask_xr,
  464. value ? mask_xs : mask_xr);
  465. } while (value != hw_ep_get_halt(udc, num, dir));
  466. return 0;
  467. }
  468. /**
  469. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  470. * interruption)
  471. * @n: interrupt bit
  472. *
  473. * This function returns an error code
  474. */
  475. static int hw_intr_clear(struct ci13xxx *udc, int n)
  476. {
  477. if (n >= REG_BITS)
  478. return -EINVAL;
  479. hw_write(udc, OP_USBINTR, BIT(n), 0);
  480. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  481. return 0;
  482. }
  483. /**
  484. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  485. * interruption)
  486. * @n: interrupt bit
  487. *
  488. * This function returns an error code
  489. */
  490. static int hw_intr_force(struct ci13xxx *udc, int n)
  491. {
  492. if (n >= REG_BITS)
  493. return -EINVAL;
  494. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  495. hw_write(udc, OP_USBINTR, BIT(n), BIT(n));
  496. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  497. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, 0);
  498. return 0;
  499. }
  500. /**
  501. * hw_is_port_high_speed: test if port is high speed
  502. *
  503. * This function returns true if high speed port
  504. */
  505. static int hw_port_is_high_speed(struct ci13xxx *udc)
  506. {
  507. return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
  508. hw_read(udc, OP_PORTSC, PORTSC_HSP);
  509. }
  510. /**
  511. * hw_port_test_get: reads port test mode value
  512. *
  513. * This function returns port test mode value
  514. */
  515. static u8 hw_port_test_get(struct ci13xxx *udc)
  516. {
  517. return hw_read(udc, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  518. }
  519. /**
  520. * hw_port_test_set: writes port test mode (execute without interruption)
  521. * @mode: new value
  522. *
  523. * This function returns an error code
  524. */
  525. static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
  526. {
  527. const u8 TEST_MODE_MAX = 7;
  528. if (mode > TEST_MODE_MAX)
  529. return -EINVAL;
  530. hw_write(udc, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  531. return 0;
  532. }
  533. /**
  534. * hw_read_intr_enable: returns interrupt enable register
  535. *
  536. * This function returns register data
  537. */
  538. static u32 hw_read_intr_enable(struct ci13xxx *udc)
  539. {
  540. return hw_read(udc, OP_USBINTR, ~0);
  541. }
  542. /**
  543. * hw_read_intr_status: returns interrupt status register
  544. *
  545. * This function returns register data
  546. */
  547. static u32 hw_read_intr_status(struct ci13xxx *udc)
  548. {
  549. return hw_read(udc, OP_USBSTS, ~0);
  550. }
  551. /**
  552. * hw_register_read: reads all device registers (execute without interruption)
  553. * @buf: destination buffer
  554. * @size: buffer size
  555. *
  556. * This function returns number of registers read
  557. */
  558. static size_t hw_register_read(struct ci13xxx *udc, u32 *buf, size_t size)
  559. {
  560. unsigned i;
  561. if (size > udc->hw_bank.size)
  562. size = udc->hw_bank.size;
  563. for (i = 0; i < size; i++)
  564. buf[i] = hw_read(udc, i * sizeof(u32), ~0);
  565. return size;
  566. }
  567. /**
  568. * hw_register_write: writes to register
  569. * @addr: register address
  570. * @data: register value
  571. *
  572. * This function returns an error code
  573. */
  574. static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
  575. {
  576. /* align */
  577. addr /= sizeof(u32);
  578. if (addr >= udc->hw_bank.size)
  579. return -EINVAL;
  580. /* align */
  581. addr *= sizeof(u32);
  582. hw_write(udc, addr, ~0, data);
  583. return 0;
  584. }
  585. /**
  586. * hw_test_and_clear_complete: test & clear complete status (execute without
  587. * interruption)
  588. * @n: endpoint number
  589. *
  590. * This function returns complete status
  591. */
  592. static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
  593. {
  594. n = ep_to_bit(udc, n);
  595. return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
  596. }
  597. /**
  598. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  599. * without interruption)
  600. *
  601. * This function returns active interrutps
  602. */
  603. static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
  604. {
  605. u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
  606. hw_write(udc, OP_USBSTS, ~0, reg);
  607. return reg;
  608. }
  609. /**
  610. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  611. * interruption)
  612. *
  613. * This function returns guard value
  614. */
  615. static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
  616. {
  617. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
  618. }
  619. /**
  620. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  621. * interruption)
  622. *
  623. * This function returns guard value
  624. */
  625. static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
  626. {
  627. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  628. }
  629. /**
  630. * hw_usb_set_address: configures USB address (execute without interruption)
  631. * @value: new USB address
  632. *
  633. * This function explicitly sets the address, without the "USBADRA" (advance)
  634. * feature, which is not supported by older versions of the controller.
  635. */
  636. static void hw_usb_set_address(struct ci13xxx *udc, u8 value)
  637. {
  638. hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR,
  639. value << ffs_nr(DEVICEADDR_USBADR));
  640. }
  641. /**
  642. * hw_usb_reset: restart device after a bus reset (execute without
  643. * interruption)
  644. *
  645. * This function returns an error code
  646. */
  647. static int hw_usb_reset(struct ci13xxx *udc)
  648. {
  649. hw_usb_set_address(udc, 0);
  650. /* ESS flushes only at end?!? */
  651. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  652. /* clear setup token semaphores */
  653. hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
  654. /* clear complete status */
  655. hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
  656. /* wait until all bits cleared */
  657. while (hw_read(udc, OP_ENDPTPRIME, ~0))
  658. udelay(10); /* not RTOS friendly */
  659. /* reset all endpoints ? */
  660. /* reset internal status and wait for further instructions
  661. no need to verify the port reset status (ESS does it) */
  662. return 0;
  663. }
  664. /******************************************************************************
  665. * DBG block
  666. *****************************************************************************/
  667. /**
  668. * show_device: prints information about device capabilities and status
  669. *
  670. * Check "device.h" for details
  671. */
  672. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  673. char *buf)
  674. {
  675. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  676. struct usb_gadget *gadget = &udc->gadget;
  677. int n = 0;
  678. if (attr == NULL || buf == NULL) {
  679. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  680. return 0;
  681. }
  682. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  683. gadget->speed);
  684. n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed = %d\n",
  685. gadget->max_speed);
  686. /* TODO: Scheduled for removal in 3.8. */
  687. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  688. gadget_is_dualspeed(gadget));
  689. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  690. gadget->is_otg);
  691. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  692. gadget->is_a_peripheral);
  693. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  694. gadget->b_hnp_enable);
  695. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  696. gadget->a_hnp_support);
  697. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  698. gadget->a_alt_hnp_support);
  699. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  700. (gadget->name ? gadget->name : ""));
  701. return n;
  702. }
  703. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  704. /**
  705. * show_driver: prints information about attached gadget (if any)
  706. *
  707. * Check "device.h" for details
  708. */
  709. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  710. char *buf)
  711. {
  712. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  713. struct usb_gadget_driver *driver = udc->driver;
  714. int n = 0;
  715. if (attr == NULL || buf == NULL) {
  716. dev_err(dev, "[%s] EINVAL\n", __func__);
  717. return 0;
  718. }
  719. if (driver == NULL)
  720. return scnprintf(buf, PAGE_SIZE,
  721. "There is no gadget attached!\n");
  722. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  723. (driver->function ? driver->function : ""));
  724. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  725. driver->max_speed);
  726. return n;
  727. }
  728. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  729. /* Maximum event message length */
  730. #define DBG_DATA_MSG 64UL
  731. /* Maximum event messages */
  732. #define DBG_DATA_MAX 128UL
  733. /* Event buffer descriptor */
  734. static struct {
  735. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  736. unsigned idx; /* index */
  737. unsigned tty; /* print to console? */
  738. rwlock_t lck; /* lock */
  739. } dbg_data = {
  740. .idx = 0,
  741. .tty = 0,
  742. .lck = __RW_LOCK_UNLOCKED(lck)
  743. };
  744. /**
  745. * dbg_dec: decrements debug event index
  746. * @idx: buffer index
  747. */
  748. static void dbg_dec(unsigned *idx)
  749. {
  750. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  751. }
  752. /**
  753. * dbg_inc: increments debug event index
  754. * @idx: buffer index
  755. */
  756. static void dbg_inc(unsigned *idx)
  757. {
  758. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  759. }
  760. /**
  761. * dbg_print: prints the common part of the event
  762. * @addr: endpoint address
  763. * @name: event name
  764. * @status: status
  765. * @extra: extra information
  766. */
  767. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  768. {
  769. struct timeval tval;
  770. unsigned int stamp;
  771. unsigned long flags;
  772. write_lock_irqsave(&dbg_data.lck, flags);
  773. do_gettimeofday(&tval);
  774. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  775. stamp = stamp * 1000000 + tval.tv_usec;
  776. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  777. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  778. stamp, addr, name, status, extra);
  779. dbg_inc(&dbg_data.idx);
  780. write_unlock_irqrestore(&dbg_data.lck, flags);
  781. if (dbg_data.tty != 0)
  782. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  783. stamp, addr, name, status, extra);
  784. }
  785. /**
  786. * dbg_done: prints a DONE event
  787. * @addr: endpoint address
  788. * @td: transfer descriptor
  789. * @status: status
  790. */
  791. static void dbg_done(u8 addr, const u32 token, int status)
  792. {
  793. char msg[DBG_DATA_MSG];
  794. scnprintf(msg, sizeof(msg), "%d %02X",
  795. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  796. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  797. dbg_print(addr, "DONE", status, msg);
  798. }
  799. /**
  800. * dbg_event: prints a generic event
  801. * @addr: endpoint address
  802. * @name: event name
  803. * @status: status
  804. */
  805. static void dbg_event(u8 addr, const char *name, int status)
  806. {
  807. if (name != NULL)
  808. dbg_print(addr, name, status, "");
  809. }
  810. /*
  811. * dbg_queue: prints a QUEUE event
  812. * @addr: endpoint address
  813. * @req: USB request
  814. * @status: status
  815. */
  816. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  817. {
  818. char msg[DBG_DATA_MSG];
  819. if (req != NULL) {
  820. scnprintf(msg, sizeof(msg),
  821. "%d %d", !req->no_interrupt, req->length);
  822. dbg_print(addr, "QUEUE", status, msg);
  823. }
  824. }
  825. /**
  826. * dbg_setup: prints a SETUP event
  827. * @addr: endpoint address
  828. * @req: setup request
  829. */
  830. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  831. {
  832. char msg[DBG_DATA_MSG];
  833. if (req != NULL) {
  834. scnprintf(msg, sizeof(msg),
  835. "%02X %02X %04X %04X %d", req->bRequestType,
  836. req->bRequest, le16_to_cpu(req->wValue),
  837. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  838. dbg_print(addr, "SETUP", 0, msg);
  839. }
  840. }
  841. /**
  842. * show_events: displays the event buffer
  843. *
  844. * Check "device.h" for details
  845. */
  846. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  847. char *buf)
  848. {
  849. unsigned long flags;
  850. unsigned i, j, n = 0;
  851. if (attr == NULL || buf == NULL) {
  852. dev_err(dev->parent, "[%s] EINVAL\n", __func__);
  853. return 0;
  854. }
  855. read_lock_irqsave(&dbg_data.lck, flags);
  856. i = dbg_data.idx;
  857. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  858. n += strlen(dbg_data.buf[i]);
  859. if (n >= PAGE_SIZE) {
  860. n -= strlen(dbg_data.buf[i]);
  861. break;
  862. }
  863. }
  864. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  865. j += scnprintf(buf + j, PAGE_SIZE - j,
  866. "%s", dbg_data.buf[i]);
  867. read_unlock_irqrestore(&dbg_data.lck, flags);
  868. return n;
  869. }
  870. /**
  871. * store_events: configure if events are going to be also printed to console
  872. *
  873. * Check "device.h" for details
  874. */
  875. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  876. const char *buf, size_t count)
  877. {
  878. unsigned tty;
  879. if (attr == NULL || buf == NULL) {
  880. dev_err(dev, "[%s] EINVAL\n", __func__);
  881. goto done;
  882. }
  883. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  884. dev_err(dev, "<1|0>: enable|disable console log\n");
  885. goto done;
  886. }
  887. dbg_data.tty = tty;
  888. dev_info(dev, "tty = %u", dbg_data.tty);
  889. done:
  890. return count;
  891. }
  892. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  893. /**
  894. * show_inters: interrupt status, enable status and historic
  895. *
  896. * Check "device.h" for details
  897. */
  898. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  899. char *buf)
  900. {
  901. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  902. unsigned long flags;
  903. u32 intr;
  904. unsigned i, j, n = 0;
  905. if (attr == NULL || buf == NULL) {
  906. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  907. return 0;
  908. }
  909. spin_lock_irqsave(&udc->lock, flags);
  910. n += scnprintf(buf + n, PAGE_SIZE - n,
  911. "status = %08x\n", hw_read_intr_status(udc));
  912. n += scnprintf(buf + n, PAGE_SIZE - n,
  913. "enable = %08x\n", hw_read_intr_enable(udc));
  914. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  915. isr_statistics.test);
  916. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  917. isr_statistics.ui);
  918. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  919. isr_statistics.uei);
  920. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  921. isr_statistics.pci);
  922. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  923. isr_statistics.uri);
  924. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  925. isr_statistics.sli);
  926. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  927. isr_statistics.none);
  928. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  929. isr_statistics.hndl.cnt);
  930. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  931. i &= ISR_MASK;
  932. intr = isr_statistics.hndl.buf[i];
  933. if (USBi_UI & intr)
  934. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  935. intr &= ~USBi_UI;
  936. if (USBi_UEI & intr)
  937. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  938. intr &= ~USBi_UEI;
  939. if (USBi_PCI & intr)
  940. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  941. intr &= ~USBi_PCI;
  942. if (USBi_URI & intr)
  943. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  944. intr &= ~USBi_URI;
  945. if (USBi_SLI & intr)
  946. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  947. intr &= ~USBi_SLI;
  948. if (intr)
  949. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  950. if (isr_statistics.hndl.buf[i])
  951. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  952. }
  953. spin_unlock_irqrestore(&udc->lock, flags);
  954. return n;
  955. }
  956. /**
  957. * store_inters: enable & force or disable an individual interrutps
  958. * (to be used for test purposes only)
  959. *
  960. * Check "device.h" for details
  961. */
  962. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  963. const char *buf, size_t count)
  964. {
  965. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  966. unsigned long flags;
  967. unsigned en, bit;
  968. if (attr == NULL || buf == NULL) {
  969. dev_err(udc->dev, "EINVAL\n");
  970. goto done;
  971. }
  972. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  973. dev_err(udc->dev, "<1|0> <bit>: enable|disable interrupt\n");
  974. goto done;
  975. }
  976. spin_lock_irqsave(&udc->lock, flags);
  977. if (en) {
  978. if (hw_intr_force(udc, bit))
  979. dev_err(dev, "invalid bit number\n");
  980. else
  981. isr_statistics.test++;
  982. } else {
  983. if (hw_intr_clear(udc, bit))
  984. dev_err(dev, "invalid bit number\n");
  985. }
  986. spin_unlock_irqrestore(&udc->lock, flags);
  987. done:
  988. return count;
  989. }
  990. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  991. /**
  992. * show_port_test: reads port test mode
  993. *
  994. * Check "device.h" for details
  995. */
  996. static ssize_t show_port_test(struct device *dev,
  997. struct device_attribute *attr, char *buf)
  998. {
  999. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1000. unsigned long flags;
  1001. unsigned mode;
  1002. if (attr == NULL || buf == NULL) {
  1003. dev_err(udc->dev, "EINVAL\n");
  1004. return 0;
  1005. }
  1006. spin_lock_irqsave(&udc->lock, flags);
  1007. mode = hw_port_test_get(udc);
  1008. spin_unlock_irqrestore(&udc->lock, flags);
  1009. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  1010. }
  1011. /**
  1012. * store_port_test: writes port test mode
  1013. *
  1014. * Check "device.h" for details
  1015. */
  1016. static ssize_t store_port_test(struct device *dev,
  1017. struct device_attribute *attr,
  1018. const char *buf, size_t count)
  1019. {
  1020. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1021. unsigned long flags;
  1022. unsigned mode;
  1023. if (attr == NULL || buf == NULL) {
  1024. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1025. goto done;
  1026. }
  1027. if (sscanf(buf, "%u", &mode) != 1) {
  1028. dev_err(udc->dev, "<mode>: set port test mode");
  1029. goto done;
  1030. }
  1031. spin_lock_irqsave(&udc->lock, flags);
  1032. if (hw_port_test_set(udc, mode))
  1033. dev_err(udc->dev, "invalid mode\n");
  1034. spin_unlock_irqrestore(&udc->lock, flags);
  1035. done:
  1036. return count;
  1037. }
  1038. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1039. show_port_test, store_port_test);
  1040. /**
  1041. * show_qheads: DMA contents of all queue heads
  1042. *
  1043. * Check "device.h" for details
  1044. */
  1045. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1046. char *buf)
  1047. {
  1048. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1049. unsigned long flags;
  1050. unsigned i, j, n = 0;
  1051. if (attr == NULL || buf == NULL) {
  1052. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1053. return 0;
  1054. }
  1055. spin_lock_irqsave(&udc->lock, flags);
  1056. for (i = 0; i < udc->hw_ep_max/2; i++) {
  1057. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1058. struct ci13xxx_ep *mEpTx =
  1059. &udc->ci13xxx_ep[i + udc->hw_ep_max/2];
  1060. n += scnprintf(buf + n, PAGE_SIZE - n,
  1061. "EP=%02i: RX=%08X TX=%08X\n",
  1062. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1063. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1064. n += scnprintf(buf + n, PAGE_SIZE - n,
  1065. " %04X: %08X %08X\n", j,
  1066. *((u32 *)mEpRx->qh.ptr + j),
  1067. *((u32 *)mEpTx->qh.ptr + j));
  1068. }
  1069. }
  1070. spin_unlock_irqrestore(&udc->lock, flags);
  1071. return n;
  1072. }
  1073. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1074. /**
  1075. * show_registers: dumps all registers
  1076. *
  1077. * Check "device.h" for details
  1078. */
  1079. #define DUMP_ENTRIES 512
  1080. static ssize_t show_registers(struct device *dev,
  1081. struct device_attribute *attr, char *buf)
  1082. {
  1083. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1084. unsigned long flags;
  1085. u32 *dump;
  1086. unsigned i, k, n = 0;
  1087. if (attr == NULL || buf == NULL) {
  1088. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1089. return 0;
  1090. }
  1091. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1092. if (!dump) {
  1093. dev_err(udc->dev, "%s: out of memory\n", __func__);
  1094. return 0;
  1095. }
  1096. spin_lock_irqsave(&udc->lock, flags);
  1097. k = hw_register_read(udc, dump, DUMP_ENTRIES);
  1098. spin_unlock_irqrestore(&udc->lock, flags);
  1099. for (i = 0; i < k; i++) {
  1100. n += scnprintf(buf + n, PAGE_SIZE - n,
  1101. "reg[0x%04X] = 0x%08X\n",
  1102. i * (unsigned)sizeof(u32), dump[i]);
  1103. }
  1104. kfree(dump);
  1105. return n;
  1106. }
  1107. /**
  1108. * store_registers: writes value to register address
  1109. *
  1110. * Check "device.h" for details
  1111. */
  1112. static ssize_t store_registers(struct device *dev,
  1113. struct device_attribute *attr,
  1114. const char *buf, size_t count)
  1115. {
  1116. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1117. unsigned long addr, data, flags;
  1118. if (attr == NULL || buf == NULL) {
  1119. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1120. goto done;
  1121. }
  1122. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1123. dev_err(udc->dev,
  1124. "<addr> <data>: write data to register address\n");
  1125. goto done;
  1126. }
  1127. spin_lock_irqsave(&udc->lock, flags);
  1128. if (hw_register_write(udc, addr, data))
  1129. dev_err(udc->dev, "invalid address range\n");
  1130. spin_unlock_irqrestore(&udc->lock, flags);
  1131. done:
  1132. return count;
  1133. }
  1134. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1135. show_registers, store_registers);
  1136. /**
  1137. * show_requests: DMA contents of all requests currently queued (all endpts)
  1138. *
  1139. * Check "device.h" for details
  1140. */
  1141. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1142. char *buf)
  1143. {
  1144. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1145. unsigned long flags;
  1146. struct list_head *ptr = NULL;
  1147. struct ci13xxx_req *req = NULL;
  1148. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1149. if (attr == NULL || buf == NULL) {
  1150. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1151. return 0;
  1152. }
  1153. spin_lock_irqsave(&udc->lock, flags);
  1154. for (i = 0; i < udc->hw_ep_max; i++)
  1155. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1156. {
  1157. req = list_entry(ptr, struct ci13xxx_req, queue);
  1158. n += scnprintf(buf + n, PAGE_SIZE - n,
  1159. "EP=%02i: TD=%08X %s\n",
  1160. i % udc->hw_ep_max/2, (u32)req->dma,
  1161. ((i < udc->hw_ep_max/2) ? "RX" : "TX"));
  1162. for (j = 0; j < qSize; j++)
  1163. n += scnprintf(buf + n, PAGE_SIZE - n,
  1164. " %04X: %08X\n", j,
  1165. *((u32 *)req->ptr + j));
  1166. }
  1167. spin_unlock_irqrestore(&udc->lock, flags);
  1168. return n;
  1169. }
  1170. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1171. /**
  1172. * dbg_create_files: initializes the attribute interface
  1173. * @dev: device
  1174. *
  1175. * This function returns an error code
  1176. */
  1177. __maybe_unused static int dbg_create_files(struct device *dev)
  1178. {
  1179. int retval = 0;
  1180. if (dev == NULL)
  1181. return -EINVAL;
  1182. retval = device_create_file(dev, &dev_attr_device);
  1183. if (retval)
  1184. goto done;
  1185. retval = device_create_file(dev, &dev_attr_driver);
  1186. if (retval)
  1187. goto rm_device;
  1188. retval = device_create_file(dev, &dev_attr_events);
  1189. if (retval)
  1190. goto rm_driver;
  1191. retval = device_create_file(dev, &dev_attr_inters);
  1192. if (retval)
  1193. goto rm_events;
  1194. retval = device_create_file(dev, &dev_attr_port_test);
  1195. if (retval)
  1196. goto rm_inters;
  1197. retval = device_create_file(dev, &dev_attr_qheads);
  1198. if (retval)
  1199. goto rm_port_test;
  1200. retval = device_create_file(dev, &dev_attr_registers);
  1201. if (retval)
  1202. goto rm_qheads;
  1203. retval = device_create_file(dev, &dev_attr_requests);
  1204. if (retval)
  1205. goto rm_registers;
  1206. return 0;
  1207. rm_registers:
  1208. device_remove_file(dev, &dev_attr_registers);
  1209. rm_qheads:
  1210. device_remove_file(dev, &dev_attr_qheads);
  1211. rm_port_test:
  1212. device_remove_file(dev, &dev_attr_port_test);
  1213. rm_inters:
  1214. device_remove_file(dev, &dev_attr_inters);
  1215. rm_events:
  1216. device_remove_file(dev, &dev_attr_events);
  1217. rm_driver:
  1218. device_remove_file(dev, &dev_attr_driver);
  1219. rm_device:
  1220. device_remove_file(dev, &dev_attr_device);
  1221. done:
  1222. return retval;
  1223. }
  1224. /**
  1225. * dbg_remove_files: destroys the attribute interface
  1226. * @dev: device
  1227. *
  1228. * This function returns an error code
  1229. */
  1230. __maybe_unused static int dbg_remove_files(struct device *dev)
  1231. {
  1232. if (dev == NULL)
  1233. return -EINVAL;
  1234. device_remove_file(dev, &dev_attr_requests);
  1235. device_remove_file(dev, &dev_attr_registers);
  1236. device_remove_file(dev, &dev_attr_qheads);
  1237. device_remove_file(dev, &dev_attr_port_test);
  1238. device_remove_file(dev, &dev_attr_inters);
  1239. device_remove_file(dev, &dev_attr_events);
  1240. device_remove_file(dev, &dev_attr_driver);
  1241. device_remove_file(dev, &dev_attr_device);
  1242. return 0;
  1243. }
  1244. /******************************************************************************
  1245. * UTIL block
  1246. *****************************************************************************/
  1247. /**
  1248. * _usb_addr: calculates endpoint address from direction & number
  1249. * @ep: endpoint
  1250. */
  1251. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1252. {
  1253. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1254. }
  1255. /**
  1256. * _hardware_queue: configures a request at hardware level
  1257. * @gadget: gadget
  1258. * @mEp: endpoint
  1259. *
  1260. * This function returns an error code
  1261. */
  1262. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1263. {
  1264. struct ci13xxx *udc = mEp->udc;
  1265. unsigned i;
  1266. int ret = 0;
  1267. unsigned length = mReq->req.length;
  1268. /* don't queue twice */
  1269. if (mReq->req.status == -EALREADY)
  1270. return -EALREADY;
  1271. mReq->req.status = -EALREADY;
  1272. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1273. mReq->req.dma = \
  1274. dma_map_single(mEp->device, mReq->req.buf,
  1275. length, mEp->dir ? DMA_TO_DEVICE :
  1276. DMA_FROM_DEVICE);
  1277. if (mReq->req.dma == 0)
  1278. return -ENOMEM;
  1279. mReq->map = 1;
  1280. }
  1281. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1282. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1283. &mReq->zdma);
  1284. if (mReq->zptr == NULL) {
  1285. if (mReq->map) {
  1286. dma_unmap_single(mEp->device, mReq->req.dma,
  1287. length, mEp->dir ? DMA_TO_DEVICE :
  1288. DMA_FROM_DEVICE);
  1289. mReq->req.dma = DMA_ADDR_INVALID;
  1290. mReq->map = 0;
  1291. }
  1292. return -ENOMEM;
  1293. }
  1294. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1295. mReq->zptr->next = TD_TERMINATE;
  1296. mReq->zptr->token = TD_STATUS_ACTIVE;
  1297. if (!mReq->req.no_interrupt)
  1298. mReq->zptr->token |= TD_IOC;
  1299. }
  1300. /*
  1301. * TD configuration
  1302. * TODO - handle requests which spawns into several TDs
  1303. */
  1304. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1305. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1306. mReq->ptr->token &= TD_TOTAL_BYTES;
  1307. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1308. if (mReq->zptr) {
  1309. mReq->ptr->next = mReq->zdma;
  1310. } else {
  1311. mReq->ptr->next = TD_TERMINATE;
  1312. if (!mReq->req.no_interrupt)
  1313. mReq->ptr->token |= TD_IOC;
  1314. }
  1315. mReq->ptr->page[0] = mReq->req.dma;
  1316. for (i = 1; i < 5; i++)
  1317. mReq->ptr->page[i] =
  1318. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1319. if (!list_empty(&mEp->qh.queue)) {
  1320. struct ci13xxx_req *mReqPrev;
  1321. int n = hw_ep_bit(mEp->num, mEp->dir);
  1322. int tmp_stat;
  1323. mReqPrev = list_entry(mEp->qh.queue.prev,
  1324. struct ci13xxx_req, queue);
  1325. if (mReqPrev->zptr)
  1326. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1327. else
  1328. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1329. wmb();
  1330. if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  1331. goto done;
  1332. do {
  1333. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1334. tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
  1335. } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
  1336. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
  1337. if (tmp_stat)
  1338. goto done;
  1339. }
  1340. /* QH configuration */
  1341. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1342. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1343. mEp->qh.ptr->cap |= QH_ZLT;
  1344. wmb(); /* synchronize before ep prime */
  1345. ret = hw_ep_prime(udc, mEp->num, mEp->dir,
  1346. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1347. done:
  1348. return ret;
  1349. }
  1350. /**
  1351. * _hardware_dequeue: handles a request at hardware level
  1352. * @gadget: gadget
  1353. * @mEp: endpoint
  1354. *
  1355. * This function returns an error code
  1356. */
  1357. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1358. {
  1359. if (mReq->req.status != -EALREADY)
  1360. return -EINVAL;
  1361. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1362. return -EBUSY;
  1363. if (mReq->zptr) {
  1364. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1365. return -EBUSY;
  1366. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1367. mReq->zptr = NULL;
  1368. }
  1369. mReq->req.status = 0;
  1370. if (mReq->map) {
  1371. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1372. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1373. mReq->req.dma = DMA_ADDR_INVALID;
  1374. mReq->map = 0;
  1375. }
  1376. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1377. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1378. mReq->req.status = -1;
  1379. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1380. mReq->req.status = -1;
  1381. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1382. mReq->req.status = -1;
  1383. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1384. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1385. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1386. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1387. return mReq->req.actual;
  1388. }
  1389. /**
  1390. * _ep_nuke: dequeues all endpoint requests
  1391. * @mEp: endpoint
  1392. *
  1393. * This function returns an error code
  1394. * Caller must hold lock
  1395. */
  1396. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1397. __releases(mEp->lock)
  1398. __acquires(mEp->lock)
  1399. {
  1400. if (mEp == NULL)
  1401. return -EINVAL;
  1402. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1403. while (!list_empty(&mEp->qh.queue)) {
  1404. /* pop oldest request */
  1405. struct ci13xxx_req *mReq = \
  1406. list_entry(mEp->qh.queue.next,
  1407. struct ci13xxx_req, queue);
  1408. list_del_init(&mReq->queue);
  1409. mReq->req.status = -ESHUTDOWN;
  1410. if (mReq->req.complete != NULL) {
  1411. spin_unlock(mEp->lock);
  1412. mReq->req.complete(&mEp->ep, &mReq->req);
  1413. spin_lock(mEp->lock);
  1414. }
  1415. }
  1416. return 0;
  1417. }
  1418. /**
  1419. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1420. * @gadget: gadget
  1421. *
  1422. * This function returns an error code
  1423. */
  1424. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1425. {
  1426. struct usb_ep *ep;
  1427. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1428. unsigned long flags;
  1429. if (gadget == NULL)
  1430. return -EINVAL;
  1431. spin_lock_irqsave(&udc->lock, flags);
  1432. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1433. udc->remote_wakeup = 0;
  1434. udc->suspended = 0;
  1435. spin_unlock_irqrestore(&udc->lock, flags);
  1436. /* flush all endpoints */
  1437. gadget_for_each_ep(ep, gadget) {
  1438. usb_ep_fifo_flush(ep);
  1439. }
  1440. usb_ep_fifo_flush(&udc->ep0out->ep);
  1441. usb_ep_fifo_flush(&udc->ep0in->ep);
  1442. if (udc->driver)
  1443. udc->driver->disconnect(gadget);
  1444. /* make sure to disable all endpoints */
  1445. gadget_for_each_ep(ep, gadget) {
  1446. usb_ep_disable(ep);
  1447. }
  1448. if (udc->status != NULL) {
  1449. usb_ep_free_request(&udc->ep0in->ep, udc->status);
  1450. udc->status = NULL;
  1451. }
  1452. return 0;
  1453. }
  1454. /******************************************************************************
  1455. * ISR block
  1456. *****************************************************************************/
  1457. /**
  1458. * isr_reset_handler: USB reset interrupt handler
  1459. * @udc: UDC device
  1460. *
  1461. * This function resets USB engine after a bus reset occurred
  1462. */
  1463. static void isr_reset_handler(struct ci13xxx *udc)
  1464. __releases(udc->lock)
  1465. __acquires(udc->lock)
  1466. {
  1467. int retval;
  1468. dbg_event(0xFF, "BUS RST", 0);
  1469. spin_unlock(&udc->lock);
  1470. retval = _gadget_stop_activity(&udc->gadget);
  1471. if (retval)
  1472. goto done;
  1473. retval = hw_usb_reset(udc);
  1474. if (retval)
  1475. goto done;
  1476. udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
  1477. if (udc->status == NULL)
  1478. retval = -ENOMEM;
  1479. spin_lock(&udc->lock);
  1480. done:
  1481. if (retval)
  1482. dev_err(udc->dev, "error: %i\n", retval);
  1483. }
  1484. /**
  1485. * isr_get_status_complete: get_status request complete function
  1486. * @ep: endpoint
  1487. * @req: request handled
  1488. *
  1489. * Caller must release lock
  1490. */
  1491. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1492. {
  1493. if (ep == NULL || req == NULL)
  1494. return;
  1495. kfree(req->buf);
  1496. usb_ep_free_request(ep, req);
  1497. }
  1498. /**
  1499. * isr_get_status_response: get_status request response
  1500. * @udc: udc struct
  1501. * @setup: setup request packet
  1502. *
  1503. * This function returns an error code
  1504. */
  1505. static int isr_get_status_response(struct ci13xxx *udc,
  1506. struct usb_ctrlrequest *setup)
  1507. __releases(mEp->lock)
  1508. __acquires(mEp->lock)
  1509. {
  1510. struct ci13xxx_ep *mEp = udc->ep0in;
  1511. struct usb_request *req = NULL;
  1512. gfp_t gfp_flags = GFP_ATOMIC;
  1513. int dir, num, retval;
  1514. if (mEp == NULL || setup == NULL)
  1515. return -EINVAL;
  1516. spin_unlock(mEp->lock);
  1517. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1518. spin_lock(mEp->lock);
  1519. if (req == NULL)
  1520. return -ENOMEM;
  1521. req->complete = isr_get_status_complete;
  1522. req->length = 2;
  1523. req->buf = kzalloc(req->length, gfp_flags);
  1524. if (req->buf == NULL) {
  1525. retval = -ENOMEM;
  1526. goto err_free_req;
  1527. }
  1528. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1529. /* Assume that device is bus powered for now. */
  1530. *(u16 *)req->buf = udc->remote_wakeup << 1;
  1531. retval = 0;
  1532. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1533. == USB_RECIP_ENDPOINT) {
  1534. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1535. TX : RX;
  1536. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1537. *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
  1538. }
  1539. /* else do nothing; reserved for future use */
  1540. spin_unlock(mEp->lock);
  1541. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1542. spin_lock(mEp->lock);
  1543. if (retval)
  1544. goto err_free_buf;
  1545. return 0;
  1546. err_free_buf:
  1547. kfree(req->buf);
  1548. err_free_req:
  1549. spin_unlock(mEp->lock);
  1550. usb_ep_free_request(&mEp->ep, req);
  1551. spin_lock(mEp->lock);
  1552. return retval;
  1553. }
  1554. /**
  1555. * isr_setup_status_complete: setup_status request complete function
  1556. * @ep: endpoint
  1557. * @req: request handled
  1558. *
  1559. * Caller must release lock. Put the port in test mode if test mode
  1560. * feature is selected.
  1561. */
  1562. static void
  1563. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1564. {
  1565. struct ci13xxx *udc = req->context;
  1566. unsigned long flags;
  1567. if (udc->setaddr) {
  1568. hw_usb_set_address(udc, udc->address);
  1569. udc->setaddr = false;
  1570. }
  1571. spin_lock_irqsave(&udc->lock, flags);
  1572. if (udc->test_mode)
  1573. hw_port_test_set(udc, udc->test_mode);
  1574. spin_unlock_irqrestore(&udc->lock, flags);
  1575. }
  1576. /**
  1577. * isr_setup_status_phase: queues the status phase of a setup transation
  1578. * @udc: udc struct
  1579. *
  1580. * This function returns an error code
  1581. */
  1582. static int isr_setup_status_phase(struct ci13xxx *udc)
  1583. __releases(mEp->lock)
  1584. __acquires(mEp->lock)
  1585. {
  1586. int retval;
  1587. struct ci13xxx_ep *mEp;
  1588. mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
  1589. udc->status->context = udc;
  1590. udc->status->complete = isr_setup_status_complete;
  1591. spin_unlock(mEp->lock);
  1592. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1593. spin_lock(mEp->lock);
  1594. return retval;
  1595. }
  1596. /**
  1597. * isr_tr_complete_low: transaction complete low level handler
  1598. * @mEp: endpoint
  1599. *
  1600. * This function returns an error code
  1601. * Caller must hold lock
  1602. */
  1603. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1604. __releases(mEp->lock)
  1605. __acquires(mEp->lock)
  1606. {
  1607. struct ci13xxx_req *mReq, *mReqTemp;
  1608. struct ci13xxx_ep *mEpTemp = mEp;
  1609. int uninitialized_var(retval);
  1610. if (list_empty(&mEp->qh.queue))
  1611. return -EINVAL;
  1612. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1613. queue) {
  1614. retval = _hardware_dequeue(mEp, mReq);
  1615. if (retval < 0)
  1616. break;
  1617. list_del_init(&mReq->queue);
  1618. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1619. if (mReq->req.complete != NULL) {
  1620. spin_unlock(mEp->lock);
  1621. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1622. mReq->req.length)
  1623. mEpTemp = mEp->udc->ep0in;
  1624. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1625. spin_lock(mEp->lock);
  1626. }
  1627. }
  1628. if (retval == -EBUSY)
  1629. retval = 0;
  1630. if (retval < 0)
  1631. dbg_event(_usb_addr(mEp), "DONE", retval);
  1632. return retval;
  1633. }
  1634. /**
  1635. * isr_tr_complete_handler: transaction complete interrupt handler
  1636. * @udc: UDC descriptor
  1637. *
  1638. * This function handles traffic events
  1639. */
  1640. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1641. __releases(udc->lock)
  1642. __acquires(udc->lock)
  1643. {
  1644. unsigned i;
  1645. u8 tmode = 0;
  1646. for (i = 0; i < udc->hw_ep_max; i++) {
  1647. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1648. int type, num, dir, err = -EINVAL;
  1649. struct usb_ctrlrequest req;
  1650. if (mEp->ep.desc == NULL)
  1651. continue; /* not configured */
  1652. if (hw_test_and_clear_complete(udc, i)) {
  1653. err = isr_tr_complete_low(mEp);
  1654. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1655. if (err > 0) /* needs status phase */
  1656. err = isr_setup_status_phase(udc);
  1657. if (err < 0) {
  1658. dbg_event(_usb_addr(mEp),
  1659. "ERROR", err);
  1660. spin_unlock(&udc->lock);
  1661. if (usb_ep_set_halt(&mEp->ep))
  1662. dev_err(udc->dev,
  1663. "error: ep_set_halt\n");
  1664. spin_lock(&udc->lock);
  1665. }
  1666. }
  1667. }
  1668. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1669. !hw_test_and_clear_setup_status(udc, i))
  1670. continue;
  1671. if (i != 0) {
  1672. dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
  1673. continue;
  1674. }
  1675. /*
  1676. * Flush data and handshake transactions of previous
  1677. * setup packet.
  1678. */
  1679. _ep_nuke(udc->ep0out);
  1680. _ep_nuke(udc->ep0in);
  1681. /* read_setup_packet */
  1682. do {
  1683. hw_test_and_set_setup_guard(udc);
  1684. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1685. } while (!hw_test_and_clear_setup_guard(udc));
  1686. type = req.bRequestType;
  1687. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1688. dbg_setup(_usb_addr(mEp), &req);
  1689. switch (req.bRequest) {
  1690. case USB_REQ_CLEAR_FEATURE:
  1691. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1692. le16_to_cpu(req.wValue) ==
  1693. USB_ENDPOINT_HALT) {
  1694. if (req.wLength != 0)
  1695. break;
  1696. num = le16_to_cpu(req.wIndex);
  1697. dir = num & USB_ENDPOINT_DIR_MASK;
  1698. num &= USB_ENDPOINT_NUMBER_MASK;
  1699. if (dir) /* TX */
  1700. num += udc->hw_ep_max/2;
  1701. if (!udc->ci13xxx_ep[num].wedge) {
  1702. spin_unlock(&udc->lock);
  1703. err = usb_ep_clear_halt(
  1704. &udc->ci13xxx_ep[num].ep);
  1705. spin_lock(&udc->lock);
  1706. if (err)
  1707. break;
  1708. }
  1709. err = isr_setup_status_phase(udc);
  1710. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1711. le16_to_cpu(req.wValue) ==
  1712. USB_DEVICE_REMOTE_WAKEUP) {
  1713. if (req.wLength != 0)
  1714. break;
  1715. udc->remote_wakeup = 0;
  1716. err = isr_setup_status_phase(udc);
  1717. } else {
  1718. goto delegate;
  1719. }
  1720. break;
  1721. case USB_REQ_GET_STATUS:
  1722. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1723. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1724. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1725. goto delegate;
  1726. if (le16_to_cpu(req.wLength) != 2 ||
  1727. le16_to_cpu(req.wValue) != 0)
  1728. break;
  1729. err = isr_get_status_response(udc, &req);
  1730. break;
  1731. case USB_REQ_SET_ADDRESS:
  1732. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1733. goto delegate;
  1734. if (le16_to_cpu(req.wLength) != 0 ||
  1735. le16_to_cpu(req.wIndex) != 0)
  1736. break;
  1737. udc->address = (u8)le16_to_cpu(req.wValue);
  1738. udc->setaddr = true;
  1739. err = isr_setup_status_phase(udc);
  1740. break;
  1741. case USB_REQ_SET_FEATURE:
  1742. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1743. le16_to_cpu(req.wValue) ==
  1744. USB_ENDPOINT_HALT) {
  1745. if (req.wLength != 0)
  1746. break;
  1747. num = le16_to_cpu(req.wIndex);
  1748. dir = num & USB_ENDPOINT_DIR_MASK;
  1749. num &= USB_ENDPOINT_NUMBER_MASK;
  1750. if (dir) /* TX */
  1751. num += udc->hw_ep_max/2;
  1752. spin_unlock(&udc->lock);
  1753. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1754. spin_lock(&udc->lock);
  1755. if (!err)
  1756. isr_setup_status_phase(udc);
  1757. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1758. if (req.wLength != 0)
  1759. break;
  1760. switch (le16_to_cpu(req.wValue)) {
  1761. case USB_DEVICE_REMOTE_WAKEUP:
  1762. udc->remote_wakeup = 1;
  1763. err = isr_setup_status_phase(udc);
  1764. break;
  1765. case USB_DEVICE_TEST_MODE:
  1766. tmode = le16_to_cpu(req.wIndex) >> 8;
  1767. switch (tmode) {
  1768. case TEST_J:
  1769. case TEST_K:
  1770. case TEST_SE0_NAK:
  1771. case TEST_PACKET:
  1772. case TEST_FORCE_EN:
  1773. udc->test_mode = tmode;
  1774. err = isr_setup_status_phase(
  1775. udc);
  1776. break;
  1777. default:
  1778. break;
  1779. }
  1780. default:
  1781. goto delegate;
  1782. }
  1783. } else {
  1784. goto delegate;
  1785. }
  1786. break;
  1787. default:
  1788. delegate:
  1789. if (req.wLength == 0) /* no data phase */
  1790. udc->ep0_dir = TX;
  1791. spin_unlock(&udc->lock);
  1792. err = udc->driver->setup(&udc->gadget, &req);
  1793. spin_lock(&udc->lock);
  1794. break;
  1795. }
  1796. if (err < 0) {
  1797. dbg_event(_usb_addr(mEp), "ERROR", err);
  1798. spin_unlock(&udc->lock);
  1799. if (usb_ep_set_halt(&mEp->ep))
  1800. dev_err(udc->dev, "error: ep_set_halt\n");
  1801. spin_lock(&udc->lock);
  1802. }
  1803. }
  1804. }
  1805. /******************************************************************************
  1806. * ENDPT block
  1807. *****************************************************************************/
  1808. /**
  1809. * ep_enable: configure endpoint, making it usable
  1810. *
  1811. * Check usb_ep_enable() at "usb_gadget.h" for details
  1812. */
  1813. static int ep_enable(struct usb_ep *ep,
  1814. const struct usb_endpoint_descriptor *desc)
  1815. {
  1816. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1817. int retval = 0;
  1818. unsigned long flags;
  1819. if (ep == NULL || desc == NULL)
  1820. return -EINVAL;
  1821. spin_lock_irqsave(mEp->lock, flags);
  1822. /* only internal SW should enable ctrl endpts */
  1823. mEp->ep.desc = desc;
  1824. if (!list_empty(&mEp->qh.queue))
  1825. dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
  1826. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1827. mEp->num = usb_endpoint_num(desc);
  1828. mEp->type = usb_endpoint_type(desc);
  1829. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1830. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1831. mEp->qh.ptr->cap = 0;
  1832. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1833. mEp->qh.ptr->cap |= QH_IOS;
  1834. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1835. mEp->qh.ptr->cap &= ~QH_MULT;
  1836. else
  1837. mEp->qh.ptr->cap &= ~QH_ZLT;
  1838. mEp->qh.ptr->cap |=
  1839. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1840. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1841. /*
  1842. * Enable endpoints in the HW other than ep0 as ep0
  1843. * is always enabled
  1844. */
  1845. if (mEp->num)
  1846. retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
  1847. spin_unlock_irqrestore(mEp->lock, flags);
  1848. return retval;
  1849. }
  1850. /**
  1851. * ep_disable: endpoint is no longer usable
  1852. *
  1853. * Check usb_ep_disable() at "usb_gadget.h" for details
  1854. */
  1855. static int ep_disable(struct usb_ep *ep)
  1856. {
  1857. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1858. int direction, retval = 0;
  1859. unsigned long flags;
  1860. if (ep == NULL)
  1861. return -EINVAL;
  1862. else if (mEp->ep.desc == NULL)
  1863. return -EBUSY;
  1864. spin_lock_irqsave(mEp->lock, flags);
  1865. /* only internal SW should disable ctrl endpts */
  1866. direction = mEp->dir;
  1867. do {
  1868. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1869. retval |= _ep_nuke(mEp);
  1870. retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
  1871. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1872. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1873. } while (mEp->dir != direction);
  1874. mEp->ep.desc = NULL;
  1875. spin_unlock_irqrestore(mEp->lock, flags);
  1876. return retval;
  1877. }
  1878. /**
  1879. * ep_alloc_request: allocate a request object to use with this endpoint
  1880. *
  1881. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1882. */
  1883. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1884. {
  1885. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1886. struct ci13xxx_req *mReq = NULL;
  1887. if (ep == NULL)
  1888. return NULL;
  1889. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1890. if (mReq != NULL) {
  1891. INIT_LIST_HEAD(&mReq->queue);
  1892. mReq->req.dma = DMA_ADDR_INVALID;
  1893. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1894. &mReq->dma);
  1895. if (mReq->ptr == NULL) {
  1896. kfree(mReq);
  1897. mReq = NULL;
  1898. }
  1899. }
  1900. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1901. return (mReq == NULL) ? NULL : &mReq->req;
  1902. }
  1903. /**
  1904. * ep_free_request: frees a request object
  1905. *
  1906. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1907. */
  1908. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1909. {
  1910. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1911. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1912. unsigned long flags;
  1913. if (ep == NULL || req == NULL) {
  1914. return;
  1915. } else if (!list_empty(&mReq->queue)) {
  1916. dev_err(mEp->udc->dev, "freeing queued request\n");
  1917. return;
  1918. }
  1919. spin_lock_irqsave(mEp->lock, flags);
  1920. if (mReq->ptr)
  1921. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1922. kfree(mReq);
  1923. dbg_event(_usb_addr(mEp), "FREE", 0);
  1924. spin_unlock_irqrestore(mEp->lock, flags);
  1925. }
  1926. /**
  1927. * ep_queue: queues (submits) an I/O request to an endpoint
  1928. *
  1929. * Check usb_ep_queue()* at usb_gadget.h" for details
  1930. */
  1931. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1932. gfp_t __maybe_unused gfp_flags)
  1933. {
  1934. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1935. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1936. struct ci13xxx *udc = mEp->udc;
  1937. int retval = 0;
  1938. unsigned long flags;
  1939. if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
  1940. return -EINVAL;
  1941. spin_lock_irqsave(mEp->lock, flags);
  1942. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1943. if (req->length)
  1944. mEp = (udc->ep0_dir == RX) ?
  1945. udc->ep0out : udc->ep0in;
  1946. if (!list_empty(&mEp->qh.queue)) {
  1947. _ep_nuke(mEp);
  1948. retval = -EOVERFLOW;
  1949. dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
  1950. _usb_addr(mEp));
  1951. }
  1952. }
  1953. /* first nuke then test link, e.g. previous status has not sent */
  1954. if (!list_empty(&mReq->queue)) {
  1955. retval = -EBUSY;
  1956. dev_err(mEp->udc->dev, "request already in queue\n");
  1957. goto done;
  1958. }
  1959. if (req->length > 4 * CI13XXX_PAGE_SIZE) {
  1960. req->length = 4 * CI13XXX_PAGE_SIZE;
  1961. retval = -EMSGSIZE;
  1962. dev_warn(mEp->udc->dev, "request length truncated\n");
  1963. }
  1964. dbg_queue(_usb_addr(mEp), req, retval);
  1965. /* push request */
  1966. mReq->req.status = -EINPROGRESS;
  1967. mReq->req.actual = 0;
  1968. retval = _hardware_enqueue(mEp, mReq);
  1969. if (retval == -EALREADY) {
  1970. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1971. retval = 0;
  1972. }
  1973. if (!retval)
  1974. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1975. done:
  1976. spin_unlock_irqrestore(mEp->lock, flags);
  1977. return retval;
  1978. }
  1979. /**
  1980. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1981. *
  1982. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1983. */
  1984. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1985. {
  1986. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1987. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1988. unsigned long flags;
  1989. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  1990. mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
  1991. list_empty(&mEp->qh.queue))
  1992. return -EINVAL;
  1993. spin_lock_irqsave(mEp->lock, flags);
  1994. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  1995. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1996. /* pop request */
  1997. list_del_init(&mReq->queue);
  1998. if (mReq->map) {
  1999. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  2000. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  2001. mReq->req.dma = DMA_ADDR_INVALID;
  2002. mReq->map = 0;
  2003. }
  2004. req->status = -ECONNRESET;
  2005. if (mReq->req.complete != NULL) {
  2006. spin_unlock(mEp->lock);
  2007. mReq->req.complete(&mEp->ep, &mReq->req);
  2008. spin_lock(mEp->lock);
  2009. }
  2010. spin_unlock_irqrestore(mEp->lock, flags);
  2011. return 0;
  2012. }
  2013. /**
  2014. * ep_set_halt: sets the endpoint halt feature
  2015. *
  2016. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2017. */
  2018. static int ep_set_halt(struct usb_ep *ep, int value)
  2019. {
  2020. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2021. int direction, retval = 0;
  2022. unsigned long flags;
  2023. if (ep == NULL || mEp->ep.desc == NULL)
  2024. return -EINVAL;
  2025. spin_lock_irqsave(mEp->lock, flags);
  2026. #ifndef STALL_IN
  2027. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2028. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2029. !list_empty(&mEp->qh.queue)) {
  2030. spin_unlock_irqrestore(mEp->lock, flags);
  2031. return -EAGAIN;
  2032. }
  2033. #endif
  2034. direction = mEp->dir;
  2035. do {
  2036. dbg_event(_usb_addr(mEp), "HALT", value);
  2037. retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
  2038. if (!value)
  2039. mEp->wedge = 0;
  2040. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2041. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2042. } while (mEp->dir != direction);
  2043. spin_unlock_irqrestore(mEp->lock, flags);
  2044. return retval;
  2045. }
  2046. /**
  2047. * ep_set_wedge: sets the halt feature and ignores clear requests
  2048. *
  2049. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2050. */
  2051. static int ep_set_wedge(struct usb_ep *ep)
  2052. {
  2053. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2054. unsigned long flags;
  2055. if (ep == NULL || mEp->ep.desc == NULL)
  2056. return -EINVAL;
  2057. spin_lock_irqsave(mEp->lock, flags);
  2058. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2059. mEp->wedge = 1;
  2060. spin_unlock_irqrestore(mEp->lock, flags);
  2061. return usb_ep_set_halt(ep);
  2062. }
  2063. /**
  2064. * ep_fifo_flush: flushes contents of a fifo
  2065. *
  2066. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2067. */
  2068. static void ep_fifo_flush(struct usb_ep *ep)
  2069. {
  2070. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2071. unsigned long flags;
  2072. if (ep == NULL) {
  2073. dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
  2074. return;
  2075. }
  2076. spin_lock_irqsave(mEp->lock, flags);
  2077. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2078. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2079. spin_unlock_irqrestore(mEp->lock, flags);
  2080. }
  2081. /**
  2082. * Endpoint-specific part of the API to the USB controller hardware
  2083. * Check "usb_gadget.h" for details
  2084. */
  2085. static const struct usb_ep_ops usb_ep_ops = {
  2086. .enable = ep_enable,
  2087. .disable = ep_disable,
  2088. .alloc_request = ep_alloc_request,
  2089. .free_request = ep_free_request,
  2090. .queue = ep_queue,
  2091. .dequeue = ep_dequeue,
  2092. .set_halt = ep_set_halt,
  2093. .set_wedge = ep_set_wedge,
  2094. .fifo_flush = ep_fifo_flush,
  2095. };
  2096. /******************************************************************************
  2097. * GADGET block
  2098. *****************************************************************************/
  2099. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2100. {
  2101. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2102. unsigned long flags;
  2103. int gadget_ready = 0;
  2104. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2105. return -EOPNOTSUPP;
  2106. spin_lock_irqsave(&udc->lock, flags);
  2107. udc->vbus_active = is_active;
  2108. if (udc->driver)
  2109. gadget_ready = 1;
  2110. spin_unlock_irqrestore(&udc->lock, flags);
  2111. if (gadget_ready) {
  2112. if (is_active) {
  2113. pm_runtime_get_sync(&_gadget->dev);
  2114. hw_device_reset(udc);
  2115. hw_device_state(udc, udc->ep0out->qh.dma);
  2116. } else {
  2117. hw_device_state(udc, 0);
  2118. if (udc->udc_driver->notify_event)
  2119. udc->udc_driver->notify_event(udc,
  2120. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2121. _gadget_stop_activity(&udc->gadget);
  2122. pm_runtime_put_sync(&_gadget->dev);
  2123. }
  2124. }
  2125. return 0;
  2126. }
  2127. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2128. {
  2129. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2130. unsigned long flags;
  2131. int ret = 0;
  2132. spin_lock_irqsave(&udc->lock, flags);
  2133. if (!udc->remote_wakeup) {
  2134. ret = -EOPNOTSUPP;
  2135. goto out;
  2136. }
  2137. if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
  2138. ret = -EINVAL;
  2139. goto out;
  2140. }
  2141. hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2142. out:
  2143. spin_unlock_irqrestore(&udc->lock, flags);
  2144. return ret;
  2145. }
  2146. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2147. {
  2148. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2149. if (udc->transceiver)
  2150. return usb_phy_set_power(udc->transceiver, mA);
  2151. return -ENOTSUPP;
  2152. }
  2153. static int ci13xxx_start(struct usb_gadget *gadget,
  2154. struct usb_gadget_driver *driver);
  2155. static int ci13xxx_stop(struct usb_gadget *gadget,
  2156. struct usb_gadget_driver *driver);
  2157. /**
  2158. * Device operations part of the API to the USB controller hardware,
  2159. * which don't involve endpoints (or i/o)
  2160. * Check "usb_gadget.h" for details
  2161. */
  2162. static const struct usb_gadget_ops usb_gadget_ops = {
  2163. .vbus_session = ci13xxx_vbus_session,
  2164. .wakeup = ci13xxx_wakeup,
  2165. .vbus_draw = ci13xxx_vbus_draw,
  2166. .udc_start = ci13xxx_start,
  2167. .udc_stop = ci13xxx_stop,
  2168. };
  2169. static int init_eps(struct ci13xxx *udc)
  2170. {
  2171. int retval = 0, i, j;
  2172. for (i = 0; i < udc->hw_ep_max/2; i++)
  2173. for (j = RX; j <= TX; j++) {
  2174. int k = i + j * udc->hw_ep_max/2;
  2175. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2176. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2177. (j == TX) ? "in" : "out");
  2178. mEp->udc = udc;
  2179. mEp->lock = &udc->lock;
  2180. mEp->device = &udc->gadget.dev;
  2181. mEp->td_pool = udc->td_pool;
  2182. mEp->ep.name = mEp->name;
  2183. mEp->ep.ops = &usb_ep_ops;
  2184. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2185. INIT_LIST_HEAD(&mEp->qh.queue);
  2186. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2187. &mEp->qh.dma);
  2188. if (mEp->qh.ptr == NULL)
  2189. retval = -ENOMEM;
  2190. else
  2191. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2192. /*
  2193. * set up shorthands for ep0 out and in endpoints,
  2194. * don't add to gadget's ep_list
  2195. */
  2196. if (i == 0) {
  2197. if (j == RX)
  2198. udc->ep0out = mEp;
  2199. else
  2200. udc->ep0in = mEp;
  2201. continue;
  2202. }
  2203. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2204. }
  2205. return retval;
  2206. }
  2207. /**
  2208. * ci13xxx_start: register a gadget driver
  2209. * @gadget: our gadget
  2210. * @driver: the driver being registered
  2211. *
  2212. * Interrupts are enabled here.
  2213. */
  2214. static int ci13xxx_start(struct usb_gadget *gadget,
  2215. struct usb_gadget_driver *driver)
  2216. {
  2217. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  2218. unsigned long flags;
  2219. int retval = -ENOMEM;
  2220. if (driver->disconnect == NULL)
  2221. return -EINVAL;
  2222. udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
  2223. retval = usb_ep_enable(&udc->ep0out->ep);
  2224. if (retval)
  2225. return retval;
  2226. udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
  2227. retval = usb_ep_enable(&udc->ep0in->ep);
  2228. if (retval)
  2229. return retval;
  2230. spin_lock_irqsave(&udc->lock, flags);
  2231. udc->driver = driver;
  2232. pm_runtime_get_sync(&udc->gadget.dev);
  2233. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2234. if (udc->vbus_active) {
  2235. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2236. hw_device_reset(udc);
  2237. } else {
  2238. pm_runtime_put_sync(&udc->gadget.dev);
  2239. goto done;
  2240. }
  2241. }
  2242. retval = hw_device_state(udc, udc->ep0out->qh.dma);
  2243. if (retval)
  2244. pm_runtime_put_sync(&udc->gadget.dev);
  2245. done:
  2246. spin_unlock_irqrestore(&udc->lock, flags);
  2247. return retval;
  2248. }
  2249. /**
  2250. * ci13xxx_stop: unregister a gadget driver
  2251. */
  2252. static int ci13xxx_stop(struct usb_gadget *gadget,
  2253. struct usb_gadget_driver *driver)
  2254. {
  2255. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  2256. unsigned long flags;
  2257. spin_lock_irqsave(&udc->lock, flags);
  2258. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2259. udc->vbus_active) {
  2260. hw_device_state(udc, 0);
  2261. if (udc->udc_driver->notify_event)
  2262. udc->udc_driver->notify_event(udc,
  2263. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2264. udc->driver = NULL;
  2265. spin_unlock_irqrestore(&udc->lock, flags);
  2266. _gadget_stop_activity(&udc->gadget);
  2267. spin_lock_irqsave(&udc->lock, flags);
  2268. pm_runtime_put(&udc->gadget.dev);
  2269. }
  2270. spin_unlock_irqrestore(&udc->lock, flags);
  2271. return 0;
  2272. }
  2273. /******************************************************************************
  2274. * BUS block
  2275. *****************************************************************************/
  2276. /**
  2277. * udc_irq: global interrupt handler
  2278. *
  2279. * This function returns IRQ_HANDLED if the IRQ has been handled
  2280. * It locks access to registers
  2281. */
  2282. static irqreturn_t udc_irq(int irq, void *data)
  2283. {
  2284. struct ci13xxx *udc = data;
  2285. irqreturn_t retval;
  2286. u32 intr;
  2287. if (udc == NULL)
  2288. return IRQ_HANDLED;
  2289. spin_lock(&udc->lock);
  2290. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2291. if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
  2292. USBMODE_CM_DEVICE) {
  2293. spin_unlock(&udc->lock);
  2294. return IRQ_NONE;
  2295. }
  2296. }
  2297. intr = hw_test_and_clear_intr_active(udc);
  2298. if (intr) {
  2299. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2300. isr_statistics.hndl.idx &= ISR_MASK;
  2301. isr_statistics.hndl.cnt++;
  2302. /* order defines priority - do NOT change it */
  2303. if (USBi_URI & intr) {
  2304. isr_statistics.uri++;
  2305. isr_reset_handler(udc);
  2306. }
  2307. if (USBi_PCI & intr) {
  2308. isr_statistics.pci++;
  2309. udc->gadget.speed = hw_port_is_high_speed(udc) ?
  2310. USB_SPEED_HIGH : USB_SPEED_FULL;
  2311. if (udc->suspended && udc->driver->resume) {
  2312. spin_unlock(&udc->lock);
  2313. udc->driver->resume(&udc->gadget);
  2314. spin_lock(&udc->lock);
  2315. udc->suspended = 0;
  2316. }
  2317. }
  2318. if (USBi_UEI & intr)
  2319. isr_statistics.uei++;
  2320. if (USBi_UI & intr) {
  2321. isr_statistics.ui++;
  2322. isr_tr_complete_handler(udc);
  2323. }
  2324. if (USBi_SLI & intr) {
  2325. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  2326. udc->driver->suspend) {
  2327. udc->suspended = 1;
  2328. spin_unlock(&udc->lock);
  2329. udc->driver->suspend(&udc->gadget);
  2330. spin_lock(&udc->lock);
  2331. }
  2332. isr_statistics.sli++;
  2333. }
  2334. retval = IRQ_HANDLED;
  2335. } else {
  2336. isr_statistics.none++;
  2337. retval = IRQ_NONE;
  2338. }
  2339. spin_unlock(&udc->lock);
  2340. return retval;
  2341. }
  2342. /**
  2343. * udc_release: driver release function
  2344. * @dev: device
  2345. *
  2346. * Currently does nothing
  2347. */
  2348. static void udc_release(struct device *dev)
  2349. {
  2350. }
  2351. /**
  2352. * udc_probe: parent probe must call this to initialize UDC
  2353. * @dev: parent device
  2354. * @regs: registers base address
  2355. * @name: driver name
  2356. *
  2357. * This function returns an error code
  2358. * No interrupts active, the IRQ has not been requested yet
  2359. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2360. */
  2361. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2362. void __iomem *regs, struct ci13xxx **_udc)
  2363. {
  2364. struct ci13xxx *udc;
  2365. int retval = 0;
  2366. if (dev == NULL || regs == NULL || driver == NULL ||
  2367. driver->name == NULL)
  2368. return -EINVAL;
  2369. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2370. if (udc == NULL)
  2371. return -ENOMEM;
  2372. spin_lock_init(&udc->lock);
  2373. udc->regs = regs;
  2374. udc->udc_driver = driver;
  2375. udc->gadget.ops = &usb_gadget_ops;
  2376. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2377. udc->gadget.max_speed = USB_SPEED_HIGH;
  2378. udc->gadget.is_otg = 0;
  2379. udc->gadget.name = driver->name;
  2380. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2381. dev_set_name(&udc->gadget.dev, "gadget");
  2382. udc->gadget.dev.dma_mask = dev->dma_mask;
  2383. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2384. udc->gadget.dev.parent = dev;
  2385. udc->gadget.dev.release = udc_release;
  2386. udc->dev = dev;
  2387. /* alloc resources */
  2388. udc->qh_pool = dma_pool_create("ci13xxx_qh", dev,
  2389. sizeof(struct ci13xxx_qh),
  2390. 64, CI13XXX_PAGE_SIZE);
  2391. if (udc->qh_pool == NULL) {
  2392. retval = -ENOMEM;
  2393. goto free_udc;
  2394. }
  2395. udc->td_pool = dma_pool_create("ci13xxx_td", dev,
  2396. sizeof(struct ci13xxx_td),
  2397. 64, CI13XXX_PAGE_SIZE);
  2398. if (udc->td_pool == NULL) {
  2399. retval = -ENOMEM;
  2400. goto free_qh_pool;
  2401. }
  2402. retval = hw_device_init(udc, regs, driver->capoffset);
  2403. if (retval < 0)
  2404. goto free_pools;
  2405. retval = init_eps(udc);
  2406. if (retval)
  2407. goto free_pools;
  2408. udc->gadget.ep0 = &udc->ep0in->ep;
  2409. udc->transceiver = usb_get_transceiver();
  2410. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2411. if (udc->transceiver == NULL) {
  2412. retval = -ENODEV;
  2413. goto free_pools;
  2414. }
  2415. }
  2416. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2417. retval = hw_device_reset(udc);
  2418. if (retval)
  2419. goto put_transceiver;
  2420. }
  2421. retval = device_register(&udc->gadget.dev);
  2422. if (retval) {
  2423. put_device(&udc->gadget.dev);
  2424. goto put_transceiver;
  2425. }
  2426. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2427. retval = dbg_create_files(&udc->gadget.dev);
  2428. #endif
  2429. if (retval)
  2430. goto unreg_device;
  2431. if (udc->transceiver) {
  2432. retval = otg_set_peripheral(udc->transceiver->otg,
  2433. &udc->gadget);
  2434. if (retval)
  2435. goto remove_dbg;
  2436. }
  2437. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2438. if (retval)
  2439. goto remove_trans;
  2440. pm_runtime_no_callbacks(&udc->gadget.dev);
  2441. pm_runtime_enable(&udc->gadget.dev);
  2442. *_udc = udc;
  2443. return retval;
  2444. remove_trans:
  2445. if (udc->transceiver) {
  2446. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2447. usb_put_transceiver(udc->transceiver);
  2448. }
  2449. dev_err(dev, "error = %i\n", retval);
  2450. remove_dbg:
  2451. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2452. dbg_remove_files(&udc->gadget.dev);
  2453. #endif
  2454. unreg_device:
  2455. device_unregister(&udc->gadget.dev);
  2456. put_transceiver:
  2457. if (udc->transceiver)
  2458. usb_put_transceiver(udc->transceiver);
  2459. free_pools:
  2460. dma_pool_destroy(udc->td_pool);
  2461. free_qh_pool:
  2462. dma_pool_destroy(udc->qh_pool);
  2463. free_udc:
  2464. kfree(udc);
  2465. *_udc = NULL;
  2466. return retval;
  2467. }
  2468. /**
  2469. * udc_remove: parent remove must call this to remove UDC
  2470. *
  2471. * No interrupts active, the IRQ has been released
  2472. */
  2473. static void udc_remove(struct ci13xxx *udc)
  2474. {
  2475. int i;
  2476. if (udc == NULL)
  2477. return;
  2478. usb_del_gadget_udc(&udc->gadget);
  2479. for (i = 0; i < udc->hw_ep_max; i++) {
  2480. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2481. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2482. }
  2483. dma_pool_destroy(udc->td_pool);
  2484. dma_pool_destroy(udc->qh_pool);
  2485. if (udc->transceiver) {
  2486. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2487. usb_put_transceiver(udc->transceiver);
  2488. }
  2489. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2490. dbg_remove_files(&udc->gadget.dev);
  2491. #endif
  2492. device_unregister(&udc->gadget.dev);
  2493. kfree(udc->hw_bank.regmap);
  2494. kfree(udc);
  2495. }
  2496. static int __devinit ci_udc_probe(struct platform_device *pdev)
  2497. {
  2498. struct device *dev = &pdev->dev;
  2499. struct ci13xxx_udc_driver *driver = dev->platform_data;
  2500. struct ci13xxx *udc;
  2501. struct resource *res;
  2502. void __iomem *base;
  2503. int ret;
  2504. if (!driver) {
  2505. dev_err(dev, "platform data missing\n");
  2506. return -ENODEV;
  2507. }
  2508. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2509. if (!res) {
  2510. dev_err(dev, "missing resource\n");
  2511. return -ENODEV;
  2512. }
  2513. base = devm_request_and_ioremap(dev, res);
  2514. if (!res) {
  2515. dev_err(dev, "can't request and ioremap resource\n");
  2516. return -ENOMEM;
  2517. }
  2518. ret = udc_probe(driver, dev, base, &udc);
  2519. if (ret)
  2520. return ret;
  2521. udc->irq = platform_get_irq(pdev, 0);
  2522. if (udc->irq < 0) {
  2523. dev_err(dev, "missing IRQ\n");
  2524. ret = -ENODEV;
  2525. goto out;
  2526. }
  2527. platform_set_drvdata(pdev, udc);
  2528. ret = request_irq(udc->irq, udc_irq, IRQF_SHARED, driver->name, udc);
  2529. out:
  2530. if (ret)
  2531. udc_remove(udc);
  2532. return ret;
  2533. }
  2534. static int __devexit ci_udc_remove(struct platform_device *pdev)
  2535. {
  2536. struct ci13xxx *udc = platform_get_drvdata(pdev);
  2537. free_irq(udc->irq, udc);
  2538. udc_remove(udc);
  2539. return 0;
  2540. }
  2541. static struct platform_driver ci_udc_driver = {
  2542. .probe = ci_udc_probe,
  2543. .remove = __devexit_p(ci_udc_remove),
  2544. .driver = {
  2545. .name = "ci_udc",
  2546. },
  2547. };
  2548. module_platform_driver(ci_udc_driver);
  2549. MODULE_ALIAS("platform:ci_udc");
  2550. MODULE_ALIAS("platform:ci13xxx");
  2551. MODULE_LICENSE("GPL v2");
  2552. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  2553. MODULE_DESCRIPTION("ChipIdea UDC Driver");