imx28.dtsi 8.1 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. };
  21. cpus {
  22. cpu@0 {
  23. compatible = "arm,arm926ejs";
  24. };
  25. };
  26. apb@80000000 {
  27. compatible = "simple-bus";
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. reg = <0x80000000 0x80000>;
  31. ranges;
  32. apbh@80000000 {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. reg = <0x80000000 0x3c900>;
  37. ranges;
  38. icoll: interrupt-controller@80000000 {
  39. compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
  40. interrupt-controller;
  41. #interrupt-cells = <1>;
  42. reg = <0x80000000 0x2000>;
  43. };
  44. hsadc@80002000 {
  45. reg = <0x80002000 2000>;
  46. interrupts = <13 87>;
  47. status = "disabled";
  48. };
  49. dma-apbh@80004000 {
  50. compatible = "fsl,imx28-dma-apbh";
  51. reg = <0x80004000 2000>;
  52. };
  53. perfmon@80006000 {
  54. reg = <0x80006000 800>;
  55. interrupts = <27>;
  56. status = "disabled";
  57. };
  58. bch@8000a000 {
  59. reg = <0x8000a000 2000>;
  60. interrupts = <41>;
  61. status = "disabled";
  62. };
  63. gpmi@8000c000 {
  64. reg = <0x8000c000 2000>;
  65. interrupts = <42 88>;
  66. status = "disabled";
  67. };
  68. ssp0: ssp@80010000 {
  69. reg = <0x80010000 2000>;
  70. interrupts = <96 82>;
  71. status = "disabled";
  72. };
  73. ssp1: ssp@80012000 {
  74. reg = <0x80012000 2000>;
  75. interrupts = <97 83>;
  76. status = "disabled";
  77. };
  78. ssp2: ssp@80014000 {
  79. reg = <0x80014000 2000>;
  80. interrupts = <98 84>;
  81. status = "disabled";
  82. };
  83. ssp3: ssp@80016000 {
  84. reg = <0x80016000 2000>;
  85. interrupts = <99 85>;
  86. status = "disabled";
  87. };
  88. pinctrl@80018000 {
  89. #address-cells = <1>;
  90. #size-cells = <0>;
  91. compatible = "fsl,imx28-pinctrl", "simple-bus";
  92. reg = <0x80018000 2000>;
  93. gpio0: gpio@0 {
  94. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  95. interrupts = <127>;
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. interrupt-controller;
  99. #interrupt-cells = <2>;
  100. };
  101. gpio1: gpio@1 {
  102. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  103. interrupts = <126>;
  104. gpio-controller;
  105. #gpio-cells = <2>;
  106. interrupt-controller;
  107. #interrupt-cells = <2>;
  108. };
  109. gpio2: gpio@2 {
  110. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  111. interrupts = <125>;
  112. gpio-controller;
  113. #gpio-cells = <2>;
  114. interrupt-controller;
  115. #interrupt-cells = <2>;
  116. };
  117. gpio3: gpio@3 {
  118. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  119. interrupts = <124>;
  120. gpio-controller;
  121. #gpio-cells = <2>;
  122. interrupt-controller;
  123. #interrupt-cells = <2>;
  124. };
  125. gpio4: gpio@4 {
  126. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  127. interrupts = <123>;
  128. gpio-controller;
  129. #gpio-cells = <2>;
  130. interrupt-controller;
  131. #interrupt-cells = <2>;
  132. };
  133. duart_pins_a: duart@0 {
  134. reg = <0>;
  135. fsl,pinmux-ids = <0x3102 0x3112>;
  136. fsl,drive-strength = <0>;
  137. fsl,voltage = <1>;
  138. fsl,pull-up = <0>;
  139. };
  140. mac0_pins_a: mac0@0 {
  141. reg = <0>;
  142. fsl,pinmux-ids = <0x4000 0x4010 0x4020
  143. 0x4030 0x4040 0x4060 0x4070
  144. 0x4080 0x4100>;
  145. fsl,drive-strength = <1>;
  146. fsl,voltage = <1>;
  147. fsl,pull-up = <1>;
  148. };
  149. mac1_pins_a: mac1@0 {
  150. reg = <0>;
  151. fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
  152. 0x40e1 0x40b1 0x40c1>;
  153. fsl,drive-strength = <1>;
  154. fsl,voltage = <1>;
  155. fsl,pull-up = <1>;
  156. };
  157. };
  158. digctl@8001c000 {
  159. reg = <0x8001c000 2000>;
  160. interrupts = <89>;
  161. status = "disabled";
  162. };
  163. etm@80022000 {
  164. reg = <0x80022000 2000>;
  165. status = "disabled";
  166. };
  167. dma-apbx@80024000 {
  168. compatible = "fsl,imx28-dma-apbx";
  169. reg = <0x80024000 2000>;
  170. };
  171. dcp@80028000 {
  172. reg = <0x80028000 2000>;
  173. interrupts = <52 53 54>;
  174. status = "disabled";
  175. };
  176. pxp@8002a000 {
  177. reg = <0x8002a000 2000>;
  178. interrupts = <39>;
  179. status = "disabled";
  180. };
  181. ocotp@8002c000 {
  182. reg = <0x8002c000 2000>;
  183. status = "disabled";
  184. };
  185. axi-ahb@8002e000 {
  186. reg = <0x8002e000 2000>;
  187. status = "disabled";
  188. };
  189. lcdif@80030000 {
  190. reg = <0x80030000 2000>;
  191. interrupts = <38 86>;
  192. status = "disabled";
  193. };
  194. can0: can@80032000 {
  195. reg = <0x80032000 2000>;
  196. interrupts = <8>;
  197. status = "disabled";
  198. };
  199. can1: can@80034000 {
  200. reg = <0x80034000 2000>;
  201. interrupts = <9>;
  202. status = "disabled";
  203. };
  204. simdbg@8003c000 {
  205. reg = <0x8003c000 200>;
  206. status = "disabled";
  207. };
  208. simgpmisel@8003c200 {
  209. reg = <0x8003c200 100>;
  210. status = "disabled";
  211. };
  212. simsspsel@8003c300 {
  213. reg = <0x8003c300 100>;
  214. status = "disabled";
  215. };
  216. simmemsel@8003c400 {
  217. reg = <0x8003c400 100>;
  218. status = "disabled";
  219. };
  220. gpiomon@8003c500 {
  221. reg = <0x8003c500 100>;
  222. status = "disabled";
  223. };
  224. simenet@8003c700 {
  225. reg = <0x8003c700 100>;
  226. status = "disabled";
  227. };
  228. armjtag@8003c800 {
  229. reg = <0x8003c800 100>;
  230. status = "disabled";
  231. };
  232. };
  233. apbx@80040000 {
  234. compatible = "simple-bus";
  235. #address-cells = <1>;
  236. #size-cells = <1>;
  237. reg = <0x80040000 0x40000>;
  238. ranges;
  239. clkctl@80040000 {
  240. reg = <0x80040000 2000>;
  241. status = "disabled";
  242. };
  243. saif0: saif@80042000 {
  244. reg = <0x80042000 2000>;
  245. interrupts = <59 80>;
  246. status = "disabled";
  247. };
  248. power@80044000 {
  249. reg = <0x80044000 2000>;
  250. status = "disabled";
  251. };
  252. saif1: saif@80046000 {
  253. reg = <0x80046000 2000>;
  254. interrupts = <58 81>;
  255. status = "disabled";
  256. };
  257. lradc@80050000 {
  258. reg = <0x80050000 2000>;
  259. status = "disabled";
  260. };
  261. spdif@80054000 {
  262. reg = <0x80054000 2000>;
  263. interrupts = <45 66>;
  264. status = "disabled";
  265. };
  266. rtc@80056000 {
  267. reg = <0x80056000 2000>;
  268. interrupts = <28 29>;
  269. status = "disabled";
  270. };
  271. i2c0: i2c@80058000 {
  272. reg = <0x80058000 2000>;
  273. interrupts = <111 68>;
  274. status = "disabled";
  275. };
  276. i2c1: i2c@8005a000 {
  277. reg = <0x8005a000 2000>;
  278. interrupts = <110 69>;
  279. status = "disabled";
  280. };
  281. pwm@80064000 {
  282. reg = <0x80064000 2000>;
  283. status = "disabled";
  284. };
  285. timrot@80068000 {
  286. reg = <0x80068000 2000>;
  287. status = "disabled";
  288. };
  289. auart0: serial@8006a000 {
  290. reg = <0x8006a000 0x2000>;
  291. interrupts = <112 70 71>;
  292. status = "disabled";
  293. };
  294. auart1: serial@8006c000 {
  295. reg = <0x8006c000 0x2000>;
  296. interrupts = <113 72 73>;
  297. status = "disabled";
  298. };
  299. auart2: serial@8006e000 {
  300. reg = <0x8006e000 0x2000>;
  301. interrupts = <114 74 75>;
  302. status = "disabled";
  303. };
  304. auart3: serial@80070000 {
  305. reg = <0x80070000 0x2000>;
  306. interrupts = <115 76 77>;
  307. status = "disabled";
  308. };
  309. auart4: serial@80072000 {
  310. reg = <0x80072000 0x2000>;
  311. interrupts = <116 78 79>;
  312. status = "disabled";
  313. };
  314. duart: serial@80074000 {
  315. compatible = "arm,pl011", "arm,primecell";
  316. reg = <0x80074000 0x1000>;
  317. interrupts = <47>;
  318. status = "disabled";
  319. };
  320. usbphy0: usbphy@8007c000 {
  321. reg = <0x8007c000 0x2000>;
  322. status = "disabled";
  323. };
  324. usbphy1: usbphy@8007e000 {
  325. reg = <0x8007e000 0x2000>;
  326. status = "disabled";
  327. };
  328. };
  329. };
  330. ahb@80080000 {
  331. compatible = "simple-bus";
  332. #address-cells = <1>;
  333. #size-cells = <1>;
  334. reg = <0x80080000 0x80000>;
  335. ranges;
  336. usbctrl0: usbctrl@80080000 {
  337. reg = <0x80080000 0x10000>;
  338. status = "disabled";
  339. };
  340. usbctrl1: usbctrl@80090000 {
  341. reg = <0x80090000 0x10000>;
  342. status = "disabled";
  343. };
  344. dflpt@800c0000 {
  345. reg = <0x800c0000 0x10000>;
  346. status = "disabled";
  347. };
  348. mac0: ethernet@800f0000 {
  349. compatible = "fsl,imx28-fec";
  350. reg = <0x800f0000 0x4000>;
  351. interrupts = <101>;
  352. status = "disabled";
  353. };
  354. mac1: ethernet@800f4000 {
  355. compatible = "fsl,imx28-fec";
  356. reg = <0x800f4000 0x4000>;
  357. interrupts = <102>;
  358. status = "disabled";
  359. };
  360. switch@800f8000 {
  361. reg = <0x800f8000 0x8000>;
  362. status = "disabled";
  363. };
  364. };
  365. };