i6300esb.h 2.4 KB

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  1. /*
  2. * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
  3. *
  4. * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights Reserved.
  5. * http://www.kernelconcepts.de
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. *
  12. * Neither kernel concepts nor Nils Faerber admit liability nor provide
  13. * warranty for any of this software. This material is provided
  14. * "AS-IS" and at no charge.
  15. *
  16. * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>
  17. * developed for
  18. * Jentro AG, Haar/Munich (Germany)
  19. *
  20. * TCO timer driver for i8xx chipsets
  21. * based on softdog.c by Alan Cox <alan@redhat.com>
  22. *
  23. * For history and the complete list of supported I/O Controller Hub's
  24. * see i8xx_tco.c
  25. */
  26. /*
  27. * Some address definitions for the TCO
  28. */
  29. /* PCI configuration registers */
  30. #define ESB_CONFIG_REG 0x60 /* Config register */
  31. #define ESB_LOCK_REG 0x68 /* WDT lock register */
  32. /* Memory mapped registers */
  33. #define ESB_TIMER1_REG BASEADDR + 0x00 /* Timer1 value after each reset */
  34. #define ESB_TIMER2_REG BASEADDR + 0x04 /* Timer2 value after each reset */
  35. #define ESB_GINTSR_REG BASEADDR + 0x08 /* General Interrupt Status Register */
  36. #define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */
  37. /*
  38. * Some register bits
  39. */
  40. /* Lock register bits */
  41. #define ESB_WDT_FUNC ( 0x01 << 2 ) /* Watchdog functionality */
  42. #define ESB_WDT_ENABLE ( 0x01 << 1 ) /* Enable WDT */
  43. #define ESB_WDT_LOCK ( 0x01 << 0 ) /* Lock (nowayout) */
  44. /* Config register bits */
  45. #define ESB_WDT_REBOOT ( 0x01 << 5 ) /* Enable reboot on timeout */
  46. #define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */
  47. #define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */
  48. /* Reload register bits */
  49. #define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */
  50. /*
  51. * Some magic constants
  52. */
  53. #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
  54. #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */