cnic.c 124 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static struct workqueue_struct *cnic_wq;
  72. static void cnic_shutdown_rings(struct cnic_dev *);
  73. static void cnic_init_rings(struct cnic_dev *);
  74. static int cnic_cm_set_pg(struct cnic_sock *);
  75. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  76. {
  77. struct cnic_uio_dev *udev = uinfo->priv;
  78. struct cnic_dev *dev;
  79. if (!capable(CAP_NET_ADMIN))
  80. return -EPERM;
  81. if (udev->uio_dev != -1)
  82. return -EBUSY;
  83. rtnl_lock();
  84. dev = udev->dev;
  85. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  86. rtnl_unlock();
  87. return -ENODEV;
  88. }
  89. udev->uio_dev = iminor(inode);
  90. cnic_init_rings(dev);
  91. rtnl_unlock();
  92. return 0;
  93. }
  94. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  95. {
  96. struct cnic_uio_dev *udev = uinfo->priv;
  97. struct cnic_dev *dev = udev->dev;
  98. cnic_shutdown_rings(dev);
  99. udev->uio_dev = -1;
  100. return 0;
  101. }
  102. static inline void cnic_hold(struct cnic_dev *dev)
  103. {
  104. atomic_inc(&dev->ref_count);
  105. }
  106. static inline void cnic_put(struct cnic_dev *dev)
  107. {
  108. atomic_dec(&dev->ref_count);
  109. }
  110. static inline void csk_hold(struct cnic_sock *csk)
  111. {
  112. atomic_inc(&csk->ref_count);
  113. }
  114. static inline void csk_put(struct cnic_sock *csk)
  115. {
  116. atomic_dec(&csk->ref_count);
  117. }
  118. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  119. {
  120. struct cnic_dev *cdev;
  121. read_lock(&cnic_dev_lock);
  122. list_for_each_entry(cdev, &cnic_dev_list, list) {
  123. if (netdev == cdev->netdev) {
  124. cnic_hold(cdev);
  125. read_unlock(&cnic_dev_lock);
  126. return cdev;
  127. }
  128. }
  129. read_unlock(&cnic_dev_lock);
  130. return NULL;
  131. }
  132. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  133. {
  134. atomic_inc(&ulp_ops->ref_count);
  135. }
  136. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  137. {
  138. atomic_dec(&ulp_ops->ref_count);
  139. }
  140. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  141. {
  142. struct cnic_local *cp = dev->cnic_priv;
  143. struct cnic_eth_dev *ethdev = cp->ethdev;
  144. struct drv_ctl_info info;
  145. struct drv_ctl_io *io = &info.data.io;
  146. info.cmd = DRV_CTL_CTX_WR_CMD;
  147. io->cid_addr = cid_addr;
  148. io->offset = off;
  149. io->data = val;
  150. ethdev->drv_ctl(dev->netdev, &info);
  151. }
  152. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  153. {
  154. struct cnic_local *cp = dev->cnic_priv;
  155. struct cnic_eth_dev *ethdev = cp->ethdev;
  156. struct drv_ctl_info info;
  157. struct drv_ctl_io *io = &info.data.io;
  158. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  159. io->offset = off;
  160. io->dma_addr = addr;
  161. ethdev->drv_ctl(dev->netdev, &info);
  162. }
  163. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  164. {
  165. struct cnic_local *cp = dev->cnic_priv;
  166. struct cnic_eth_dev *ethdev = cp->ethdev;
  167. struct drv_ctl_info info;
  168. struct drv_ctl_l2_ring *ring = &info.data.ring;
  169. if (start)
  170. info.cmd = DRV_CTL_START_L2_CMD;
  171. else
  172. info.cmd = DRV_CTL_STOP_L2_CMD;
  173. ring->cid = cid;
  174. ring->client_id = cl_id;
  175. ethdev->drv_ctl(dev->netdev, &info);
  176. }
  177. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  178. {
  179. struct cnic_local *cp = dev->cnic_priv;
  180. struct cnic_eth_dev *ethdev = cp->ethdev;
  181. struct drv_ctl_info info;
  182. struct drv_ctl_io *io = &info.data.io;
  183. info.cmd = DRV_CTL_IO_WR_CMD;
  184. io->offset = off;
  185. io->data = val;
  186. ethdev->drv_ctl(dev->netdev, &info);
  187. }
  188. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  189. {
  190. struct cnic_local *cp = dev->cnic_priv;
  191. struct cnic_eth_dev *ethdev = cp->ethdev;
  192. struct drv_ctl_info info;
  193. struct drv_ctl_io *io = &info.data.io;
  194. info.cmd = DRV_CTL_IO_RD_CMD;
  195. io->offset = off;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. return io->data;
  198. }
  199. static int cnic_in_use(struct cnic_sock *csk)
  200. {
  201. return test_bit(SK_F_INUSE, &csk->flags);
  202. }
  203. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  204. {
  205. struct cnic_local *cp = dev->cnic_priv;
  206. struct cnic_eth_dev *ethdev = cp->ethdev;
  207. struct drv_ctl_info info;
  208. info.cmd = cmd;
  209. info.data.credit.credit_count = count;
  210. ethdev->drv_ctl(dev->netdev, &info);
  211. }
  212. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  213. {
  214. u32 i;
  215. for (i = 0; i < cp->max_cid_space; i++) {
  216. if (cp->ctx_tbl[i].cid == cid) {
  217. *l5_cid = i;
  218. return 0;
  219. }
  220. }
  221. return -EINVAL;
  222. }
  223. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  224. struct cnic_sock *csk)
  225. {
  226. struct iscsi_path path_req;
  227. char *buf = NULL;
  228. u16 len = 0;
  229. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  230. struct cnic_ulp_ops *ulp_ops;
  231. struct cnic_uio_dev *udev = cp->udev;
  232. if (!udev || udev->uio_dev == -1)
  233. return -ENODEV;
  234. if (csk) {
  235. len = sizeof(path_req);
  236. buf = (char *) &path_req;
  237. memset(&path_req, 0, len);
  238. msg_type = ISCSI_KEVENT_PATH_REQ;
  239. path_req.handle = (u64) csk->l5_cid;
  240. if (test_bit(SK_F_IPV6, &csk->flags)) {
  241. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  242. sizeof(struct in6_addr));
  243. path_req.ip_addr_len = 16;
  244. } else {
  245. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  246. sizeof(struct in_addr));
  247. path_req.ip_addr_len = 4;
  248. }
  249. path_req.vlan_id = csk->vlan_id;
  250. path_req.pmtu = csk->mtu;
  251. }
  252. rcu_read_lock();
  253. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  254. if (ulp_ops)
  255. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  256. rcu_read_unlock();
  257. return 0;
  258. }
  259. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  260. char *buf, u16 len)
  261. {
  262. int rc = -EINVAL;
  263. switch (msg_type) {
  264. case ISCSI_UEVENT_PATH_UPDATE: {
  265. struct cnic_local *cp;
  266. u32 l5_cid;
  267. struct cnic_sock *csk;
  268. struct iscsi_path *path_resp;
  269. if (len < sizeof(*path_resp))
  270. break;
  271. path_resp = (struct iscsi_path *) buf;
  272. cp = dev->cnic_priv;
  273. l5_cid = (u32) path_resp->handle;
  274. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  275. break;
  276. rcu_read_lock();
  277. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  278. rc = -ENODEV;
  279. rcu_read_unlock();
  280. break;
  281. }
  282. csk = &cp->csk_tbl[l5_cid];
  283. csk_hold(csk);
  284. if (cnic_in_use(csk)) {
  285. memcpy(csk->ha, path_resp->mac_addr, 6);
  286. if (test_bit(SK_F_IPV6, &csk->flags))
  287. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  288. sizeof(struct in6_addr));
  289. else
  290. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  291. sizeof(struct in_addr));
  292. if (is_valid_ether_addr(csk->ha))
  293. cnic_cm_set_pg(csk);
  294. }
  295. csk_put(csk);
  296. rcu_read_unlock();
  297. rc = 0;
  298. }
  299. }
  300. return rc;
  301. }
  302. static int cnic_offld_prep(struct cnic_sock *csk)
  303. {
  304. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  305. return 0;
  306. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  307. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  308. return 0;
  309. }
  310. return 1;
  311. }
  312. static int cnic_close_prep(struct cnic_sock *csk)
  313. {
  314. clear_bit(SK_F_CONNECT_START, &csk->flags);
  315. smp_mb__after_clear_bit();
  316. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  317. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  318. msleep(1);
  319. return 1;
  320. }
  321. return 0;
  322. }
  323. static int cnic_abort_prep(struct cnic_sock *csk)
  324. {
  325. clear_bit(SK_F_CONNECT_START, &csk->flags);
  326. smp_mb__after_clear_bit();
  327. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  328. msleep(1);
  329. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  330. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  331. return 1;
  332. }
  333. return 0;
  334. }
  335. static void cnic_uio_stop(void)
  336. {
  337. struct cnic_dev *dev;
  338. read_lock(&cnic_dev_lock);
  339. list_for_each_entry(dev, &cnic_dev_list, list) {
  340. struct cnic_local *cp = dev->cnic_priv;
  341. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  342. }
  343. read_unlock(&cnic_dev_lock);
  344. }
  345. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  346. {
  347. struct cnic_dev *dev;
  348. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  349. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  350. return -EINVAL;
  351. }
  352. mutex_lock(&cnic_lock);
  353. if (cnic_ulp_tbl[ulp_type]) {
  354. pr_err("%s: Type %d has already been registered\n",
  355. __func__, ulp_type);
  356. mutex_unlock(&cnic_lock);
  357. return -EBUSY;
  358. }
  359. read_lock(&cnic_dev_lock);
  360. list_for_each_entry(dev, &cnic_dev_list, list) {
  361. struct cnic_local *cp = dev->cnic_priv;
  362. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  363. }
  364. read_unlock(&cnic_dev_lock);
  365. atomic_set(&ulp_ops->ref_count, 0);
  366. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  367. mutex_unlock(&cnic_lock);
  368. /* Prevent race conditions with netdev_event */
  369. rtnl_lock();
  370. read_lock(&cnic_dev_lock);
  371. list_for_each_entry(dev, &cnic_dev_list, list) {
  372. struct cnic_local *cp = dev->cnic_priv;
  373. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  374. ulp_ops->cnic_init(dev);
  375. }
  376. read_unlock(&cnic_dev_lock);
  377. rtnl_unlock();
  378. return 0;
  379. }
  380. int cnic_unregister_driver(int ulp_type)
  381. {
  382. struct cnic_dev *dev;
  383. struct cnic_ulp_ops *ulp_ops;
  384. int i = 0;
  385. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  386. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  387. return -EINVAL;
  388. }
  389. mutex_lock(&cnic_lock);
  390. ulp_ops = cnic_ulp_tbl[ulp_type];
  391. if (!ulp_ops) {
  392. pr_err("%s: Type %d has not been registered\n",
  393. __func__, ulp_type);
  394. goto out_unlock;
  395. }
  396. read_lock(&cnic_dev_lock);
  397. list_for_each_entry(dev, &cnic_dev_list, list) {
  398. struct cnic_local *cp = dev->cnic_priv;
  399. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  400. pr_err("%s: Type %d still has devices registered\n",
  401. __func__, ulp_type);
  402. read_unlock(&cnic_dev_lock);
  403. goto out_unlock;
  404. }
  405. }
  406. read_unlock(&cnic_dev_lock);
  407. if (ulp_type == CNIC_ULP_ISCSI)
  408. cnic_uio_stop();
  409. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  410. mutex_unlock(&cnic_lock);
  411. synchronize_rcu();
  412. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  413. msleep(100);
  414. i++;
  415. }
  416. if (atomic_read(&ulp_ops->ref_count) != 0)
  417. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  418. return 0;
  419. out_unlock:
  420. mutex_unlock(&cnic_lock);
  421. return -EINVAL;
  422. }
  423. static int cnic_start_hw(struct cnic_dev *);
  424. static void cnic_stop_hw(struct cnic_dev *);
  425. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  426. void *ulp_ctx)
  427. {
  428. struct cnic_local *cp = dev->cnic_priv;
  429. struct cnic_ulp_ops *ulp_ops;
  430. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  431. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  432. return -EINVAL;
  433. }
  434. mutex_lock(&cnic_lock);
  435. if (cnic_ulp_tbl[ulp_type] == NULL) {
  436. pr_err("%s: Driver with type %d has not been registered\n",
  437. __func__, ulp_type);
  438. mutex_unlock(&cnic_lock);
  439. return -EAGAIN;
  440. }
  441. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  442. pr_err("%s: Type %d has already been registered to this device\n",
  443. __func__, ulp_type);
  444. mutex_unlock(&cnic_lock);
  445. return -EBUSY;
  446. }
  447. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  448. cp->ulp_handle[ulp_type] = ulp_ctx;
  449. ulp_ops = cnic_ulp_tbl[ulp_type];
  450. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  451. cnic_hold(dev);
  452. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  453. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  454. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  455. mutex_unlock(&cnic_lock);
  456. return 0;
  457. }
  458. EXPORT_SYMBOL(cnic_register_driver);
  459. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  460. {
  461. struct cnic_local *cp = dev->cnic_priv;
  462. int i = 0;
  463. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  464. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  465. return -EINVAL;
  466. }
  467. mutex_lock(&cnic_lock);
  468. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  469. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  470. cnic_put(dev);
  471. } else {
  472. pr_err("%s: device not registered to this ulp type %d\n",
  473. __func__, ulp_type);
  474. mutex_unlock(&cnic_lock);
  475. return -EINVAL;
  476. }
  477. mutex_unlock(&cnic_lock);
  478. synchronize_rcu();
  479. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  480. i < 20) {
  481. msleep(100);
  482. i++;
  483. }
  484. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  485. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  486. return 0;
  487. }
  488. EXPORT_SYMBOL(cnic_unregister_driver);
  489. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  490. {
  491. id_tbl->start = start_id;
  492. id_tbl->max = size;
  493. id_tbl->next = 0;
  494. spin_lock_init(&id_tbl->lock);
  495. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  496. if (!id_tbl->table)
  497. return -ENOMEM;
  498. return 0;
  499. }
  500. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  501. {
  502. kfree(id_tbl->table);
  503. id_tbl->table = NULL;
  504. }
  505. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  506. {
  507. int ret = -1;
  508. id -= id_tbl->start;
  509. if (id >= id_tbl->max)
  510. return ret;
  511. spin_lock(&id_tbl->lock);
  512. if (!test_bit(id, id_tbl->table)) {
  513. set_bit(id, id_tbl->table);
  514. ret = 0;
  515. }
  516. spin_unlock(&id_tbl->lock);
  517. return ret;
  518. }
  519. /* Returns -1 if not successful */
  520. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  521. {
  522. u32 id;
  523. spin_lock(&id_tbl->lock);
  524. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  525. if (id >= id_tbl->max) {
  526. id = -1;
  527. if (id_tbl->next != 0) {
  528. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  529. if (id >= id_tbl->next)
  530. id = -1;
  531. }
  532. }
  533. if (id < id_tbl->max) {
  534. set_bit(id, id_tbl->table);
  535. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  536. id += id_tbl->start;
  537. }
  538. spin_unlock(&id_tbl->lock);
  539. return id;
  540. }
  541. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  542. {
  543. if (id == -1)
  544. return;
  545. id -= id_tbl->start;
  546. if (id >= id_tbl->max)
  547. return;
  548. clear_bit(id, id_tbl->table);
  549. }
  550. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  551. {
  552. int i;
  553. if (!dma->pg_arr)
  554. return;
  555. for (i = 0; i < dma->num_pages; i++) {
  556. if (dma->pg_arr[i]) {
  557. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  558. dma->pg_arr[i], dma->pg_map_arr[i]);
  559. dma->pg_arr[i] = NULL;
  560. }
  561. }
  562. if (dma->pgtbl) {
  563. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  564. dma->pgtbl, dma->pgtbl_map);
  565. dma->pgtbl = NULL;
  566. }
  567. kfree(dma->pg_arr);
  568. dma->pg_arr = NULL;
  569. dma->num_pages = 0;
  570. }
  571. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  572. {
  573. int i;
  574. u32 *page_table = dma->pgtbl;
  575. for (i = 0; i < dma->num_pages; i++) {
  576. /* Each entry needs to be in big endian format. */
  577. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  578. page_table++;
  579. *page_table = (u32) dma->pg_map_arr[i];
  580. page_table++;
  581. }
  582. }
  583. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  584. {
  585. int i;
  586. u32 *page_table = dma->pgtbl;
  587. for (i = 0; i < dma->num_pages; i++) {
  588. /* Each entry needs to be in little endian format. */
  589. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  590. page_table++;
  591. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  592. page_table++;
  593. }
  594. }
  595. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  596. int pages, int use_pg_tbl)
  597. {
  598. int i, size;
  599. struct cnic_local *cp = dev->cnic_priv;
  600. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  601. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  602. if (dma->pg_arr == NULL)
  603. return -ENOMEM;
  604. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  605. dma->num_pages = pages;
  606. for (i = 0; i < pages; i++) {
  607. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  608. BCM_PAGE_SIZE,
  609. &dma->pg_map_arr[i],
  610. GFP_ATOMIC);
  611. if (dma->pg_arr[i] == NULL)
  612. goto error;
  613. }
  614. if (!use_pg_tbl)
  615. return 0;
  616. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  617. ~(BCM_PAGE_SIZE - 1);
  618. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  619. &dma->pgtbl_map, GFP_ATOMIC);
  620. if (dma->pgtbl == NULL)
  621. goto error;
  622. cp->setup_pgtbl(dev, dma);
  623. return 0;
  624. error:
  625. cnic_free_dma(dev, dma);
  626. return -ENOMEM;
  627. }
  628. static void cnic_free_context(struct cnic_dev *dev)
  629. {
  630. struct cnic_local *cp = dev->cnic_priv;
  631. int i;
  632. for (i = 0; i < cp->ctx_blks; i++) {
  633. if (cp->ctx_arr[i].ctx) {
  634. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  635. cp->ctx_arr[i].ctx,
  636. cp->ctx_arr[i].mapping);
  637. cp->ctx_arr[i].ctx = NULL;
  638. }
  639. }
  640. }
  641. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  642. {
  643. uio_unregister_device(&udev->cnic_uinfo);
  644. if (udev->l2_buf) {
  645. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  646. udev->l2_buf, udev->l2_buf_map);
  647. udev->l2_buf = NULL;
  648. }
  649. if (udev->l2_ring) {
  650. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  651. udev->l2_ring, udev->l2_ring_map);
  652. udev->l2_ring = NULL;
  653. }
  654. }
  655. static void cnic_free_uio(struct cnic_uio_dev *udev)
  656. {
  657. if (!udev)
  658. return;
  659. __cnic_free_uio(udev);
  660. }
  661. static void cnic_free_resc(struct cnic_dev *dev)
  662. {
  663. struct cnic_local *cp = dev->cnic_priv;
  664. struct cnic_uio_dev *udev = cp->udev;
  665. int i = 0;
  666. if (udev) {
  667. while (udev->uio_dev != -1 && i < 15) {
  668. msleep(100);
  669. i++;
  670. }
  671. cnic_free_uio(udev);
  672. cp->udev = NULL;
  673. }
  674. cnic_free_context(dev);
  675. kfree(cp->ctx_arr);
  676. cp->ctx_arr = NULL;
  677. cp->ctx_blks = 0;
  678. cnic_free_dma(dev, &cp->gbl_buf_info);
  679. cnic_free_dma(dev, &cp->conn_buf_info);
  680. cnic_free_dma(dev, &cp->kwq_info);
  681. cnic_free_dma(dev, &cp->kwq_16_data_info);
  682. cnic_free_dma(dev, &cp->kcq1.dma);
  683. kfree(cp->iscsi_tbl);
  684. cp->iscsi_tbl = NULL;
  685. kfree(cp->ctx_tbl);
  686. cp->ctx_tbl = NULL;
  687. cnic_free_id_tbl(&cp->cid_tbl);
  688. }
  689. static int cnic_alloc_context(struct cnic_dev *dev)
  690. {
  691. struct cnic_local *cp = dev->cnic_priv;
  692. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  693. int i, k, arr_size;
  694. cp->ctx_blk_size = BCM_PAGE_SIZE;
  695. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  696. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  697. sizeof(struct cnic_ctx);
  698. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  699. if (cp->ctx_arr == NULL)
  700. return -ENOMEM;
  701. k = 0;
  702. for (i = 0; i < 2; i++) {
  703. u32 j, reg, off, lo, hi;
  704. if (i == 0)
  705. off = BNX2_PG_CTX_MAP;
  706. else
  707. off = BNX2_ISCSI_CTX_MAP;
  708. reg = cnic_reg_rd_ind(dev, off);
  709. lo = reg >> 16;
  710. hi = reg & 0xffff;
  711. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  712. cp->ctx_arr[k].cid = j;
  713. }
  714. cp->ctx_blks = k;
  715. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  716. cp->ctx_blks = 0;
  717. return -ENOMEM;
  718. }
  719. for (i = 0; i < cp->ctx_blks; i++) {
  720. cp->ctx_arr[i].ctx =
  721. dma_alloc_coherent(&dev->pcidev->dev,
  722. BCM_PAGE_SIZE,
  723. &cp->ctx_arr[i].mapping,
  724. GFP_KERNEL);
  725. if (cp->ctx_arr[i].ctx == NULL)
  726. return -ENOMEM;
  727. }
  728. }
  729. return 0;
  730. }
  731. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  732. {
  733. int err, i, is_bnx2 = 0;
  734. struct kcqe **kcq;
  735. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  736. is_bnx2 = 1;
  737. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  738. if (err)
  739. return err;
  740. kcq = (struct kcqe **) info->dma.pg_arr;
  741. info->kcq = kcq;
  742. if (is_bnx2)
  743. return 0;
  744. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  745. struct bnx2x_bd_chain_next *next =
  746. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  747. int j = i + 1;
  748. if (j >= KCQ_PAGE_CNT)
  749. j = 0;
  750. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  751. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  752. }
  753. return 0;
  754. }
  755. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  756. {
  757. struct cnic_local *cp = dev->cnic_priv;
  758. struct cnic_uio_dev *udev;
  759. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  760. if (!udev)
  761. return -ENOMEM;
  762. udev->uio_dev = -1;
  763. udev->dev = dev;
  764. udev->pdev = dev->pcidev;
  765. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  766. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  767. &udev->l2_ring_map,
  768. GFP_KERNEL | __GFP_COMP);
  769. if (!udev->l2_ring)
  770. return -ENOMEM;
  771. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  772. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  773. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  774. &udev->l2_buf_map,
  775. GFP_KERNEL | __GFP_COMP);
  776. if (!udev->l2_buf)
  777. return -ENOMEM;
  778. cp->udev = udev;
  779. return 0;
  780. }
  781. static int cnic_init_uio(struct cnic_dev *dev)
  782. {
  783. struct cnic_local *cp = dev->cnic_priv;
  784. struct cnic_uio_dev *udev = cp->udev;
  785. struct uio_info *uinfo;
  786. int ret = 0;
  787. if (!udev)
  788. return -ENOMEM;
  789. udev->uio_dev = -1;
  790. uinfo = &udev->cnic_uinfo;
  791. uinfo->mem[0].addr = dev->netdev->base_addr;
  792. uinfo->mem[0].internal_addr = dev->regview;
  793. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  794. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  795. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  796. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  797. PAGE_MASK;
  798. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  799. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  800. else
  801. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  802. uinfo->name = "bnx2_cnic";
  803. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  804. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  805. PAGE_MASK;
  806. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  807. uinfo->name = "bnx2x_cnic";
  808. }
  809. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  810. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  811. uinfo->mem[2].size = udev->l2_ring_size;
  812. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  813. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  814. uinfo->mem[3].size = udev->l2_buf_size;
  815. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  816. uinfo->version = CNIC_MODULE_VERSION;
  817. uinfo->irq = UIO_IRQ_CUSTOM;
  818. uinfo->open = cnic_uio_open;
  819. uinfo->release = cnic_uio_close;
  820. uinfo->priv = udev;
  821. ret = uio_register_device(&udev->pdev->dev, uinfo);
  822. return ret;
  823. }
  824. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  825. {
  826. struct cnic_local *cp = dev->cnic_priv;
  827. int ret;
  828. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  829. if (ret)
  830. goto error;
  831. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  832. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  833. if (ret)
  834. goto error;
  835. ret = cnic_alloc_context(dev);
  836. if (ret)
  837. goto error;
  838. ret = cnic_alloc_uio_rings(dev, 2);
  839. if (ret)
  840. goto error;
  841. ret = cnic_init_uio(dev);
  842. if (ret)
  843. goto error;
  844. return 0;
  845. error:
  846. cnic_free_resc(dev);
  847. return ret;
  848. }
  849. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  850. {
  851. struct cnic_local *cp = dev->cnic_priv;
  852. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  853. int total_mem, blks, i;
  854. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  855. blks = total_mem / ctx_blk_size;
  856. if (total_mem % ctx_blk_size)
  857. blks++;
  858. if (blks > cp->ethdev->ctx_tbl_len)
  859. return -ENOMEM;
  860. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  861. if (cp->ctx_arr == NULL)
  862. return -ENOMEM;
  863. cp->ctx_blks = blks;
  864. cp->ctx_blk_size = ctx_blk_size;
  865. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  866. cp->ctx_align = 0;
  867. else
  868. cp->ctx_align = ctx_blk_size;
  869. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  870. for (i = 0; i < blks; i++) {
  871. cp->ctx_arr[i].ctx =
  872. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  873. &cp->ctx_arr[i].mapping,
  874. GFP_KERNEL);
  875. if (cp->ctx_arr[i].ctx == NULL)
  876. return -ENOMEM;
  877. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  878. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  879. cnic_free_context(dev);
  880. cp->ctx_blk_size += cp->ctx_align;
  881. i = -1;
  882. continue;
  883. }
  884. }
  885. }
  886. return 0;
  887. }
  888. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  889. {
  890. struct cnic_local *cp = dev->cnic_priv;
  891. struct cnic_eth_dev *ethdev = cp->ethdev;
  892. u32 start_cid = ethdev->starting_cid;
  893. int i, j, n, ret, pages;
  894. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  895. cp->iro_arr = ethdev->iro_arr;
  896. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  897. cp->iscsi_start_cid = start_cid;
  898. if (start_cid < BNX2X_ISCSI_START_CID) {
  899. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  900. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  901. cp->max_cid_space += delta;
  902. }
  903. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  904. GFP_KERNEL);
  905. if (!cp->iscsi_tbl)
  906. goto error;
  907. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  908. cp->max_cid_space, GFP_KERNEL);
  909. if (!cp->ctx_tbl)
  910. goto error;
  911. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  912. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  913. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  914. }
  915. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  916. PAGE_SIZE;
  917. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  918. if (ret)
  919. return -ENOMEM;
  920. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  921. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  922. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  923. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  924. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  925. off;
  926. if ((i % n) == (n - 1))
  927. j++;
  928. }
  929. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  930. if (ret)
  931. goto error;
  932. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  933. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  934. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  935. if (ret)
  936. goto error;
  937. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  938. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  939. if (ret)
  940. goto error;
  941. ret = cnic_alloc_bnx2x_context(dev);
  942. if (ret)
  943. goto error;
  944. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  945. cp->l2_rx_ring_size = 15;
  946. ret = cnic_alloc_uio_rings(dev, 4);
  947. if (ret)
  948. goto error;
  949. ret = cnic_init_uio(dev);
  950. if (ret)
  951. goto error;
  952. return 0;
  953. error:
  954. cnic_free_resc(dev);
  955. return -ENOMEM;
  956. }
  957. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  958. {
  959. return cp->max_kwq_idx -
  960. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  961. }
  962. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  963. u32 num_wqes)
  964. {
  965. struct cnic_local *cp = dev->cnic_priv;
  966. struct kwqe *prod_qe;
  967. u16 prod, sw_prod, i;
  968. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  969. return -EAGAIN; /* bnx2 is down */
  970. spin_lock_bh(&cp->cnic_ulp_lock);
  971. if (num_wqes > cnic_kwq_avail(cp) &&
  972. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  973. spin_unlock_bh(&cp->cnic_ulp_lock);
  974. return -EAGAIN;
  975. }
  976. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  977. prod = cp->kwq_prod_idx;
  978. sw_prod = prod & MAX_KWQ_IDX;
  979. for (i = 0; i < num_wqes; i++) {
  980. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  981. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  982. prod++;
  983. sw_prod = prod & MAX_KWQ_IDX;
  984. }
  985. cp->kwq_prod_idx = prod;
  986. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  987. spin_unlock_bh(&cp->cnic_ulp_lock);
  988. return 0;
  989. }
  990. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  991. union l5cm_specific_data *l5_data)
  992. {
  993. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  994. dma_addr_t map;
  995. map = ctx->kwqe_data_mapping;
  996. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  997. l5_data->phy_address.hi = (u64) map >> 32;
  998. return ctx->kwqe_data;
  999. }
  1000. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1001. u32 type, union l5cm_specific_data *l5_data)
  1002. {
  1003. struct cnic_local *cp = dev->cnic_priv;
  1004. struct l5cm_spe kwqe;
  1005. struct kwqe_16 *kwq[1];
  1006. int ret;
  1007. kwqe.hdr.conn_and_cmd_data =
  1008. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1009. BNX2X_HW_CID(cp, cid)));
  1010. kwqe.hdr.type = cpu_to_le16(type);
  1011. kwqe.hdr.reserved1 = 0;
  1012. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1013. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1014. kwq[0] = (struct kwqe_16 *) &kwqe;
  1015. spin_lock_bh(&cp->cnic_ulp_lock);
  1016. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1017. spin_unlock_bh(&cp->cnic_ulp_lock);
  1018. if (ret == 1)
  1019. return 0;
  1020. return -EBUSY;
  1021. }
  1022. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1023. struct kcqe *cqes[], u32 num_cqes)
  1024. {
  1025. struct cnic_local *cp = dev->cnic_priv;
  1026. struct cnic_ulp_ops *ulp_ops;
  1027. rcu_read_lock();
  1028. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1029. if (likely(ulp_ops)) {
  1030. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1031. cqes, num_cqes);
  1032. }
  1033. rcu_read_unlock();
  1034. }
  1035. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1036. {
  1037. struct cnic_local *cp = dev->cnic_priv;
  1038. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1039. int hq_bds, pages;
  1040. u32 pfid = cp->pfid;
  1041. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1042. cp->num_ccells = req1->num_ccells_per_conn;
  1043. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1044. cp->num_iscsi_tasks;
  1045. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1046. BNX2X_ISCSI_R2TQE_SIZE;
  1047. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1048. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1049. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1050. cp->num_cqs = req1->num_cqs;
  1051. if (!dev->max_iscsi_conn)
  1052. return 0;
  1053. /* init Tstorm RAM */
  1054. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1055. req1->rq_num_wqes);
  1056. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1057. PAGE_SIZE);
  1058. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1059. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1060. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1061. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1062. req1->num_tasks_per_conn);
  1063. /* init Ustorm RAM */
  1064. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1065. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1066. req1->rq_buffer_size);
  1067. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1068. PAGE_SIZE);
  1069. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1070. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1071. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1072. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1073. req1->num_tasks_per_conn);
  1074. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1075. req1->rq_num_wqes);
  1076. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1077. req1->cq_num_wqes);
  1078. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1079. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1080. /* init Xstorm RAM */
  1081. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1082. PAGE_SIZE);
  1083. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1084. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1085. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1086. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1087. req1->num_tasks_per_conn);
  1088. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1089. hq_bds);
  1090. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1091. req1->num_tasks_per_conn);
  1092. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1093. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1094. /* init Cstorm RAM */
  1095. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1096. PAGE_SIZE);
  1097. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1098. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1099. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1100. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1101. req1->num_tasks_per_conn);
  1102. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1103. req1->cq_num_wqes);
  1104. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1105. hq_bds);
  1106. return 0;
  1107. }
  1108. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1109. {
  1110. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1111. struct cnic_local *cp = dev->cnic_priv;
  1112. u32 pfid = cp->pfid;
  1113. struct iscsi_kcqe kcqe;
  1114. struct kcqe *cqes[1];
  1115. memset(&kcqe, 0, sizeof(kcqe));
  1116. if (!dev->max_iscsi_conn) {
  1117. kcqe.completion_status =
  1118. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1119. goto done;
  1120. }
  1121. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1122. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1123. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1124. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1125. req2->error_bit_map[1]);
  1126. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1127. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1128. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1129. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1130. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1131. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1132. req2->error_bit_map[1]);
  1133. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1134. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1135. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1136. done:
  1137. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1138. cqes[0] = (struct kcqe *) &kcqe;
  1139. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1140. return 0;
  1141. }
  1142. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1143. {
  1144. struct cnic_local *cp = dev->cnic_priv;
  1145. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1146. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1147. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1148. cnic_free_dma(dev, &iscsi->hq_info);
  1149. cnic_free_dma(dev, &iscsi->r2tq_info);
  1150. cnic_free_dma(dev, &iscsi->task_array_info);
  1151. }
  1152. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1153. ctx->cid = 0;
  1154. }
  1155. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1156. {
  1157. u32 cid;
  1158. int ret, pages;
  1159. struct cnic_local *cp = dev->cnic_priv;
  1160. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1161. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1162. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1163. if (cid == -1) {
  1164. ret = -ENOMEM;
  1165. goto error;
  1166. }
  1167. ctx->cid = cid;
  1168. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1169. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1170. if (ret)
  1171. goto error;
  1172. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1173. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1174. if (ret)
  1175. goto error;
  1176. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1177. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1178. if (ret)
  1179. goto error;
  1180. return 0;
  1181. error:
  1182. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1183. return ret;
  1184. }
  1185. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1186. struct regpair *ctx_addr)
  1187. {
  1188. struct cnic_local *cp = dev->cnic_priv;
  1189. struct cnic_eth_dev *ethdev = cp->ethdev;
  1190. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1191. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1192. unsigned long align_off = 0;
  1193. dma_addr_t ctx_map;
  1194. void *ctx;
  1195. if (cp->ctx_align) {
  1196. unsigned long mask = cp->ctx_align - 1;
  1197. if (cp->ctx_arr[blk].mapping & mask)
  1198. align_off = cp->ctx_align -
  1199. (cp->ctx_arr[blk].mapping & mask);
  1200. }
  1201. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1202. (off * BNX2X_CONTEXT_MEM_SIZE);
  1203. ctx = cp->ctx_arr[blk].ctx + align_off +
  1204. (off * BNX2X_CONTEXT_MEM_SIZE);
  1205. if (init)
  1206. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1207. ctx_addr->lo = ctx_map & 0xffffffff;
  1208. ctx_addr->hi = (u64) ctx_map >> 32;
  1209. return ctx;
  1210. }
  1211. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1212. u32 num)
  1213. {
  1214. struct cnic_local *cp = dev->cnic_priv;
  1215. struct iscsi_kwqe_conn_offload1 *req1 =
  1216. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1217. struct iscsi_kwqe_conn_offload2 *req2 =
  1218. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1219. struct iscsi_kwqe_conn_offload3 *req3;
  1220. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1221. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1222. u32 cid = ctx->cid;
  1223. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1224. struct iscsi_context *ictx;
  1225. struct regpair context_addr;
  1226. int i, j, n = 2, n_max;
  1227. ctx->ctx_flags = 0;
  1228. if (!req2->num_additional_wqes)
  1229. return -EINVAL;
  1230. n_max = req2->num_additional_wqes + 2;
  1231. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1232. if (ictx == NULL)
  1233. return -ENOMEM;
  1234. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1235. ictx->xstorm_ag_context.hq_prod = 1;
  1236. ictx->xstorm_st_context.iscsi.first_burst_length =
  1237. ISCSI_DEF_FIRST_BURST_LEN;
  1238. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1239. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1240. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1241. req1->sq_page_table_addr_lo;
  1242. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1243. req1->sq_page_table_addr_hi;
  1244. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1245. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1246. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1247. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1248. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1249. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1250. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1251. iscsi->hq_info.pgtbl[0];
  1252. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1253. iscsi->hq_info.pgtbl[1];
  1254. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1255. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1256. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1257. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1258. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1259. iscsi->r2tq_info.pgtbl[0];
  1260. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1261. iscsi->r2tq_info.pgtbl[1];
  1262. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1263. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1264. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1265. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1266. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1267. BNX2X_ISCSI_PBL_NOT_CACHED;
  1268. ictx->xstorm_st_context.iscsi.flags.flags |=
  1269. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1270. ictx->xstorm_st_context.iscsi.flags.flags |=
  1271. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1272. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1273. /* TSTORM requires the base address of RQ DB & not PTE */
  1274. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1275. req2->rq_page_table_addr_lo & PAGE_MASK;
  1276. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1277. req2->rq_page_table_addr_hi;
  1278. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1279. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1280. ictx->tstorm_st_context.tcp.flags2 |=
  1281. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1282. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1283. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1284. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1285. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1286. req2->rq_page_table_addr_lo;
  1287. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1288. req2->rq_page_table_addr_hi;
  1289. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1290. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1291. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1292. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1293. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1294. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1295. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1296. iscsi->r2tq_info.pgtbl[0];
  1297. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1298. iscsi->r2tq_info.pgtbl[1];
  1299. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1300. req1->cq_page_table_addr_lo;
  1301. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1302. req1->cq_page_table_addr_hi;
  1303. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1304. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1305. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1306. ictx->ustorm_st_context.task_pbe_cache_index =
  1307. BNX2X_ISCSI_PBL_NOT_CACHED;
  1308. ictx->ustorm_st_context.task_pdu_cache_index =
  1309. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1310. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1311. if (j == 3) {
  1312. if (n >= n_max)
  1313. break;
  1314. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1315. j = 0;
  1316. }
  1317. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1318. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1319. req3->qp_first_pte[j].hi;
  1320. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1321. req3->qp_first_pte[j].lo;
  1322. }
  1323. ictx->ustorm_st_context.task_pbl_base.lo =
  1324. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1325. ictx->ustorm_st_context.task_pbl_base.hi =
  1326. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1327. ictx->ustorm_st_context.tce_phy_addr.lo =
  1328. iscsi->task_array_info.pgtbl[0];
  1329. ictx->ustorm_st_context.tce_phy_addr.hi =
  1330. iscsi->task_array_info.pgtbl[1];
  1331. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1332. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1333. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1334. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1335. ISCSI_DEF_MAX_BURST_LEN;
  1336. ictx->ustorm_st_context.negotiated_rx |=
  1337. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1338. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1339. ictx->cstorm_st_context.hq_pbl_base.lo =
  1340. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1341. ictx->cstorm_st_context.hq_pbl_base.hi =
  1342. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1343. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1344. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1345. ictx->cstorm_st_context.task_pbl_base.lo =
  1346. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1347. ictx->cstorm_st_context.task_pbl_base.hi =
  1348. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1349. /* CSTORM and USTORM initialization is different, CSTORM requires
  1350. * CQ DB base & not PTE addr */
  1351. ictx->cstorm_st_context.cq_db_base.lo =
  1352. req1->cq_page_table_addr_lo & PAGE_MASK;
  1353. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1354. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1355. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1356. for (i = 0; i < cp->num_cqs; i++) {
  1357. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1358. ISCSI_INITIAL_SN;
  1359. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1360. ISCSI_INITIAL_SN;
  1361. }
  1362. ictx->xstorm_ag_context.cdu_reserved =
  1363. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1364. ISCSI_CONNECTION_TYPE);
  1365. ictx->ustorm_ag_context.cdu_usage =
  1366. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1367. ISCSI_CONNECTION_TYPE);
  1368. return 0;
  1369. }
  1370. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1371. u32 num, int *work)
  1372. {
  1373. struct iscsi_kwqe_conn_offload1 *req1;
  1374. struct iscsi_kwqe_conn_offload2 *req2;
  1375. struct cnic_local *cp = dev->cnic_priv;
  1376. struct cnic_context *ctx;
  1377. struct iscsi_kcqe kcqe;
  1378. struct kcqe *cqes[1];
  1379. u32 l5_cid;
  1380. int ret = 0;
  1381. if (num < 2) {
  1382. *work = num;
  1383. return -EINVAL;
  1384. }
  1385. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1386. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1387. if ((num - 2) < req2->num_additional_wqes) {
  1388. *work = num;
  1389. return -EINVAL;
  1390. }
  1391. *work = 2 + req2->num_additional_wqes;;
  1392. l5_cid = req1->iscsi_conn_id;
  1393. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1394. return -EINVAL;
  1395. memset(&kcqe, 0, sizeof(kcqe));
  1396. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1397. kcqe.iscsi_conn_id = l5_cid;
  1398. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1399. ctx = &cp->ctx_tbl[l5_cid];
  1400. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1401. kcqe.completion_status =
  1402. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1403. goto done;
  1404. }
  1405. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1406. atomic_dec(&cp->iscsi_conn);
  1407. goto done;
  1408. }
  1409. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1410. if (ret) {
  1411. atomic_dec(&cp->iscsi_conn);
  1412. ret = 0;
  1413. goto done;
  1414. }
  1415. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1416. if (ret < 0) {
  1417. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1418. atomic_dec(&cp->iscsi_conn);
  1419. goto done;
  1420. }
  1421. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1422. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1423. done:
  1424. cqes[0] = (struct kcqe *) &kcqe;
  1425. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1426. return ret;
  1427. }
  1428. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1429. {
  1430. struct cnic_local *cp = dev->cnic_priv;
  1431. struct iscsi_kwqe_conn_update *req =
  1432. (struct iscsi_kwqe_conn_update *) kwqe;
  1433. void *data;
  1434. union l5cm_specific_data l5_data;
  1435. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1436. int ret;
  1437. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1438. return -EINVAL;
  1439. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1440. if (!data)
  1441. return -ENOMEM;
  1442. memcpy(data, kwqe, sizeof(struct kwqe));
  1443. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1444. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1445. return ret;
  1446. }
  1447. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1448. {
  1449. struct cnic_local *cp = dev->cnic_priv;
  1450. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1451. union l5cm_specific_data l5_data;
  1452. int ret;
  1453. u32 hw_cid, type;
  1454. init_waitqueue_head(&ctx->waitq);
  1455. ctx->wait_cond = 0;
  1456. memset(&l5_data, 0, sizeof(l5_data));
  1457. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1458. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  1459. & SPE_HDR_CONN_TYPE;
  1460. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1461. SPE_HDR_FUNCTION_ID);
  1462. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1463. hw_cid, type, &l5_data);
  1464. if (ret == 0)
  1465. wait_event(ctx->waitq, ctx->wait_cond);
  1466. return ret;
  1467. }
  1468. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1469. {
  1470. struct cnic_local *cp = dev->cnic_priv;
  1471. struct iscsi_kwqe_conn_destroy *req =
  1472. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1473. u32 l5_cid = req->reserved0;
  1474. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1475. int ret = 0;
  1476. struct iscsi_kcqe kcqe;
  1477. struct kcqe *cqes[1];
  1478. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1479. goto skip_cfc_delete;
  1480. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1481. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1482. if (delta > (2 * HZ))
  1483. delta = 0;
  1484. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1485. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1486. goto destroy_reply;
  1487. }
  1488. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1489. skip_cfc_delete:
  1490. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1491. atomic_dec(&cp->iscsi_conn);
  1492. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1493. destroy_reply:
  1494. memset(&kcqe, 0, sizeof(kcqe));
  1495. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1496. kcqe.iscsi_conn_id = l5_cid;
  1497. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1498. kcqe.iscsi_conn_context_id = req->context_id;
  1499. cqes[0] = (struct kcqe *) &kcqe;
  1500. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1501. return ret;
  1502. }
  1503. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1504. struct l4_kwq_connect_req1 *kwqe1,
  1505. struct l4_kwq_connect_req3 *kwqe3,
  1506. struct l5cm_active_conn_buffer *conn_buf)
  1507. {
  1508. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1509. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1510. &conn_buf->xstorm_conn_buffer;
  1511. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1512. &conn_buf->tstorm_conn_buffer;
  1513. struct regpair context_addr;
  1514. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1515. struct in6_addr src_ip, dst_ip;
  1516. int i;
  1517. u32 *addrp;
  1518. addrp = (u32 *) &conn_addr->local_ip_addr;
  1519. for (i = 0; i < 4; i++, addrp++)
  1520. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1521. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1522. for (i = 0; i < 4; i++, addrp++)
  1523. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1524. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1525. xstorm_buf->context_addr.hi = context_addr.hi;
  1526. xstorm_buf->context_addr.lo = context_addr.lo;
  1527. xstorm_buf->mss = 0xffff;
  1528. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1529. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1530. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1531. xstorm_buf->pseudo_header_checksum =
  1532. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1533. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1534. tstorm_buf->params |=
  1535. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1536. if (kwqe3->ka_timeout) {
  1537. tstorm_buf->ka_enable = 1;
  1538. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1539. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1540. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1541. }
  1542. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1543. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1544. tstorm_buf->max_rt_time = 0xffffffff;
  1545. }
  1546. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1547. {
  1548. struct cnic_local *cp = dev->cnic_priv;
  1549. u32 pfid = cp->pfid;
  1550. u8 *mac = dev->mac_addr;
  1551. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1552. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1553. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1554. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1555. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1556. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1557. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1558. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1559. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1560. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1561. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1562. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1563. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1564. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1565. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1566. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1567. mac[4]);
  1568. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1569. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1570. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1571. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1572. mac[2]);
  1573. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1574. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1575. mac[1]);
  1576. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1577. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1578. mac[0]);
  1579. }
  1580. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1581. {
  1582. struct cnic_local *cp = dev->cnic_priv;
  1583. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1584. u16 tstorm_flags = 0;
  1585. if (tcp_ts) {
  1586. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1587. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1588. }
  1589. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1590. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1591. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1592. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1593. }
  1594. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1595. u32 num, int *work)
  1596. {
  1597. struct cnic_local *cp = dev->cnic_priv;
  1598. struct l4_kwq_connect_req1 *kwqe1 =
  1599. (struct l4_kwq_connect_req1 *) wqes[0];
  1600. struct l4_kwq_connect_req3 *kwqe3;
  1601. struct l5cm_active_conn_buffer *conn_buf;
  1602. struct l5cm_conn_addr_params *conn_addr;
  1603. union l5cm_specific_data l5_data;
  1604. u32 l5_cid = kwqe1->pg_cid;
  1605. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1606. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1607. int ret;
  1608. if (num < 2) {
  1609. *work = num;
  1610. return -EINVAL;
  1611. }
  1612. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1613. *work = 3;
  1614. else
  1615. *work = 2;
  1616. if (num < *work) {
  1617. *work = num;
  1618. return -EINVAL;
  1619. }
  1620. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1621. netdev_err(dev->netdev, "conn_buf size too big\n");
  1622. return -ENOMEM;
  1623. }
  1624. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1625. if (!conn_buf)
  1626. return -ENOMEM;
  1627. memset(conn_buf, 0, sizeof(*conn_buf));
  1628. conn_addr = &conn_buf->conn_addr_buf;
  1629. conn_addr->remote_addr_0 = csk->ha[0];
  1630. conn_addr->remote_addr_1 = csk->ha[1];
  1631. conn_addr->remote_addr_2 = csk->ha[2];
  1632. conn_addr->remote_addr_3 = csk->ha[3];
  1633. conn_addr->remote_addr_4 = csk->ha[4];
  1634. conn_addr->remote_addr_5 = csk->ha[5];
  1635. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1636. struct l4_kwq_connect_req2 *kwqe2 =
  1637. (struct l4_kwq_connect_req2 *) wqes[1];
  1638. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1639. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1640. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1641. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1642. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1643. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1644. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1645. }
  1646. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1647. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1648. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1649. conn_addr->local_tcp_port = kwqe1->src_port;
  1650. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1651. conn_addr->pmtu = kwqe3->pmtu;
  1652. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1653. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1654. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1655. cnic_bnx2x_set_tcp_timestamp(dev,
  1656. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1657. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1658. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1659. if (!ret)
  1660. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1661. return ret;
  1662. }
  1663. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1664. {
  1665. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1666. union l5cm_specific_data l5_data;
  1667. int ret;
  1668. memset(&l5_data, 0, sizeof(l5_data));
  1669. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1670. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1671. return ret;
  1672. }
  1673. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1674. {
  1675. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1676. union l5cm_specific_data l5_data;
  1677. int ret;
  1678. memset(&l5_data, 0, sizeof(l5_data));
  1679. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1680. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1681. return ret;
  1682. }
  1683. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1684. {
  1685. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1686. struct l4_kcq kcqe;
  1687. struct kcqe *cqes[1];
  1688. memset(&kcqe, 0, sizeof(kcqe));
  1689. kcqe.pg_host_opaque = req->host_opaque;
  1690. kcqe.pg_cid = req->host_opaque;
  1691. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1692. cqes[0] = (struct kcqe *) &kcqe;
  1693. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1694. return 0;
  1695. }
  1696. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1697. {
  1698. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1699. struct l4_kcq kcqe;
  1700. struct kcqe *cqes[1];
  1701. memset(&kcqe, 0, sizeof(kcqe));
  1702. kcqe.pg_host_opaque = req->pg_host_opaque;
  1703. kcqe.pg_cid = req->pg_cid;
  1704. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1705. cqes[0] = (struct kcqe *) &kcqe;
  1706. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1707. return 0;
  1708. }
  1709. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1710. u32 num_wqes)
  1711. {
  1712. int i, work, ret;
  1713. u32 opcode;
  1714. struct kwqe *kwqe;
  1715. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1716. return -EAGAIN; /* bnx2 is down */
  1717. for (i = 0; i < num_wqes; ) {
  1718. kwqe = wqes[i];
  1719. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1720. work = 1;
  1721. switch (opcode) {
  1722. case ISCSI_KWQE_OPCODE_INIT1:
  1723. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1724. break;
  1725. case ISCSI_KWQE_OPCODE_INIT2:
  1726. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1727. break;
  1728. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1729. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1730. num_wqes - i, &work);
  1731. break;
  1732. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1733. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1734. break;
  1735. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1736. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1737. break;
  1738. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1739. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1740. &work);
  1741. break;
  1742. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1743. ret = cnic_bnx2x_close(dev, kwqe);
  1744. break;
  1745. case L4_KWQE_OPCODE_VALUE_RESET:
  1746. ret = cnic_bnx2x_reset(dev, kwqe);
  1747. break;
  1748. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1749. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1750. break;
  1751. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1752. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1753. break;
  1754. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1755. ret = 0;
  1756. break;
  1757. default:
  1758. ret = 0;
  1759. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1760. opcode);
  1761. break;
  1762. }
  1763. if (ret < 0)
  1764. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1765. opcode);
  1766. i += work;
  1767. }
  1768. return 0;
  1769. }
  1770. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1771. {
  1772. struct cnic_local *cp = dev->cnic_priv;
  1773. int i, j, comp = 0;
  1774. i = 0;
  1775. j = 1;
  1776. while (num_cqes) {
  1777. struct cnic_ulp_ops *ulp_ops;
  1778. int ulp_type;
  1779. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1780. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1781. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1782. comp++;
  1783. while (j < num_cqes) {
  1784. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1785. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1786. break;
  1787. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1788. comp++;
  1789. j++;
  1790. }
  1791. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1792. ulp_type = CNIC_ULP_RDMA;
  1793. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1794. ulp_type = CNIC_ULP_ISCSI;
  1795. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1796. ulp_type = CNIC_ULP_L4;
  1797. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1798. goto end;
  1799. else {
  1800. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1801. kcqe_op_flag);
  1802. goto end;
  1803. }
  1804. rcu_read_lock();
  1805. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1806. if (likely(ulp_ops)) {
  1807. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1808. cp->completed_kcq + i, j);
  1809. }
  1810. rcu_read_unlock();
  1811. end:
  1812. num_cqes -= j;
  1813. i += j;
  1814. j = 1;
  1815. }
  1816. if (unlikely(comp))
  1817. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  1818. }
  1819. static u16 cnic_bnx2_next_idx(u16 idx)
  1820. {
  1821. return idx + 1;
  1822. }
  1823. static u16 cnic_bnx2_hw_idx(u16 idx)
  1824. {
  1825. return idx;
  1826. }
  1827. static u16 cnic_bnx2x_next_idx(u16 idx)
  1828. {
  1829. idx++;
  1830. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1831. idx++;
  1832. return idx;
  1833. }
  1834. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1835. {
  1836. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1837. idx++;
  1838. return idx;
  1839. }
  1840. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  1841. {
  1842. struct cnic_local *cp = dev->cnic_priv;
  1843. u16 i, ri, hw_prod, last;
  1844. struct kcqe *kcqe;
  1845. int kcqe_cnt = 0, last_cnt = 0;
  1846. i = ri = last = info->sw_prod_idx;
  1847. ri &= MAX_KCQ_IDX;
  1848. hw_prod = *info->hw_prod_idx_ptr;
  1849. hw_prod = cp->hw_idx(hw_prod);
  1850. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1851. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1852. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1853. i = cp->next_idx(i);
  1854. ri = i & MAX_KCQ_IDX;
  1855. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1856. last_cnt = kcqe_cnt;
  1857. last = i;
  1858. }
  1859. }
  1860. info->sw_prod_idx = last;
  1861. return last_cnt;
  1862. }
  1863. static int cnic_l2_completion(struct cnic_local *cp)
  1864. {
  1865. u16 hw_cons, sw_cons;
  1866. struct cnic_uio_dev *udev = cp->udev;
  1867. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1868. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  1869. u32 cmd;
  1870. int comp = 0;
  1871. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1872. return 0;
  1873. hw_cons = *cp->rx_cons_ptr;
  1874. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1875. hw_cons++;
  1876. sw_cons = cp->rx_cons;
  1877. while (sw_cons != hw_cons) {
  1878. u8 cqe_fp_flags;
  1879. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1880. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1881. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1882. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1883. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1884. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1885. cmd == RAMROD_CMD_ID_ETH_HALT)
  1886. comp++;
  1887. }
  1888. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1889. }
  1890. return comp;
  1891. }
  1892. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1893. {
  1894. u16 rx_cons, tx_cons;
  1895. int comp = 0;
  1896. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  1897. return;
  1898. rx_cons = *cp->rx_cons_ptr;
  1899. tx_cons = *cp->tx_cons_ptr;
  1900. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1901. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1902. comp = cnic_l2_completion(cp);
  1903. cp->tx_cons = tx_cons;
  1904. cp->rx_cons = rx_cons;
  1905. if (cp->udev)
  1906. uio_event_notify(&cp->udev->cnic_uinfo);
  1907. }
  1908. if (comp)
  1909. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1910. }
  1911. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  1912. {
  1913. struct cnic_local *cp = dev->cnic_priv;
  1914. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1915. int kcqe_cnt;
  1916. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1917. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  1918. service_kcqes(dev, kcqe_cnt);
  1919. /* Tell compiler that status_blk fields can change. */
  1920. barrier();
  1921. if (status_idx != *cp->kcq1.status_idx_ptr) {
  1922. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1923. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1924. } else
  1925. break;
  1926. }
  1927. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  1928. cnic_chk_pkt_rings(cp);
  1929. return status_idx;
  1930. }
  1931. static int cnic_service_bnx2(void *data, void *status_blk)
  1932. {
  1933. struct cnic_dev *dev = data;
  1934. struct cnic_local *cp = dev->cnic_priv;
  1935. u32 status_idx = *cp->kcq1.status_idx_ptr;
  1936. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1937. return status_idx;
  1938. return cnic_service_bnx2_queues(dev);
  1939. }
  1940. static void cnic_service_bnx2_msix(unsigned long data)
  1941. {
  1942. struct cnic_dev *dev = (struct cnic_dev *) data;
  1943. struct cnic_local *cp = dev->cnic_priv;
  1944. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  1945. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1946. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1947. }
  1948. static void cnic_doirq(struct cnic_dev *dev)
  1949. {
  1950. struct cnic_local *cp = dev->cnic_priv;
  1951. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  1952. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1953. prefetch(cp->status_blk.gen);
  1954. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1955. tasklet_schedule(&cp->cnic_irq_task);
  1956. }
  1957. }
  1958. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1959. {
  1960. struct cnic_dev *dev = dev_instance;
  1961. struct cnic_local *cp = dev->cnic_priv;
  1962. if (cp->ack_int)
  1963. cp->ack_int(dev);
  1964. cnic_doirq(dev);
  1965. return IRQ_HANDLED;
  1966. }
  1967. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1968. u16 index, u8 op, u8 update)
  1969. {
  1970. struct cnic_local *cp = dev->cnic_priv;
  1971. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1972. COMMAND_REG_INT_ACK);
  1973. struct igu_ack_register igu_ack;
  1974. igu_ack.status_block_index = index;
  1975. igu_ack.sb_id_and_flags =
  1976. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1977. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1978. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1979. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1980. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1981. }
  1982. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1983. {
  1984. struct cnic_local *cp = dev->cnic_priv;
  1985. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  1986. IGU_INT_DISABLE, 0);
  1987. }
  1988. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  1989. {
  1990. u32 last_status = *info->status_idx_ptr;
  1991. int kcqe_cnt;
  1992. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  1993. service_kcqes(dev, kcqe_cnt);
  1994. /* Tell compiler that sblk fields can change. */
  1995. barrier();
  1996. if (last_status == *info->status_idx_ptr)
  1997. break;
  1998. last_status = *info->status_idx_ptr;
  1999. }
  2000. return last_status;
  2001. }
  2002. static void cnic_service_bnx2x_bh(unsigned long data)
  2003. {
  2004. struct cnic_dev *dev = (struct cnic_dev *) data;
  2005. struct cnic_local *cp = dev->cnic_priv;
  2006. u32 status_idx;
  2007. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2008. return;
  2009. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2010. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2011. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2012. status_idx, IGU_INT_ENABLE, 1);
  2013. }
  2014. static int cnic_service_bnx2x(void *data, void *status_blk)
  2015. {
  2016. struct cnic_dev *dev = data;
  2017. struct cnic_local *cp = dev->cnic_priv;
  2018. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2019. cnic_doirq(dev);
  2020. cnic_chk_pkt_rings(cp);
  2021. return 0;
  2022. }
  2023. static void cnic_ulp_stop(struct cnic_dev *dev)
  2024. {
  2025. struct cnic_local *cp = dev->cnic_priv;
  2026. int if_type;
  2027. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2028. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2029. struct cnic_ulp_ops *ulp_ops;
  2030. mutex_lock(&cnic_lock);
  2031. ulp_ops = cp->ulp_ops[if_type];
  2032. if (!ulp_ops) {
  2033. mutex_unlock(&cnic_lock);
  2034. continue;
  2035. }
  2036. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2037. mutex_unlock(&cnic_lock);
  2038. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2039. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2040. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2041. }
  2042. }
  2043. static void cnic_ulp_start(struct cnic_dev *dev)
  2044. {
  2045. struct cnic_local *cp = dev->cnic_priv;
  2046. int if_type;
  2047. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2048. struct cnic_ulp_ops *ulp_ops;
  2049. mutex_lock(&cnic_lock);
  2050. ulp_ops = cp->ulp_ops[if_type];
  2051. if (!ulp_ops || !ulp_ops->cnic_start) {
  2052. mutex_unlock(&cnic_lock);
  2053. continue;
  2054. }
  2055. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2056. mutex_unlock(&cnic_lock);
  2057. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2058. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2059. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2060. }
  2061. }
  2062. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2063. {
  2064. struct cnic_dev *dev = data;
  2065. switch (info->cmd) {
  2066. case CNIC_CTL_STOP_CMD:
  2067. cnic_hold(dev);
  2068. cnic_ulp_stop(dev);
  2069. cnic_stop_hw(dev);
  2070. cnic_put(dev);
  2071. break;
  2072. case CNIC_CTL_START_CMD:
  2073. cnic_hold(dev);
  2074. if (!cnic_start_hw(dev))
  2075. cnic_ulp_start(dev);
  2076. cnic_put(dev);
  2077. break;
  2078. case CNIC_CTL_COMPLETION_CMD: {
  2079. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2080. u32 l5_cid;
  2081. struct cnic_local *cp = dev->cnic_priv;
  2082. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2083. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2084. ctx->wait_cond = 1;
  2085. wake_up(&ctx->waitq);
  2086. }
  2087. break;
  2088. }
  2089. default:
  2090. return -EINVAL;
  2091. }
  2092. return 0;
  2093. }
  2094. static void cnic_ulp_init(struct cnic_dev *dev)
  2095. {
  2096. int i;
  2097. struct cnic_local *cp = dev->cnic_priv;
  2098. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2099. struct cnic_ulp_ops *ulp_ops;
  2100. mutex_lock(&cnic_lock);
  2101. ulp_ops = cnic_ulp_tbl[i];
  2102. if (!ulp_ops || !ulp_ops->cnic_init) {
  2103. mutex_unlock(&cnic_lock);
  2104. continue;
  2105. }
  2106. ulp_get(ulp_ops);
  2107. mutex_unlock(&cnic_lock);
  2108. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2109. ulp_ops->cnic_init(dev);
  2110. ulp_put(ulp_ops);
  2111. }
  2112. }
  2113. static void cnic_ulp_exit(struct cnic_dev *dev)
  2114. {
  2115. int i;
  2116. struct cnic_local *cp = dev->cnic_priv;
  2117. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2118. struct cnic_ulp_ops *ulp_ops;
  2119. mutex_lock(&cnic_lock);
  2120. ulp_ops = cnic_ulp_tbl[i];
  2121. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2122. mutex_unlock(&cnic_lock);
  2123. continue;
  2124. }
  2125. ulp_get(ulp_ops);
  2126. mutex_unlock(&cnic_lock);
  2127. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2128. ulp_ops->cnic_exit(dev);
  2129. ulp_put(ulp_ops);
  2130. }
  2131. }
  2132. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2133. {
  2134. struct cnic_dev *dev = csk->dev;
  2135. struct l4_kwq_offload_pg *l4kwqe;
  2136. struct kwqe *wqes[1];
  2137. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2138. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2139. wqes[0] = (struct kwqe *) l4kwqe;
  2140. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2141. l4kwqe->flags =
  2142. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2143. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2144. l4kwqe->da0 = csk->ha[0];
  2145. l4kwqe->da1 = csk->ha[1];
  2146. l4kwqe->da2 = csk->ha[2];
  2147. l4kwqe->da3 = csk->ha[3];
  2148. l4kwqe->da4 = csk->ha[4];
  2149. l4kwqe->da5 = csk->ha[5];
  2150. l4kwqe->sa0 = dev->mac_addr[0];
  2151. l4kwqe->sa1 = dev->mac_addr[1];
  2152. l4kwqe->sa2 = dev->mac_addr[2];
  2153. l4kwqe->sa3 = dev->mac_addr[3];
  2154. l4kwqe->sa4 = dev->mac_addr[4];
  2155. l4kwqe->sa5 = dev->mac_addr[5];
  2156. l4kwqe->etype = ETH_P_IP;
  2157. l4kwqe->ipid_start = DEF_IPID_START;
  2158. l4kwqe->host_opaque = csk->l5_cid;
  2159. if (csk->vlan_id) {
  2160. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2161. l4kwqe->vlan_tag = csk->vlan_id;
  2162. l4kwqe->l2hdr_nbytes += 4;
  2163. }
  2164. return dev->submit_kwqes(dev, wqes, 1);
  2165. }
  2166. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2167. {
  2168. struct cnic_dev *dev = csk->dev;
  2169. struct l4_kwq_update_pg *l4kwqe;
  2170. struct kwqe *wqes[1];
  2171. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2172. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2173. wqes[0] = (struct kwqe *) l4kwqe;
  2174. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2175. l4kwqe->flags =
  2176. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2177. l4kwqe->pg_cid = csk->pg_cid;
  2178. l4kwqe->da0 = csk->ha[0];
  2179. l4kwqe->da1 = csk->ha[1];
  2180. l4kwqe->da2 = csk->ha[2];
  2181. l4kwqe->da3 = csk->ha[3];
  2182. l4kwqe->da4 = csk->ha[4];
  2183. l4kwqe->da5 = csk->ha[5];
  2184. l4kwqe->pg_host_opaque = csk->l5_cid;
  2185. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2186. return dev->submit_kwqes(dev, wqes, 1);
  2187. }
  2188. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2189. {
  2190. struct cnic_dev *dev = csk->dev;
  2191. struct l4_kwq_upload *l4kwqe;
  2192. struct kwqe *wqes[1];
  2193. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2194. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2195. wqes[0] = (struct kwqe *) l4kwqe;
  2196. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2197. l4kwqe->flags =
  2198. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2199. l4kwqe->cid = csk->pg_cid;
  2200. return dev->submit_kwqes(dev, wqes, 1);
  2201. }
  2202. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2203. {
  2204. struct cnic_dev *dev = csk->dev;
  2205. struct l4_kwq_connect_req1 *l4kwqe1;
  2206. struct l4_kwq_connect_req2 *l4kwqe2;
  2207. struct l4_kwq_connect_req3 *l4kwqe3;
  2208. struct kwqe *wqes[3];
  2209. u8 tcp_flags = 0;
  2210. int num_wqes = 2;
  2211. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2212. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2213. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2214. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2215. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2216. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2217. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2218. l4kwqe3->flags =
  2219. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2220. l4kwqe3->ka_timeout = csk->ka_timeout;
  2221. l4kwqe3->ka_interval = csk->ka_interval;
  2222. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2223. l4kwqe3->tos = csk->tos;
  2224. l4kwqe3->ttl = csk->ttl;
  2225. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2226. l4kwqe3->pmtu = csk->mtu;
  2227. l4kwqe3->rcv_buf = csk->rcv_buf;
  2228. l4kwqe3->snd_buf = csk->snd_buf;
  2229. l4kwqe3->seed = csk->seed;
  2230. wqes[0] = (struct kwqe *) l4kwqe1;
  2231. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2232. wqes[1] = (struct kwqe *) l4kwqe2;
  2233. wqes[2] = (struct kwqe *) l4kwqe3;
  2234. num_wqes = 3;
  2235. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2236. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2237. l4kwqe2->flags =
  2238. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2239. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2240. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2241. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2242. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2243. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2244. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2245. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2246. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2247. sizeof(struct tcphdr);
  2248. } else {
  2249. wqes[1] = (struct kwqe *) l4kwqe3;
  2250. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2251. sizeof(struct tcphdr);
  2252. }
  2253. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2254. l4kwqe1->flags =
  2255. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2256. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2257. l4kwqe1->cid = csk->cid;
  2258. l4kwqe1->pg_cid = csk->pg_cid;
  2259. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2260. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2261. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2262. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2263. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2264. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2265. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2266. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2267. if (csk->tcp_flags & SK_TCP_NAGLE)
  2268. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2269. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2270. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2271. if (csk->tcp_flags & SK_TCP_SACK)
  2272. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2273. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2274. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2275. l4kwqe1->tcp_flags = tcp_flags;
  2276. return dev->submit_kwqes(dev, wqes, num_wqes);
  2277. }
  2278. static int cnic_cm_close_req(struct cnic_sock *csk)
  2279. {
  2280. struct cnic_dev *dev = csk->dev;
  2281. struct l4_kwq_close_req *l4kwqe;
  2282. struct kwqe *wqes[1];
  2283. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2284. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2285. wqes[0] = (struct kwqe *) l4kwqe;
  2286. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2287. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2288. l4kwqe->cid = csk->cid;
  2289. return dev->submit_kwqes(dev, wqes, 1);
  2290. }
  2291. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2292. {
  2293. struct cnic_dev *dev = csk->dev;
  2294. struct l4_kwq_reset_req *l4kwqe;
  2295. struct kwqe *wqes[1];
  2296. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2297. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2298. wqes[0] = (struct kwqe *) l4kwqe;
  2299. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2300. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2301. l4kwqe->cid = csk->cid;
  2302. return dev->submit_kwqes(dev, wqes, 1);
  2303. }
  2304. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2305. u32 l5_cid, struct cnic_sock **csk, void *context)
  2306. {
  2307. struct cnic_local *cp = dev->cnic_priv;
  2308. struct cnic_sock *csk1;
  2309. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2310. return -EINVAL;
  2311. if (cp->ctx_tbl) {
  2312. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2313. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2314. return -EAGAIN;
  2315. }
  2316. csk1 = &cp->csk_tbl[l5_cid];
  2317. if (atomic_read(&csk1->ref_count))
  2318. return -EAGAIN;
  2319. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2320. return -EBUSY;
  2321. csk1->dev = dev;
  2322. csk1->cid = cid;
  2323. csk1->l5_cid = l5_cid;
  2324. csk1->ulp_type = ulp_type;
  2325. csk1->context = context;
  2326. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2327. csk1->ka_interval = DEF_KA_INTERVAL;
  2328. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2329. csk1->tos = DEF_TOS;
  2330. csk1->ttl = DEF_TTL;
  2331. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2332. csk1->rcv_buf = DEF_RCV_BUF;
  2333. csk1->snd_buf = DEF_SND_BUF;
  2334. csk1->seed = DEF_SEED;
  2335. *csk = csk1;
  2336. return 0;
  2337. }
  2338. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2339. {
  2340. if (csk->src_port) {
  2341. struct cnic_dev *dev = csk->dev;
  2342. struct cnic_local *cp = dev->cnic_priv;
  2343. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2344. csk->src_port = 0;
  2345. }
  2346. }
  2347. static void cnic_close_conn(struct cnic_sock *csk)
  2348. {
  2349. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2350. cnic_cm_upload_pg(csk);
  2351. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2352. }
  2353. cnic_cm_cleanup(csk);
  2354. }
  2355. static int cnic_cm_destroy(struct cnic_sock *csk)
  2356. {
  2357. if (!cnic_in_use(csk))
  2358. return -EINVAL;
  2359. csk_hold(csk);
  2360. clear_bit(SK_F_INUSE, &csk->flags);
  2361. smp_mb__after_clear_bit();
  2362. while (atomic_read(&csk->ref_count) != 1)
  2363. msleep(1);
  2364. cnic_cm_cleanup(csk);
  2365. csk->flags = 0;
  2366. csk_put(csk);
  2367. return 0;
  2368. }
  2369. static inline u16 cnic_get_vlan(struct net_device *dev,
  2370. struct net_device **vlan_dev)
  2371. {
  2372. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2373. *vlan_dev = vlan_dev_real_dev(dev);
  2374. return vlan_dev_vlan_id(dev);
  2375. }
  2376. *vlan_dev = dev;
  2377. return 0;
  2378. }
  2379. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2380. struct dst_entry **dst)
  2381. {
  2382. #if defined(CONFIG_INET)
  2383. struct flowi fl;
  2384. int err;
  2385. struct rtable *rt;
  2386. memset(&fl, 0, sizeof(fl));
  2387. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2388. err = ip_route_output_key(&init_net, &rt, &fl);
  2389. if (!err)
  2390. *dst = &rt->dst;
  2391. return err;
  2392. #else
  2393. return -ENETUNREACH;
  2394. #endif
  2395. }
  2396. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2397. struct dst_entry **dst)
  2398. {
  2399. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2400. struct flowi fl;
  2401. memset(&fl, 0, sizeof(fl));
  2402. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2403. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2404. fl.oif = dst_addr->sin6_scope_id;
  2405. *dst = ip6_route_output(&init_net, NULL, &fl);
  2406. if (*dst)
  2407. return 0;
  2408. #endif
  2409. return -ENETUNREACH;
  2410. }
  2411. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2412. int ulp_type)
  2413. {
  2414. struct cnic_dev *dev = NULL;
  2415. struct dst_entry *dst;
  2416. struct net_device *netdev = NULL;
  2417. int err = -ENETUNREACH;
  2418. if (dst_addr->sin_family == AF_INET)
  2419. err = cnic_get_v4_route(dst_addr, &dst);
  2420. else if (dst_addr->sin_family == AF_INET6) {
  2421. struct sockaddr_in6 *dst_addr6 =
  2422. (struct sockaddr_in6 *) dst_addr;
  2423. err = cnic_get_v6_route(dst_addr6, &dst);
  2424. } else
  2425. return NULL;
  2426. if (err)
  2427. return NULL;
  2428. if (!dst->dev)
  2429. goto done;
  2430. cnic_get_vlan(dst->dev, &netdev);
  2431. dev = cnic_from_netdev(netdev);
  2432. done:
  2433. dst_release(dst);
  2434. if (dev)
  2435. cnic_put(dev);
  2436. return dev;
  2437. }
  2438. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2439. {
  2440. struct cnic_dev *dev = csk->dev;
  2441. struct cnic_local *cp = dev->cnic_priv;
  2442. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2443. }
  2444. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2445. {
  2446. struct cnic_dev *dev = csk->dev;
  2447. struct cnic_local *cp = dev->cnic_priv;
  2448. int is_v6, rc = 0;
  2449. struct dst_entry *dst = NULL;
  2450. struct net_device *realdev;
  2451. u32 local_port;
  2452. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2453. saddr->remote.v6.sin6_family == AF_INET6)
  2454. is_v6 = 1;
  2455. else if (saddr->local.v4.sin_family == AF_INET &&
  2456. saddr->remote.v4.sin_family == AF_INET)
  2457. is_v6 = 0;
  2458. else
  2459. return -EINVAL;
  2460. clear_bit(SK_F_IPV6, &csk->flags);
  2461. if (is_v6) {
  2462. set_bit(SK_F_IPV6, &csk->flags);
  2463. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2464. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2465. sizeof(struct in6_addr));
  2466. csk->dst_port = saddr->remote.v6.sin6_port;
  2467. local_port = saddr->local.v6.sin6_port;
  2468. } else {
  2469. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2470. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2471. csk->dst_port = saddr->remote.v4.sin_port;
  2472. local_port = saddr->local.v4.sin_port;
  2473. }
  2474. csk->vlan_id = 0;
  2475. csk->mtu = dev->netdev->mtu;
  2476. if (dst && dst->dev) {
  2477. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2478. if (realdev == dev->netdev) {
  2479. csk->vlan_id = vlan;
  2480. csk->mtu = dst_mtu(dst);
  2481. }
  2482. }
  2483. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2484. local_port < CNIC_LOCAL_PORT_MAX) {
  2485. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2486. local_port = 0;
  2487. } else
  2488. local_port = 0;
  2489. if (!local_port) {
  2490. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2491. if (local_port == -1) {
  2492. rc = -ENOMEM;
  2493. goto err_out;
  2494. }
  2495. }
  2496. csk->src_port = local_port;
  2497. err_out:
  2498. dst_release(dst);
  2499. return rc;
  2500. }
  2501. static void cnic_init_csk_state(struct cnic_sock *csk)
  2502. {
  2503. csk->state = 0;
  2504. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2505. clear_bit(SK_F_CLOSING, &csk->flags);
  2506. }
  2507. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2508. {
  2509. int err = 0;
  2510. if (!cnic_in_use(csk))
  2511. return -EINVAL;
  2512. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2513. return -EINVAL;
  2514. cnic_init_csk_state(csk);
  2515. err = cnic_get_route(csk, saddr);
  2516. if (err)
  2517. goto err_out;
  2518. err = cnic_resolve_addr(csk, saddr);
  2519. if (!err)
  2520. return 0;
  2521. err_out:
  2522. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2523. return err;
  2524. }
  2525. static int cnic_cm_abort(struct cnic_sock *csk)
  2526. {
  2527. struct cnic_local *cp = csk->dev->cnic_priv;
  2528. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2529. if (!cnic_in_use(csk))
  2530. return -EINVAL;
  2531. if (cnic_abort_prep(csk))
  2532. return cnic_cm_abort_req(csk);
  2533. /* Getting here means that we haven't started connect, or
  2534. * connect was not successful.
  2535. */
  2536. cp->close_conn(csk, opcode);
  2537. if (csk->state != opcode)
  2538. return -EALREADY;
  2539. return 0;
  2540. }
  2541. static int cnic_cm_close(struct cnic_sock *csk)
  2542. {
  2543. if (!cnic_in_use(csk))
  2544. return -EINVAL;
  2545. if (cnic_close_prep(csk)) {
  2546. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2547. return cnic_cm_close_req(csk);
  2548. } else {
  2549. return -EALREADY;
  2550. }
  2551. return 0;
  2552. }
  2553. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2554. u8 opcode)
  2555. {
  2556. struct cnic_ulp_ops *ulp_ops;
  2557. int ulp_type = csk->ulp_type;
  2558. rcu_read_lock();
  2559. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2560. if (ulp_ops) {
  2561. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2562. ulp_ops->cm_connect_complete(csk);
  2563. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2564. ulp_ops->cm_close_complete(csk);
  2565. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2566. ulp_ops->cm_remote_abort(csk);
  2567. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2568. ulp_ops->cm_abort_complete(csk);
  2569. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2570. ulp_ops->cm_remote_close(csk);
  2571. }
  2572. rcu_read_unlock();
  2573. }
  2574. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2575. {
  2576. if (cnic_offld_prep(csk)) {
  2577. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2578. cnic_cm_update_pg(csk);
  2579. else
  2580. cnic_cm_offload_pg(csk);
  2581. }
  2582. return 0;
  2583. }
  2584. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2585. {
  2586. struct cnic_local *cp = dev->cnic_priv;
  2587. u32 l5_cid = kcqe->pg_host_opaque;
  2588. u8 opcode = kcqe->op_code;
  2589. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2590. csk_hold(csk);
  2591. if (!cnic_in_use(csk))
  2592. goto done;
  2593. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2594. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2595. goto done;
  2596. }
  2597. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2598. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2599. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2600. cnic_cm_upcall(cp, csk,
  2601. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2602. goto done;
  2603. }
  2604. csk->pg_cid = kcqe->pg_cid;
  2605. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2606. cnic_cm_conn_req(csk);
  2607. done:
  2608. csk_put(csk);
  2609. }
  2610. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2611. {
  2612. struct cnic_local *cp = dev->cnic_priv;
  2613. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2614. u8 opcode = l4kcqe->op_code;
  2615. u32 l5_cid;
  2616. struct cnic_sock *csk;
  2617. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2618. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2619. cnic_cm_process_offld_pg(dev, l4kcqe);
  2620. return;
  2621. }
  2622. l5_cid = l4kcqe->conn_id;
  2623. if (opcode & 0x80)
  2624. l5_cid = l4kcqe->cid;
  2625. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2626. return;
  2627. csk = &cp->csk_tbl[l5_cid];
  2628. csk_hold(csk);
  2629. if (!cnic_in_use(csk)) {
  2630. csk_put(csk);
  2631. return;
  2632. }
  2633. switch (opcode) {
  2634. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2635. if (l4kcqe->status != 0) {
  2636. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2637. cnic_cm_upcall(cp, csk,
  2638. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2639. }
  2640. break;
  2641. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2642. if (l4kcqe->status == 0)
  2643. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2644. smp_mb__before_clear_bit();
  2645. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2646. cnic_cm_upcall(cp, csk, opcode);
  2647. break;
  2648. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2649. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2650. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2651. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2652. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2653. cp->close_conn(csk, opcode);
  2654. break;
  2655. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2656. cnic_cm_upcall(cp, csk, opcode);
  2657. break;
  2658. }
  2659. csk_put(csk);
  2660. }
  2661. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2662. {
  2663. struct cnic_dev *dev = data;
  2664. int i;
  2665. for (i = 0; i < num; i++)
  2666. cnic_cm_process_kcqe(dev, kcqe[i]);
  2667. }
  2668. static struct cnic_ulp_ops cm_ulp_ops = {
  2669. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2670. };
  2671. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2672. {
  2673. struct cnic_local *cp = dev->cnic_priv;
  2674. kfree(cp->csk_tbl);
  2675. cp->csk_tbl = NULL;
  2676. cnic_free_id_tbl(&cp->csk_port_tbl);
  2677. }
  2678. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2679. {
  2680. struct cnic_local *cp = dev->cnic_priv;
  2681. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2682. GFP_KERNEL);
  2683. if (!cp->csk_tbl)
  2684. return -ENOMEM;
  2685. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2686. CNIC_LOCAL_PORT_MIN)) {
  2687. cnic_cm_free_mem(dev);
  2688. return -ENOMEM;
  2689. }
  2690. return 0;
  2691. }
  2692. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2693. {
  2694. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  2695. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  2696. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2697. csk->state = opcode;
  2698. }
  2699. /* 1. If event opcode matches the expected event in csk->state
  2700. * 2. If the expected event is CLOSE_COMP, we accept any event
  2701. * 3. If the expected event is 0, meaning the connection was never
  2702. * never established, we accept the opcode from cm_abort.
  2703. */
  2704. if (opcode == csk->state || csk->state == 0 ||
  2705. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  2706. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2707. if (csk->state == 0)
  2708. csk->state = opcode;
  2709. return 1;
  2710. }
  2711. }
  2712. return 0;
  2713. }
  2714. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2715. {
  2716. struct cnic_dev *dev = csk->dev;
  2717. struct cnic_local *cp = dev->cnic_priv;
  2718. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  2719. cnic_cm_upcall(cp, csk, opcode);
  2720. return;
  2721. }
  2722. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2723. cnic_close_conn(csk);
  2724. csk->state = opcode;
  2725. cnic_cm_upcall(cp, csk, opcode);
  2726. }
  2727. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2728. {
  2729. }
  2730. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2731. {
  2732. u32 seed;
  2733. get_random_bytes(&seed, 4);
  2734. cnic_ctx_wr(dev, 45, 0, seed);
  2735. return 0;
  2736. }
  2737. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2738. {
  2739. struct cnic_dev *dev = csk->dev;
  2740. struct cnic_local *cp = dev->cnic_priv;
  2741. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2742. union l5cm_specific_data l5_data;
  2743. u32 cmd = 0;
  2744. int close_complete = 0;
  2745. switch (opcode) {
  2746. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2747. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2748. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2749. if (cnic_ready_to_close(csk, opcode)) {
  2750. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2751. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2752. else
  2753. close_complete = 1;
  2754. }
  2755. break;
  2756. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2757. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2758. break;
  2759. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2760. close_complete = 1;
  2761. break;
  2762. }
  2763. if (cmd) {
  2764. memset(&l5_data, 0, sizeof(l5_data));
  2765. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2766. &l5_data);
  2767. } else if (close_complete) {
  2768. ctx->timestamp = jiffies;
  2769. cnic_close_conn(csk);
  2770. cnic_cm_upcall(cp, csk, csk->state);
  2771. }
  2772. }
  2773. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2774. {
  2775. struct cnic_local *cp = dev->cnic_priv;
  2776. int i;
  2777. if (!cp->ctx_tbl)
  2778. return;
  2779. if (!netif_running(dev->netdev))
  2780. return;
  2781. for (i = 0; i < cp->max_cid_space; i++) {
  2782. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2783. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2784. msleep(10);
  2785. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2786. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2787. ctx->cid);
  2788. }
  2789. cancel_delayed_work(&cp->delete_task);
  2790. flush_workqueue(cnic_wq);
  2791. if (atomic_read(&cp->iscsi_conn) != 0)
  2792. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  2793. atomic_read(&cp->iscsi_conn));
  2794. }
  2795. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2796. {
  2797. struct cnic_local *cp = dev->cnic_priv;
  2798. u32 pfid = cp->pfid;
  2799. u32 port = CNIC_PORT(cp);
  2800. cnic_init_bnx2x_mac(dev);
  2801. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2802. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2803. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  2804. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2805. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  2806. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2807. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  2808. DEF_MAX_DA_COUNT);
  2809. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2810. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  2811. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2812. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  2813. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2814. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  2815. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2816. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  2817. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  2818. DEF_MAX_CWND);
  2819. return 0;
  2820. }
  2821. static void cnic_delete_task(struct work_struct *work)
  2822. {
  2823. struct cnic_local *cp;
  2824. struct cnic_dev *dev;
  2825. u32 i;
  2826. int need_resched = 0;
  2827. cp = container_of(work, struct cnic_local, delete_task.work);
  2828. dev = cp->dev;
  2829. for (i = 0; i < cp->max_cid_space; i++) {
  2830. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2831. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  2832. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2833. continue;
  2834. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  2835. need_resched = 1;
  2836. continue;
  2837. }
  2838. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2839. continue;
  2840. cnic_bnx2x_destroy_ramrod(dev, i);
  2841. cnic_free_bnx2x_conn_resc(dev, i);
  2842. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  2843. atomic_dec(&cp->iscsi_conn);
  2844. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2845. }
  2846. if (need_resched)
  2847. queue_delayed_work(cnic_wq, &cp->delete_task,
  2848. msecs_to_jiffies(10));
  2849. }
  2850. static int cnic_cm_open(struct cnic_dev *dev)
  2851. {
  2852. struct cnic_local *cp = dev->cnic_priv;
  2853. int err;
  2854. err = cnic_cm_alloc_mem(dev);
  2855. if (err)
  2856. return err;
  2857. err = cp->start_cm(dev);
  2858. if (err)
  2859. goto err_out;
  2860. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  2861. dev->cm_create = cnic_cm_create;
  2862. dev->cm_destroy = cnic_cm_destroy;
  2863. dev->cm_connect = cnic_cm_connect;
  2864. dev->cm_abort = cnic_cm_abort;
  2865. dev->cm_close = cnic_cm_close;
  2866. dev->cm_select_dev = cnic_cm_select_dev;
  2867. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2868. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2869. return 0;
  2870. err_out:
  2871. cnic_cm_free_mem(dev);
  2872. return err;
  2873. }
  2874. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2875. {
  2876. struct cnic_local *cp = dev->cnic_priv;
  2877. int i;
  2878. cp->stop_cm(dev);
  2879. if (!cp->csk_tbl)
  2880. return 0;
  2881. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2882. struct cnic_sock *csk = &cp->csk_tbl[i];
  2883. clear_bit(SK_F_INUSE, &csk->flags);
  2884. cnic_cm_cleanup(csk);
  2885. }
  2886. cnic_cm_free_mem(dev);
  2887. return 0;
  2888. }
  2889. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2890. {
  2891. u32 cid_addr;
  2892. int i;
  2893. cid_addr = GET_CID_ADDR(cid);
  2894. for (i = 0; i < CTX_SIZE; i += 4)
  2895. cnic_ctx_wr(dev, cid_addr, i, 0);
  2896. }
  2897. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2898. {
  2899. struct cnic_local *cp = dev->cnic_priv;
  2900. int ret = 0, i;
  2901. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2902. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2903. return 0;
  2904. for (i = 0; i < cp->ctx_blks; i++) {
  2905. int j;
  2906. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2907. u32 val;
  2908. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2909. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2910. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2911. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2912. (u64) cp->ctx_arr[i].mapping >> 32);
  2913. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2914. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2915. for (j = 0; j < 10; j++) {
  2916. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2917. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2918. break;
  2919. udelay(5);
  2920. }
  2921. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2922. ret = -EBUSY;
  2923. break;
  2924. }
  2925. }
  2926. return ret;
  2927. }
  2928. static void cnic_free_irq(struct cnic_dev *dev)
  2929. {
  2930. struct cnic_local *cp = dev->cnic_priv;
  2931. struct cnic_eth_dev *ethdev = cp->ethdev;
  2932. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2933. cp->disable_int_sync(dev);
  2934. tasklet_kill(&cp->cnic_irq_task);
  2935. free_irq(ethdev->irq_arr[0].vector, dev);
  2936. }
  2937. }
  2938. static int cnic_request_irq(struct cnic_dev *dev)
  2939. {
  2940. struct cnic_local *cp = dev->cnic_priv;
  2941. struct cnic_eth_dev *ethdev = cp->ethdev;
  2942. int err;
  2943. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  2944. if (err)
  2945. tasklet_disable(&cp->cnic_irq_task);
  2946. return err;
  2947. }
  2948. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2949. {
  2950. struct cnic_local *cp = dev->cnic_priv;
  2951. struct cnic_eth_dev *ethdev = cp->ethdev;
  2952. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2953. int err, i = 0;
  2954. int sblk_num = cp->status_blk_num;
  2955. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2956. BNX2_HC_SB_CONFIG_1;
  2957. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2958. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2959. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2960. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2961. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  2962. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2963. (unsigned long) dev);
  2964. err = cnic_request_irq(dev);
  2965. if (err)
  2966. return err;
  2967. while (cp->status_blk.bnx2->status_completion_producer_index &&
  2968. i < 10) {
  2969. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2970. 1 << (11 + sblk_num));
  2971. udelay(10);
  2972. i++;
  2973. barrier();
  2974. }
  2975. if (cp->status_blk.bnx2->status_completion_producer_index) {
  2976. cnic_free_irq(dev);
  2977. goto failed;
  2978. }
  2979. } else {
  2980. struct status_block *sblk = cp->status_blk.gen;
  2981. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2982. int i = 0;
  2983. while (sblk->status_completion_producer_index && i < 10) {
  2984. CNIC_WR(dev, BNX2_HC_COMMAND,
  2985. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2986. udelay(10);
  2987. i++;
  2988. barrier();
  2989. }
  2990. if (sblk->status_completion_producer_index)
  2991. goto failed;
  2992. }
  2993. return 0;
  2994. failed:
  2995. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  2996. return -EBUSY;
  2997. }
  2998. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2999. {
  3000. struct cnic_local *cp = dev->cnic_priv;
  3001. struct cnic_eth_dev *ethdev = cp->ethdev;
  3002. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3003. return;
  3004. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3005. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3006. }
  3007. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3008. {
  3009. struct cnic_local *cp = dev->cnic_priv;
  3010. struct cnic_eth_dev *ethdev = cp->ethdev;
  3011. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3012. return;
  3013. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3014. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3015. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3016. synchronize_irq(ethdev->irq_arr[0].vector);
  3017. }
  3018. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3019. {
  3020. struct cnic_local *cp = dev->cnic_priv;
  3021. struct cnic_eth_dev *ethdev = cp->ethdev;
  3022. struct cnic_uio_dev *udev = cp->udev;
  3023. u32 cid_addr, tx_cid, sb_id;
  3024. u32 val, offset0, offset1, offset2, offset3;
  3025. int i;
  3026. struct tx_bd *txbd;
  3027. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3028. struct status_block *s_blk = cp->status_blk.gen;
  3029. sb_id = cp->status_blk_num;
  3030. tx_cid = 20;
  3031. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3032. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3033. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3034. tx_cid = TX_TSS_CID + sb_id - 1;
  3035. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3036. (TX_TSS_CID << 7));
  3037. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3038. }
  3039. cp->tx_cons = *cp->tx_cons_ptr;
  3040. cid_addr = GET_CID_ADDR(tx_cid);
  3041. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3042. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3043. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3044. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3045. offset0 = BNX2_L2CTX_TYPE_XI;
  3046. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3047. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3048. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3049. } else {
  3050. cnic_init_context(dev, tx_cid);
  3051. cnic_init_context(dev, tx_cid + 1);
  3052. offset0 = BNX2_L2CTX_TYPE;
  3053. offset1 = BNX2_L2CTX_CMD_TYPE;
  3054. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3055. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3056. }
  3057. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3058. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3059. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3060. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3061. txbd = (struct tx_bd *) udev->l2_ring;
  3062. buf_map = udev->l2_buf_map;
  3063. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3064. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3065. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3066. }
  3067. val = (u64) ring_map >> 32;
  3068. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3069. txbd->tx_bd_haddr_hi = val;
  3070. val = (u64) ring_map & 0xffffffff;
  3071. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3072. txbd->tx_bd_haddr_lo = val;
  3073. }
  3074. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3075. {
  3076. struct cnic_local *cp = dev->cnic_priv;
  3077. struct cnic_eth_dev *ethdev = cp->ethdev;
  3078. struct cnic_uio_dev *udev = cp->udev;
  3079. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3080. int i;
  3081. struct rx_bd *rxbd;
  3082. struct status_block *s_blk = cp->status_blk.gen;
  3083. dma_addr_t ring_map = udev->l2_ring_map;
  3084. sb_id = cp->status_blk_num;
  3085. cnic_init_context(dev, 2);
  3086. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3087. coal_reg = BNX2_HC_COMMAND;
  3088. coal_val = CNIC_RD(dev, coal_reg);
  3089. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3090. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3091. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3092. coal_reg = BNX2_HC_COALESCE_NOW;
  3093. coal_val = 1 << (11 + sb_id);
  3094. }
  3095. i = 0;
  3096. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3097. CNIC_WR(dev, coal_reg, coal_val);
  3098. udelay(10);
  3099. i++;
  3100. barrier();
  3101. }
  3102. cp->rx_cons = *cp->rx_cons_ptr;
  3103. cid_addr = GET_CID_ADDR(2);
  3104. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3105. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3106. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3107. if (sb_id == 0)
  3108. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3109. else
  3110. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3111. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3112. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3113. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3114. dma_addr_t buf_map;
  3115. int n = (i % cp->l2_rx_ring_size) + 1;
  3116. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3117. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3118. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3119. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3120. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3121. }
  3122. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3123. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3124. rxbd->rx_bd_haddr_hi = val;
  3125. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3126. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3127. rxbd->rx_bd_haddr_lo = val;
  3128. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3129. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3130. }
  3131. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3132. {
  3133. struct kwqe *wqes[1], l2kwqe;
  3134. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3135. wqes[0] = &l2kwqe;
  3136. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3137. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3138. KWQE_OPCODE_SHIFT) | 2;
  3139. dev->submit_kwqes(dev, wqes, 1);
  3140. }
  3141. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3142. {
  3143. struct cnic_local *cp = dev->cnic_priv;
  3144. u32 val;
  3145. val = cp->func << 2;
  3146. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3147. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3148. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3149. dev->mac_addr[0] = (u8) (val >> 8);
  3150. dev->mac_addr[1] = (u8) val;
  3151. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3152. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3153. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3154. dev->mac_addr[2] = (u8) (val >> 24);
  3155. dev->mac_addr[3] = (u8) (val >> 16);
  3156. dev->mac_addr[4] = (u8) (val >> 8);
  3157. dev->mac_addr[5] = (u8) val;
  3158. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3159. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3160. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3161. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3162. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3163. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3164. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3165. }
  3166. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3167. {
  3168. struct cnic_local *cp = dev->cnic_priv;
  3169. struct cnic_eth_dev *ethdev = cp->ethdev;
  3170. struct status_block *sblk = cp->status_blk.gen;
  3171. u32 val, kcq_cid_addr, kwq_cid_addr;
  3172. int err;
  3173. cnic_set_bnx2_mac(dev);
  3174. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3175. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3176. if (BCM_PAGE_BITS > 12)
  3177. val |= (12 - 8) << 4;
  3178. else
  3179. val |= (BCM_PAGE_BITS - 8) << 4;
  3180. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3181. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3182. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3183. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3184. err = cnic_setup_5709_context(dev, 1);
  3185. if (err)
  3186. return err;
  3187. cnic_init_context(dev, KWQ_CID);
  3188. cnic_init_context(dev, KCQ_CID);
  3189. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3190. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3191. cp->max_kwq_idx = MAX_KWQ_IDX;
  3192. cp->kwq_prod_idx = 0;
  3193. cp->kwq_con_idx = 0;
  3194. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3195. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3196. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3197. else
  3198. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3199. /* Initialize the kernel work queue context. */
  3200. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3201. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3202. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3203. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3204. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3205. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3206. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3207. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3208. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3209. val = (u32) cp->kwq_info.pgtbl_map;
  3210. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3211. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3212. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3213. cp->kcq1.sw_prod_idx = 0;
  3214. cp->kcq1.hw_prod_idx_ptr =
  3215. (u16 *) &sblk->status_completion_producer_index;
  3216. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3217. /* Initialize the kernel complete queue context. */
  3218. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3219. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3220. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3221. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3222. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3223. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3224. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3225. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3226. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3227. val = (u32) cp->kcq1.dma.pgtbl_map;
  3228. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3229. cp->int_num = 0;
  3230. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3231. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3232. u32 sb_id = cp->status_blk_num;
  3233. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3234. cp->kcq1.hw_prod_idx_ptr =
  3235. (u16 *) &msblk->status_completion_producer_index;
  3236. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3237. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3238. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3239. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3240. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3241. }
  3242. /* Enable Commnad Scheduler notification when we write to the
  3243. * host producer index of the kernel contexts. */
  3244. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3245. /* Enable Command Scheduler notification when we write to either
  3246. * the Send Queue or Receive Queue producer indexes of the kernel
  3247. * bypass contexts. */
  3248. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3249. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3250. /* Notify COM when the driver post an application buffer. */
  3251. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3252. /* Set the CP and COM doorbells. These two processors polls the
  3253. * doorbell for a non zero value before running. This must be done
  3254. * after setting up the kernel queue contexts. */
  3255. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3256. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3257. cnic_init_bnx2_tx_ring(dev);
  3258. cnic_init_bnx2_rx_ring(dev);
  3259. err = cnic_init_bnx2_irq(dev);
  3260. if (err) {
  3261. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3262. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3263. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3264. return err;
  3265. }
  3266. return 0;
  3267. }
  3268. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3269. {
  3270. struct cnic_local *cp = dev->cnic_priv;
  3271. struct cnic_eth_dev *ethdev = cp->ethdev;
  3272. u32 start_offset = ethdev->ctx_tbl_offset;
  3273. int i;
  3274. for (i = 0; i < cp->ctx_blks; i++) {
  3275. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3276. dma_addr_t map = ctx->mapping;
  3277. if (cp->ctx_align) {
  3278. unsigned long mask = cp->ctx_align - 1;
  3279. map = (map + mask) & ~mask;
  3280. }
  3281. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3282. }
  3283. }
  3284. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3285. {
  3286. struct cnic_local *cp = dev->cnic_priv;
  3287. struct cnic_eth_dev *ethdev = cp->ethdev;
  3288. int err = 0;
  3289. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3290. (unsigned long) dev);
  3291. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3292. err = cnic_request_irq(dev);
  3293. return err;
  3294. }
  3295. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3296. u16 sb_id, u8 sb_index,
  3297. u8 disable)
  3298. {
  3299. u32 addr = BAR_CSTRORM_INTMEM +
  3300. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3301. offsetof(struct hc_status_block_data_e1x, index_data) +
  3302. sizeof(struct hc_index_data)*sb_index +
  3303. offsetof(struct hc_index_data, flags);
  3304. u16 flags = CNIC_RD16(dev, addr);
  3305. /* clear and set */
  3306. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3307. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3308. HC_INDEX_DATA_HC_ENABLED);
  3309. CNIC_WR16(dev, addr, flags);
  3310. }
  3311. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3312. {
  3313. struct cnic_local *cp = dev->cnic_priv;
  3314. u8 sb_id = cp->status_blk_num;
  3315. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3316. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3317. offsetof(struct hc_status_block_data_e1x, index_data) +
  3318. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3319. offsetof(struct hc_index_data, timeout), 64 / 12);
  3320. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3321. }
  3322. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3323. {
  3324. }
  3325. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3326. struct client_init_ramrod_data *data)
  3327. {
  3328. struct cnic_local *cp = dev->cnic_priv;
  3329. struct cnic_uio_dev *udev = cp->udev;
  3330. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3331. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3332. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3333. int port = CNIC_PORT(cp);
  3334. int i;
  3335. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3336. u32 val;
  3337. memset(txbd, 0, BCM_PAGE_SIZE);
  3338. buf_map = udev->l2_buf_map;
  3339. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3340. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3341. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3342. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3343. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3344. reg_bd->addr_hi = start_bd->addr_hi;
  3345. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3346. start_bd->nbytes = cpu_to_le16(0x10);
  3347. start_bd->nbd = cpu_to_le16(3);
  3348. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3349. start_bd->general_data = (UNICAST_ADDRESS <<
  3350. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3351. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3352. }
  3353. val = (u64) ring_map >> 32;
  3354. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3355. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3356. val = (u64) ring_map & 0xffffffff;
  3357. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3358. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3359. /* Other ramrod params */
  3360. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3361. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3362. /* reset xstorm per client statistics */
  3363. if (cli < MAX_STAT_COUNTER_ID) {
  3364. val = BAR_XSTRORM_INTMEM +
  3365. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3366. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3367. CNIC_WR(dev, val + i * 4, 0);
  3368. }
  3369. cp->tx_cons_ptr =
  3370. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3371. }
  3372. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3373. struct client_init_ramrod_data *data)
  3374. {
  3375. struct cnic_local *cp = dev->cnic_priv;
  3376. struct cnic_uio_dev *udev = cp->udev;
  3377. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3378. BCM_PAGE_SIZE);
  3379. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3380. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3381. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3382. int i;
  3383. int port = CNIC_PORT(cp);
  3384. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3385. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3386. u32 val;
  3387. dma_addr_t ring_map = udev->l2_ring_map;
  3388. /* General data */
  3389. data->general.client_id = cli;
  3390. data->general.statistics_en_flg = 1;
  3391. data->general.statistics_counter_id = cli;
  3392. data->general.activate_flg = 1;
  3393. data->general.sp_client_id = cli;
  3394. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3395. dma_addr_t buf_map;
  3396. int n = (i % cp->l2_rx_ring_size) + 1;
  3397. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3398. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3399. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3400. }
  3401. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3402. rxbd->addr_hi = cpu_to_le32(val);
  3403. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3404. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3405. rxbd->addr_lo = cpu_to_le32(val);
  3406. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3407. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3408. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3409. rxcqe->addr_hi = cpu_to_le32(val);
  3410. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3411. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3412. rxcqe->addr_lo = cpu_to_le32(val);
  3413. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3414. /* Other ramrod params */
  3415. data->rx.client_qzone_id = cl_qzone_id;
  3416. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3417. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3418. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3419. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3420. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3421. data->rx.outer_vlan_removal_enable_flg = 1;
  3422. /* reset tstorm and ustorm per client statistics */
  3423. if (cli < MAX_STAT_COUNTER_ID) {
  3424. val = BAR_TSTRORM_INTMEM +
  3425. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3426. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3427. CNIC_WR(dev, val + i * 4, 0);
  3428. val = BAR_USTRORM_INTMEM +
  3429. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3430. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3431. CNIC_WR(dev, val + i * 4, 0);
  3432. }
  3433. cp->rx_cons_ptr =
  3434. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3435. }
  3436. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3437. {
  3438. struct cnic_local *cp = dev->cnic_priv;
  3439. u32 base, addr, val;
  3440. int port = CNIC_PORT(cp);
  3441. dev->max_iscsi_conn = 0;
  3442. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3443. if (base == 0)
  3444. return;
  3445. addr = BNX2X_SHMEM_ADDR(base,
  3446. dev_info.port_hw_config[port].iscsi_mac_upper);
  3447. val = CNIC_RD(dev, addr);
  3448. dev->mac_addr[0] = (u8) (val >> 8);
  3449. dev->mac_addr[1] = (u8) val;
  3450. addr = BNX2X_SHMEM_ADDR(base,
  3451. dev_info.port_hw_config[port].iscsi_mac_lower);
  3452. val = CNIC_RD(dev, addr);
  3453. dev->mac_addr[2] = (u8) (val >> 24);
  3454. dev->mac_addr[3] = (u8) (val >> 16);
  3455. dev->mac_addr[4] = (u8) (val >> 8);
  3456. dev->mac_addr[5] = (u8) val;
  3457. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3458. val = CNIC_RD(dev, addr);
  3459. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3460. u16 val16;
  3461. addr = BNX2X_SHMEM_ADDR(base,
  3462. drv_lic_key[port].max_iscsi_init_conn);
  3463. val16 = CNIC_RD16(dev, addr);
  3464. if (val16)
  3465. val16 ^= 0x1e1e;
  3466. dev->max_iscsi_conn = val16;
  3467. }
  3468. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3469. int func = CNIC_FUNC(cp);
  3470. u32 mf_cfg_addr;
  3471. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3472. addr = mf_cfg_addr +
  3473. offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
  3474. val = CNIC_RD(dev, addr);
  3475. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3476. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3477. addr = mf_cfg_addr +
  3478. offsetof(struct mf_cfg,
  3479. func_mf_config[func].config);
  3480. val = CNIC_RD(dev, addr);
  3481. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3482. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3483. dev->max_iscsi_conn = 0;
  3484. }
  3485. }
  3486. }
  3487. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3488. {
  3489. struct cnic_local *cp = dev->cnic_priv;
  3490. struct cnic_eth_dev *ethdev = cp->ethdev;
  3491. int func = CNIC_FUNC(cp), ret, i;
  3492. u32 pfid;
  3493. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3494. cp->pfid = func;
  3495. pfid = cp->pfid;
  3496. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3497. cp->iscsi_start_cid);
  3498. if (ret)
  3499. return -ENOMEM;
  3500. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3501. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3502. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3503. cp->kcq1.sw_prod_idx = 0;
  3504. cp->kcq1.hw_prod_idx_ptr =
  3505. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3506. cp->kcq1.status_idx_ptr =
  3507. &sb->sb.running_index[SM_RX_ID];
  3508. cnic_get_bnx2x_iscsi_info(dev);
  3509. /* Only 1 EQ */
  3510. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3511. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3512. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3513. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3514. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3515. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3516. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3517. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3518. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3519. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3520. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3521. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3522. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3523. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  3524. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3525. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3526. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  3527. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3528. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  3529. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3530. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  3531. HC_INDEX_ISCSI_EQ_CONS);
  3532. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3533. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3534. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  3535. cp->conn_buf_info.pgtbl[2 * i]);
  3536. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3537. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  3538. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3539. }
  3540. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3541. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  3542. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3543. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3544. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  3545. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3546. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3547. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  3548. cnic_setup_bnx2x_context(dev);
  3549. ret = cnic_init_bnx2x_irq(dev);
  3550. if (ret)
  3551. return ret;
  3552. return 0;
  3553. }
  3554. static void cnic_init_rings(struct cnic_dev *dev)
  3555. {
  3556. struct cnic_local *cp = dev->cnic_priv;
  3557. struct cnic_uio_dev *udev = cp->udev;
  3558. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3559. return;
  3560. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3561. cnic_init_bnx2_tx_ring(dev);
  3562. cnic_init_bnx2_rx_ring(dev);
  3563. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3564. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3565. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3566. u32 cl_qzone_id, type;
  3567. struct client_init_ramrod_data *data;
  3568. union l5cm_specific_data l5_data;
  3569. struct ustorm_eth_rx_producers rx_prods = {0};
  3570. u32 off, i;
  3571. rx_prods.bd_prod = 0;
  3572. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3573. barrier();
  3574. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3575. off = BAR_USTRORM_INTMEM +
  3576. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli);
  3577. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3578. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3579. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3580. data = udev->l2_buf;
  3581. memset(data, 0, sizeof(*data));
  3582. cnic_init_bnx2x_tx_ring(dev, data);
  3583. cnic_init_bnx2x_rx_ring(dev, data);
  3584. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  3585. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  3586. type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3587. & SPE_HDR_CONN_TYPE;
  3588. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3589. SPE_HDR_FUNCTION_ID);
  3590. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3591. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3592. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3593. i = 0;
  3594. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3595. ++i < 10)
  3596. msleep(1);
  3597. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3598. netdev_err(dev->netdev,
  3599. "iSCSI CLIENT_SETUP did not complete\n");
  3600. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3601. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3602. }
  3603. }
  3604. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3605. {
  3606. struct cnic_local *cp = dev->cnic_priv;
  3607. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3608. return;
  3609. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3610. cnic_shutdown_bnx2_rx_ring(dev);
  3611. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3612. struct cnic_local *cp = dev->cnic_priv;
  3613. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3614. union l5cm_specific_data l5_data;
  3615. int i;
  3616. u32 type;
  3617. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3618. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3619. l5_data.phy_address.lo = cli;
  3620. l5_data.phy_address.hi = 0;
  3621. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3622. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3623. i = 0;
  3624. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3625. ++i < 10)
  3626. msleep(1);
  3627. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3628. netdev_err(dev->netdev,
  3629. "iSCSI CLIENT_HALT did not complete\n");
  3630. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3631. memset(&l5_data, 0, sizeof(l5_data));
  3632. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3633. & SPE_HDR_CONN_TYPE;
  3634. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3635. SPE_HDR_FUNCTION_ID);
  3636. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  3637. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3638. msleep(10);
  3639. }
  3640. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3641. }
  3642. static int cnic_register_netdev(struct cnic_dev *dev)
  3643. {
  3644. struct cnic_local *cp = dev->cnic_priv;
  3645. struct cnic_eth_dev *ethdev = cp->ethdev;
  3646. int err;
  3647. if (!ethdev)
  3648. return -ENODEV;
  3649. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3650. return 0;
  3651. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3652. if (err)
  3653. netdev_err(dev->netdev, "register_cnic failed\n");
  3654. return err;
  3655. }
  3656. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3657. {
  3658. struct cnic_local *cp = dev->cnic_priv;
  3659. struct cnic_eth_dev *ethdev = cp->ethdev;
  3660. if (!ethdev)
  3661. return;
  3662. ethdev->drv_unregister_cnic(dev->netdev);
  3663. }
  3664. static int cnic_start_hw(struct cnic_dev *dev)
  3665. {
  3666. struct cnic_local *cp = dev->cnic_priv;
  3667. struct cnic_eth_dev *ethdev = cp->ethdev;
  3668. int err;
  3669. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3670. return -EALREADY;
  3671. dev->regview = ethdev->io_base;
  3672. cp->chip_id = ethdev->chip_id;
  3673. pci_dev_get(dev->pcidev);
  3674. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3675. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3676. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3677. err = cp->alloc_resc(dev);
  3678. if (err) {
  3679. netdev_err(dev->netdev, "allocate resource failure\n");
  3680. goto err1;
  3681. }
  3682. err = cp->start_hw(dev);
  3683. if (err)
  3684. goto err1;
  3685. err = cnic_cm_open(dev);
  3686. if (err)
  3687. goto err1;
  3688. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3689. cp->enable_int(dev);
  3690. return 0;
  3691. err1:
  3692. cp->free_resc(dev);
  3693. pci_dev_put(dev->pcidev);
  3694. return err;
  3695. }
  3696. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3697. {
  3698. cnic_disable_bnx2_int_sync(dev);
  3699. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3700. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3701. cnic_init_context(dev, KWQ_CID);
  3702. cnic_init_context(dev, KCQ_CID);
  3703. cnic_setup_5709_context(dev, 0);
  3704. cnic_free_irq(dev);
  3705. cnic_free_resc(dev);
  3706. }
  3707. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3708. {
  3709. struct cnic_local *cp = dev->cnic_priv;
  3710. cnic_free_irq(dev);
  3711. *cp->kcq1.hw_prod_idx_ptr = 0;
  3712. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3713. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  3714. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  3715. cnic_free_resc(dev);
  3716. }
  3717. static void cnic_stop_hw(struct cnic_dev *dev)
  3718. {
  3719. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3720. struct cnic_local *cp = dev->cnic_priv;
  3721. int i = 0;
  3722. /* Need to wait for the ring shutdown event to complete
  3723. * before clearing the CNIC_UP flag.
  3724. */
  3725. while (cp->udev->uio_dev != -1 && i < 15) {
  3726. msleep(100);
  3727. i++;
  3728. }
  3729. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3730. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3731. synchronize_rcu();
  3732. cnic_cm_shutdown(dev);
  3733. cp->stop_hw(dev);
  3734. pci_dev_put(dev->pcidev);
  3735. }
  3736. }
  3737. static void cnic_free_dev(struct cnic_dev *dev)
  3738. {
  3739. int i = 0;
  3740. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3741. msleep(100);
  3742. i++;
  3743. }
  3744. if (atomic_read(&dev->ref_count) != 0)
  3745. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3746. netdev_info(dev->netdev, "Removed CNIC device\n");
  3747. dev_put(dev->netdev);
  3748. kfree(dev);
  3749. }
  3750. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3751. struct pci_dev *pdev)
  3752. {
  3753. struct cnic_dev *cdev;
  3754. struct cnic_local *cp;
  3755. int alloc_size;
  3756. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3757. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3758. if (cdev == NULL) {
  3759. netdev_err(dev, "allocate dev struct failure\n");
  3760. return NULL;
  3761. }
  3762. cdev->netdev = dev;
  3763. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3764. cdev->register_device = cnic_register_device;
  3765. cdev->unregister_device = cnic_unregister_device;
  3766. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3767. cp = cdev->cnic_priv;
  3768. cp->dev = cdev;
  3769. cp->l2_single_buf_size = 0x400;
  3770. cp->l2_rx_ring_size = 3;
  3771. spin_lock_init(&cp->cnic_ulp_lock);
  3772. netdev_info(dev, "Added CNIC device\n");
  3773. return cdev;
  3774. }
  3775. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3776. {
  3777. struct pci_dev *pdev;
  3778. struct cnic_dev *cdev;
  3779. struct cnic_local *cp;
  3780. struct cnic_eth_dev *ethdev = NULL;
  3781. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3782. probe = symbol_get(bnx2_cnic_probe);
  3783. if (probe) {
  3784. ethdev = (*probe)(dev);
  3785. symbol_put(bnx2_cnic_probe);
  3786. }
  3787. if (!ethdev)
  3788. return NULL;
  3789. pdev = ethdev->pdev;
  3790. if (!pdev)
  3791. return NULL;
  3792. dev_hold(dev);
  3793. pci_dev_get(pdev);
  3794. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3795. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3796. u8 rev;
  3797. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3798. if (rev < 0x10) {
  3799. pci_dev_put(pdev);
  3800. goto cnic_err;
  3801. }
  3802. }
  3803. pci_dev_put(pdev);
  3804. cdev = cnic_alloc_dev(dev, pdev);
  3805. if (cdev == NULL)
  3806. goto cnic_err;
  3807. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3808. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3809. cp = cdev->cnic_priv;
  3810. cp->ethdev = ethdev;
  3811. cdev->pcidev = pdev;
  3812. cp->cnic_ops = &cnic_bnx2_ops;
  3813. cp->start_hw = cnic_start_bnx2_hw;
  3814. cp->stop_hw = cnic_stop_bnx2_hw;
  3815. cp->setup_pgtbl = cnic_setup_page_tbl;
  3816. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3817. cp->free_resc = cnic_free_resc;
  3818. cp->start_cm = cnic_cm_init_bnx2_hw;
  3819. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3820. cp->enable_int = cnic_enable_bnx2_int;
  3821. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3822. cp->close_conn = cnic_close_bnx2_conn;
  3823. cp->next_idx = cnic_bnx2_next_idx;
  3824. cp->hw_idx = cnic_bnx2_hw_idx;
  3825. return cdev;
  3826. cnic_err:
  3827. dev_put(dev);
  3828. return NULL;
  3829. }
  3830. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3831. {
  3832. struct pci_dev *pdev;
  3833. struct cnic_dev *cdev;
  3834. struct cnic_local *cp;
  3835. struct cnic_eth_dev *ethdev = NULL;
  3836. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3837. probe = symbol_get(bnx2x_cnic_probe);
  3838. if (probe) {
  3839. ethdev = (*probe)(dev);
  3840. symbol_put(bnx2x_cnic_probe);
  3841. }
  3842. if (!ethdev)
  3843. return NULL;
  3844. pdev = ethdev->pdev;
  3845. if (!pdev)
  3846. return NULL;
  3847. dev_hold(dev);
  3848. cdev = cnic_alloc_dev(dev, pdev);
  3849. if (cdev == NULL) {
  3850. dev_put(dev);
  3851. return NULL;
  3852. }
  3853. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3854. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3855. cp = cdev->cnic_priv;
  3856. cp->ethdev = ethdev;
  3857. cdev->pcidev = pdev;
  3858. cp->cnic_ops = &cnic_bnx2x_ops;
  3859. cp->start_hw = cnic_start_bnx2x_hw;
  3860. cp->stop_hw = cnic_stop_bnx2x_hw;
  3861. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3862. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3863. cp->free_resc = cnic_free_resc;
  3864. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3865. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3866. cp->enable_int = cnic_enable_bnx2x_int;
  3867. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3868. cp->ack_int = cnic_ack_bnx2x_msix;
  3869. cp->close_conn = cnic_close_bnx2x_conn;
  3870. cp->next_idx = cnic_bnx2x_next_idx;
  3871. cp->hw_idx = cnic_bnx2x_hw_idx;
  3872. return cdev;
  3873. }
  3874. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3875. {
  3876. struct ethtool_drvinfo drvinfo;
  3877. struct cnic_dev *cdev = NULL;
  3878. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3879. memset(&drvinfo, 0, sizeof(drvinfo));
  3880. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3881. if (!strcmp(drvinfo.driver, "bnx2"))
  3882. cdev = init_bnx2_cnic(dev);
  3883. if (!strcmp(drvinfo.driver, "bnx2x"))
  3884. cdev = init_bnx2x_cnic(dev);
  3885. if (cdev) {
  3886. write_lock(&cnic_dev_lock);
  3887. list_add(&cdev->list, &cnic_dev_list);
  3888. write_unlock(&cnic_dev_lock);
  3889. }
  3890. }
  3891. return cdev;
  3892. }
  3893. /**
  3894. * netdev event handler
  3895. */
  3896. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3897. void *ptr)
  3898. {
  3899. struct net_device *netdev = ptr;
  3900. struct cnic_dev *dev;
  3901. int if_type;
  3902. int new_dev = 0;
  3903. dev = cnic_from_netdev(netdev);
  3904. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3905. /* Check for the hot-plug device */
  3906. dev = is_cnic_dev(netdev);
  3907. if (dev) {
  3908. new_dev = 1;
  3909. cnic_hold(dev);
  3910. }
  3911. }
  3912. if (dev) {
  3913. struct cnic_local *cp = dev->cnic_priv;
  3914. if (new_dev)
  3915. cnic_ulp_init(dev);
  3916. else if (event == NETDEV_UNREGISTER)
  3917. cnic_ulp_exit(dev);
  3918. if (event == NETDEV_UP) {
  3919. if (cnic_register_netdev(dev) != 0) {
  3920. cnic_put(dev);
  3921. goto done;
  3922. }
  3923. if (!cnic_start_hw(dev))
  3924. cnic_ulp_start(dev);
  3925. }
  3926. rcu_read_lock();
  3927. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3928. struct cnic_ulp_ops *ulp_ops;
  3929. void *ctx;
  3930. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3931. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3932. continue;
  3933. ctx = cp->ulp_handle[if_type];
  3934. ulp_ops->indicate_netevent(ctx, event);
  3935. }
  3936. rcu_read_unlock();
  3937. if (event == NETDEV_GOING_DOWN) {
  3938. cnic_ulp_stop(dev);
  3939. cnic_stop_hw(dev);
  3940. cnic_unregister_netdev(dev);
  3941. } else if (event == NETDEV_UNREGISTER) {
  3942. write_lock(&cnic_dev_lock);
  3943. list_del_init(&dev->list);
  3944. write_unlock(&cnic_dev_lock);
  3945. cnic_put(dev);
  3946. cnic_free_dev(dev);
  3947. goto done;
  3948. }
  3949. cnic_put(dev);
  3950. }
  3951. done:
  3952. return NOTIFY_DONE;
  3953. }
  3954. static struct notifier_block cnic_netdev_notifier = {
  3955. .notifier_call = cnic_netdev_event
  3956. };
  3957. static void cnic_release(void)
  3958. {
  3959. struct cnic_dev *dev;
  3960. while (!list_empty(&cnic_dev_list)) {
  3961. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3962. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3963. cnic_ulp_stop(dev);
  3964. cnic_stop_hw(dev);
  3965. }
  3966. cnic_ulp_exit(dev);
  3967. cnic_unregister_netdev(dev);
  3968. list_del_init(&dev->list);
  3969. cnic_free_dev(dev);
  3970. }
  3971. }
  3972. static int __init cnic_init(void)
  3973. {
  3974. int rc = 0;
  3975. pr_info("%s", version);
  3976. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3977. if (rc) {
  3978. cnic_release();
  3979. return rc;
  3980. }
  3981. cnic_wq = create_singlethread_workqueue("cnic_wq");
  3982. if (!cnic_wq) {
  3983. cnic_release();
  3984. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3985. return -ENOMEM;
  3986. }
  3987. return 0;
  3988. }
  3989. static void __exit cnic_exit(void)
  3990. {
  3991. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3992. cnic_release();
  3993. destroy_workqueue(cnic_wq);
  3994. }
  3995. module_init(cnic_init);
  3996. module_exit(cnic_exit);