cputable.c 66 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/export.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. #include <asm/setup.h>
  22. struct cpu_spec* cur_cpu_spec = NULL;
  23. EXPORT_SYMBOL(cur_cpu_spec);
  24. /* The platform string corresponding to the real PVR */
  25. const char *powerpc_base_platform;
  26. /* NOTE:
  27. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  28. * the responsibility of the appropriate CPU save/restore functions to
  29. * eventually copy these settings over. Those save/restore aren't yet
  30. * part of the cputable though. That has to be fixed for both ppc32
  31. * and ppc64
  32. */
  33. #ifdef CONFIG_PPC32
  34. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  46. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  48. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  55. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  56. #endif /* CONFIG_PPC32 */
  57. #ifdef CONFIG_PPC64
  58. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  60. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  61. extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec);
  62. extern void __restore_cpu_pa6t(void);
  63. extern void __restore_cpu_ppc970(void);
  64. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  65. extern void __restore_cpu_power7(void);
  66. extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_power8(void);
  68. extern void __restore_cpu_a2(void);
  69. #endif /* CONFIG_PPC64 */
  70. #if defined(CONFIG_E500)
  71. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  72. extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec);
  73. extern void __restore_cpu_e5500(void);
  74. extern void __restore_cpu_e6500(void);
  75. #endif /* CONFIG_E500 */
  76. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  77. * ones as well...
  78. */
  79. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  80. PPC_FEATURE_HAS_MMU)
  81. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  82. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  83. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  84. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  85. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  86. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  87. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  88. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  89. PPC_FEATURE_TRUE_LE | \
  90. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  91. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  92. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  93. PPC_FEATURE_TRUE_LE | \
  94. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  95. #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  96. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  97. PPC_FEATURE_TRUE_LE | \
  98. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  99. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  100. PPC_FEATURE_TRUE_LE | \
  101. PPC_FEATURE_HAS_ALTIVEC_COMP)
  102. #ifdef CONFIG_PPC_BOOK3E_64
  103. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  104. #else
  105. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  106. PPC_FEATURE_BOOKE)
  107. #endif
  108. static struct cpu_spec __initdata cpu_specs[] = {
  109. #ifdef CONFIG_PPC_BOOK3S_64
  110. { /* Power3 */
  111. .pvr_mask = 0xffff0000,
  112. .pvr_value = 0x00400000,
  113. .cpu_name = "POWER3 (630)",
  114. .cpu_features = CPU_FTRS_POWER3,
  115. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  116. .mmu_features = MMU_FTR_HPTE_TABLE,
  117. .icache_bsize = 128,
  118. .dcache_bsize = 128,
  119. .num_pmcs = 8,
  120. .pmc_type = PPC_PMC_IBM,
  121. .oprofile_cpu_type = "ppc64/power3",
  122. .oprofile_type = PPC_OPROFILE_RS64,
  123. .platform = "power3",
  124. },
  125. { /* Power3+ */
  126. .pvr_mask = 0xffff0000,
  127. .pvr_value = 0x00410000,
  128. .cpu_name = "POWER3 (630+)",
  129. .cpu_features = CPU_FTRS_POWER3,
  130. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  131. .mmu_features = MMU_FTR_HPTE_TABLE,
  132. .icache_bsize = 128,
  133. .dcache_bsize = 128,
  134. .num_pmcs = 8,
  135. .pmc_type = PPC_PMC_IBM,
  136. .oprofile_cpu_type = "ppc64/power3",
  137. .oprofile_type = PPC_OPROFILE_RS64,
  138. .platform = "power3",
  139. },
  140. { /* Northstar */
  141. .pvr_mask = 0xffff0000,
  142. .pvr_value = 0x00330000,
  143. .cpu_name = "RS64-II (northstar)",
  144. .cpu_features = CPU_FTRS_RS64,
  145. .cpu_user_features = COMMON_USER_PPC64,
  146. .mmu_features = MMU_FTR_HPTE_TABLE,
  147. .icache_bsize = 128,
  148. .dcache_bsize = 128,
  149. .num_pmcs = 8,
  150. .pmc_type = PPC_PMC_IBM,
  151. .oprofile_cpu_type = "ppc64/rs64",
  152. .oprofile_type = PPC_OPROFILE_RS64,
  153. .platform = "rs64",
  154. },
  155. { /* Pulsar */
  156. .pvr_mask = 0xffff0000,
  157. .pvr_value = 0x00340000,
  158. .cpu_name = "RS64-III (pulsar)",
  159. .cpu_features = CPU_FTRS_RS64,
  160. .cpu_user_features = COMMON_USER_PPC64,
  161. .mmu_features = MMU_FTR_HPTE_TABLE,
  162. .icache_bsize = 128,
  163. .dcache_bsize = 128,
  164. .num_pmcs = 8,
  165. .pmc_type = PPC_PMC_IBM,
  166. .oprofile_cpu_type = "ppc64/rs64",
  167. .oprofile_type = PPC_OPROFILE_RS64,
  168. .platform = "rs64",
  169. },
  170. { /* I-star */
  171. .pvr_mask = 0xffff0000,
  172. .pvr_value = 0x00360000,
  173. .cpu_name = "RS64-III (icestar)",
  174. .cpu_features = CPU_FTRS_RS64,
  175. .cpu_user_features = COMMON_USER_PPC64,
  176. .mmu_features = MMU_FTR_HPTE_TABLE,
  177. .icache_bsize = 128,
  178. .dcache_bsize = 128,
  179. .num_pmcs = 8,
  180. .pmc_type = PPC_PMC_IBM,
  181. .oprofile_cpu_type = "ppc64/rs64",
  182. .oprofile_type = PPC_OPROFILE_RS64,
  183. .platform = "rs64",
  184. },
  185. { /* S-star */
  186. .pvr_mask = 0xffff0000,
  187. .pvr_value = 0x00370000,
  188. .cpu_name = "RS64-IV (sstar)",
  189. .cpu_features = CPU_FTRS_RS64,
  190. .cpu_user_features = COMMON_USER_PPC64,
  191. .mmu_features = MMU_FTR_HPTE_TABLE,
  192. .icache_bsize = 128,
  193. .dcache_bsize = 128,
  194. .num_pmcs = 8,
  195. .pmc_type = PPC_PMC_IBM,
  196. .oprofile_cpu_type = "ppc64/rs64",
  197. .oprofile_type = PPC_OPROFILE_RS64,
  198. .platform = "rs64",
  199. },
  200. { /* Power4 */
  201. .pvr_mask = 0xffff0000,
  202. .pvr_value = 0x00350000,
  203. .cpu_name = "POWER4 (gp)",
  204. .cpu_features = CPU_FTRS_POWER4,
  205. .cpu_user_features = COMMON_USER_POWER4,
  206. .mmu_features = MMU_FTRS_POWER4,
  207. .icache_bsize = 128,
  208. .dcache_bsize = 128,
  209. .num_pmcs = 8,
  210. .pmc_type = PPC_PMC_IBM,
  211. .oprofile_cpu_type = "ppc64/power4",
  212. .oprofile_type = PPC_OPROFILE_POWER4,
  213. .platform = "power4",
  214. },
  215. { /* Power4+ */
  216. .pvr_mask = 0xffff0000,
  217. .pvr_value = 0x00380000,
  218. .cpu_name = "POWER4+ (gq)",
  219. .cpu_features = CPU_FTRS_POWER4,
  220. .cpu_user_features = COMMON_USER_POWER4,
  221. .mmu_features = MMU_FTRS_POWER4,
  222. .icache_bsize = 128,
  223. .dcache_bsize = 128,
  224. .num_pmcs = 8,
  225. .pmc_type = PPC_PMC_IBM,
  226. .oprofile_cpu_type = "ppc64/power4",
  227. .oprofile_type = PPC_OPROFILE_POWER4,
  228. .platform = "power4",
  229. },
  230. { /* PPC970 */
  231. .pvr_mask = 0xffff0000,
  232. .pvr_value = 0x00390000,
  233. .cpu_name = "PPC970",
  234. .cpu_features = CPU_FTRS_PPC970,
  235. .cpu_user_features = COMMON_USER_POWER4 |
  236. PPC_FEATURE_HAS_ALTIVEC_COMP,
  237. .mmu_features = MMU_FTRS_PPC970,
  238. .icache_bsize = 128,
  239. .dcache_bsize = 128,
  240. .num_pmcs = 8,
  241. .pmc_type = PPC_PMC_IBM,
  242. .cpu_setup = __setup_cpu_ppc970,
  243. .cpu_restore = __restore_cpu_ppc970,
  244. .oprofile_cpu_type = "ppc64/970",
  245. .oprofile_type = PPC_OPROFILE_POWER4,
  246. .platform = "ppc970",
  247. },
  248. { /* PPC970FX */
  249. .pvr_mask = 0xffff0000,
  250. .pvr_value = 0x003c0000,
  251. .cpu_name = "PPC970FX",
  252. .cpu_features = CPU_FTRS_PPC970,
  253. .cpu_user_features = COMMON_USER_POWER4 |
  254. PPC_FEATURE_HAS_ALTIVEC_COMP,
  255. .mmu_features = MMU_FTRS_PPC970,
  256. .icache_bsize = 128,
  257. .dcache_bsize = 128,
  258. .num_pmcs = 8,
  259. .pmc_type = PPC_PMC_IBM,
  260. .cpu_setup = __setup_cpu_ppc970,
  261. .cpu_restore = __restore_cpu_ppc970,
  262. .oprofile_cpu_type = "ppc64/970",
  263. .oprofile_type = PPC_OPROFILE_POWER4,
  264. .platform = "ppc970",
  265. },
  266. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  267. .pvr_mask = 0xffffffff,
  268. .pvr_value = 0x00440100,
  269. .cpu_name = "PPC970MP",
  270. .cpu_features = CPU_FTRS_PPC970,
  271. .cpu_user_features = COMMON_USER_POWER4 |
  272. PPC_FEATURE_HAS_ALTIVEC_COMP,
  273. .mmu_features = MMU_FTR_HPTE_TABLE,
  274. .icache_bsize = 128,
  275. .dcache_bsize = 128,
  276. .num_pmcs = 8,
  277. .pmc_type = PPC_PMC_IBM,
  278. .cpu_setup = __setup_cpu_ppc970,
  279. .cpu_restore = __restore_cpu_ppc970,
  280. .oprofile_cpu_type = "ppc64/970MP",
  281. .oprofile_type = PPC_OPROFILE_POWER4,
  282. .platform = "ppc970",
  283. },
  284. { /* PPC970MP */
  285. .pvr_mask = 0xffff0000,
  286. .pvr_value = 0x00440000,
  287. .cpu_name = "PPC970MP",
  288. .cpu_features = CPU_FTRS_PPC970,
  289. .cpu_user_features = COMMON_USER_POWER4 |
  290. PPC_FEATURE_HAS_ALTIVEC_COMP,
  291. .mmu_features = MMU_FTRS_PPC970,
  292. .icache_bsize = 128,
  293. .dcache_bsize = 128,
  294. .num_pmcs = 8,
  295. .pmc_type = PPC_PMC_IBM,
  296. .cpu_setup = __setup_cpu_ppc970MP,
  297. .cpu_restore = __restore_cpu_ppc970,
  298. .oprofile_cpu_type = "ppc64/970MP",
  299. .oprofile_type = PPC_OPROFILE_POWER4,
  300. .platform = "ppc970",
  301. },
  302. { /* PPC970GX */
  303. .pvr_mask = 0xffff0000,
  304. .pvr_value = 0x00450000,
  305. .cpu_name = "PPC970GX",
  306. .cpu_features = CPU_FTRS_PPC970,
  307. .cpu_user_features = COMMON_USER_POWER4 |
  308. PPC_FEATURE_HAS_ALTIVEC_COMP,
  309. .mmu_features = MMU_FTRS_PPC970,
  310. .icache_bsize = 128,
  311. .dcache_bsize = 128,
  312. .num_pmcs = 8,
  313. .pmc_type = PPC_PMC_IBM,
  314. .cpu_setup = __setup_cpu_ppc970,
  315. .oprofile_cpu_type = "ppc64/970",
  316. .oprofile_type = PPC_OPROFILE_POWER4,
  317. .platform = "ppc970",
  318. },
  319. { /* Power5 GR */
  320. .pvr_mask = 0xffff0000,
  321. .pvr_value = 0x003a0000,
  322. .cpu_name = "POWER5 (gr)",
  323. .cpu_features = CPU_FTRS_POWER5,
  324. .cpu_user_features = COMMON_USER_POWER5,
  325. .mmu_features = MMU_FTRS_POWER5,
  326. .icache_bsize = 128,
  327. .dcache_bsize = 128,
  328. .num_pmcs = 6,
  329. .pmc_type = PPC_PMC_IBM,
  330. .oprofile_cpu_type = "ppc64/power5",
  331. .oprofile_type = PPC_OPROFILE_POWER4,
  332. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  333. * and above but only works on POWER5 and above
  334. */
  335. .oprofile_mmcra_sihv = MMCRA_SIHV,
  336. .oprofile_mmcra_sipr = MMCRA_SIPR,
  337. .platform = "power5",
  338. },
  339. { /* Power5++ */
  340. .pvr_mask = 0xffffff00,
  341. .pvr_value = 0x003b0300,
  342. .cpu_name = "POWER5+ (gs)",
  343. .cpu_features = CPU_FTRS_POWER5,
  344. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  345. .mmu_features = MMU_FTRS_POWER5,
  346. .icache_bsize = 128,
  347. .dcache_bsize = 128,
  348. .num_pmcs = 6,
  349. .oprofile_cpu_type = "ppc64/power5++",
  350. .oprofile_type = PPC_OPROFILE_POWER4,
  351. .oprofile_mmcra_sihv = MMCRA_SIHV,
  352. .oprofile_mmcra_sipr = MMCRA_SIPR,
  353. .platform = "power5+",
  354. },
  355. { /* Power5 GS */
  356. .pvr_mask = 0xffff0000,
  357. .pvr_value = 0x003b0000,
  358. .cpu_name = "POWER5+ (gs)",
  359. .cpu_features = CPU_FTRS_POWER5,
  360. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  361. .mmu_features = MMU_FTRS_POWER5,
  362. .icache_bsize = 128,
  363. .dcache_bsize = 128,
  364. .num_pmcs = 6,
  365. .pmc_type = PPC_PMC_IBM,
  366. .oprofile_cpu_type = "ppc64/power5+",
  367. .oprofile_type = PPC_OPROFILE_POWER4,
  368. .oprofile_mmcra_sihv = MMCRA_SIHV,
  369. .oprofile_mmcra_sipr = MMCRA_SIPR,
  370. .platform = "power5+",
  371. },
  372. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  373. .pvr_mask = 0xffffffff,
  374. .pvr_value = 0x0f000001,
  375. .cpu_name = "POWER5+",
  376. .cpu_features = CPU_FTRS_POWER5,
  377. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  378. .mmu_features = MMU_FTRS_POWER5,
  379. .icache_bsize = 128,
  380. .dcache_bsize = 128,
  381. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  382. .oprofile_type = PPC_OPROFILE_POWER4,
  383. .platform = "power5+",
  384. },
  385. { /* Power6 */
  386. .pvr_mask = 0xffff0000,
  387. .pvr_value = 0x003e0000,
  388. .cpu_name = "POWER6 (raw)",
  389. .cpu_features = CPU_FTRS_POWER6,
  390. .cpu_user_features = COMMON_USER_POWER6 |
  391. PPC_FEATURE_POWER6_EXT,
  392. .mmu_features = MMU_FTRS_POWER6,
  393. .icache_bsize = 128,
  394. .dcache_bsize = 128,
  395. .num_pmcs = 6,
  396. .pmc_type = PPC_PMC_IBM,
  397. .oprofile_cpu_type = "ppc64/power6",
  398. .oprofile_type = PPC_OPROFILE_POWER4,
  399. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  400. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  401. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  402. POWER6_MMCRA_OTHER,
  403. .platform = "power6x",
  404. },
  405. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  406. .pvr_mask = 0xffffffff,
  407. .pvr_value = 0x0f000002,
  408. .cpu_name = "POWER6 (architected)",
  409. .cpu_features = CPU_FTRS_POWER6,
  410. .cpu_user_features = COMMON_USER_POWER6,
  411. .mmu_features = MMU_FTRS_POWER6,
  412. .icache_bsize = 128,
  413. .dcache_bsize = 128,
  414. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  415. .oprofile_type = PPC_OPROFILE_POWER4,
  416. .platform = "power6",
  417. },
  418. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  419. .pvr_mask = 0xffffffff,
  420. .pvr_value = 0x0f000003,
  421. .cpu_name = "POWER7 (architected)",
  422. .cpu_features = CPU_FTRS_POWER7,
  423. .cpu_user_features = COMMON_USER_POWER7,
  424. .mmu_features = MMU_FTRS_POWER7,
  425. .icache_bsize = 128,
  426. .dcache_bsize = 128,
  427. .oprofile_type = PPC_OPROFILE_POWER4,
  428. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  429. .cpu_setup = __setup_cpu_power7,
  430. .cpu_restore = __restore_cpu_power7,
  431. .platform = "power7",
  432. },
  433. { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
  434. .pvr_mask = 0xffffffff,
  435. .pvr_value = 0x0f000004,
  436. .cpu_name = "POWER8 (architected)",
  437. .cpu_features = CPU_FTRS_POWER8,
  438. .cpu_user_features = COMMON_USER_POWER8,
  439. .mmu_features = MMU_FTRS_POWER8,
  440. .icache_bsize = 128,
  441. .dcache_bsize = 128,
  442. .oprofile_type = PPC_OPROFILE_POWER4,
  443. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  444. .cpu_setup = __setup_cpu_power8,
  445. .cpu_restore = __restore_cpu_power8,
  446. .platform = "power8",
  447. },
  448. { /* Power7 */
  449. .pvr_mask = 0xffff0000,
  450. .pvr_value = 0x003f0000,
  451. .cpu_name = "POWER7 (raw)",
  452. .cpu_features = CPU_FTRS_POWER7,
  453. .cpu_user_features = COMMON_USER_POWER7,
  454. .mmu_features = MMU_FTRS_POWER7,
  455. .icache_bsize = 128,
  456. .dcache_bsize = 128,
  457. .num_pmcs = 6,
  458. .pmc_type = PPC_PMC_IBM,
  459. .oprofile_cpu_type = "ppc64/power7",
  460. .oprofile_type = PPC_OPROFILE_POWER4,
  461. .cpu_setup = __setup_cpu_power7,
  462. .cpu_restore = __restore_cpu_power7,
  463. .platform = "power7",
  464. },
  465. { /* Power7+ */
  466. .pvr_mask = 0xffff0000,
  467. .pvr_value = 0x004A0000,
  468. .cpu_name = "POWER7+ (raw)",
  469. .cpu_features = CPU_FTRS_POWER7,
  470. .cpu_user_features = COMMON_USER_POWER7,
  471. .mmu_features = MMU_FTRS_POWER7,
  472. .icache_bsize = 128,
  473. .dcache_bsize = 128,
  474. .num_pmcs = 6,
  475. .pmc_type = PPC_PMC_IBM,
  476. .oprofile_cpu_type = "ppc64/power7",
  477. .oprofile_type = PPC_OPROFILE_POWER4,
  478. .cpu_setup = __setup_cpu_power7,
  479. .cpu_restore = __restore_cpu_power7,
  480. .platform = "power7+",
  481. },
  482. { /* Power8 */
  483. .pvr_mask = 0xffff0000,
  484. .pvr_value = 0x004b0000,
  485. .cpu_name = "POWER8 (raw)",
  486. .cpu_features = CPU_FTRS_POWER8,
  487. .cpu_user_features = COMMON_USER_POWER8,
  488. .mmu_features = MMU_FTRS_POWER8,
  489. .icache_bsize = 128,
  490. .dcache_bsize = 128,
  491. .num_pmcs = 6,
  492. .pmc_type = PPC_PMC_IBM,
  493. .oprofile_cpu_type = "ppc64/power8",
  494. .oprofile_type = PPC_OPROFILE_POWER4,
  495. .cpu_setup = __setup_cpu_power8,
  496. .cpu_restore = __restore_cpu_power8,
  497. .platform = "power8",
  498. },
  499. { /* Cell Broadband Engine */
  500. .pvr_mask = 0xffff0000,
  501. .pvr_value = 0x00700000,
  502. .cpu_name = "Cell Broadband Engine",
  503. .cpu_features = CPU_FTRS_CELL,
  504. .cpu_user_features = COMMON_USER_PPC64 |
  505. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  506. PPC_FEATURE_SMT,
  507. .mmu_features = MMU_FTRS_CELL,
  508. .icache_bsize = 128,
  509. .dcache_bsize = 128,
  510. .num_pmcs = 4,
  511. .pmc_type = PPC_PMC_IBM,
  512. .oprofile_cpu_type = "ppc64/cell-be",
  513. .oprofile_type = PPC_OPROFILE_CELL,
  514. .platform = "ppc-cell-be",
  515. },
  516. { /* PA Semi PA6T */
  517. .pvr_mask = 0x7fff0000,
  518. .pvr_value = 0x00900000,
  519. .cpu_name = "PA6T",
  520. .cpu_features = CPU_FTRS_PA6T,
  521. .cpu_user_features = COMMON_USER_PA6T,
  522. .mmu_features = MMU_FTRS_PA6T,
  523. .icache_bsize = 64,
  524. .dcache_bsize = 64,
  525. .num_pmcs = 6,
  526. .pmc_type = PPC_PMC_PA6T,
  527. .cpu_setup = __setup_cpu_pa6t,
  528. .cpu_restore = __restore_cpu_pa6t,
  529. .oprofile_cpu_type = "ppc64/pa6t",
  530. .oprofile_type = PPC_OPROFILE_PA6T,
  531. .platform = "pa6t",
  532. },
  533. { /* default match */
  534. .pvr_mask = 0x00000000,
  535. .pvr_value = 0x00000000,
  536. .cpu_name = "POWER4 (compatible)",
  537. .cpu_features = CPU_FTRS_COMPATIBLE,
  538. .cpu_user_features = COMMON_USER_PPC64,
  539. .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
  540. .icache_bsize = 128,
  541. .dcache_bsize = 128,
  542. .num_pmcs = 6,
  543. .pmc_type = PPC_PMC_IBM,
  544. .platform = "power4",
  545. }
  546. #endif /* CONFIG_PPC_BOOK3S_64 */
  547. #ifdef CONFIG_PPC32
  548. #if CLASSIC_PPC
  549. { /* 601 */
  550. .pvr_mask = 0xffff0000,
  551. .pvr_value = 0x00010000,
  552. .cpu_name = "601",
  553. .cpu_features = CPU_FTRS_PPC601,
  554. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  555. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  556. .mmu_features = MMU_FTR_HPTE_TABLE,
  557. .icache_bsize = 32,
  558. .dcache_bsize = 32,
  559. .machine_check = machine_check_generic,
  560. .platform = "ppc601",
  561. },
  562. { /* 603 */
  563. .pvr_mask = 0xffff0000,
  564. .pvr_value = 0x00030000,
  565. .cpu_name = "603",
  566. .cpu_features = CPU_FTRS_603,
  567. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  568. .mmu_features = 0,
  569. .icache_bsize = 32,
  570. .dcache_bsize = 32,
  571. .cpu_setup = __setup_cpu_603,
  572. .machine_check = machine_check_generic,
  573. .platform = "ppc603",
  574. },
  575. { /* 603e */
  576. .pvr_mask = 0xffff0000,
  577. .pvr_value = 0x00060000,
  578. .cpu_name = "603e",
  579. .cpu_features = CPU_FTRS_603,
  580. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  581. .mmu_features = 0,
  582. .icache_bsize = 32,
  583. .dcache_bsize = 32,
  584. .cpu_setup = __setup_cpu_603,
  585. .machine_check = machine_check_generic,
  586. .platform = "ppc603",
  587. },
  588. { /* 603ev */
  589. .pvr_mask = 0xffff0000,
  590. .pvr_value = 0x00070000,
  591. .cpu_name = "603ev",
  592. .cpu_features = CPU_FTRS_603,
  593. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  594. .mmu_features = 0,
  595. .icache_bsize = 32,
  596. .dcache_bsize = 32,
  597. .cpu_setup = __setup_cpu_603,
  598. .machine_check = machine_check_generic,
  599. .platform = "ppc603",
  600. },
  601. { /* 604 */
  602. .pvr_mask = 0xffff0000,
  603. .pvr_value = 0x00040000,
  604. .cpu_name = "604",
  605. .cpu_features = CPU_FTRS_604,
  606. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  607. .mmu_features = MMU_FTR_HPTE_TABLE,
  608. .icache_bsize = 32,
  609. .dcache_bsize = 32,
  610. .num_pmcs = 2,
  611. .cpu_setup = __setup_cpu_604,
  612. .machine_check = machine_check_generic,
  613. .platform = "ppc604",
  614. },
  615. { /* 604e */
  616. .pvr_mask = 0xfffff000,
  617. .pvr_value = 0x00090000,
  618. .cpu_name = "604e",
  619. .cpu_features = CPU_FTRS_604,
  620. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  621. .mmu_features = MMU_FTR_HPTE_TABLE,
  622. .icache_bsize = 32,
  623. .dcache_bsize = 32,
  624. .num_pmcs = 4,
  625. .cpu_setup = __setup_cpu_604,
  626. .machine_check = machine_check_generic,
  627. .platform = "ppc604",
  628. },
  629. { /* 604r */
  630. .pvr_mask = 0xffff0000,
  631. .pvr_value = 0x00090000,
  632. .cpu_name = "604r",
  633. .cpu_features = CPU_FTRS_604,
  634. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  635. .mmu_features = MMU_FTR_HPTE_TABLE,
  636. .icache_bsize = 32,
  637. .dcache_bsize = 32,
  638. .num_pmcs = 4,
  639. .cpu_setup = __setup_cpu_604,
  640. .machine_check = machine_check_generic,
  641. .platform = "ppc604",
  642. },
  643. { /* 604ev */
  644. .pvr_mask = 0xffff0000,
  645. .pvr_value = 0x000a0000,
  646. .cpu_name = "604ev",
  647. .cpu_features = CPU_FTRS_604,
  648. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  649. .mmu_features = MMU_FTR_HPTE_TABLE,
  650. .icache_bsize = 32,
  651. .dcache_bsize = 32,
  652. .num_pmcs = 4,
  653. .cpu_setup = __setup_cpu_604,
  654. .machine_check = machine_check_generic,
  655. .platform = "ppc604",
  656. },
  657. { /* 740/750 (0x4202, don't support TAU ?) */
  658. .pvr_mask = 0xffffffff,
  659. .pvr_value = 0x00084202,
  660. .cpu_name = "740/750",
  661. .cpu_features = CPU_FTRS_740_NOTAU,
  662. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  663. .mmu_features = MMU_FTR_HPTE_TABLE,
  664. .icache_bsize = 32,
  665. .dcache_bsize = 32,
  666. .num_pmcs = 4,
  667. .cpu_setup = __setup_cpu_750,
  668. .machine_check = machine_check_generic,
  669. .platform = "ppc750",
  670. },
  671. { /* 750CX (80100 and 8010x?) */
  672. .pvr_mask = 0xfffffff0,
  673. .pvr_value = 0x00080100,
  674. .cpu_name = "750CX",
  675. .cpu_features = CPU_FTRS_750,
  676. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  677. .mmu_features = MMU_FTR_HPTE_TABLE,
  678. .icache_bsize = 32,
  679. .dcache_bsize = 32,
  680. .num_pmcs = 4,
  681. .cpu_setup = __setup_cpu_750cx,
  682. .machine_check = machine_check_generic,
  683. .platform = "ppc750",
  684. },
  685. { /* 750CX (82201 and 82202) */
  686. .pvr_mask = 0xfffffff0,
  687. .pvr_value = 0x00082200,
  688. .cpu_name = "750CX",
  689. .cpu_features = CPU_FTRS_750,
  690. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  691. .mmu_features = MMU_FTR_HPTE_TABLE,
  692. .icache_bsize = 32,
  693. .dcache_bsize = 32,
  694. .num_pmcs = 4,
  695. .pmc_type = PPC_PMC_IBM,
  696. .cpu_setup = __setup_cpu_750cx,
  697. .machine_check = machine_check_generic,
  698. .platform = "ppc750",
  699. },
  700. { /* 750CXe (82214) */
  701. .pvr_mask = 0xfffffff0,
  702. .pvr_value = 0x00082210,
  703. .cpu_name = "750CXe",
  704. .cpu_features = CPU_FTRS_750,
  705. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  706. .mmu_features = MMU_FTR_HPTE_TABLE,
  707. .icache_bsize = 32,
  708. .dcache_bsize = 32,
  709. .num_pmcs = 4,
  710. .pmc_type = PPC_PMC_IBM,
  711. .cpu_setup = __setup_cpu_750cx,
  712. .machine_check = machine_check_generic,
  713. .platform = "ppc750",
  714. },
  715. { /* 750CXe "Gekko" (83214) */
  716. .pvr_mask = 0xffffffff,
  717. .pvr_value = 0x00083214,
  718. .cpu_name = "750CXe",
  719. .cpu_features = CPU_FTRS_750,
  720. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  721. .mmu_features = MMU_FTR_HPTE_TABLE,
  722. .icache_bsize = 32,
  723. .dcache_bsize = 32,
  724. .num_pmcs = 4,
  725. .pmc_type = PPC_PMC_IBM,
  726. .cpu_setup = __setup_cpu_750cx,
  727. .machine_check = machine_check_generic,
  728. .platform = "ppc750",
  729. },
  730. { /* 750CL (and "Broadway") */
  731. .pvr_mask = 0xfffff0e0,
  732. .pvr_value = 0x00087000,
  733. .cpu_name = "750CL",
  734. .cpu_features = CPU_FTRS_750CL,
  735. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  736. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  737. .icache_bsize = 32,
  738. .dcache_bsize = 32,
  739. .num_pmcs = 4,
  740. .pmc_type = PPC_PMC_IBM,
  741. .cpu_setup = __setup_cpu_750,
  742. .machine_check = machine_check_generic,
  743. .platform = "ppc750",
  744. .oprofile_cpu_type = "ppc/750",
  745. .oprofile_type = PPC_OPROFILE_G4,
  746. },
  747. { /* 745/755 */
  748. .pvr_mask = 0xfffff000,
  749. .pvr_value = 0x00083000,
  750. .cpu_name = "745/755",
  751. .cpu_features = CPU_FTRS_750,
  752. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  753. .mmu_features = MMU_FTR_HPTE_TABLE,
  754. .icache_bsize = 32,
  755. .dcache_bsize = 32,
  756. .num_pmcs = 4,
  757. .pmc_type = PPC_PMC_IBM,
  758. .cpu_setup = __setup_cpu_750,
  759. .machine_check = machine_check_generic,
  760. .platform = "ppc750",
  761. },
  762. { /* 750FX rev 1.x */
  763. .pvr_mask = 0xffffff00,
  764. .pvr_value = 0x70000100,
  765. .cpu_name = "750FX",
  766. .cpu_features = CPU_FTRS_750FX1,
  767. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  768. .mmu_features = MMU_FTR_HPTE_TABLE,
  769. .icache_bsize = 32,
  770. .dcache_bsize = 32,
  771. .num_pmcs = 4,
  772. .pmc_type = PPC_PMC_IBM,
  773. .cpu_setup = __setup_cpu_750,
  774. .machine_check = machine_check_generic,
  775. .platform = "ppc750",
  776. .oprofile_cpu_type = "ppc/750",
  777. .oprofile_type = PPC_OPROFILE_G4,
  778. },
  779. { /* 750FX rev 2.0 must disable HID0[DPM] */
  780. .pvr_mask = 0xffffffff,
  781. .pvr_value = 0x70000200,
  782. .cpu_name = "750FX",
  783. .cpu_features = CPU_FTRS_750FX2,
  784. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  785. .mmu_features = MMU_FTR_HPTE_TABLE,
  786. .icache_bsize = 32,
  787. .dcache_bsize = 32,
  788. .num_pmcs = 4,
  789. .pmc_type = PPC_PMC_IBM,
  790. .cpu_setup = __setup_cpu_750,
  791. .machine_check = machine_check_generic,
  792. .platform = "ppc750",
  793. .oprofile_cpu_type = "ppc/750",
  794. .oprofile_type = PPC_OPROFILE_G4,
  795. },
  796. { /* 750FX (All revs except 2.0) */
  797. .pvr_mask = 0xffff0000,
  798. .pvr_value = 0x70000000,
  799. .cpu_name = "750FX",
  800. .cpu_features = CPU_FTRS_750FX,
  801. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  802. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  803. .icache_bsize = 32,
  804. .dcache_bsize = 32,
  805. .num_pmcs = 4,
  806. .pmc_type = PPC_PMC_IBM,
  807. .cpu_setup = __setup_cpu_750fx,
  808. .machine_check = machine_check_generic,
  809. .platform = "ppc750",
  810. .oprofile_cpu_type = "ppc/750",
  811. .oprofile_type = PPC_OPROFILE_G4,
  812. },
  813. { /* 750GX */
  814. .pvr_mask = 0xffff0000,
  815. .pvr_value = 0x70020000,
  816. .cpu_name = "750GX",
  817. .cpu_features = CPU_FTRS_750GX,
  818. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  819. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  820. .icache_bsize = 32,
  821. .dcache_bsize = 32,
  822. .num_pmcs = 4,
  823. .pmc_type = PPC_PMC_IBM,
  824. .cpu_setup = __setup_cpu_750fx,
  825. .machine_check = machine_check_generic,
  826. .platform = "ppc750",
  827. .oprofile_cpu_type = "ppc/750",
  828. .oprofile_type = PPC_OPROFILE_G4,
  829. },
  830. { /* 740/750 (L2CR bit need fixup for 740) */
  831. .pvr_mask = 0xffff0000,
  832. .pvr_value = 0x00080000,
  833. .cpu_name = "740/750",
  834. .cpu_features = CPU_FTRS_740,
  835. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  836. .mmu_features = MMU_FTR_HPTE_TABLE,
  837. .icache_bsize = 32,
  838. .dcache_bsize = 32,
  839. .num_pmcs = 4,
  840. .pmc_type = PPC_PMC_IBM,
  841. .cpu_setup = __setup_cpu_750,
  842. .machine_check = machine_check_generic,
  843. .platform = "ppc750",
  844. },
  845. { /* 7400 rev 1.1 ? (no TAU) */
  846. .pvr_mask = 0xffffffff,
  847. .pvr_value = 0x000c1101,
  848. .cpu_name = "7400 (1.1)",
  849. .cpu_features = CPU_FTRS_7400_NOTAU,
  850. .cpu_user_features = COMMON_USER |
  851. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  852. .mmu_features = MMU_FTR_HPTE_TABLE,
  853. .icache_bsize = 32,
  854. .dcache_bsize = 32,
  855. .num_pmcs = 4,
  856. .pmc_type = PPC_PMC_G4,
  857. .cpu_setup = __setup_cpu_7400,
  858. .machine_check = machine_check_generic,
  859. .platform = "ppc7400",
  860. },
  861. { /* 7400 */
  862. .pvr_mask = 0xffff0000,
  863. .pvr_value = 0x000c0000,
  864. .cpu_name = "7400",
  865. .cpu_features = CPU_FTRS_7400,
  866. .cpu_user_features = COMMON_USER |
  867. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  868. .mmu_features = MMU_FTR_HPTE_TABLE,
  869. .icache_bsize = 32,
  870. .dcache_bsize = 32,
  871. .num_pmcs = 4,
  872. .pmc_type = PPC_PMC_G4,
  873. .cpu_setup = __setup_cpu_7400,
  874. .machine_check = machine_check_generic,
  875. .platform = "ppc7400",
  876. },
  877. { /* 7410 */
  878. .pvr_mask = 0xffff0000,
  879. .pvr_value = 0x800c0000,
  880. .cpu_name = "7410",
  881. .cpu_features = CPU_FTRS_7400,
  882. .cpu_user_features = COMMON_USER |
  883. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  884. .mmu_features = MMU_FTR_HPTE_TABLE,
  885. .icache_bsize = 32,
  886. .dcache_bsize = 32,
  887. .num_pmcs = 4,
  888. .pmc_type = PPC_PMC_G4,
  889. .cpu_setup = __setup_cpu_7410,
  890. .machine_check = machine_check_generic,
  891. .platform = "ppc7400",
  892. },
  893. { /* 7450 2.0 - no doze/nap */
  894. .pvr_mask = 0xffffffff,
  895. .pvr_value = 0x80000200,
  896. .cpu_name = "7450",
  897. .cpu_features = CPU_FTRS_7450_20,
  898. .cpu_user_features = COMMON_USER |
  899. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  900. .mmu_features = MMU_FTR_HPTE_TABLE,
  901. .icache_bsize = 32,
  902. .dcache_bsize = 32,
  903. .num_pmcs = 6,
  904. .pmc_type = PPC_PMC_G4,
  905. .cpu_setup = __setup_cpu_745x,
  906. .oprofile_cpu_type = "ppc/7450",
  907. .oprofile_type = PPC_OPROFILE_G4,
  908. .machine_check = machine_check_generic,
  909. .platform = "ppc7450",
  910. },
  911. { /* 7450 2.1 */
  912. .pvr_mask = 0xffffffff,
  913. .pvr_value = 0x80000201,
  914. .cpu_name = "7450",
  915. .cpu_features = CPU_FTRS_7450_21,
  916. .cpu_user_features = COMMON_USER |
  917. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  918. .mmu_features = MMU_FTR_HPTE_TABLE,
  919. .icache_bsize = 32,
  920. .dcache_bsize = 32,
  921. .num_pmcs = 6,
  922. .pmc_type = PPC_PMC_G4,
  923. .cpu_setup = __setup_cpu_745x,
  924. .oprofile_cpu_type = "ppc/7450",
  925. .oprofile_type = PPC_OPROFILE_G4,
  926. .machine_check = machine_check_generic,
  927. .platform = "ppc7450",
  928. },
  929. { /* 7450 2.3 and newer */
  930. .pvr_mask = 0xffff0000,
  931. .pvr_value = 0x80000000,
  932. .cpu_name = "7450",
  933. .cpu_features = CPU_FTRS_7450_23,
  934. .cpu_user_features = COMMON_USER |
  935. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  936. .mmu_features = MMU_FTR_HPTE_TABLE,
  937. .icache_bsize = 32,
  938. .dcache_bsize = 32,
  939. .num_pmcs = 6,
  940. .pmc_type = PPC_PMC_G4,
  941. .cpu_setup = __setup_cpu_745x,
  942. .oprofile_cpu_type = "ppc/7450",
  943. .oprofile_type = PPC_OPROFILE_G4,
  944. .machine_check = machine_check_generic,
  945. .platform = "ppc7450",
  946. },
  947. { /* 7455 rev 1.x */
  948. .pvr_mask = 0xffffff00,
  949. .pvr_value = 0x80010100,
  950. .cpu_name = "7455",
  951. .cpu_features = CPU_FTRS_7455_1,
  952. .cpu_user_features = COMMON_USER |
  953. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  954. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  955. .icache_bsize = 32,
  956. .dcache_bsize = 32,
  957. .num_pmcs = 6,
  958. .pmc_type = PPC_PMC_G4,
  959. .cpu_setup = __setup_cpu_745x,
  960. .oprofile_cpu_type = "ppc/7450",
  961. .oprofile_type = PPC_OPROFILE_G4,
  962. .machine_check = machine_check_generic,
  963. .platform = "ppc7450",
  964. },
  965. { /* 7455 rev 2.0 */
  966. .pvr_mask = 0xffffffff,
  967. .pvr_value = 0x80010200,
  968. .cpu_name = "7455",
  969. .cpu_features = CPU_FTRS_7455_20,
  970. .cpu_user_features = COMMON_USER |
  971. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  972. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  973. .icache_bsize = 32,
  974. .dcache_bsize = 32,
  975. .num_pmcs = 6,
  976. .pmc_type = PPC_PMC_G4,
  977. .cpu_setup = __setup_cpu_745x,
  978. .oprofile_cpu_type = "ppc/7450",
  979. .oprofile_type = PPC_OPROFILE_G4,
  980. .machine_check = machine_check_generic,
  981. .platform = "ppc7450",
  982. },
  983. { /* 7455 others */
  984. .pvr_mask = 0xffff0000,
  985. .pvr_value = 0x80010000,
  986. .cpu_name = "7455",
  987. .cpu_features = CPU_FTRS_7455,
  988. .cpu_user_features = COMMON_USER |
  989. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  990. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  991. .icache_bsize = 32,
  992. .dcache_bsize = 32,
  993. .num_pmcs = 6,
  994. .pmc_type = PPC_PMC_G4,
  995. .cpu_setup = __setup_cpu_745x,
  996. .oprofile_cpu_type = "ppc/7450",
  997. .oprofile_type = PPC_OPROFILE_G4,
  998. .machine_check = machine_check_generic,
  999. .platform = "ppc7450",
  1000. },
  1001. { /* 7447/7457 Rev 1.0 */
  1002. .pvr_mask = 0xffffffff,
  1003. .pvr_value = 0x80020100,
  1004. .cpu_name = "7447/7457",
  1005. .cpu_features = CPU_FTRS_7447_10,
  1006. .cpu_user_features = COMMON_USER |
  1007. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1008. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1009. .icache_bsize = 32,
  1010. .dcache_bsize = 32,
  1011. .num_pmcs = 6,
  1012. .pmc_type = PPC_PMC_G4,
  1013. .cpu_setup = __setup_cpu_745x,
  1014. .oprofile_cpu_type = "ppc/7450",
  1015. .oprofile_type = PPC_OPROFILE_G4,
  1016. .machine_check = machine_check_generic,
  1017. .platform = "ppc7450",
  1018. },
  1019. { /* 7447/7457 Rev 1.1 */
  1020. .pvr_mask = 0xffffffff,
  1021. .pvr_value = 0x80020101,
  1022. .cpu_name = "7447/7457",
  1023. .cpu_features = CPU_FTRS_7447_10,
  1024. .cpu_user_features = COMMON_USER |
  1025. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1026. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1027. .icache_bsize = 32,
  1028. .dcache_bsize = 32,
  1029. .num_pmcs = 6,
  1030. .pmc_type = PPC_PMC_G4,
  1031. .cpu_setup = __setup_cpu_745x,
  1032. .oprofile_cpu_type = "ppc/7450",
  1033. .oprofile_type = PPC_OPROFILE_G4,
  1034. .machine_check = machine_check_generic,
  1035. .platform = "ppc7450",
  1036. },
  1037. { /* 7447/7457 Rev 1.2 and later */
  1038. .pvr_mask = 0xffff0000,
  1039. .pvr_value = 0x80020000,
  1040. .cpu_name = "7447/7457",
  1041. .cpu_features = CPU_FTRS_7447,
  1042. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1043. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1044. .icache_bsize = 32,
  1045. .dcache_bsize = 32,
  1046. .num_pmcs = 6,
  1047. .pmc_type = PPC_PMC_G4,
  1048. .cpu_setup = __setup_cpu_745x,
  1049. .oprofile_cpu_type = "ppc/7450",
  1050. .oprofile_type = PPC_OPROFILE_G4,
  1051. .machine_check = machine_check_generic,
  1052. .platform = "ppc7450",
  1053. },
  1054. { /* 7447A */
  1055. .pvr_mask = 0xffff0000,
  1056. .pvr_value = 0x80030000,
  1057. .cpu_name = "7447A",
  1058. .cpu_features = CPU_FTRS_7447A,
  1059. .cpu_user_features = COMMON_USER |
  1060. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1061. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1062. .icache_bsize = 32,
  1063. .dcache_bsize = 32,
  1064. .num_pmcs = 6,
  1065. .pmc_type = PPC_PMC_G4,
  1066. .cpu_setup = __setup_cpu_745x,
  1067. .oprofile_cpu_type = "ppc/7450",
  1068. .oprofile_type = PPC_OPROFILE_G4,
  1069. .machine_check = machine_check_generic,
  1070. .platform = "ppc7450",
  1071. },
  1072. { /* 7448 */
  1073. .pvr_mask = 0xffff0000,
  1074. .pvr_value = 0x80040000,
  1075. .cpu_name = "7448",
  1076. .cpu_features = CPU_FTRS_7448,
  1077. .cpu_user_features = COMMON_USER |
  1078. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1079. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1080. .icache_bsize = 32,
  1081. .dcache_bsize = 32,
  1082. .num_pmcs = 6,
  1083. .pmc_type = PPC_PMC_G4,
  1084. .cpu_setup = __setup_cpu_745x,
  1085. .oprofile_cpu_type = "ppc/7450",
  1086. .oprofile_type = PPC_OPROFILE_G4,
  1087. .machine_check = machine_check_generic,
  1088. .platform = "ppc7450",
  1089. },
  1090. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1091. .pvr_mask = 0x7fff0000,
  1092. .pvr_value = 0x00810000,
  1093. .cpu_name = "82xx",
  1094. .cpu_features = CPU_FTRS_82XX,
  1095. .cpu_user_features = COMMON_USER,
  1096. .mmu_features = 0,
  1097. .icache_bsize = 32,
  1098. .dcache_bsize = 32,
  1099. .cpu_setup = __setup_cpu_603,
  1100. .machine_check = machine_check_generic,
  1101. .platform = "ppc603",
  1102. },
  1103. { /* All G2_LE (603e core, plus some) have the same pvr */
  1104. .pvr_mask = 0x7fff0000,
  1105. .pvr_value = 0x00820000,
  1106. .cpu_name = "G2_LE",
  1107. .cpu_features = CPU_FTRS_G2_LE,
  1108. .cpu_user_features = COMMON_USER,
  1109. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1110. .icache_bsize = 32,
  1111. .dcache_bsize = 32,
  1112. .cpu_setup = __setup_cpu_603,
  1113. .machine_check = machine_check_generic,
  1114. .platform = "ppc603",
  1115. },
  1116. { /* e300c1 (a 603e core, plus some) on 83xx */
  1117. .pvr_mask = 0x7fff0000,
  1118. .pvr_value = 0x00830000,
  1119. .cpu_name = "e300c1",
  1120. .cpu_features = CPU_FTRS_E300,
  1121. .cpu_user_features = COMMON_USER,
  1122. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1123. .icache_bsize = 32,
  1124. .dcache_bsize = 32,
  1125. .cpu_setup = __setup_cpu_603,
  1126. .machine_check = machine_check_generic,
  1127. .platform = "ppc603",
  1128. },
  1129. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1130. .pvr_mask = 0x7fff0000,
  1131. .pvr_value = 0x00840000,
  1132. .cpu_name = "e300c2",
  1133. .cpu_features = CPU_FTRS_E300C2,
  1134. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1135. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1136. MMU_FTR_NEED_DTLB_SW_LRU,
  1137. .icache_bsize = 32,
  1138. .dcache_bsize = 32,
  1139. .cpu_setup = __setup_cpu_603,
  1140. .machine_check = machine_check_generic,
  1141. .platform = "ppc603",
  1142. },
  1143. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1144. .pvr_mask = 0x7fff0000,
  1145. .pvr_value = 0x00850000,
  1146. .cpu_name = "e300c3",
  1147. .cpu_features = CPU_FTRS_E300,
  1148. .cpu_user_features = COMMON_USER,
  1149. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1150. MMU_FTR_NEED_DTLB_SW_LRU,
  1151. .icache_bsize = 32,
  1152. .dcache_bsize = 32,
  1153. .cpu_setup = __setup_cpu_603,
  1154. .num_pmcs = 4,
  1155. .oprofile_cpu_type = "ppc/e300",
  1156. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1157. .platform = "ppc603",
  1158. },
  1159. { /* e300c4 (e300c1, plus one IU) */
  1160. .pvr_mask = 0x7fff0000,
  1161. .pvr_value = 0x00860000,
  1162. .cpu_name = "e300c4",
  1163. .cpu_features = CPU_FTRS_E300,
  1164. .cpu_user_features = COMMON_USER,
  1165. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1166. MMU_FTR_NEED_DTLB_SW_LRU,
  1167. .icache_bsize = 32,
  1168. .dcache_bsize = 32,
  1169. .cpu_setup = __setup_cpu_603,
  1170. .machine_check = machine_check_generic,
  1171. .num_pmcs = 4,
  1172. .oprofile_cpu_type = "ppc/e300",
  1173. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1174. .platform = "ppc603",
  1175. },
  1176. { /* default match, we assume split I/D cache & TB (non-601)... */
  1177. .pvr_mask = 0x00000000,
  1178. .pvr_value = 0x00000000,
  1179. .cpu_name = "(generic PPC)",
  1180. .cpu_features = CPU_FTRS_CLASSIC32,
  1181. .cpu_user_features = COMMON_USER,
  1182. .mmu_features = MMU_FTR_HPTE_TABLE,
  1183. .icache_bsize = 32,
  1184. .dcache_bsize = 32,
  1185. .machine_check = machine_check_generic,
  1186. .platform = "ppc603",
  1187. },
  1188. #endif /* CLASSIC_PPC */
  1189. #ifdef CONFIG_8xx
  1190. { /* 8xx */
  1191. .pvr_mask = 0xffff0000,
  1192. .pvr_value = 0x00500000,
  1193. .cpu_name = "8xx",
  1194. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1195. * if the 8xx code is there.... */
  1196. .cpu_features = CPU_FTRS_8XX,
  1197. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1198. .mmu_features = MMU_FTR_TYPE_8xx,
  1199. .icache_bsize = 16,
  1200. .dcache_bsize = 16,
  1201. .platform = "ppc823",
  1202. },
  1203. #endif /* CONFIG_8xx */
  1204. #ifdef CONFIG_40x
  1205. { /* 403GC */
  1206. .pvr_mask = 0xffffff00,
  1207. .pvr_value = 0x00200200,
  1208. .cpu_name = "403GC",
  1209. .cpu_features = CPU_FTRS_40X,
  1210. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1211. .mmu_features = MMU_FTR_TYPE_40x,
  1212. .icache_bsize = 16,
  1213. .dcache_bsize = 16,
  1214. .machine_check = machine_check_4xx,
  1215. .platform = "ppc403",
  1216. },
  1217. { /* 403GCX */
  1218. .pvr_mask = 0xffffff00,
  1219. .pvr_value = 0x00201400,
  1220. .cpu_name = "403GCX",
  1221. .cpu_features = CPU_FTRS_40X,
  1222. .cpu_user_features = PPC_FEATURE_32 |
  1223. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1224. .mmu_features = MMU_FTR_TYPE_40x,
  1225. .icache_bsize = 16,
  1226. .dcache_bsize = 16,
  1227. .machine_check = machine_check_4xx,
  1228. .platform = "ppc403",
  1229. },
  1230. { /* 403G ?? */
  1231. .pvr_mask = 0xffff0000,
  1232. .pvr_value = 0x00200000,
  1233. .cpu_name = "403G ??",
  1234. .cpu_features = CPU_FTRS_40X,
  1235. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1236. .mmu_features = MMU_FTR_TYPE_40x,
  1237. .icache_bsize = 16,
  1238. .dcache_bsize = 16,
  1239. .machine_check = machine_check_4xx,
  1240. .platform = "ppc403",
  1241. },
  1242. { /* 405GP */
  1243. .pvr_mask = 0xffff0000,
  1244. .pvr_value = 0x40110000,
  1245. .cpu_name = "405GP",
  1246. .cpu_features = CPU_FTRS_40X,
  1247. .cpu_user_features = PPC_FEATURE_32 |
  1248. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1249. .mmu_features = MMU_FTR_TYPE_40x,
  1250. .icache_bsize = 32,
  1251. .dcache_bsize = 32,
  1252. .machine_check = machine_check_4xx,
  1253. .platform = "ppc405",
  1254. },
  1255. { /* STB 03xxx */
  1256. .pvr_mask = 0xffff0000,
  1257. .pvr_value = 0x40130000,
  1258. .cpu_name = "STB03xxx",
  1259. .cpu_features = CPU_FTRS_40X,
  1260. .cpu_user_features = PPC_FEATURE_32 |
  1261. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1262. .mmu_features = MMU_FTR_TYPE_40x,
  1263. .icache_bsize = 32,
  1264. .dcache_bsize = 32,
  1265. .machine_check = machine_check_4xx,
  1266. .platform = "ppc405",
  1267. },
  1268. { /* STB 04xxx */
  1269. .pvr_mask = 0xffff0000,
  1270. .pvr_value = 0x41810000,
  1271. .cpu_name = "STB04xxx",
  1272. .cpu_features = CPU_FTRS_40X,
  1273. .cpu_user_features = PPC_FEATURE_32 |
  1274. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1275. .mmu_features = MMU_FTR_TYPE_40x,
  1276. .icache_bsize = 32,
  1277. .dcache_bsize = 32,
  1278. .machine_check = machine_check_4xx,
  1279. .platform = "ppc405",
  1280. },
  1281. { /* NP405L */
  1282. .pvr_mask = 0xffff0000,
  1283. .pvr_value = 0x41610000,
  1284. .cpu_name = "NP405L",
  1285. .cpu_features = CPU_FTRS_40X,
  1286. .cpu_user_features = PPC_FEATURE_32 |
  1287. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1288. .mmu_features = MMU_FTR_TYPE_40x,
  1289. .icache_bsize = 32,
  1290. .dcache_bsize = 32,
  1291. .machine_check = machine_check_4xx,
  1292. .platform = "ppc405",
  1293. },
  1294. { /* NP4GS3 */
  1295. .pvr_mask = 0xffff0000,
  1296. .pvr_value = 0x40B10000,
  1297. .cpu_name = "NP4GS3",
  1298. .cpu_features = CPU_FTRS_40X,
  1299. .cpu_user_features = PPC_FEATURE_32 |
  1300. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1301. .mmu_features = MMU_FTR_TYPE_40x,
  1302. .icache_bsize = 32,
  1303. .dcache_bsize = 32,
  1304. .machine_check = machine_check_4xx,
  1305. .platform = "ppc405",
  1306. },
  1307. { /* NP405H */
  1308. .pvr_mask = 0xffff0000,
  1309. .pvr_value = 0x41410000,
  1310. .cpu_name = "NP405H",
  1311. .cpu_features = CPU_FTRS_40X,
  1312. .cpu_user_features = PPC_FEATURE_32 |
  1313. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1314. .mmu_features = MMU_FTR_TYPE_40x,
  1315. .icache_bsize = 32,
  1316. .dcache_bsize = 32,
  1317. .machine_check = machine_check_4xx,
  1318. .platform = "ppc405",
  1319. },
  1320. { /* 405GPr */
  1321. .pvr_mask = 0xffff0000,
  1322. .pvr_value = 0x50910000,
  1323. .cpu_name = "405GPr",
  1324. .cpu_features = CPU_FTRS_40X,
  1325. .cpu_user_features = PPC_FEATURE_32 |
  1326. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1327. .mmu_features = MMU_FTR_TYPE_40x,
  1328. .icache_bsize = 32,
  1329. .dcache_bsize = 32,
  1330. .machine_check = machine_check_4xx,
  1331. .platform = "ppc405",
  1332. },
  1333. { /* STBx25xx */
  1334. .pvr_mask = 0xffff0000,
  1335. .pvr_value = 0x51510000,
  1336. .cpu_name = "STBx25xx",
  1337. .cpu_features = CPU_FTRS_40X,
  1338. .cpu_user_features = PPC_FEATURE_32 |
  1339. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1340. .mmu_features = MMU_FTR_TYPE_40x,
  1341. .icache_bsize = 32,
  1342. .dcache_bsize = 32,
  1343. .machine_check = machine_check_4xx,
  1344. .platform = "ppc405",
  1345. },
  1346. { /* 405LP */
  1347. .pvr_mask = 0xffff0000,
  1348. .pvr_value = 0x41F10000,
  1349. .cpu_name = "405LP",
  1350. .cpu_features = CPU_FTRS_40X,
  1351. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1352. .mmu_features = MMU_FTR_TYPE_40x,
  1353. .icache_bsize = 32,
  1354. .dcache_bsize = 32,
  1355. .machine_check = machine_check_4xx,
  1356. .platform = "ppc405",
  1357. },
  1358. { /* Xilinx Virtex-II Pro */
  1359. .pvr_mask = 0xfffff000,
  1360. .pvr_value = 0x20010000,
  1361. .cpu_name = "Virtex-II Pro",
  1362. .cpu_features = CPU_FTRS_40X,
  1363. .cpu_user_features = PPC_FEATURE_32 |
  1364. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1365. .mmu_features = MMU_FTR_TYPE_40x,
  1366. .icache_bsize = 32,
  1367. .dcache_bsize = 32,
  1368. .machine_check = machine_check_4xx,
  1369. .platform = "ppc405",
  1370. },
  1371. { /* Xilinx Virtex-4 FX */
  1372. .pvr_mask = 0xfffff000,
  1373. .pvr_value = 0x20011000,
  1374. .cpu_name = "Virtex-4 FX",
  1375. .cpu_features = CPU_FTRS_40X,
  1376. .cpu_user_features = PPC_FEATURE_32 |
  1377. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1378. .mmu_features = MMU_FTR_TYPE_40x,
  1379. .icache_bsize = 32,
  1380. .dcache_bsize = 32,
  1381. .machine_check = machine_check_4xx,
  1382. .platform = "ppc405",
  1383. },
  1384. { /* 405EP */
  1385. .pvr_mask = 0xffff0000,
  1386. .pvr_value = 0x51210000,
  1387. .cpu_name = "405EP",
  1388. .cpu_features = CPU_FTRS_40X,
  1389. .cpu_user_features = PPC_FEATURE_32 |
  1390. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1391. .mmu_features = MMU_FTR_TYPE_40x,
  1392. .icache_bsize = 32,
  1393. .dcache_bsize = 32,
  1394. .machine_check = machine_check_4xx,
  1395. .platform = "ppc405",
  1396. },
  1397. { /* 405EX Rev. A/B with Security */
  1398. .pvr_mask = 0xffff000f,
  1399. .pvr_value = 0x12910007,
  1400. .cpu_name = "405EX Rev. A/B",
  1401. .cpu_features = CPU_FTRS_40X,
  1402. .cpu_user_features = PPC_FEATURE_32 |
  1403. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1404. .mmu_features = MMU_FTR_TYPE_40x,
  1405. .icache_bsize = 32,
  1406. .dcache_bsize = 32,
  1407. .machine_check = machine_check_4xx,
  1408. .platform = "ppc405",
  1409. },
  1410. { /* 405EX Rev. C without Security */
  1411. .pvr_mask = 0xffff000f,
  1412. .pvr_value = 0x1291000d,
  1413. .cpu_name = "405EX Rev. C",
  1414. .cpu_features = CPU_FTRS_40X,
  1415. .cpu_user_features = PPC_FEATURE_32 |
  1416. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1417. .mmu_features = MMU_FTR_TYPE_40x,
  1418. .icache_bsize = 32,
  1419. .dcache_bsize = 32,
  1420. .machine_check = machine_check_4xx,
  1421. .platform = "ppc405",
  1422. },
  1423. { /* 405EX Rev. C with Security */
  1424. .pvr_mask = 0xffff000f,
  1425. .pvr_value = 0x1291000f,
  1426. .cpu_name = "405EX Rev. C",
  1427. .cpu_features = CPU_FTRS_40X,
  1428. .cpu_user_features = PPC_FEATURE_32 |
  1429. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1430. .mmu_features = MMU_FTR_TYPE_40x,
  1431. .icache_bsize = 32,
  1432. .dcache_bsize = 32,
  1433. .machine_check = machine_check_4xx,
  1434. .platform = "ppc405",
  1435. },
  1436. { /* 405EX Rev. D without Security */
  1437. .pvr_mask = 0xffff000f,
  1438. .pvr_value = 0x12910003,
  1439. .cpu_name = "405EX Rev. D",
  1440. .cpu_features = CPU_FTRS_40X,
  1441. .cpu_user_features = PPC_FEATURE_32 |
  1442. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1443. .mmu_features = MMU_FTR_TYPE_40x,
  1444. .icache_bsize = 32,
  1445. .dcache_bsize = 32,
  1446. .machine_check = machine_check_4xx,
  1447. .platform = "ppc405",
  1448. },
  1449. { /* 405EX Rev. D with Security */
  1450. .pvr_mask = 0xffff000f,
  1451. .pvr_value = 0x12910005,
  1452. .cpu_name = "405EX Rev. D",
  1453. .cpu_features = CPU_FTRS_40X,
  1454. .cpu_user_features = PPC_FEATURE_32 |
  1455. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1456. .mmu_features = MMU_FTR_TYPE_40x,
  1457. .icache_bsize = 32,
  1458. .dcache_bsize = 32,
  1459. .machine_check = machine_check_4xx,
  1460. .platform = "ppc405",
  1461. },
  1462. { /* 405EXr Rev. A/B without Security */
  1463. .pvr_mask = 0xffff000f,
  1464. .pvr_value = 0x12910001,
  1465. .cpu_name = "405EXr Rev. A/B",
  1466. .cpu_features = CPU_FTRS_40X,
  1467. .cpu_user_features = PPC_FEATURE_32 |
  1468. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1469. .mmu_features = MMU_FTR_TYPE_40x,
  1470. .icache_bsize = 32,
  1471. .dcache_bsize = 32,
  1472. .machine_check = machine_check_4xx,
  1473. .platform = "ppc405",
  1474. },
  1475. { /* 405EXr Rev. C without Security */
  1476. .pvr_mask = 0xffff000f,
  1477. .pvr_value = 0x12910009,
  1478. .cpu_name = "405EXr Rev. C",
  1479. .cpu_features = CPU_FTRS_40X,
  1480. .cpu_user_features = PPC_FEATURE_32 |
  1481. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1482. .mmu_features = MMU_FTR_TYPE_40x,
  1483. .icache_bsize = 32,
  1484. .dcache_bsize = 32,
  1485. .machine_check = machine_check_4xx,
  1486. .platform = "ppc405",
  1487. },
  1488. { /* 405EXr Rev. C with Security */
  1489. .pvr_mask = 0xffff000f,
  1490. .pvr_value = 0x1291000b,
  1491. .cpu_name = "405EXr Rev. C",
  1492. .cpu_features = CPU_FTRS_40X,
  1493. .cpu_user_features = PPC_FEATURE_32 |
  1494. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1495. .mmu_features = MMU_FTR_TYPE_40x,
  1496. .icache_bsize = 32,
  1497. .dcache_bsize = 32,
  1498. .machine_check = machine_check_4xx,
  1499. .platform = "ppc405",
  1500. },
  1501. { /* 405EXr Rev. D without Security */
  1502. .pvr_mask = 0xffff000f,
  1503. .pvr_value = 0x12910000,
  1504. .cpu_name = "405EXr Rev. D",
  1505. .cpu_features = CPU_FTRS_40X,
  1506. .cpu_user_features = PPC_FEATURE_32 |
  1507. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1508. .mmu_features = MMU_FTR_TYPE_40x,
  1509. .icache_bsize = 32,
  1510. .dcache_bsize = 32,
  1511. .machine_check = machine_check_4xx,
  1512. .platform = "ppc405",
  1513. },
  1514. { /* 405EXr Rev. D with Security */
  1515. .pvr_mask = 0xffff000f,
  1516. .pvr_value = 0x12910002,
  1517. .cpu_name = "405EXr Rev. D",
  1518. .cpu_features = CPU_FTRS_40X,
  1519. .cpu_user_features = PPC_FEATURE_32 |
  1520. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1521. .mmu_features = MMU_FTR_TYPE_40x,
  1522. .icache_bsize = 32,
  1523. .dcache_bsize = 32,
  1524. .machine_check = machine_check_4xx,
  1525. .platform = "ppc405",
  1526. },
  1527. {
  1528. /* 405EZ */
  1529. .pvr_mask = 0xffff0000,
  1530. .pvr_value = 0x41510000,
  1531. .cpu_name = "405EZ",
  1532. .cpu_features = CPU_FTRS_40X,
  1533. .cpu_user_features = PPC_FEATURE_32 |
  1534. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1535. .mmu_features = MMU_FTR_TYPE_40x,
  1536. .icache_bsize = 32,
  1537. .dcache_bsize = 32,
  1538. .machine_check = machine_check_4xx,
  1539. .platform = "ppc405",
  1540. },
  1541. { /* APM8018X */
  1542. .pvr_mask = 0xffff0000,
  1543. .pvr_value = 0x7ff11432,
  1544. .cpu_name = "APM8018X",
  1545. .cpu_features = CPU_FTRS_40X,
  1546. .cpu_user_features = PPC_FEATURE_32 |
  1547. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1548. .mmu_features = MMU_FTR_TYPE_40x,
  1549. .icache_bsize = 32,
  1550. .dcache_bsize = 32,
  1551. .machine_check = machine_check_4xx,
  1552. .platform = "ppc405",
  1553. },
  1554. { /* default match */
  1555. .pvr_mask = 0x00000000,
  1556. .pvr_value = 0x00000000,
  1557. .cpu_name = "(generic 40x PPC)",
  1558. .cpu_features = CPU_FTRS_40X,
  1559. .cpu_user_features = PPC_FEATURE_32 |
  1560. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1561. .mmu_features = MMU_FTR_TYPE_40x,
  1562. .icache_bsize = 32,
  1563. .dcache_bsize = 32,
  1564. .machine_check = machine_check_4xx,
  1565. .platform = "ppc405",
  1566. }
  1567. #endif /* CONFIG_40x */
  1568. #ifdef CONFIG_44x
  1569. {
  1570. .pvr_mask = 0xf0000fff,
  1571. .pvr_value = 0x40000850,
  1572. .cpu_name = "440GR Rev. A",
  1573. .cpu_features = CPU_FTRS_44X,
  1574. .cpu_user_features = COMMON_USER_BOOKE,
  1575. .mmu_features = MMU_FTR_TYPE_44x,
  1576. .icache_bsize = 32,
  1577. .dcache_bsize = 32,
  1578. .machine_check = machine_check_4xx,
  1579. .platform = "ppc440",
  1580. },
  1581. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1582. .pvr_mask = 0xf0000fff,
  1583. .pvr_value = 0x40000858,
  1584. .cpu_name = "440EP Rev. A",
  1585. .cpu_features = CPU_FTRS_44X,
  1586. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1587. .mmu_features = MMU_FTR_TYPE_44x,
  1588. .icache_bsize = 32,
  1589. .dcache_bsize = 32,
  1590. .cpu_setup = __setup_cpu_440ep,
  1591. .machine_check = machine_check_4xx,
  1592. .platform = "ppc440",
  1593. },
  1594. {
  1595. .pvr_mask = 0xf0000fff,
  1596. .pvr_value = 0x400008d3,
  1597. .cpu_name = "440GR Rev. B",
  1598. .cpu_features = CPU_FTRS_44X,
  1599. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1600. .mmu_features = MMU_FTR_TYPE_44x,
  1601. .icache_bsize = 32,
  1602. .dcache_bsize = 32,
  1603. .machine_check = machine_check_4xx,
  1604. .platform = "ppc440",
  1605. },
  1606. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1607. .pvr_mask = 0xf0000ff7,
  1608. .pvr_value = 0x400008d4,
  1609. .cpu_name = "440EP Rev. C",
  1610. .cpu_features = CPU_FTRS_44X,
  1611. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1612. .mmu_features = MMU_FTR_TYPE_44x,
  1613. .icache_bsize = 32,
  1614. .dcache_bsize = 32,
  1615. .cpu_setup = __setup_cpu_440ep,
  1616. .machine_check = machine_check_4xx,
  1617. .platform = "ppc440",
  1618. },
  1619. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1620. .pvr_mask = 0xf0000fff,
  1621. .pvr_value = 0x400008db,
  1622. .cpu_name = "440EP Rev. B",
  1623. .cpu_features = CPU_FTRS_44X,
  1624. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1625. .mmu_features = MMU_FTR_TYPE_44x,
  1626. .icache_bsize = 32,
  1627. .dcache_bsize = 32,
  1628. .cpu_setup = __setup_cpu_440ep,
  1629. .machine_check = machine_check_4xx,
  1630. .platform = "ppc440",
  1631. },
  1632. { /* 440GRX */
  1633. .pvr_mask = 0xf0000ffb,
  1634. .pvr_value = 0x200008D0,
  1635. .cpu_name = "440GRX",
  1636. .cpu_features = CPU_FTRS_44X,
  1637. .cpu_user_features = COMMON_USER_BOOKE,
  1638. .mmu_features = MMU_FTR_TYPE_44x,
  1639. .icache_bsize = 32,
  1640. .dcache_bsize = 32,
  1641. .cpu_setup = __setup_cpu_440grx,
  1642. .machine_check = machine_check_440A,
  1643. .platform = "ppc440",
  1644. },
  1645. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1646. .pvr_mask = 0xf0000ffb,
  1647. .pvr_value = 0x200008D8,
  1648. .cpu_name = "440EPX",
  1649. .cpu_features = CPU_FTRS_44X,
  1650. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1651. .mmu_features = MMU_FTR_TYPE_44x,
  1652. .icache_bsize = 32,
  1653. .dcache_bsize = 32,
  1654. .cpu_setup = __setup_cpu_440epx,
  1655. .machine_check = machine_check_440A,
  1656. .platform = "ppc440",
  1657. },
  1658. { /* 440GP Rev. B */
  1659. .pvr_mask = 0xf0000fff,
  1660. .pvr_value = 0x40000440,
  1661. .cpu_name = "440GP Rev. B",
  1662. .cpu_features = CPU_FTRS_44X,
  1663. .cpu_user_features = COMMON_USER_BOOKE,
  1664. .mmu_features = MMU_FTR_TYPE_44x,
  1665. .icache_bsize = 32,
  1666. .dcache_bsize = 32,
  1667. .machine_check = machine_check_4xx,
  1668. .platform = "ppc440gp",
  1669. },
  1670. { /* 440GP Rev. C */
  1671. .pvr_mask = 0xf0000fff,
  1672. .pvr_value = 0x40000481,
  1673. .cpu_name = "440GP Rev. C",
  1674. .cpu_features = CPU_FTRS_44X,
  1675. .cpu_user_features = COMMON_USER_BOOKE,
  1676. .mmu_features = MMU_FTR_TYPE_44x,
  1677. .icache_bsize = 32,
  1678. .dcache_bsize = 32,
  1679. .machine_check = machine_check_4xx,
  1680. .platform = "ppc440gp",
  1681. },
  1682. { /* 440GX Rev. A */
  1683. .pvr_mask = 0xf0000fff,
  1684. .pvr_value = 0x50000850,
  1685. .cpu_name = "440GX Rev. A",
  1686. .cpu_features = CPU_FTRS_44X,
  1687. .cpu_user_features = COMMON_USER_BOOKE,
  1688. .mmu_features = MMU_FTR_TYPE_44x,
  1689. .icache_bsize = 32,
  1690. .dcache_bsize = 32,
  1691. .cpu_setup = __setup_cpu_440gx,
  1692. .machine_check = machine_check_440A,
  1693. .platform = "ppc440",
  1694. },
  1695. { /* 440GX Rev. B */
  1696. .pvr_mask = 0xf0000fff,
  1697. .pvr_value = 0x50000851,
  1698. .cpu_name = "440GX Rev. B",
  1699. .cpu_features = CPU_FTRS_44X,
  1700. .cpu_user_features = COMMON_USER_BOOKE,
  1701. .mmu_features = MMU_FTR_TYPE_44x,
  1702. .icache_bsize = 32,
  1703. .dcache_bsize = 32,
  1704. .cpu_setup = __setup_cpu_440gx,
  1705. .machine_check = machine_check_440A,
  1706. .platform = "ppc440",
  1707. },
  1708. { /* 440GX Rev. C */
  1709. .pvr_mask = 0xf0000fff,
  1710. .pvr_value = 0x50000892,
  1711. .cpu_name = "440GX Rev. C",
  1712. .cpu_features = CPU_FTRS_44X,
  1713. .cpu_user_features = COMMON_USER_BOOKE,
  1714. .mmu_features = MMU_FTR_TYPE_44x,
  1715. .icache_bsize = 32,
  1716. .dcache_bsize = 32,
  1717. .cpu_setup = __setup_cpu_440gx,
  1718. .machine_check = machine_check_440A,
  1719. .platform = "ppc440",
  1720. },
  1721. { /* 440GX Rev. F */
  1722. .pvr_mask = 0xf0000fff,
  1723. .pvr_value = 0x50000894,
  1724. .cpu_name = "440GX Rev. F",
  1725. .cpu_features = CPU_FTRS_44X,
  1726. .cpu_user_features = COMMON_USER_BOOKE,
  1727. .mmu_features = MMU_FTR_TYPE_44x,
  1728. .icache_bsize = 32,
  1729. .dcache_bsize = 32,
  1730. .cpu_setup = __setup_cpu_440gx,
  1731. .machine_check = machine_check_440A,
  1732. .platform = "ppc440",
  1733. },
  1734. { /* 440SP Rev. A */
  1735. .pvr_mask = 0xfff00fff,
  1736. .pvr_value = 0x53200891,
  1737. .cpu_name = "440SP Rev. A",
  1738. .cpu_features = CPU_FTRS_44X,
  1739. .cpu_user_features = COMMON_USER_BOOKE,
  1740. .mmu_features = MMU_FTR_TYPE_44x,
  1741. .icache_bsize = 32,
  1742. .dcache_bsize = 32,
  1743. .machine_check = machine_check_4xx,
  1744. .platform = "ppc440",
  1745. },
  1746. { /* 440SPe Rev. A */
  1747. .pvr_mask = 0xfff00fff,
  1748. .pvr_value = 0x53400890,
  1749. .cpu_name = "440SPe Rev. A",
  1750. .cpu_features = CPU_FTRS_44X,
  1751. .cpu_user_features = COMMON_USER_BOOKE,
  1752. .mmu_features = MMU_FTR_TYPE_44x,
  1753. .icache_bsize = 32,
  1754. .dcache_bsize = 32,
  1755. .cpu_setup = __setup_cpu_440spe,
  1756. .machine_check = machine_check_440A,
  1757. .platform = "ppc440",
  1758. },
  1759. { /* 440SPe Rev. B */
  1760. .pvr_mask = 0xfff00fff,
  1761. .pvr_value = 0x53400891,
  1762. .cpu_name = "440SPe Rev. B",
  1763. .cpu_features = CPU_FTRS_44X,
  1764. .cpu_user_features = COMMON_USER_BOOKE,
  1765. .mmu_features = MMU_FTR_TYPE_44x,
  1766. .icache_bsize = 32,
  1767. .dcache_bsize = 32,
  1768. .cpu_setup = __setup_cpu_440spe,
  1769. .machine_check = machine_check_440A,
  1770. .platform = "ppc440",
  1771. },
  1772. { /* 440 in Xilinx Virtex-5 FXT */
  1773. .pvr_mask = 0xfffffff0,
  1774. .pvr_value = 0x7ff21910,
  1775. .cpu_name = "440 in Virtex-5 FXT",
  1776. .cpu_features = CPU_FTRS_44X,
  1777. .cpu_user_features = COMMON_USER_BOOKE,
  1778. .mmu_features = MMU_FTR_TYPE_44x,
  1779. .icache_bsize = 32,
  1780. .dcache_bsize = 32,
  1781. .cpu_setup = __setup_cpu_440x5,
  1782. .machine_check = machine_check_440A,
  1783. .platform = "ppc440",
  1784. },
  1785. { /* 460EX */
  1786. .pvr_mask = 0xffff0006,
  1787. .pvr_value = 0x13020002,
  1788. .cpu_name = "460EX",
  1789. .cpu_features = CPU_FTRS_440x6,
  1790. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1791. .mmu_features = MMU_FTR_TYPE_44x,
  1792. .icache_bsize = 32,
  1793. .dcache_bsize = 32,
  1794. .cpu_setup = __setup_cpu_460ex,
  1795. .machine_check = machine_check_440A,
  1796. .platform = "ppc440",
  1797. },
  1798. { /* 460EX Rev B */
  1799. .pvr_mask = 0xffff0007,
  1800. .pvr_value = 0x13020004,
  1801. .cpu_name = "460EX Rev. B",
  1802. .cpu_features = CPU_FTRS_440x6,
  1803. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1804. .mmu_features = MMU_FTR_TYPE_44x,
  1805. .icache_bsize = 32,
  1806. .dcache_bsize = 32,
  1807. .cpu_setup = __setup_cpu_460ex,
  1808. .machine_check = machine_check_440A,
  1809. .platform = "ppc440",
  1810. },
  1811. { /* 460GT */
  1812. .pvr_mask = 0xffff0006,
  1813. .pvr_value = 0x13020000,
  1814. .cpu_name = "460GT",
  1815. .cpu_features = CPU_FTRS_440x6,
  1816. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1817. .mmu_features = MMU_FTR_TYPE_44x,
  1818. .icache_bsize = 32,
  1819. .dcache_bsize = 32,
  1820. .cpu_setup = __setup_cpu_460gt,
  1821. .machine_check = machine_check_440A,
  1822. .platform = "ppc440",
  1823. },
  1824. { /* 460GT Rev B */
  1825. .pvr_mask = 0xffff0007,
  1826. .pvr_value = 0x13020005,
  1827. .cpu_name = "460GT Rev. B",
  1828. .cpu_features = CPU_FTRS_440x6,
  1829. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1830. .mmu_features = MMU_FTR_TYPE_44x,
  1831. .icache_bsize = 32,
  1832. .dcache_bsize = 32,
  1833. .cpu_setup = __setup_cpu_460gt,
  1834. .machine_check = machine_check_440A,
  1835. .platform = "ppc440",
  1836. },
  1837. { /* 460SX */
  1838. .pvr_mask = 0xffffff00,
  1839. .pvr_value = 0x13541800,
  1840. .cpu_name = "460SX",
  1841. .cpu_features = CPU_FTRS_44X,
  1842. .cpu_user_features = COMMON_USER_BOOKE,
  1843. .mmu_features = MMU_FTR_TYPE_44x,
  1844. .icache_bsize = 32,
  1845. .dcache_bsize = 32,
  1846. .cpu_setup = __setup_cpu_460sx,
  1847. .machine_check = machine_check_440A,
  1848. .platform = "ppc440",
  1849. },
  1850. { /* 464 in APM821xx */
  1851. .pvr_mask = 0xfffffff0,
  1852. .pvr_value = 0x12C41C80,
  1853. .cpu_name = "APM821XX",
  1854. .cpu_features = CPU_FTRS_44X,
  1855. .cpu_user_features = COMMON_USER_BOOKE |
  1856. PPC_FEATURE_HAS_FPU,
  1857. .mmu_features = MMU_FTR_TYPE_44x,
  1858. .icache_bsize = 32,
  1859. .dcache_bsize = 32,
  1860. .cpu_setup = __setup_cpu_apm821xx,
  1861. .machine_check = machine_check_440A,
  1862. .platform = "ppc440",
  1863. },
  1864. { /* 476 DD2 core */
  1865. .pvr_mask = 0xffffffff,
  1866. .pvr_value = 0x11a52080,
  1867. .cpu_name = "476",
  1868. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1869. .cpu_user_features = COMMON_USER_BOOKE |
  1870. PPC_FEATURE_HAS_FPU,
  1871. .mmu_features = MMU_FTR_TYPE_47x |
  1872. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1873. .icache_bsize = 32,
  1874. .dcache_bsize = 128,
  1875. .machine_check = machine_check_47x,
  1876. .platform = "ppc470",
  1877. },
  1878. { /* 476fpe */
  1879. .pvr_mask = 0xffff0000,
  1880. .pvr_value = 0x7ff50000,
  1881. .cpu_name = "476fpe",
  1882. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1883. .cpu_user_features = COMMON_USER_BOOKE |
  1884. PPC_FEATURE_HAS_FPU,
  1885. .mmu_features = MMU_FTR_TYPE_47x |
  1886. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1887. .icache_bsize = 32,
  1888. .dcache_bsize = 128,
  1889. .machine_check = machine_check_47x,
  1890. .platform = "ppc470",
  1891. },
  1892. { /* 476 iss */
  1893. .pvr_mask = 0xffff0000,
  1894. .pvr_value = 0x00050000,
  1895. .cpu_name = "476",
  1896. .cpu_features = CPU_FTRS_47X,
  1897. .cpu_user_features = COMMON_USER_BOOKE |
  1898. PPC_FEATURE_HAS_FPU,
  1899. .mmu_features = MMU_FTR_TYPE_47x |
  1900. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1901. .icache_bsize = 32,
  1902. .dcache_bsize = 128,
  1903. .machine_check = machine_check_47x,
  1904. .platform = "ppc470",
  1905. },
  1906. { /* 476 others */
  1907. .pvr_mask = 0xffff0000,
  1908. .pvr_value = 0x11a50000,
  1909. .cpu_name = "476",
  1910. .cpu_features = CPU_FTRS_47X,
  1911. .cpu_user_features = COMMON_USER_BOOKE |
  1912. PPC_FEATURE_HAS_FPU,
  1913. .mmu_features = MMU_FTR_TYPE_47x |
  1914. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1915. .icache_bsize = 32,
  1916. .dcache_bsize = 128,
  1917. .machine_check = machine_check_47x,
  1918. .platform = "ppc470",
  1919. },
  1920. { /* default match */
  1921. .pvr_mask = 0x00000000,
  1922. .pvr_value = 0x00000000,
  1923. .cpu_name = "(generic 44x PPC)",
  1924. .cpu_features = CPU_FTRS_44X,
  1925. .cpu_user_features = COMMON_USER_BOOKE,
  1926. .mmu_features = MMU_FTR_TYPE_44x,
  1927. .icache_bsize = 32,
  1928. .dcache_bsize = 32,
  1929. .machine_check = machine_check_4xx,
  1930. .platform = "ppc440",
  1931. }
  1932. #endif /* CONFIG_44x */
  1933. #ifdef CONFIG_E200
  1934. { /* e200z5 */
  1935. .pvr_mask = 0xfff00000,
  1936. .pvr_value = 0x81000000,
  1937. .cpu_name = "e200z5",
  1938. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1939. .cpu_features = CPU_FTRS_E200,
  1940. .cpu_user_features = COMMON_USER_BOOKE |
  1941. PPC_FEATURE_HAS_EFP_SINGLE |
  1942. PPC_FEATURE_UNIFIED_CACHE,
  1943. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1944. .dcache_bsize = 32,
  1945. .machine_check = machine_check_e200,
  1946. .platform = "ppc5554",
  1947. },
  1948. { /* e200z6 */
  1949. .pvr_mask = 0xfff00000,
  1950. .pvr_value = 0x81100000,
  1951. .cpu_name = "e200z6",
  1952. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1953. .cpu_features = CPU_FTRS_E200,
  1954. .cpu_user_features = COMMON_USER_BOOKE |
  1955. PPC_FEATURE_HAS_SPE_COMP |
  1956. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1957. PPC_FEATURE_UNIFIED_CACHE,
  1958. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1959. .dcache_bsize = 32,
  1960. .machine_check = machine_check_e200,
  1961. .platform = "ppc5554",
  1962. },
  1963. { /* default match */
  1964. .pvr_mask = 0x00000000,
  1965. .pvr_value = 0x00000000,
  1966. .cpu_name = "(generic E200 PPC)",
  1967. .cpu_features = CPU_FTRS_E200,
  1968. .cpu_user_features = COMMON_USER_BOOKE |
  1969. PPC_FEATURE_HAS_EFP_SINGLE |
  1970. PPC_FEATURE_UNIFIED_CACHE,
  1971. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1972. .dcache_bsize = 32,
  1973. .cpu_setup = __setup_cpu_e200,
  1974. .machine_check = machine_check_e200,
  1975. .platform = "ppc5554",
  1976. }
  1977. #endif /* CONFIG_E200 */
  1978. #endif /* CONFIG_PPC32 */
  1979. #ifdef CONFIG_E500
  1980. #ifdef CONFIG_PPC32
  1981. { /* e500 */
  1982. .pvr_mask = 0xffff0000,
  1983. .pvr_value = 0x80200000,
  1984. .cpu_name = "e500",
  1985. .cpu_features = CPU_FTRS_E500,
  1986. .cpu_user_features = COMMON_USER_BOOKE |
  1987. PPC_FEATURE_HAS_SPE_COMP |
  1988. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1989. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1990. .icache_bsize = 32,
  1991. .dcache_bsize = 32,
  1992. .num_pmcs = 4,
  1993. .oprofile_cpu_type = "ppc/e500",
  1994. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1995. .cpu_setup = __setup_cpu_e500v1,
  1996. .machine_check = machine_check_e500,
  1997. .platform = "ppc8540",
  1998. },
  1999. { /* e500v2 */
  2000. .pvr_mask = 0xffff0000,
  2001. .pvr_value = 0x80210000,
  2002. .cpu_name = "e500v2",
  2003. .cpu_features = CPU_FTRS_E500_2,
  2004. .cpu_user_features = COMMON_USER_BOOKE |
  2005. PPC_FEATURE_HAS_SPE_COMP |
  2006. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  2007. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  2008. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  2009. .icache_bsize = 32,
  2010. .dcache_bsize = 32,
  2011. .num_pmcs = 4,
  2012. .oprofile_cpu_type = "ppc/e500",
  2013. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2014. .cpu_setup = __setup_cpu_e500v2,
  2015. .machine_check = machine_check_e500,
  2016. .platform = "ppc8548",
  2017. },
  2018. { /* e500mc */
  2019. .pvr_mask = 0xffff0000,
  2020. .pvr_value = 0x80230000,
  2021. .cpu_name = "e500mc",
  2022. .cpu_features = CPU_FTRS_E500MC,
  2023. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2024. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2025. MMU_FTR_USE_TLBILX,
  2026. .icache_bsize = 64,
  2027. .dcache_bsize = 64,
  2028. .num_pmcs = 4,
  2029. .oprofile_cpu_type = "ppc/e500mc",
  2030. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2031. .cpu_setup = __setup_cpu_e500mc,
  2032. .machine_check = machine_check_e500mc,
  2033. .platform = "ppce500mc",
  2034. },
  2035. #endif /* CONFIG_PPC32 */
  2036. { /* e5500 */
  2037. .pvr_mask = 0xffff0000,
  2038. .pvr_value = 0x80240000,
  2039. .cpu_name = "e5500",
  2040. .cpu_features = CPU_FTRS_E5500,
  2041. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2042. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2043. MMU_FTR_USE_TLBILX,
  2044. .icache_bsize = 64,
  2045. .dcache_bsize = 64,
  2046. .num_pmcs = 4,
  2047. .oprofile_cpu_type = "ppc/e500mc",
  2048. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2049. .cpu_setup = __setup_cpu_e5500,
  2050. #ifndef CONFIG_PPC32
  2051. .cpu_restore = __restore_cpu_e5500,
  2052. #endif
  2053. .machine_check = machine_check_e500mc,
  2054. .platform = "ppce5500",
  2055. },
  2056. { /* e6500 */
  2057. .pvr_mask = 0xffff0000,
  2058. .pvr_value = 0x80400000,
  2059. .cpu_name = "e6500",
  2060. .cpu_features = CPU_FTRS_E6500,
  2061. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
  2062. PPC_FEATURE_HAS_ALTIVEC_COMP,
  2063. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2064. MMU_FTR_USE_TLBILX,
  2065. .icache_bsize = 64,
  2066. .dcache_bsize = 64,
  2067. .num_pmcs = 4,
  2068. .oprofile_cpu_type = "ppc/e6500",
  2069. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2070. .cpu_setup = __setup_cpu_e6500,
  2071. #ifndef CONFIG_PPC32
  2072. .cpu_restore = __restore_cpu_e6500,
  2073. #endif
  2074. .machine_check = machine_check_e500mc,
  2075. .platform = "ppce6500",
  2076. },
  2077. #ifdef CONFIG_PPC32
  2078. { /* default match */
  2079. .pvr_mask = 0x00000000,
  2080. .pvr_value = 0x00000000,
  2081. .cpu_name = "(generic E500 PPC)",
  2082. .cpu_features = CPU_FTRS_E500,
  2083. .cpu_user_features = COMMON_USER_BOOKE |
  2084. PPC_FEATURE_HAS_SPE_COMP |
  2085. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  2086. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2087. .icache_bsize = 32,
  2088. .dcache_bsize = 32,
  2089. .machine_check = machine_check_e500,
  2090. .platform = "powerpc",
  2091. }
  2092. #endif /* CONFIG_PPC32 */
  2093. #endif /* CONFIG_E500 */
  2094. #ifdef CONFIG_PPC_A2
  2095. { /* Standard A2 (>= DD2) + FPU core */
  2096. .pvr_mask = 0xffff0000,
  2097. .pvr_value = 0x00480000,
  2098. .cpu_name = "A2 (>= DD2)",
  2099. .cpu_features = CPU_FTRS_A2,
  2100. .cpu_user_features = COMMON_USER_PPC64,
  2101. .mmu_features = MMU_FTRS_A2,
  2102. .icache_bsize = 64,
  2103. .dcache_bsize = 64,
  2104. .num_pmcs = 0,
  2105. .cpu_setup = __setup_cpu_a2,
  2106. .cpu_restore = __restore_cpu_a2,
  2107. .machine_check = machine_check_generic,
  2108. .platform = "ppca2",
  2109. },
  2110. { /* This is a default entry to get going, to be replaced by
  2111. * a real one at some stage
  2112. */
  2113. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  2114. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  2115. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  2116. .pvr_mask = 0x00000000,
  2117. .pvr_value = 0x00000000,
  2118. .cpu_name = "Book3E",
  2119. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  2120. .cpu_user_features = COMMON_USER_PPC64,
  2121. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  2122. MMU_FTR_USE_TLBIVAX_BCAST |
  2123. MMU_FTR_LOCK_BCAST_INVAL,
  2124. .icache_bsize = 64,
  2125. .dcache_bsize = 64,
  2126. .num_pmcs = 0,
  2127. .machine_check = machine_check_generic,
  2128. .platform = "power6",
  2129. },
  2130. #endif /* CONFIG_PPC_A2 */
  2131. };
  2132. static struct cpu_spec the_cpu_spec;
  2133. static struct cpu_spec * __init setup_cpu_spec(unsigned long offset,
  2134. struct cpu_spec *s)
  2135. {
  2136. struct cpu_spec *t = &the_cpu_spec;
  2137. struct cpu_spec old;
  2138. t = PTRRELOC(t);
  2139. old = *t;
  2140. /* Copy everything, then do fixups */
  2141. *t = *s;
  2142. /*
  2143. * If we are overriding a previous value derived from the real
  2144. * PVR with a new value obtained using a logical PVR value,
  2145. * don't modify the performance monitor fields.
  2146. */
  2147. if (old.num_pmcs && !s->num_pmcs) {
  2148. t->num_pmcs = old.num_pmcs;
  2149. t->pmc_type = old.pmc_type;
  2150. t->oprofile_type = old.oprofile_type;
  2151. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2152. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2153. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2154. /*
  2155. * If we have passed through this logic once before and
  2156. * have pulled the default case because the real PVR was
  2157. * not found inside cpu_specs[], then we are possibly
  2158. * running in compatibility mode. In that case, let the
  2159. * oprofiler know which set of compatibility counters to
  2160. * pull from by making sure the oprofile_cpu_type string
  2161. * is set to that of compatibility mode. If the
  2162. * oprofile_cpu_type already has a value, then we are
  2163. * possibly overriding a real PVR with a logical one,
  2164. * and, in that case, keep the current value for
  2165. * oprofile_cpu_type.
  2166. */
  2167. if (old.oprofile_cpu_type != NULL) {
  2168. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2169. t->oprofile_type = old.oprofile_type;
  2170. }
  2171. }
  2172. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2173. /*
  2174. * Set the base platform string once; assumes
  2175. * we're called with real pvr first.
  2176. */
  2177. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2178. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2179. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2180. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2181. * that processor. I will consolidate that at a later time, for now,
  2182. * just use #ifdef. We also don't need to PTRRELOC the function
  2183. * pointer on ppc64 and booke as we are running at 0 in real mode
  2184. * on ppc64 and reloc_offset is always 0 on booke.
  2185. */
  2186. if (t->cpu_setup) {
  2187. t->cpu_setup(offset, t);
  2188. }
  2189. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2190. return t;
  2191. }
  2192. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2193. {
  2194. struct cpu_spec *s = cpu_specs;
  2195. int i;
  2196. s = PTRRELOC(s);
  2197. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2198. if ((pvr & s->pvr_mask) == s->pvr_value)
  2199. return setup_cpu_spec(offset, s);
  2200. }
  2201. BUG();
  2202. return NULL;
  2203. }