nouveau_drv.c 13 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include <linux/module.h>
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "drm_crtc_helper.h"
  29. #include "nouveau_drv.h"
  30. #include "nouveau_agp.h"
  31. #include "nouveau_abi16.h"
  32. #include "nouveau_hw.h"
  33. #include "nouveau_fb.h"
  34. #include "nouveau_fbcon.h"
  35. #include "nouveau_pm.h"
  36. #include <engine/fifo.h>
  37. #include "nv50_display.h"
  38. #include "drm_pciids.h"
  39. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  40. int nouveau_modeset = -1;
  41. module_param_named(modeset, nouveau_modeset, int, 0400);
  42. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  43. int nouveau_vram_pushbuf;
  44. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  45. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  46. int nouveau_vram_notify = 0;
  47. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  48. MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
  49. char *nouveau_vram_type;
  50. module_param_named(vram_type, nouveau_vram_type, charp, 0400);
  51. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  52. int nouveau_duallink = 1;
  53. module_param_named(duallink, nouveau_duallink, int, 0400);
  54. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  55. int nouveau_uscript_lvds = -1;
  56. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  57. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  58. int nouveau_uscript_tmds = -1;
  59. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  60. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  61. int nouveau_ignorelid = 0;
  62. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  63. MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  64. int nouveau_noaccel = -1;
  65. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  66. MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  67. int nouveau_nofbaccel = 0;
  68. module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  69. MODULE_PARM_DESC(force_post, "Force POST");
  70. int nouveau_force_post = 0;
  71. module_param_named(force_post, nouveau_force_post, int, 0400);
  72. MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
  73. int nouveau_override_conntype = 0;
  74. module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
  75. MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
  76. int nouveau_tv_disable = 0;
  77. module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
  78. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  79. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  80. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  81. "\t\tDefault: PAL\n"
  82. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  83. char *nouveau_tv_norm;
  84. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  85. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  86. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  87. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  88. "\t\t0x100 vgaattr, 0x200 EVO (G80+)");
  89. int nouveau_reg_debug;
  90. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  91. MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
  92. char *nouveau_perflvl;
  93. module_param_named(perflvl, nouveau_perflvl, charp, 0400);
  94. MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
  95. int nouveau_perflvl_wr;
  96. module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
  97. MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
  98. int nouveau_msi;
  99. module_param_named(msi, nouveau_msi, int, 0400);
  100. MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
  101. int nouveau_ctxfw;
  102. module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  103. MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
  104. int nouveau_mxmdcb = 1;
  105. module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
  106. int nouveau_fbpercrtc;
  107. #if 0
  108. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  109. #endif
  110. static struct drm_driver driver;
  111. int __devinit
  112. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  113. {
  114. return drm_get_pci_dev(pdev, ent, &driver);
  115. }
  116. void
  117. nouveau_pci_remove(struct pci_dev *pdev)
  118. {
  119. struct drm_device *dev = pci_get_drvdata(pdev);
  120. drm_put_dev(dev);
  121. }
  122. int
  123. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  124. {
  125. struct drm_device *dev = pci_get_drvdata(pdev);
  126. struct drm_nouveau_private *dev_priv = dev->dev_private;
  127. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  128. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  129. struct nouveau_channel *chan;
  130. struct drm_crtc *crtc;
  131. int ret, i, e;
  132. NV_INFO(dev, "Disabling display...\n");
  133. nouveau_display_fini(dev);
  134. NV_INFO(dev, "Disabling fbcon...\n");
  135. nouveau_fbcon_set_suspend(dev, 1);
  136. NV_INFO(dev, "Unpinning framebuffer(s)...\n");
  137. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  138. struct nouveau_framebuffer *nouveau_fb;
  139. nouveau_fb = nouveau_framebuffer(crtc->fb);
  140. if (!nouveau_fb || !nouveau_fb->nvbo)
  141. continue;
  142. nouveau_bo_unpin(nouveau_fb->nvbo);
  143. }
  144. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  145. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  146. nouveau_bo_unmap(nv_crtc->cursor.nvbo);
  147. nouveau_bo_unpin(nv_crtc->cursor.nvbo);
  148. }
  149. NV_INFO(dev, "Evicting buffers...\n");
  150. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  151. NV_INFO(dev, "Idling channels...\n");
  152. for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
  153. chan = dev_priv->channels.ptr[i];
  154. if (chan && chan->pushbuf_bo)
  155. nouveau_channel_idle(chan);
  156. }
  157. for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
  158. if (!dev_priv->eng[e])
  159. continue;
  160. ret = dev_priv->eng[e]->fini(dev, e, true);
  161. if (ret) {
  162. NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
  163. goto out_abort;
  164. }
  165. }
  166. ret = pinstmem->suspend(dev);
  167. if (ret) {
  168. NV_ERROR(dev, "... failed: %d\n", ret);
  169. goto out_abort;
  170. }
  171. NV_INFO(dev, "Suspending GPU objects...\n");
  172. ret = nouveau_gpuobj_suspend(dev);
  173. if (ret) {
  174. NV_ERROR(dev, "... failed: %d\n", ret);
  175. pinstmem->resume(dev);
  176. goto out_abort;
  177. }
  178. nouveau_agp_fini(dev);
  179. return 0;
  180. out_abort:
  181. NV_INFO(dev, "Re-enabling acceleration..\n");
  182. for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
  183. if (dev_priv->eng[e])
  184. dev_priv->eng[e]->init(dev, e);
  185. }
  186. return ret;
  187. }
  188. int
  189. nouveau_pci_resume(struct pci_dev *pdev)
  190. {
  191. struct drm_device *dev = pci_get_drvdata(pdev);
  192. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  193. struct drm_nouveau_private *dev_priv = dev->dev_private;
  194. struct nouveau_engine *engine = &dev_priv->engine;
  195. struct drm_crtc *crtc;
  196. int ret, i;
  197. /* Make sure the AGP controller is in a consistent state */
  198. nouveau_agp_reset(dev);
  199. /* Make the CRTCs accessible */
  200. engine->display.early_init(dev);
  201. NV_INFO(dev, "POSTing device...\n");
  202. ret = nouveau_run_vbios_init(dev);
  203. if (ret)
  204. return ret;
  205. nouveau_agp_init(dev);
  206. NV_INFO(dev, "Restoring GPU objects...\n");
  207. nouveau_gpuobj_resume(dev);
  208. NV_INFO(dev, "Reinitialising engines...\n");
  209. engine->instmem.resume(dev);
  210. engine->mc.init(dev);
  211. engine->timer.init(dev);
  212. engine->fb.init(dev);
  213. for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
  214. if (dev_priv->eng[i])
  215. dev_priv->eng[i]->init(dev, i);
  216. }
  217. nouveau_irq_postinstall(dev);
  218. /* Re-write SKIPS, they'll have been lost over the suspend */
  219. if (nouveau_vram_pushbuf) {
  220. struct nouveau_channel *chan;
  221. int j;
  222. for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
  223. chan = dev_priv->channels.ptr[i];
  224. if (!chan || !chan->pushbuf_bo)
  225. continue;
  226. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  227. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  228. }
  229. }
  230. nouveau_pm_resume(dev);
  231. NV_INFO(dev, "Restoring mode...\n");
  232. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  233. struct nouveau_framebuffer *nouveau_fb;
  234. nouveau_fb = nouveau_framebuffer(crtc->fb);
  235. if (!nouveau_fb || !nouveau_fb->nvbo)
  236. continue;
  237. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  238. }
  239. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  240. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  241. ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
  242. if (!ret)
  243. ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
  244. if (ret)
  245. NV_ERROR(dev, "Could not pin/map cursor.\n");
  246. }
  247. nouveau_fbcon_set_suspend(dev, 0);
  248. nouveau_fbcon_zfill_all(dev);
  249. nouveau_display_init(dev);
  250. /* Force CLUT to get re-loaded during modeset */
  251. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  252. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  253. nv_crtc->lut.depth = 0;
  254. }
  255. drm_helper_resume_force_mode(dev);
  256. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  257. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  258. u32 offset = nv_crtc->cursor.nvbo->bo.offset;
  259. nv_crtc->cursor.set_offset(nv_crtc, offset);
  260. nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
  261. nv_crtc->cursor_saved_y);
  262. }
  263. return 0;
  264. }
  265. static struct drm_ioctl_desc nouveau_ioctls[] = {
  266. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
  267. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  268. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
  269. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
  270. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
  271. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
  272. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
  273. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
  274. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
  275. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
  276. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
  277. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
  278. };
  279. static const struct file_operations nouveau_driver_fops = {
  280. .owner = THIS_MODULE,
  281. .open = drm_open,
  282. .release = drm_release,
  283. .unlocked_ioctl = drm_ioctl,
  284. .mmap = nouveau_ttm_mmap,
  285. .poll = drm_poll,
  286. .fasync = drm_fasync,
  287. .read = drm_read,
  288. #if defined(CONFIG_COMPAT)
  289. .compat_ioctl = nouveau_compat_ioctl,
  290. #endif
  291. .llseek = noop_llseek,
  292. };
  293. int nouveau_drm_load(struct drm_device *, unsigned long);
  294. int nouveau_drm_unload(struct drm_device *);
  295. static struct drm_driver driver = {
  296. .driver_features =
  297. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  298. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  299. DRIVER_MODESET | DRIVER_PRIME,
  300. .load = nouveau_drm_load,
  301. .firstopen = nouveau_firstopen,
  302. .lastclose = nouveau_lastclose,
  303. .unload = nouveau_drm_unload,
  304. .open = nouveau_open,
  305. .preclose = nouveau_preclose,
  306. .postclose = nouveau_postclose,
  307. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  308. .debugfs_init = nouveau_debugfs_init,
  309. .debugfs_cleanup = nouveau_debugfs_takedown,
  310. #endif
  311. .irq_preinstall = nouveau_irq_preinstall,
  312. .irq_postinstall = nouveau_irq_postinstall,
  313. .irq_uninstall = nouveau_irq_uninstall,
  314. .irq_handler = nouveau_irq_handler,
  315. .get_vblank_counter = drm_vblank_count,
  316. .enable_vblank = nouveau_vblank_enable,
  317. .disable_vblank = nouveau_vblank_disable,
  318. .ioctls = nouveau_ioctls,
  319. .fops = &nouveau_driver_fops,
  320. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  321. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  322. .gem_prime_export = nouveau_gem_prime_export,
  323. .gem_prime_import = nouveau_gem_prime_import,
  324. .gem_init_object = nouveau_gem_object_new,
  325. .gem_free_object = nouveau_gem_object_del,
  326. .gem_open_object = nouveau_gem_object_open,
  327. .gem_close_object = nouveau_gem_object_close,
  328. .dumb_create = nouveau_display_dumb_create,
  329. .dumb_map_offset = nouveau_display_dumb_map_offset,
  330. .dumb_destroy = nouveau_display_dumb_destroy,
  331. .name = DRIVER_NAME,
  332. .desc = DRIVER_DESC,
  333. #ifdef GIT_REVISION
  334. .date = GIT_REVISION,
  335. #else
  336. .date = DRIVER_DATE,
  337. #endif
  338. .major = DRIVER_MAJOR,
  339. .minor = DRIVER_MINOR,
  340. .patchlevel = DRIVER_PATCHLEVEL,
  341. };
  342. int __init nouveau_init(struct pci_driver *pdrv)
  343. {
  344. driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
  345. if (nouveau_modeset == -1) {
  346. #ifdef CONFIG_VGA_CONSOLE
  347. if (vgacon_text_force())
  348. nouveau_modeset = 0;
  349. else
  350. #endif
  351. nouveau_modeset = 1;
  352. }
  353. if (!nouveau_modeset)
  354. return 0;
  355. nouveau_register_dsm_handler();
  356. return drm_pci_init(&driver, pdrv);
  357. }
  358. void __exit nouveau_exit(struct pci_driver *pdrv)
  359. {
  360. if (!nouveau_modeset)
  361. return;
  362. drm_pci_exit(&driver, pdrv);
  363. nouveau_unregister_dsm_handler();
  364. }