cpu-probe.c 14 KB

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  1. /*
  2. * Processor capabilities determination functions.
  3. *
  4. * Copyright (C) xxxx the Anonymous
  5. * Copyright (C) 2003 Maciej W. Rozycki
  6. * Copyright (C) 1994 - 2003 Ralf Baechle
  7. * Copyright (C) 2001 MIPS Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. #include <linux/config.h>
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ptrace.h>
  18. #include <linux/stddef.h>
  19. #include <asm/cpu.h>
  20. #include <asm/fpu.h>
  21. #include <asm/mipsregs.h>
  22. #include <asm/system.h>
  23. /*
  24. * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  25. * the implementation of the "wait" feature differs between CPU families. This
  26. * points to the function that implements CPU specific wait.
  27. * The wait instruction stops the pipeline and reduces the power consumption of
  28. * the CPU very much.
  29. */
  30. void (*cpu_wait)(void) = NULL;
  31. static void r3081_wait(void)
  32. {
  33. unsigned long cfg = read_c0_conf();
  34. write_c0_conf(cfg | R30XX_CONF_HALT);
  35. }
  36. static void r39xx_wait(void)
  37. {
  38. unsigned long cfg = read_c0_conf();
  39. write_c0_conf(cfg | TX39_CONF_HALT);
  40. }
  41. static void r4k_wait(void)
  42. {
  43. __asm__(".set\tmips3\n\t"
  44. "wait\n\t"
  45. ".set\tmips0");
  46. }
  47. /* The Au1xxx wait is available only if using 32khz counter or
  48. * external timer source, but specifically not CP0 Counter. */
  49. int allow_au1k_wait;
  50. static void au1k_wait(void)
  51. {
  52. unsigned long addr = 0;
  53. /* using the wait instruction makes CP0 counter unusable */
  54. __asm__("la %0,au1k_wait\n\t"
  55. ".set mips3\n\t"
  56. "cache 0x14,0(%0)\n\t"
  57. "cache 0x14,32(%0)\n\t"
  58. "sync\n\t"
  59. "nop\n\t"
  60. "wait\n\t"
  61. "nop\n\t"
  62. "nop\n\t"
  63. "nop\n\t"
  64. "nop\n\t"
  65. ".set mips0\n\t"
  66. : : "r" (addr));
  67. }
  68. static inline void check_wait(void)
  69. {
  70. struct cpuinfo_mips *c = &current_cpu_data;
  71. printk("Checking for 'wait' instruction... ");
  72. switch (c->cputype) {
  73. case CPU_R3081:
  74. case CPU_R3081E:
  75. cpu_wait = r3081_wait;
  76. printk(" available.\n");
  77. break;
  78. case CPU_TX3927:
  79. cpu_wait = r39xx_wait;
  80. printk(" available.\n");
  81. break;
  82. case CPU_R4200:
  83. /* case CPU_R4300: */
  84. case CPU_R4600:
  85. case CPU_R4640:
  86. case CPU_R4650:
  87. case CPU_R4700:
  88. case CPU_R5000:
  89. case CPU_NEVADA:
  90. case CPU_RM7000:
  91. case CPU_RM9000:
  92. case CPU_TX49XX:
  93. case CPU_4KC:
  94. case CPU_4KEC:
  95. case CPU_4KSC:
  96. case CPU_5KC:
  97. /* case CPU_20KC:*/
  98. case CPU_24K:
  99. case CPU_25KF:
  100. cpu_wait = r4k_wait;
  101. printk(" available.\n");
  102. break;
  103. case CPU_AU1000:
  104. case CPU_AU1100:
  105. case CPU_AU1500:
  106. case CPU_AU1550:
  107. case CPU_AU1200:
  108. if (allow_au1k_wait) {
  109. cpu_wait = au1k_wait;
  110. printk(" available.\n");
  111. } else
  112. printk(" unavailable.\n");
  113. break;
  114. default:
  115. printk(" unavailable.\n");
  116. break;
  117. }
  118. }
  119. void __init check_bugs32(void)
  120. {
  121. check_wait();
  122. }
  123. /*
  124. * Probe whether cpu has config register by trying to play with
  125. * alternate cache bit and see whether it matters.
  126. * It's used by cpu_probe to distinguish between R3000A and R3081.
  127. */
  128. static inline int cpu_has_confreg(void)
  129. {
  130. #ifdef CONFIG_CPU_R3000
  131. extern unsigned long r3k_cache_size(unsigned long);
  132. unsigned long size1, size2;
  133. unsigned long cfg = read_c0_conf();
  134. size1 = r3k_cache_size(ST0_ISC);
  135. write_c0_conf(cfg ^ R30XX_CONF_AC);
  136. size2 = r3k_cache_size(ST0_ISC);
  137. write_c0_conf(cfg);
  138. return size1 != size2;
  139. #else
  140. return 0;
  141. #endif
  142. }
  143. /*
  144. * Get the FPU Implementation/Revision.
  145. */
  146. static inline unsigned long cpu_get_fpu_id(void)
  147. {
  148. unsigned long tmp, fpu_id;
  149. tmp = read_c0_status();
  150. __enable_fpu();
  151. fpu_id = read_32bit_cp1_register(CP1_REVISION);
  152. write_c0_status(tmp);
  153. return fpu_id;
  154. }
  155. /*
  156. * Check the CPU has an FPU the official way.
  157. */
  158. static inline int __cpu_has_fpu(void)
  159. {
  160. return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
  161. }
  162. #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
  163. | MIPS_CPU_COUNTER)
  164. static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
  165. {
  166. switch (c->processor_id & 0xff00) {
  167. case PRID_IMP_R2000:
  168. c->cputype = CPU_R2000;
  169. c->isa_level = MIPS_CPU_ISA_I;
  170. c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
  171. if (__cpu_has_fpu())
  172. c->options |= MIPS_CPU_FPU;
  173. c->tlbsize = 64;
  174. break;
  175. case PRID_IMP_R3000:
  176. if ((c->processor_id & 0xff) == PRID_REV_R3000A)
  177. if (cpu_has_confreg())
  178. c->cputype = CPU_R3081E;
  179. else
  180. c->cputype = CPU_R3000A;
  181. else
  182. c->cputype = CPU_R3000;
  183. c->isa_level = MIPS_CPU_ISA_I;
  184. c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
  185. if (__cpu_has_fpu())
  186. c->options |= MIPS_CPU_FPU;
  187. c->tlbsize = 64;
  188. break;
  189. case PRID_IMP_R4000:
  190. if (read_c0_config() & CONF_SC) {
  191. if ((c->processor_id & 0xff) >= PRID_REV_R4400)
  192. c->cputype = CPU_R4400PC;
  193. else
  194. c->cputype = CPU_R4000PC;
  195. } else {
  196. if ((c->processor_id & 0xff) >= PRID_REV_R4400)
  197. c->cputype = CPU_R4400SC;
  198. else
  199. c->cputype = CPU_R4000SC;
  200. }
  201. c->isa_level = MIPS_CPU_ISA_III;
  202. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  203. MIPS_CPU_WATCH | MIPS_CPU_VCE |
  204. MIPS_CPU_LLSC;
  205. c->tlbsize = 48;
  206. break;
  207. case PRID_IMP_VR41XX:
  208. switch (c->processor_id & 0xf0) {
  209. case PRID_REV_VR4111:
  210. c->cputype = CPU_VR4111;
  211. break;
  212. case PRID_REV_VR4121:
  213. c->cputype = CPU_VR4121;
  214. break;
  215. case PRID_REV_VR4122:
  216. if ((c->processor_id & 0xf) < 0x3)
  217. c->cputype = CPU_VR4122;
  218. else
  219. c->cputype = CPU_VR4181A;
  220. break;
  221. case PRID_REV_VR4130:
  222. if ((c->processor_id & 0xf) < 0x4)
  223. c->cputype = CPU_VR4131;
  224. else
  225. c->cputype = CPU_VR4133;
  226. break;
  227. default:
  228. printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
  229. c->cputype = CPU_VR41XX;
  230. break;
  231. }
  232. c->isa_level = MIPS_CPU_ISA_III;
  233. c->options = R4K_OPTS;
  234. c->tlbsize = 32;
  235. break;
  236. case PRID_IMP_R4300:
  237. c->cputype = CPU_R4300;
  238. c->isa_level = MIPS_CPU_ISA_III;
  239. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  240. MIPS_CPU_LLSC;
  241. c->tlbsize = 32;
  242. break;
  243. case PRID_IMP_R4600:
  244. c->cputype = CPU_R4600;
  245. c->isa_level = MIPS_CPU_ISA_III;
  246. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
  247. c->tlbsize = 48;
  248. break;
  249. #if 0
  250. case PRID_IMP_R4650:
  251. /*
  252. * This processor doesn't have an MMU, so it's not
  253. * "real easy" to run Linux on it. It is left purely
  254. * for documentation. Commented out because it shares
  255. * it's c0_prid id number with the TX3900.
  256. */
  257. c->cputype = CPU_R4650;
  258. c->isa_level = MIPS_CPU_ISA_III;
  259. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
  260. c->tlbsize = 48;
  261. break;
  262. #endif
  263. case PRID_IMP_TX39:
  264. c->isa_level = MIPS_CPU_ISA_I;
  265. c->options = MIPS_CPU_TLB;
  266. if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
  267. c->cputype = CPU_TX3927;
  268. c->tlbsize = 64;
  269. } else {
  270. switch (c->processor_id & 0xff) {
  271. case PRID_REV_TX3912:
  272. c->cputype = CPU_TX3912;
  273. c->tlbsize = 32;
  274. break;
  275. case PRID_REV_TX3922:
  276. c->cputype = CPU_TX3922;
  277. c->tlbsize = 64;
  278. break;
  279. default:
  280. c->cputype = CPU_UNKNOWN;
  281. break;
  282. }
  283. }
  284. break;
  285. case PRID_IMP_R4700:
  286. c->cputype = CPU_R4700;
  287. c->isa_level = MIPS_CPU_ISA_III;
  288. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  289. MIPS_CPU_LLSC;
  290. c->tlbsize = 48;
  291. break;
  292. case PRID_IMP_TX49:
  293. c->cputype = CPU_TX49XX;
  294. c->isa_level = MIPS_CPU_ISA_III;
  295. c->options = R4K_OPTS | MIPS_CPU_LLSC;
  296. if (!(c->processor_id & 0x08))
  297. c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
  298. c->tlbsize = 48;
  299. break;
  300. case PRID_IMP_R5000:
  301. c->cputype = CPU_R5000;
  302. c->isa_level = MIPS_CPU_ISA_IV;
  303. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  304. MIPS_CPU_LLSC;
  305. c->tlbsize = 48;
  306. break;
  307. case PRID_IMP_R5432:
  308. c->cputype = CPU_R5432;
  309. c->isa_level = MIPS_CPU_ISA_IV;
  310. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  311. MIPS_CPU_WATCH | MIPS_CPU_LLSC;
  312. c->tlbsize = 48;
  313. break;
  314. case PRID_IMP_R5500:
  315. c->cputype = CPU_R5500;
  316. c->isa_level = MIPS_CPU_ISA_IV;
  317. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  318. MIPS_CPU_WATCH | MIPS_CPU_LLSC;
  319. c->tlbsize = 48;
  320. break;
  321. case PRID_IMP_NEVADA:
  322. c->cputype = CPU_NEVADA;
  323. c->isa_level = MIPS_CPU_ISA_IV;
  324. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  325. MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
  326. c->tlbsize = 48;
  327. break;
  328. case PRID_IMP_R6000:
  329. c->cputype = CPU_R6000;
  330. c->isa_level = MIPS_CPU_ISA_II;
  331. c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
  332. MIPS_CPU_LLSC;
  333. c->tlbsize = 32;
  334. break;
  335. case PRID_IMP_R6000A:
  336. c->cputype = CPU_R6000A;
  337. c->isa_level = MIPS_CPU_ISA_II;
  338. c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
  339. MIPS_CPU_LLSC;
  340. c->tlbsize = 32;
  341. break;
  342. case PRID_IMP_RM7000:
  343. c->cputype = CPU_RM7000;
  344. c->isa_level = MIPS_CPU_ISA_IV;
  345. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  346. MIPS_CPU_LLSC;
  347. /*
  348. * Undocumented RM7000: Bit 29 in the info register of
  349. * the RM7000 v2.0 indicates if the TLB has 48 or 64
  350. * entries.
  351. *
  352. * 29 1 => 64 entry JTLB
  353. * 0 => 48 entry JTLB
  354. */
  355. c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
  356. break;
  357. case PRID_IMP_RM9000:
  358. c->cputype = CPU_RM9000;
  359. c->isa_level = MIPS_CPU_ISA_IV;
  360. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  361. MIPS_CPU_LLSC;
  362. /*
  363. * Bit 29 in the info register of the RM9000
  364. * indicates if the TLB has 48 or 64 entries.
  365. *
  366. * 29 1 => 64 entry JTLB
  367. * 0 => 48 entry JTLB
  368. */
  369. c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
  370. break;
  371. case PRID_IMP_R8000:
  372. c->cputype = CPU_R8000;
  373. c->isa_level = MIPS_CPU_ISA_IV;
  374. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  375. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  376. MIPS_CPU_LLSC;
  377. c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
  378. break;
  379. case PRID_IMP_R10000:
  380. c->cputype = CPU_R10000;
  381. c->isa_level = MIPS_CPU_ISA_IV;
  382. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  383. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  384. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  385. MIPS_CPU_LLSC;
  386. c->tlbsize = 64;
  387. break;
  388. case PRID_IMP_R12000:
  389. c->cputype = CPU_R12000;
  390. c->isa_level = MIPS_CPU_ISA_IV;
  391. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  392. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  393. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  394. MIPS_CPU_LLSC;
  395. c->tlbsize = 64;
  396. break;
  397. }
  398. }
  399. static inline void decode_config1(struct cpuinfo_mips *c)
  400. {
  401. unsigned long config0 = read_c0_config();
  402. unsigned long config1;
  403. if ((config0 & (1 << 31)) == 0)
  404. return; /* actually wort a panic() */
  405. /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
  406. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  407. MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
  408. MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
  409. config1 = read_c0_config1();
  410. if (config1 & (1 << 3))
  411. c->options |= MIPS_CPU_WATCH;
  412. if (config1 & (1 << 2))
  413. c->options |= MIPS_CPU_MIPS16;
  414. if (config1 & (1 << 1))
  415. c->options |= MIPS_CPU_EJTAG;
  416. if (config1 & 1) {
  417. c->options |= MIPS_CPU_FPU;
  418. c->options |= MIPS_CPU_32FPR;
  419. }
  420. c->scache.flags = MIPS_CACHE_NOT_PRESENT;
  421. c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
  422. }
  423. static inline void cpu_probe_mips(struct cpuinfo_mips *c)
  424. {
  425. decode_config1(c);
  426. switch (c->processor_id & 0xff00) {
  427. case PRID_IMP_4KC:
  428. c->cputype = CPU_4KC;
  429. c->isa_level = MIPS_CPU_ISA_M32;
  430. break;
  431. case PRID_IMP_4KEC:
  432. c->cputype = CPU_4KEC;
  433. c->isa_level = MIPS_CPU_ISA_M32;
  434. break;
  435. case PRID_IMP_4KECR2:
  436. c->cputype = CPU_4KEC;
  437. c->isa_level = MIPS_CPU_ISA_M32;
  438. break;
  439. case PRID_IMP_4KSC:
  440. c->cputype = CPU_4KSC;
  441. c->isa_level = MIPS_CPU_ISA_M32;
  442. break;
  443. case PRID_IMP_5KC:
  444. c->cputype = CPU_5KC;
  445. c->isa_level = MIPS_CPU_ISA_M64;
  446. break;
  447. case PRID_IMP_20KC:
  448. c->cputype = CPU_20KC;
  449. c->isa_level = MIPS_CPU_ISA_M64;
  450. break;
  451. case PRID_IMP_24K:
  452. c->cputype = CPU_24K;
  453. c->isa_level = MIPS_CPU_ISA_M32;
  454. break;
  455. case PRID_IMP_25KF:
  456. c->cputype = CPU_25KF;
  457. c->isa_level = MIPS_CPU_ISA_M64;
  458. /* Probe for L2 cache */
  459. c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  460. break;
  461. }
  462. }
  463. static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
  464. {
  465. decode_config1(c);
  466. switch (c->processor_id & 0xff00) {
  467. case PRID_IMP_AU1_REV1:
  468. case PRID_IMP_AU1_REV2:
  469. switch ((c->processor_id >> 24) & 0xff) {
  470. case 0:
  471. c->cputype = CPU_AU1000;
  472. break;
  473. case 1:
  474. c->cputype = CPU_AU1500;
  475. break;
  476. case 2:
  477. c->cputype = CPU_AU1100;
  478. break;
  479. case 3:
  480. c->cputype = CPU_AU1550;
  481. break;
  482. case 4:
  483. c->cputype = CPU_AU1200;
  484. break;
  485. default:
  486. panic("Unknown Au Core!");
  487. break;
  488. }
  489. c->isa_level = MIPS_CPU_ISA_M32;
  490. break;
  491. }
  492. }
  493. static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
  494. {
  495. decode_config1(c);
  496. switch (c->processor_id & 0xff00) {
  497. case PRID_IMP_SB1:
  498. c->cputype = CPU_SB1;
  499. c->isa_level = MIPS_CPU_ISA_M64;
  500. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  501. MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
  502. MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
  503. MIPS_CPU_WATCH | MIPS_CPU_LLSC;
  504. #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
  505. /* FPU in pass1 is known to have issues. */
  506. c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
  507. #endif
  508. break;
  509. }
  510. }
  511. static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
  512. {
  513. decode_config1(c);
  514. switch (c->processor_id & 0xff00) {
  515. case PRID_IMP_SR71000:
  516. c->cputype = CPU_SR71000;
  517. c->isa_level = MIPS_CPU_ISA_M64;
  518. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  519. MIPS_CPU_4KTLB | MIPS_CPU_FPU |
  520. MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
  521. c->scache.ways = 8;
  522. c->tlbsize = 64;
  523. break;
  524. }
  525. }
  526. __init void cpu_probe(void)
  527. {
  528. struct cpuinfo_mips *c = &current_cpu_data;
  529. c->processor_id = PRID_IMP_UNKNOWN;
  530. c->fpu_id = FPIR_IMP_NONE;
  531. c->cputype = CPU_UNKNOWN;
  532. c->processor_id = read_c0_prid();
  533. switch (c->processor_id & 0xff0000) {
  534. case PRID_COMP_LEGACY:
  535. cpu_probe_legacy(c);
  536. break;
  537. case PRID_COMP_MIPS:
  538. cpu_probe_mips(c);
  539. break;
  540. case PRID_COMP_ALCHEMY:
  541. cpu_probe_alchemy(c);
  542. break;
  543. case PRID_COMP_SIBYTE:
  544. cpu_probe_sibyte(c);
  545. break;
  546. case PRID_COMP_SANDCRAFT:
  547. cpu_probe_sandcraft(c);
  548. break;
  549. default:
  550. c->cputype = CPU_UNKNOWN;
  551. }
  552. if (c->options & MIPS_CPU_FPU)
  553. c->fpu_id = cpu_get_fpu_id();
  554. }
  555. __init void cpu_report(void)
  556. {
  557. struct cpuinfo_mips *c = &current_cpu_data;
  558. printk("CPU revision is: %08x\n", c->processor_id);
  559. if (c->options & MIPS_CPU_FPU)
  560. printk("FPU revision is: %08x\n", c->fpu_id);
  561. }