solos-pci.c 32 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  55. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  56. #define DATA_RAM_SIZE 32768
  57. #define BUF_SIZE 4096
  58. #define FPGA_PAGE 528 /* FPGA flash page size*/
  59. #define SOLOS_PAGE 512 /* Solos flash page size*/
  60. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  61. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  62. #define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
  63. #define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
  64. #define RX_DMA_SIZE 2048
  65. static int atmdebug = 0;
  66. static int firmware_upgrade = 0;
  67. static int fpga_upgrade = 0;
  68. struct pkt_hdr {
  69. __le16 size;
  70. __le16 vpi;
  71. __le16 vci;
  72. __le16 type;
  73. };
  74. struct solos_skb_cb {
  75. struct atm_vcc *vcc;
  76. uint32_t dma_addr;
  77. };
  78. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  79. #define PKT_DATA 0
  80. #define PKT_COMMAND 1
  81. #define PKT_POPEN 3
  82. #define PKT_PCLOSE 4
  83. #define PKT_STATUS 5
  84. struct solos_card {
  85. void __iomem *config_regs;
  86. void __iomem *buffers;
  87. int nr_ports;
  88. int tx_mask;
  89. struct pci_dev *dev;
  90. struct atm_dev *atmdev[4];
  91. struct tasklet_struct tlet;
  92. spinlock_t tx_lock;
  93. spinlock_t tx_queue_lock;
  94. spinlock_t cli_queue_lock;
  95. spinlock_t param_queue_lock;
  96. struct list_head param_queue;
  97. struct sk_buff_head tx_queue[4];
  98. struct sk_buff_head cli_queue[4];
  99. struct sk_buff *tx_skb[4];
  100. struct sk_buff *rx_skb[4];
  101. wait_queue_head_t param_wq;
  102. wait_queue_head_t fw_wq;
  103. int using_dma;
  104. };
  105. struct solos_param {
  106. struct list_head list;
  107. pid_t pid;
  108. int port;
  109. struct sk_buff *response;
  110. wait_queue_head_t wq;
  111. };
  112. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  113. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  114. MODULE_DESCRIPTION("Solos PCI driver");
  115. MODULE_VERSION(VERSION);
  116. MODULE_LICENSE("GPL");
  117. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  118. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  119. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  120. module_param(atmdebug, int, 0644);
  121. module_param(firmware_upgrade, int, 0444);
  122. module_param(fpga_upgrade, int, 0444);
  123. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  124. struct atm_vcc *vcc);
  125. static int fpga_tx(struct solos_card *);
  126. static irqreturn_t solos_irq(int irq, void *dev_id);
  127. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  128. static int list_vccs(int vci);
  129. static void release_vccs(struct atm_dev *dev);
  130. static int atm_init(struct solos_card *);
  131. static void atm_remove(struct solos_card *);
  132. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  133. static void solos_bh(unsigned long);
  134. static int print_buffer(struct sk_buff *buf);
  135. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  136. {
  137. if (vcc->pop)
  138. vcc->pop(vcc, skb);
  139. else
  140. dev_kfree_skb_any(skb);
  141. }
  142. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  143. char *buf)
  144. {
  145. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  146. struct solos_card *card = atmdev->dev_data;
  147. struct solos_param prm;
  148. struct sk_buff *skb;
  149. struct pkt_hdr *header;
  150. int buflen;
  151. buflen = strlen(attr->attr.name) + 10;
  152. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  153. if (!skb) {
  154. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  155. return -ENOMEM;
  156. }
  157. header = (void *)skb_put(skb, sizeof(*header));
  158. buflen = snprintf((void *)&header[1], buflen - 1,
  159. "L%05d\n%s\n", current->pid, attr->attr.name);
  160. skb_put(skb, buflen);
  161. header->size = cpu_to_le16(buflen);
  162. header->vpi = cpu_to_le16(0);
  163. header->vci = cpu_to_le16(0);
  164. header->type = cpu_to_le16(PKT_COMMAND);
  165. prm.pid = current->pid;
  166. prm.response = NULL;
  167. prm.port = SOLOS_CHAN(atmdev);
  168. spin_lock_irq(&card->param_queue_lock);
  169. list_add(&prm.list, &card->param_queue);
  170. spin_unlock_irq(&card->param_queue_lock);
  171. fpga_queue(card, prm.port, skb, NULL);
  172. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  173. spin_lock_irq(&card->param_queue_lock);
  174. list_del(&prm.list);
  175. spin_unlock_irq(&card->param_queue_lock);
  176. if (!prm.response)
  177. return -EIO;
  178. buflen = prm.response->len;
  179. memcpy(buf, prm.response->data, buflen);
  180. kfree_skb(prm.response);
  181. return buflen;
  182. }
  183. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  184. const char *buf, size_t count)
  185. {
  186. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  187. struct solos_card *card = atmdev->dev_data;
  188. struct solos_param prm;
  189. struct sk_buff *skb;
  190. struct pkt_hdr *header;
  191. int buflen;
  192. ssize_t ret;
  193. buflen = strlen(attr->attr.name) + 11 + count;
  194. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  195. if (!skb) {
  196. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  197. return -ENOMEM;
  198. }
  199. header = (void *)skb_put(skb, sizeof(*header));
  200. buflen = snprintf((void *)&header[1], buflen - 1,
  201. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  202. skb_put(skb, buflen);
  203. header->size = cpu_to_le16(buflen);
  204. header->vpi = cpu_to_le16(0);
  205. header->vci = cpu_to_le16(0);
  206. header->type = cpu_to_le16(PKT_COMMAND);
  207. prm.pid = current->pid;
  208. prm.response = NULL;
  209. prm.port = SOLOS_CHAN(atmdev);
  210. spin_lock_irq(&card->param_queue_lock);
  211. list_add(&prm.list, &card->param_queue);
  212. spin_unlock_irq(&card->param_queue_lock);
  213. fpga_queue(card, prm.port, skb, NULL);
  214. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  215. spin_lock_irq(&card->param_queue_lock);
  216. list_del(&prm.list);
  217. spin_unlock_irq(&card->param_queue_lock);
  218. skb = prm.response;
  219. if (!skb)
  220. return -EIO;
  221. buflen = skb->len;
  222. /* Sometimes it has a newline, sometimes it doesn't. */
  223. if (skb->data[buflen - 1] == '\n')
  224. buflen--;
  225. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  226. ret = count;
  227. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  228. ret = -EIO;
  229. else {
  230. /* We know we have enough space allocated for this; we allocated
  231. it ourselves */
  232. skb->data[buflen] = 0;
  233. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  234. skb->data);
  235. ret = -EIO;
  236. }
  237. kfree_skb(skb);
  238. return ret;
  239. }
  240. static char *next_string(struct sk_buff *skb)
  241. {
  242. int i = 0;
  243. char *this = skb->data;
  244. while (i < skb->len) {
  245. if (this[i] == '\n') {
  246. this[i] = 0;
  247. skb_pull(skb, i);
  248. return this;
  249. }
  250. }
  251. return NULL;
  252. }
  253. /*
  254. * Status packet has fields separated by \n, starting with a version number
  255. * for the information therein. Fields are....
  256. *
  257. * packet version
  258. * TxBitRate (version >= 1)
  259. * RxBitRate (version >= 1)
  260. * State (version >= 1)
  261. */
  262. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  263. {
  264. char *str, *end, *state_str;
  265. int ver, rate_up, rate_down, state, snr, attn;
  266. if (!card->atmdev[port])
  267. return -ENODEV;
  268. str = next_string(skb);
  269. if (!str)
  270. return -EIO;
  271. ver = simple_strtol(str, NULL, 10);
  272. if (ver < 1) {
  273. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  274. ver);
  275. return -EIO;
  276. }
  277. str = next_string(skb);
  278. rate_up = simple_strtol(str, &end, 10);
  279. if (*end)
  280. return -EIO;
  281. str = next_string(skb);
  282. rate_down = simple_strtol(str, &end, 10);
  283. if (*end)
  284. return -EIO;
  285. state_str = next_string(skb);
  286. if (!strcmp(state_str, "Showtime"))
  287. state = ATM_PHY_SIG_FOUND;
  288. else {
  289. state = ATM_PHY_SIG_LOST;
  290. release_vccs(card->atmdev[port]);
  291. }
  292. str = next_string(skb);
  293. snr = simple_strtol(str, &end, 10);
  294. if (*end)
  295. return -EIO;
  296. str = next_string(skb);
  297. attn = simple_strtol(str, &end, 10);
  298. if (*end)
  299. return -EIO;
  300. if (state == ATM_PHY_SIG_LOST && !rate_up && !rate_down)
  301. dev_info(&card->dev->dev, "Port %d ATM state: %s\n",
  302. port, state_str);
  303. else
  304. dev_info(&card->dev->dev, "Port %d ATM state: %s (%d/%d kb/s, SNR %ddB, Attn %ddB)\n",
  305. port, state_str, rate_up/1000, rate_down/1000,
  306. snr, attn);
  307. card->atmdev[port]->link_rate = rate_down;
  308. card->atmdev[port]->signal = state;
  309. return 0;
  310. }
  311. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  312. {
  313. struct solos_param *prm;
  314. unsigned long flags;
  315. int cmdpid;
  316. int found = 0;
  317. if (skb->len < 7)
  318. return 0;
  319. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  320. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  321. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  322. skb->data[6] != '\n')
  323. return 0;
  324. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  325. spin_lock_irqsave(&card->param_queue_lock, flags);
  326. list_for_each_entry(prm, &card->param_queue, list) {
  327. if (prm->port == port && prm->pid == cmdpid) {
  328. prm->response = skb;
  329. skb_pull(skb, 7);
  330. wake_up(&card->param_wq);
  331. found = 1;
  332. break;
  333. }
  334. }
  335. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  336. return found;
  337. }
  338. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  339. char *buf)
  340. {
  341. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  342. struct solos_card *card = atmdev->dev_data;
  343. struct sk_buff *skb;
  344. spin_lock(&card->cli_queue_lock);
  345. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  346. spin_unlock(&card->cli_queue_lock);
  347. if(skb == NULL)
  348. return sprintf(buf, "No data.\n");
  349. memcpy(buf, skb->data, skb->len);
  350. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  351. kfree_skb(skb);
  352. return skb->len;
  353. }
  354. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  355. {
  356. struct sk_buff *skb;
  357. struct pkt_hdr *header;
  358. // dev_dbg(&card->dev->dev, "size: %d\n", size);
  359. if (size > (BUF_SIZE - sizeof(*header))) {
  360. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  361. return 0;
  362. }
  363. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  364. if (!skb) {
  365. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  366. return 0;
  367. }
  368. header = (void *)skb_put(skb, sizeof(*header));
  369. header->size = cpu_to_le16(size);
  370. header->vpi = cpu_to_le16(0);
  371. header->vci = cpu_to_le16(0);
  372. header->type = cpu_to_le16(PKT_COMMAND);
  373. memcpy(skb_put(skb, size), buf, size);
  374. fpga_queue(card, dev, skb, NULL);
  375. return 0;
  376. }
  377. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  378. const char *buf, size_t count)
  379. {
  380. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  381. struct solos_card *card = atmdev->dev_data;
  382. int err;
  383. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  384. return err?:count;
  385. }
  386. static DEVICE_ATTR(console, 0644, console_show, console_store);
  387. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  388. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  389. #include "solos-attrlist.c"
  390. #undef SOLOS_ATTR_RO
  391. #undef SOLOS_ATTR_RW
  392. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  393. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  394. static struct attribute *solos_attrs[] = {
  395. #include "solos-attrlist.c"
  396. NULL
  397. };
  398. static struct attribute_group solos_attr_group = {
  399. .attrs = solos_attrs,
  400. .name = "parameters",
  401. };
  402. static int flash_upgrade(struct solos_card *card, int chip)
  403. {
  404. const struct firmware *fw;
  405. const char *fw_name;
  406. uint32_t data32 = 0;
  407. int blocksize = 0;
  408. int numblocks = 0;
  409. int offset;
  410. if (chip == 0) {
  411. fw_name = "solos-FPGA.bin";
  412. blocksize = FPGA_BLOCK;
  413. } else {
  414. fw_name = "solos-Firmware.bin";
  415. blocksize = SOLOS_BLOCK;
  416. }
  417. if (request_firmware(&fw, fw_name, &card->dev->dev))
  418. return -ENOENT;
  419. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  420. numblocks = fw->size / blocksize;
  421. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  422. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  423. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  424. iowrite32(1, card->config_regs + FPGA_MODE);
  425. data32 = ioread32(card->config_regs + FPGA_MODE);
  426. /* Set mode to Chip Erase */
  427. dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
  428. chip?"Solos":"FPGA");
  429. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  430. iowrite32(1, card->config_regs + WRITE_FLASH);
  431. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  432. for (offset = 0; offset < fw->size; offset += blocksize) {
  433. int i;
  434. /* Clear write flag */
  435. iowrite32(0, card->config_regs + WRITE_FLASH);
  436. /* Set mode to Block Write */
  437. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  438. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  439. /* Copy block to buffer, swapping each 16 bits */
  440. for(i = 0; i < blocksize; i += 4) {
  441. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  442. iowrite32(word, RX_BUF(card, 3) + i);
  443. }
  444. /* Specify block number and then trigger flash write */
  445. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  446. iowrite32(1, card->config_regs + WRITE_FLASH);
  447. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  448. }
  449. release_firmware(fw);
  450. iowrite32(0, card->config_regs + WRITE_FLASH);
  451. iowrite32(0, card->config_regs + FPGA_MODE);
  452. iowrite32(0, card->config_regs + FLASH_MODE);
  453. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  454. return 0;
  455. }
  456. static irqreturn_t solos_irq(int irq, void *dev_id)
  457. {
  458. struct solos_card *card = dev_id;
  459. int handled = 1;
  460. //ACK IRQ
  461. iowrite32(0, card->config_regs + IRQ_CLEAR);
  462. //Disable IRQs from FPGA
  463. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  464. if (card->atmdev[0])
  465. tasklet_schedule(&card->tlet);
  466. else
  467. wake_up(&card->fw_wq);
  468. //Enable IRQs from FPGA
  469. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  470. return IRQ_RETVAL(handled);
  471. }
  472. void solos_bh(unsigned long card_arg)
  473. {
  474. struct solos_card *card = (void *)card_arg;
  475. int port;
  476. uint32_t card_flags;
  477. uint32_t rx_done = 0;
  478. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  479. /* The TX bits are set if the channel is busy; clear if not. We want to
  480. invoke fpga_tx() unless _all_ the bits for active channels are set */
  481. if ((card_flags & card->tx_mask) != card->tx_mask)
  482. fpga_tx(card);
  483. for (port = 0; port < card->nr_ports; port++) {
  484. if (card_flags & (0x10 << port)) {
  485. struct pkt_hdr _hdr, *header;
  486. struct sk_buff *skb;
  487. struct atm_vcc *vcc;
  488. int size;
  489. if (card->using_dma) {
  490. skb = card->rx_skb[port];
  491. card->rx_skb[port] = NULL;
  492. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  493. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  494. header = (void *)skb->data;
  495. size = le16_to_cpu(header->size);
  496. skb_put(skb, size + sizeof(*header));
  497. skb_pull(skb, sizeof(*header));
  498. } else {
  499. header = &_hdr;
  500. rx_done |= 0x10 << port;
  501. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  502. size = le16_to_cpu(header->size);
  503. skb = alloc_skb(size + 1, GFP_ATOMIC);
  504. if (!skb) {
  505. if (net_ratelimit())
  506. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  507. continue;
  508. }
  509. memcpy_fromio(skb_put(skb, size),
  510. RX_BUF(card, port) + sizeof(*header),
  511. size);
  512. }
  513. if (atmdebug) {
  514. dev_info(&card->dev->dev, "Received: device %d\n", port);
  515. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  516. size, le16_to_cpu(header->vpi),
  517. le16_to_cpu(header->vci));
  518. print_buffer(skb);
  519. }
  520. switch (le16_to_cpu(header->type)) {
  521. case PKT_DATA:
  522. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  523. le16_to_cpu(header->vci));
  524. if (!vcc) {
  525. if (net_ratelimit())
  526. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  527. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  528. port);
  529. continue;
  530. }
  531. atm_charge(vcc, skb->truesize);
  532. vcc->push(vcc, skb);
  533. atomic_inc(&vcc->stats->rx);
  534. break;
  535. case PKT_STATUS:
  536. process_status(card, port, skb);
  537. dev_kfree_skb_any(skb);
  538. break;
  539. case PKT_COMMAND:
  540. default: /* FIXME: Not really, surely? */
  541. if (process_command(card, port, skb))
  542. break;
  543. spin_lock(&card->cli_queue_lock);
  544. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  545. if (net_ratelimit())
  546. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  547. port);
  548. dev_kfree_skb_any(skb);
  549. } else
  550. skb_queue_tail(&card->cli_queue[port], skb);
  551. spin_unlock(&card->cli_queue_lock);
  552. break;
  553. }
  554. }
  555. /* Allocate RX skbs for any ports which need them */
  556. if (card->using_dma && card->atmdev[port] &&
  557. !card->rx_skb[port]) {
  558. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  559. if (skb) {
  560. SKB_CB(skb)->dma_addr =
  561. pci_map_single(card->dev, skb->data,
  562. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  563. iowrite32(SKB_CB(skb)->dma_addr,
  564. card->config_regs + RX_DMA_ADDR(port));
  565. card->rx_skb[port] = skb;
  566. } else {
  567. if (net_ratelimit())
  568. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  569. /* We'll have to try again later */
  570. tasklet_schedule(&card->tlet);
  571. }
  572. }
  573. }
  574. if (rx_done)
  575. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  576. return;
  577. }
  578. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  579. {
  580. struct hlist_head *head;
  581. struct atm_vcc *vcc = NULL;
  582. struct hlist_node *node;
  583. struct sock *s;
  584. read_lock(&vcc_sklist_lock);
  585. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  586. sk_for_each(s, node, head) {
  587. vcc = atm_sk(s);
  588. if (vcc->dev == dev && vcc->vci == vci &&
  589. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  590. goto out;
  591. }
  592. vcc = NULL;
  593. out:
  594. read_unlock(&vcc_sklist_lock);
  595. return vcc;
  596. }
  597. static int list_vccs(int vci)
  598. {
  599. struct hlist_head *head;
  600. struct atm_vcc *vcc;
  601. struct hlist_node *node;
  602. struct sock *s;
  603. int num_found = 0;
  604. int i;
  605. read_lock(&vcc_sklist_lock);
  606. if (vci != 0){
  607. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  608. sk_for_each(s, node, head) {
  609. num_found ++;
  610. vcc = atm_sk(s);
  611. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  612. vcc->dev->number,
  613. vcc->vpi,
  614. vcc->vci);
  615. }
  616. } else {
  617. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  618. head = &vcc_hash[i];
  619. sk_for_each(s, node, head) {
  620. num_found ++;
  621. vcc = atm_sk(s);
  622. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  623. vcc->dev->number,
  624. vcc->vpi,
  625. vcc->vci);
  626. }
  627. }
  628. }
  629. read_unlock(&vcc_sklist_lock);
  630. return num_found;
  631. }
  632. static void release_vccs(struct atm_dev *dev)
  633. {
  634. int i;
  635. write_lock_irq(&vcc_sklist_lock);
  636. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  637. struct hlist_head *head = &vcc_hash[i];
  638. struct hlist_node *node, *tmp;
  639. struct sock *s;
  640. struct atm_vcc *vcc;
  641. sk_for_each_safe(s, node, tmp, head) {
  642. vcc = atm_sk(s);
  643. if (vcc->dev == dev) {
  644. vcc_release_async(vcc, -EPIPE);
  645. sk_del_node_init(s);
  646. }
  647. }
  648. }
  649. write_unlock_irq(&vcc_sklist_lock);
  650. }
  651. static int popen(struct atm_vcc *vcc)
  652. {
  653. struct solos_card *card = vcc->dev->dev_data;
  654. struct sk_buff *skb;
  655. struct pkt_hdr *header;
  656. if (vcc->qos.aal != ATM_AAL5) {
  657. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  658. vcc->qos.aal);
  659. return -EINVAL;
  660. }
  661. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  662. if (!skb && net_ratelimit()) {
  663. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  664. return -ENOMEM;
  665. }
  666. header = (void *)skb_put(skb, sizeof(*header));
  667. header->size = cpu_to_le16(0);
  668. header->vpi = cpu_to_le16(vcc->vpi);
  669. header->vci = cpu_to_le16(vcc->vci);
  670. header->type = cpu_to_le16(PKT_POPEN);
  671. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  672. // dev_dbg(&card->dev->dev, "Open for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  673. set_bit(ATM_VF_ADDR, &vcc->flags); // accept the vpi / vci
  674. set_bit(ATM_VF_READY, &vcc->flags);
  675. list_vccs(0);
  676. return 0;
  677. }
  678. static void pclose(struct atm_vcc *vcc)
  679. {
  680. struct solos_card *card = vcc->dev->dev_data;
  681. struct sk_buff *skb;
  682. struct pkt_hdr *header;
  683. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  684. if (!skb) {
  685. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  686. return;
  687. }
  688. header = (void *)skb_put(skb, sizeof(*header));
  689. header->size = cpu_to_le16(0);
  690. header->vpi = cpu_to_le16(vcc->vpi);
  691. header->vci = cpu_to_le16(vcc->vci);
  692. header->type = cpu_to_le16(PKT_PCLOSE);
  693. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  694. // dev_dbg(&card->dev->dev, "Close for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  695. clear_bit(ATM_VF_ADDR, &vcc->flags);
  696. clear_bit(ATM_VF_READY, &vcc->flags);
  697. return;
  698. }
  699. static int print_buffer(struct sk_buff *buf)
  700. {
  701. int len,i;
  702. char msg[500];
  703. char item[10];
  704. len = buf->len;
  705. for (i = 0; i < len; i++){
  706. if(i % 8 == 0)
  707. sprintf(msg, "%02X: ", i);
  708. sprintf(item,"%02X ",*(buf->data + i));
  709. strcat(msg, item);
  710. if(i % 8 == 7) {
  711. sprintf(item, "\n");
  712. strcat(msg, item);
  713. printk(KERN_DEBUG "%s", msg);
  714. }
  715. }
  716. if (i % 8 != 0) {
  717. sprintf(item, "\n");
  718. strcat(msg, item);
  719. printk(KERN_DEBUG "%s", msg);
  720. }
  721. printk(KERN_DEBUG "\n");
  722. return 0;
  723. }
  724. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  725. struct atm_vcc *vcc)
  726. {
  727. int old_len;
  728. unsigned long flags;
  729. SKB_CB(skb)->vcc = vcc;
  730. spin_lock_irqsave(&card->tx_queue_lock, flags);
  731. old_len = skb_queue_len(&card->tx_queue[port]);
  732. skb_queue_tail(&card->tx_queue[port], skb);
  733. if (!old_len) {
  734. card->tx_mask |= (1 << port);
  735. }
  736. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  737. /* Theoretically we could just schedule the tasklet here, but
  738. that introduces latency we don't want -- it's noticeable */
  739. if (!old_len)
  740. fpga_tx(card);
  741. }
  742. static int fpga_tx(struct solos_card *card)
  743. {
  744. uint32_t tx_pending;
  745. uint32_t tx_started = 0;
  746. struct sk_buff *skb;
  747. struct atm_vcc *vcc;
  748. unsigned char port;
  749. unsigned long flags;
  750. spin_lock_irqsave(&card->tx_lock, flags);
  751. tx_pending = ioread32(card->config_regs + FLAGS_ADDR) & card->tx_mask;
  752. dev_vdbg(&card->dev->dev, "TX Flags are %X\n", tx_pending);
  753. for (port = 0; port < card->nr_ports; port++) {
  754. if (card->atmdev[port] && !(tx_pending & (1 << port))) {
  755. struct sk_buff *oldskb = card->tx_skb[port];
  756. if (oldskb)
  757. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  758. oldskb->len, PCI_DMA_TODEVICE);
  759. spin_lock(&card->tx_queue_lock);
  760. skb = skb_dequeue(&card->tx_queue[port]);
  761. if (!skb)
  762. card->tx_mask &= ~(1 << port);
  763. spin_unlock(&card->tx_queue_lock);
  764. if (skb && !card->using_dma) {
  765. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  766. tx_started |= 1 << port; //Set TX full flag
  767. oldskb = skb; /* We're done with this skb already */
  768. } else if (skb && card->using_dma) {
  769. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  770. skb->len, PCI_DMA_TODEVICE);
  771. iowrite32(SKB_CB(skb)->dma_addr,
  772. card->config_regs + TX_DMA_ADDR(port));
  773. }
  774. if (!oldskb)
  775. continue;
  776. /* Clean up and free oldskb now it's gone */
  777. if (atmdebug) {
  778. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  779. port);
  780. print_buffer(oldskb);
  781. }
  782. vcc = SKB_CB(oldskb)->vcc;
  783. if (vcc) {
  784. atomic_inc(&vcc->stats->tx);
  785. solos_pop(vcc, oldskb);
  786. } else
  787. dev_kfree_skb_irq(oldskb);
  788. }
  789. }
  790. if (tx_started)
  791. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  792. spin_unlock_irqrestore(&card->tx_lock, flags);
  793. return 0;
  794. }
  795. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  796. {
  797. struct solos_card *card = vcc->dev->dev_data;
  798. struct pkt_hdr *header;
  799. int pktlen;
  800. //dev_dbg(&card->dev->dev, "psend called.\n");
  801. //dev_dbg(&card->dev->dev, "dev,vpi,vci = %d,%d,%d\n",SOLOS_CHAN(vcc->dev),vcc->vpi,vcc->vci);
  802. pktlen = skb->len;
  803. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  804. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  805. solos_pop(vcc, skb);
  806. return 0;
  807. }
  808. if (!skb_clone_writable(skb, sizeof(*header))) {
  809. int expand_by = 0;
  810. int ret;
  811. if (skb_headroom(skb) < sizeof(*header))
  812. expand_by = sizeof(*header) - skb_headroom(skb);
  813. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  814. if (ret) {
  815. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  816. solos_pop(vcc, skb);
  817. return ret;
  818. }
  819. }
  820. header = (void *)skb_push(skb, sizeof(*header));
  821. /* This does _not_ include the size of the header */
  822. header->size = cpu_to_le16(pktlen);
  823. header->vpi = cpu_to_le16(vcc->vpi);
  824. header->vci = cpu_to_le16(vcc->vci);
  825. header->type = cpu_to_le16(PKT_DATA);
  826. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  827. return 0;
  828. }
  829. static struct atmdev_ops fpga_ops = {
  830. .open = popen,
  831. .close = pclose,
  832. .ioctl = NULL,
  833. .getsockopt = NULL,
  834. .setsockopt = NULL,
  835. .send = psend,
  836. .send_oam = NULL,
  837. .phy_put = NULL,
  838. .phy_get = NULL,
  839. .change_qos = NULL,
  840. .proc_read = NULL,
  841. .owner = THIS_MODULE
  842. };
  843. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  844. {
  845. int err, i;
  846. uint16_t fpga_ver;
  847. uint8_t major_ver, minor_ver;
  848. uint32_t data32;
  849. struct solos_card *card;
  850. card = kzalloc(sizeof(*card), GFP_KERNEL);
  851. if (!card)
  852. return -ENOMEM;
  853. card->dev = dev;
  854. init_waitqueue_head(&card->fw_wq);
  855. init_waitqueue_head(&card->param_wq);
  856. err = pci_enable_device(dev);
  857. if (err) {
  858. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  859. goto out;
  860. }
  861. err = pci_set_dma_mask(dev, DMA_32BIT_MASK);
  862. if (err) {
  863. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  864. goto out;
  865. }
  866. err = pci_request_regions(dev, "solos");
  867. if (err) {
  868. dev_warn(&dev->dev, "Failed to request regions\n");
  869. goto out;
  870. }
  871. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  872. if (!card->config_regs) {
  873. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  874. goto out_release_regions;
  875. }
  876. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  877. if (!card->buffers) {
  878. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  879. goto out_unmap_config;
  880. }
  881. // for(i=0;i<64 ;i+=4){
  882. // data32=ioread32(card->buffers + i);
  883. // dev_dbg(&card->dev->dev, "%08lX\n",(unsigned long)data32);
  884. // }
  885. //Fill Config Mem with zeros
  886. for(i = 0; i < 128; i += 4)
  887. iowrite32(0, card->config_regs + i);
  888. //Set RX empty flags
  889. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  890. data32 = ioread32(card->config_regs + FPGA_VER);
  891. fpga_ver = (data32 & 0x0000FFFF);
  892. major_ver = ((data32 & 0xFF000000) >> 24);
  893. minor_ver = ((data32 & 0x00FF0000) >> 16);
  894. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  895. major_ver, minor_ver, fpga_ver);
  896. if (fpga_ver > 27)
  897. card->using_dma = 1;
  898. card->nr_ports = 2; /* FIXME: Detect daughterboard */
  899. pci_set_drvdata(dev, card);
  900. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  901. spin_lock_init(&card->tx_lock);
  902. spin_lock_init(&card->tx_queue_lock);
  903. spin_lock_init(&card->cli_queue_lock);
  904. spin_lock_init(&card->param_queue_lock);
  905. INIT_LIST_HEAD(&card->param_queue);
  906. /*
  907. // Set Loopback mode
  908. data32 = 0x00010000;
  909. iowrite32(data32,card->config_regs + FLAGS_ADDR);
  910. */
  911. /*
  912. // Fill Buffers with zeros
  913. for (i = 0; i < BUF_SIZE * 8; i += 4)
  914. iowrite32(0, card->buffers + i);
  915. */
  916. /*
  917. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  918. iowrite32(0x12345678, card->buffers + i + (0*BUF_SIZE));
  919. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  920. iowrite32(0xabcdef98, card->buffers + i + (1*BUF_SIZE));
  921. // Read Config Memory
  922. printk(KERN_DEBUG "Reading Config MEM\n");
  923. i = 0;
  924. for(i = 0; i < 16; i++) {
  925. data32=ioread32(card->buffers + i*(BUF_SIZE/2));
  926. printk(KERN_ALERT "Addr: %lX Data: %08lX\n",
  927. (unsigned long)(addr_start + i*(BUF_SIZE/2)),
  928. (unsigned long)data32);
  929. }
  930. */
  931. //dev_dbg(&card->dev->dev, "Requesting IRQ: %d\n",dev->irq);
  932. err = request_irq(dev->irq, solos_irq, IRQF_DISABLED|IRQF_SHARED,
  933. "solos-pci", card);
  934. if (err) {
  935. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  936. goto out_unmap_both;
  937. }
  938. // Enable IRQs
  939. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  940. if (fpga_upgrade)
  941. flash_upgrade(card, 0);
  942. if (firmware_upgrade)
  943. flash_upgrade(card, 1);
  944. err = atm_init(card);
  945. if (err)
  946. goto out_free_irq;
  947. return 0;
  948. out_free_irq:
  949. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  950. free_irq(dev->irq, card);
  951. tasklet_kill(&card->tlet);
  952. out_unmap_both:
  953. pci_set_drvdata(dev, NULL);
  954. pci_iounmap(dev, card->config_regs);
  955. out_unmap_config:
  956. pci_iounmap(dev, card->buffers);
  957. out_release_regions:
  958. pci_release_regions(dev);
  959. out:
  960. return err;
  961. }
  962. static int atm_init(struct solos_card *card)
  963. {
  964. int i;
  965. for (i = 0; i < card->nr_ports; i++) {
  966. struct sk_buff *skb;
  967. struct pkt_hdr *header;
  968. skb_queue_head_init(&card->tx_queue[i]);
  969. skb_queue_head_init(&card->cli_queue[i]);
  970. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  971. if (!card->atmdev[i]) {
  972. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  973. atm_remove(card);
  974. return -ENODEV;
  975. }
  976. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  977. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  978. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  979. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  980. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  981. card->atmdev[i]->ci_range.vpi_bits = 8;
  982. card->atmdev[i]->ci_range.vci_bits = 16;
  983. card->atmdev[i]->dev_data = card;
  984. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  985. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  986. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  987. if (!skb) {
  988. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  989. continue;
  990. }
  991. header = (void *)skb_put(skb, sizeof(*header));
  992. header->size = cpu_to_le16(0);
  993. header->vpi = cpu_to_le16(0);
  994. header->vci = cpu_to_le16(0);
  995. header->type = cpu_to_le16(PKT_STATUS);
  996. fpga_queue(card, i, skb, NULL);
  997. }
  998. return 0;
  999. }
  1000. static void atm_remove(struct solos_card *card)
  1001. {
  1002. int i;
  1003. for (i = 0; i < card->nr_ports; i++) {
  1004. if (card->atmdev[i]) {
  1005. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1006. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1007. atm_dev_deregister(card->atmdev[i]);
  1008. }
  1009. }
  1010. }
  1011. static void fpga_remove(struct pci_dev *dev)
  1012. {
  1013. struct solos_card *card = pci_get_drvdata(dev);
  1014. atm_remove(card);
  1015. dev_vdbg(&dev->dev, "Freeing IRQ\n");
  1016. // Disable IRQs from FPGA
  1017. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1018. free_irq(dev->irq, card);
  1019. tasklet_kill(&card->tlet);
  1020. // iowrite32(0x01,pciregs);
  1021. dev_vdbg(&dev->dev, "Unmapping PCI resource\n");
  1022. pci_iounmap(dev, card->buffers);
  1023. pci_iounmap(dev, card->config_regs);
  1024. dev_vdbg(&dev->dev, "Releasing PCI Region\n");
  1025. pci_release_regions(dev);
  1026. pci_disable_device(dev);
  1027. pci_set_drvdata(dev, NULL);
  1028. kfree(card);
  1029. // dev_dbg(&card->dev->dev, "fpga_remove\n");
  1030. return;
  1031. }
  1032. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1033. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1034. { 0, }
  1035. };
  1036. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1037. static struct pci_driver fpga_driver = {
  1038. .name = "solos",
  1039. .id_table = fpga_pci_tbl,
  1040. .probe = fpga_probe,
  1041. .remove = fpga_remove,
  1042. };
  1043. static int __init solos_pci_init(void)
  1044. {
  1045. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1046. return pci_register_driver(&fpga_driver);
  1047. }
  1048. static void __exit solos_pci_exit(void)
  1049. {
  1050. pci_unregister_driver(&fpga_driver);
  1051. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1052. }
  1053. module_init(solos_pci_init);
  1054. module_exit(solos_pci_exit);