regmap-mmio.c 6.2 KB

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  1. /*
  2. * Register map access API - MMIO support
  3. *
  4. * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/init.h>
  21. #include <linux/io.h>
  22. #include <linux/module.h>
  23. #include <linux/regmap.h>
  24. #include <linux/slab.h>
  25. struct regmap_mmio_context {
  26. void __iomem *regs;
  27. unsigned val_bytes;
  28. struct clk *clk;
  29. };
  30. static int regmap_mmio_gather_write(void *context,
  31. const void *reg, size_t reg_size,
  32. const void *val, size_t val_size)
  33. {
  34. struct regmap_mmio_context *ctx = context;
  35. u32 offset;
  36. int ret;
  37. BUG_ON(reg_size != 4);
  38. if (!IS_ERR(ctx->clk)) {
  39. ret = clk_enable(ctx->clk);
  40. if (ret < 0)
  41. return ret;
  42. }
  43. offset = *(u32 *)reg;
  44. while (val_size) {
  45. switch (ctx->val_bytes) {
  46. case 1:
  47. writeb(*(u8 *)val, ctx->regs + offset);
  48. break;
  49. case 2:
  50. writew(*(u16 *)val, ctx->regs + offset);
  51. break;
  52. case 4:
  53. writel(*(u32 *)val, ctx->regs + offset);
  54. break;
  55. #ifdef CONFIG_64BIT
  56. case 8:
  57. writeq(*(u64 *)val, ctx->regs + offset);
  58. break;
  59. #endif
  60. default:
  61. /* Should be caught by regmap_mmio_check_config */
  62. BUG();
  63. }
  64. val_size -= ctx->val_bytes;
  65. val += ctx->val_bytes;
  66. offset += ctx->val_bytes;
  67. }
  68. if (!IS_ERR(ctx->clk))
  69. clk_disable(ctx->clk);
  70. return 0;
  71. }
  72. static int regmap_mmio_write(void *context, const void *data, size_t count)
  73. {
  74. BUG_ON(count < 4);
  75. return regmap_mmio_gather_write(context, data, 4, data + 4, count - 4);
  76. }
  77. static int regmap_mmio_read(void *context,
  78. const void *reg, size_t reg_size,
  79. void *val, size_t val_size)
  80. {
  81. struct regmap_mmio_context *ctx = context;
  82. u32 offset;
  83. int ret;
  84. BUG_ON(reg_size != 4);
  85. if (!IS_ERR(ctx->clk)) {
  86. ret = clk_enable(ctx->clk);
  87. if (ret < 0)
  88. return ret;
  89. }
  90. offset = *(u32 *)reg;
  91. while (val_size) {
  92. switch (ctx->val_bytes) {
  93. case 1:
  94. *(u8 *)val = readb(ctx->regs + offset);
  95. break;
  96. case 2:
  97. *(u16 *)val = readw(ctx->regs + offset);
  98. break;
  99. case 4:
  100. *(u32 *)val = readl(ctx->regs + offset);
  101. break;
  102. #ifdef CONFIG_64BIT
  103. case 8:
  104. *(u64 *)val = readq(ctx->regs + offset);
  105. break;
  106. #endif
  107. default:
  108. /* Should be caught by regmap_mmio_check_config */
  109. BUG();
  110. }
  111. val_size -= ctx->val_bytes;
  112. val += ctx->val_bytes;
  113. offset += ctx->val_bytes;
  114. }
  115. if (!IS_ERR(ctx->clk))
  116. clk_disable(ctx->clk);
  117. return 0;
  118. }
  119. static void regmap_mmio_free_context(void *context)
  120. {
  121. struct regmap_mmio_context *ctx = context;
  122. if (!IS_ERR(ctx->clk)) {
  123. clk_unprepare(ctx->clk);
  124. clk_put(ctx->clk);
  125. }
  126. kfree(context);
  127. }
  128. static struct regmap_bus regmap_mmio = {
  129. .fast_io = true,
  130. .write = regmap_mmio_write,
  131. .gather_write = regmap_mmio_gather_write,
  132. .read = regmap_mmio_read,
  133. .free_context = regmap_mmio_free_context,
  134. .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
  135. .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
  136. };
  137. static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
  138. const char *clk_id,
  139. void __iomem *regs,
  140. const struct regmap_config *config)
  141. {
  142. struct regmap_mmio_context *ctx;
  143. int min_stride;
  144. int ret;
  145. if (config->reg_bits != 32)
  146. return ERR_PTR(-EINVAL);
  147. if (config->pad_bits)
  148. return ERR_PTR(-EINVAL);
  149. switch (config->val_bits) {
  150. case 8:
  151. /* The core treats 0 as 1 */
  152. min_stride = 0;
  153. break;
  154. case 16:
  155. min_stride = 2;
  156. break;
  157. case 32:
  158. min_stride = 4;
  159. break;
  160. #ifdef CONFIG_64BIT
  161. case 64:
  162. min_stride = 8;
  163. break;
  164. #endif
  165. break;
  166. default:
  167. return ERR_PTR(-EINVAL);
  168. }
  169. if (config->reg_stride < min_stride)
  170. return ERR_PTR(-EINVAL);
  171. switch (config->reg_format_endian) {
  172. case REGMAP_ENDIAN_DEFAULT:
  173. case REGMAP_ENDIAN_NATIVE:
  174. break;
  175. default:
  176. return ERR_PTR(-EINVAL);
  177. }
  178. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  179. if (!ctx)
  180. return ERR_PTR(-ENOMEM);
  181. ctx->regs = regs;
  182. ctx->val_bytes = config->val_bits / 8;
  183. ctx->clk = ERR_PTR(-ENODEV);
  184. if (clk_id == NULL)
  185. return ctx;
  186. ctx->clk = clk_get(dev, clk_id);
  187. if (IS_ERR(ctx->clk)) {
  188. ret = PTR_ERR(ctx->clk);
  189. goto err_free;
  190. }
  191. ret = clk_prepare(ctx->clk);
  192. if (ret < 0) {
  193. clk_put(ctx->clk);
  194. goto err_free;
  195. }
  196. return ctx;
  197. err_free:
  198. kfree(ctx);
  199. return ERR_PTR(ret);
  200. }
  201. /**
  202. * regmap_init_mmio_clk(): Initialise register map with register clock
  203. *
  204. * @dev: Device that will be interacted with
  205. * @clk_id: register clock consumer ID
  206. * @regs: Pointer to memory-mapped IO region
  207. * @config: Configuration for register map
  208. *
  209. * The return value will be an ERR_PTR() on error or a valid pointer to
  210. * a struct regmap.
  211. */
  212. struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id,
  213. void __iomem *regs,
  214. const struct regmap_config *config)
  215. {
  216. struct regmap_mmio_context *ctx;
  217. ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
  218. if (IS_ERR(ctx))
  219. return ERR_CAST(ctx);
  220. return regmap_init(dev, &regmap_mmio, ctx, config);
  221. }
  222. EXPORT_SYMBOL_GPL(regmap_init_mmio_clk);
  223. /**
  224. * devm_regmap_init_mmio_clk(): Initialise managed register map with clock
  225. *
  226. * @dev: Device that will be interacted with
  227. * @clk_id: register clock consumer ID
  228. * @regs: Pointer to memory-mapped IO region
  229. * @config: Configuration for register map
  230. *
  231. * The return value will be an ERR_PTR() on error or a valid pointer
  232. * to a struct regmap. The regmap will be automatically freed by the
  233. * device management code.
  234. */
  235. struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id,
  236. void __iomem *regs,
  237. const struct regmap_config *config)
  238. {
  239. struct regmap_mmio_context *ctx;
  240. ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
  241. if (IS_ERR(ctx))
  242. return ERR_CAST(ctx);
  243. return devm_regmap_init(dev, &regmap_mmio, ctx, config);
  244. }
  245. EXPORT_SYMBOL_GPL(devm_regmap_init_mmio_clk);
  246. MODULE_LICENSE("GPL v2");