perf_event.c 8.3 KB

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  1. /*
  2. * Linux performance counter support for ARC700 series
  3. *
  4. * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * This code is inspired by the perf support of various other architectures.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/errno.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/perf_event.h>
  17. #include <linux/platform_device.h>
  18. #include <asm/arcregs.h>
  19. struct arc_pmu {
  20. struct pmu pmu;
  21. int counter_size; /* in bits */
  22. int n_counters;
  23. unsigned long used_mask[BITS_TO_LONGS(ARC_PMU_MAX_HWEVENTS)];
  24. int ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
  25. };
  26. /* read counter #idx; note that counter# != event# on ARC! */
  27. static uint64_t arc_pmu_read_counter(int idx)
  28. {
  29. uint32_t tmp;
  30. uint64_t result;
  31. /*
  32. * ARC supports making 'snapshots' of the counters, so we don't
  33. * need to care about counters wrapping to 0 underneath our feet
  34. */
  35. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  36. tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
  37. write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
  38. result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
  39. result |= read_aux_reg(ARC_REG_PCT_SNAPL);
  40. return result;
  41. }
  42. static void arc_perf_event_update(struct perf_event *event,
  43. struct hw_perf_event *hwc, int idx)
  44. {
  45. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  46. uint64_t prev_raw_count, new_raw_count;
  47. int64_t delta;
  48. do {
  49. prev_raw_count = local64_read(&hwc->prev_count);
  50. new_raw_count = arc_pmu_read_counter(idx);
  51. } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  52. new_raw_count) != prev_raw_count);
  53. delta = (new_raw_count - prev_raw_count) &
  54. ((1ULL << arc_pmu->counter_size) - 1ULL);
  55. local64_add(delta, &event->count);
  56. local64_sub(delta, &hwc->period_left);
  57. }
  58. static void arc_pmu_read(struct perf_event *event)
  59. {
  60. arc_perf_event_update(event, &event->hw, event->hw.idx);
  61. }
  62. static int arc_pmu_cache_event(u64 config)
  63. {
  64. unsigned int cache_type, cache_op, cache_result;
  65. int ret;
  66. cache_type = (config >> 0) & 0xff;
  67. cache_op = (config >> 8) & 0xff;
  68. cache_result = (config >> 16) & 0xff;
  69. if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  70. return -EINVAL;
  71. if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  72. return -EINVAL;
  73. if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  74. return -EINVAL;
  75. ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
  76. if (ret == CACHE_OP_UNSUPPORTED)
  77. return -ENOENT;
  78. return ret;
  79. }
  80. /* initializes hw_perf_event structure if event is supported */
  81. static int arc_pmu_event_init(struct perf_event *event)
  82. {
  83. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  84. struct hw_perf_event *hwc = &event->hw;
  85. int ret;
  86. /* ARC 700 PMU does not support sampling events */
  87. if (is_sampling_event(event))
  88. return -ENOENT;
  89. switch (event->attr.type) {
  90. case PERF_TYPE_HARDWARE:
  91. if (event->attr.config >= PERF_COUNT_HW_MAX)
  92. return -ENOENT;
  93. if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
  94. return -ENOENT;
  95. hwc->config = arc_pmu->ev_hw_idx[event->attr.config];
  96. pr_debug("initializing event %d with cfg %d\n",
  97. (int) event->attr.config, (int) hwc->config);
  98. return 0;
  99. case PERF_TYPE_HW_CACHE:
  100. ret = arc_pmu_cache_event(event->attr.config);
  101. if (ret < 0)
  102. return ret;
  103. hwc->config = arc_pmu->ev_hw_idx[ret];
  104. return 0;
  105. default:
  106. return -ENOENT;
  107. }
  108. }
  109. /* starts all counters */
  110. static void arc_pmu_enable(struct pmu *pmu)
  111. {
  112. uint32_t tmp;
  113. tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
  114. write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
  115. }
  116. /* stops all counters */
  117. static void arc_pmu_disable(struct pmu *pmu)
  118. {
  119. uint32_t tmp;
  120. tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
  121. write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
  122. }
  123. /*
  124. * Assigns hardware counter to hardware condition.
  125. * Note that there is no separate start/stop mechanism;
  126. * stopping is achieved by assigning the 'never' condition
  127. */
  128. static void arc_pmu_start(struct perf_event *event, int flags)
  129. {
  130. struct hw_perf_event *hwc = &event->hw;
  131. int idx = hwc->idx;
  132. if (WARN_ON_ONCE(idx == -1))
  133. return;
  134. if (flags & PERF_EF_RELOAD)
  135. WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
  136. event->hw.state = 0;
  137. /* enable ARC pmu here */
  138. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  139. write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);
  140. }
  141. static void arc_pmu_stop(struct perf_event *event, int flags)
  142. {
  143. struct hw_perf_event *hwc = &event->hw;
  144. int idx = hwc->idx;
  145. if (!(event->hw.state & PERF_HES_STOPPED)) {
  146. /* stop ARC pmu here */
  147. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  148. /* condition code #0 is always "never" */
  149. write_aux_reg(ARC_REG_PCT_CONFIG, 0);
  150. event->hw.state |= PERF_HES_STOPPED;
  151. }
  152. if ((flags & PERF_EF_UPDATE) &&
  153. !(event->hw.state & PERF_HES_UPTODATE)) {
  154. arc_perf_event_update(event, &event->hw, idx);
  155. event->hw.state |= PERF_HES_UPTODATE;
  156. }
  157. }
  158. static void arc_pmu_del(struct perf_event *event, int flags)
  159. {
  160. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  161. arc_pmu_stop(event, PERF_EF_UPDATE);
  162. __clear_bit(event->hw.idx, arc_pmu->used_mask);
  163. perf_event_update_userpage(event);
  164. }
  165. /* allocate hardware counter and optionally start counting */
  166. static int arc_pmu_add(struct perf_event *event, int flags)
  167. {
  168. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  169. struct hw_perf_event *hwc = &event->hw;
  170. int idx = hwc->idx;
  171. if (__test_and_set_bit(idx, arc_pmu->used_mask)) {
  172. idx = find_first_zero_bit(arc_pmu->used_mask,
  173. arc_pmu->n_counters);
  174. if (idx == arc_pmu->n_counters)
  175. return -EAGAIN;
  176. __set_bit(idx, arc_pmu->used_mask);
  177. hwc->idx = idx;
  178. }
  179. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  180. write_aux_reg(ARC_REG_PCT_CONFIG, 0);
  181. write_aux_reg(ARC_REG_PCT_COUNTL, 0);
  182. write_aux_reg(ARC_REG_PCT_COUNTH, 0);
  183. local64_set(&hwc->prev_count, 0);
  184. hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  185. if (flags & PERF_EF_START)
  186. arc_pmu_start(event, PERF_EF_RELOAD);
  187. perf_event_update_userpage(event);
  188. return 0;
  189. }
  190. static int arc_pmu_device_probe(struct platform_device *pdev)
  191. {
  192. struct arc_pmu *arc_pmu;
  193. struct arc_reg_pct_build pct_bcr;
  194. struct arc_reg_cc_build cc_bcr;
  195. int i, j, ret;
  196. union cc_name {
  197. struct {
  198. uint32_t word0, word1;
  199. char sentinel;
  200. } indiv;
  201. char str[9];
  202. } cc_name;
  203. READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
  204. if (!pct_bcr.v) {
  205. pr_err("This core does not have performance counters!\n");
  206. return -ENODEV;
  207. }
  208. arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu),
  209. GFP_KERNEL);
  210. if (!arc_pmu)
  211. return -ENOMEM;
  212. arc_pmu->n_counters = pct_bcr.c;
  213. BUG_ON(arc_pmu->n_counters > ARC_PMU_MAX_HWEVENTS);
  214. arc_pmu->counter_size = 32 + (pct_bcr.s << 4);
  215. pr_info("ARC PMU found with %d counters of size %d bits\n",
  216. arc_pmu->n_counters, arc_pmu->counter_size);
  217. READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
  218. if (!cc_bcr.v)
  219. pr_err("Strange! Performance counters exist, but no countable conditions?\n");
  220. pr_info("ARC PMU has %d countable conditions\n", cc_bcr.c);
  221. cc_name.str[8] = 0;
  222. for (i = 0; i < PERF_COUNT_HW_MAX; i++)
  223. arc_pmu->ev_hw_idx[i] = -1;
  224. for (j = 0; j < cc_bcr.c; j++) {
  225. write_aux_reg(ARC_REG_CC_INDEX, j);
  226. cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
  227. cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
  228. for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
  229. if (arc_pmu_ev_hw_map[i] &&
  230. !strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
  231. strlen(arc_pmu_ev_hw_map[i])) {
  232. pr_debug("mapping %d to idx %d with name %s\n",
  233. i, j, cc_name.str);
  234. arc_pmu->ev_hw_idx[i] = j;
  235. }
  236. }
  237. }
  238. arc_pmu->pmu = (struct pmu) {
  239. .pmu_enable = arc_pmu_enable,
  240. .pmu_disable = arc_pmu_disable,
  241. .event_init = arc_pmu_event_init,
  242. .add = arc_pmu_add,
  243. .del = arc_pmu_del,
  244. .start = arc_pmu_start,
  245. .stop = arc_pmu_stop,
  246. .read = arc_pmu_read,
  247. };
  248. ret = perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW);
  249. return ret;
  250. }
  251. #ifdef CONFIG_OF
  252. static const struct of_device_id arc_pmu_match[] = {
  253. { .compatible = "snps,arc700-pmu" },
  254. {},
  255. };
  256. MODULE_DEVICE_TABLE(of, arc_pmu_match);
  257. #endif
  258. static struct platform_driver arc_pmu_driver = {
  259. .driver = {
  260. .name = "arc700-pmu",
  261. .of_match_table = of_match_ptr(arc_pmu_match),
  262. },
  263. .probe = arc_pmu_device_probe,
  264. };
  265. module_platform_driver(arc_pmu_driver);
  266. MODULE_LICENSE("GPL");
  267. MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
  268. MODULE_DESCRIPTION("ARC PMU driver");