setup-r8a7778.c 4.3 KB

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  1. /*
  2. * r8a7778 processor support
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/io.h>
  22. #include <linux/irqchip/arm-gic.h>
  23. #include <linux/of.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/irqchip.h>
  27. #include <linux/sh_timer.h>
  28. #include <mach/irqs.h>
  29. #include <mach/r8a7778.h>
  30. #include <mach/common.h>
  31. #include <asm/mach/arch.h>
  32. #include <asm/hardware/cache-l2x0.h>
  33. /* TMU */
  34. static struct resource sh_tmu0_resources[] = {
  35. DEFINE_RES_MEM(0xffd80008, 12),
  36. DEFINE_RES_IRQ(gic_iid(0x40)),
  37. };
  38. static struct sh_timer_config sh_tmu0_platform_data = {
  39. .name = "TMU00",
  40. .channel_offset = 0x4,
  41. .timer_bit = 0,
  42. .clockevent_rating = 200,
  43. };
  44. static struct resource sh_tmu1_resources[] = {
  45. DEFINE_RES_MEM(0xffd80014, 12),
  46. DEFINE_RES_IRQ(gic_iid(0x41)),
  47. };
  48. static struct sh_timer_config sh_tmu1_platform_data = {
  49. .name = "TMU01",
  50. .channel_offset = 0x10,
  51. .timer_bit = 1,
  52. .clocksource_rating = 200,
  53. };
  54. #define PLATFORM_INFO(n, i) \
  55. { \
  56. .parent = &platform_bus, \
  57. .name = #n, \
  58. .id = i, \
  59. .res = n ## i ## _resources, \
  60. .num_res = ARRAY_SIZE(n ## i ##_resources), \
  61. .data = &n ## i ##_platform_data, \
  62. .size_data = sizeof(n ## i ## _platform_data), \
  63. }
  64. struct platform_device_info platform_devinfo[] = {
  65. PLATFORM_INFO(sh_tmu, 0),
  66. PLATFORM_INFO(sh_tmu, 1),
  67. };
  68. void __init r8a7778_add_standard_devices(void)
  69. {
  70. int i;
  71. #ifdef CONFIG_CACHE_L2X0
  72. void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
  73. if (base) {
  74. /*
  75. * Early BRESP enable, Shared attribute override enable, 64K*16way
  76. * don't call iounmap(base)
  77. */
  78. l2x0_init(base, 0x40470000, 0x82000fff);
  79. }
  80. #endif
  81. for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
  82. platform_device_register_full(&platform_devinfo[i]);
  83. }
  84. #define INT2SMSKCR0 0x82288 /* 0xfe782288 */
  85. #define INT2SMSKCR1 0x8228c /* 0xfe78228c */
  86. #define INT2NTSR0 0x00018 /* 0xfe700018 */
  87. #define INT2NTSR1 0x0002c /* 0xfe70002c */
  88. static void __init r8a7778_init_irq_common(void)
  89. {
  90. void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
  91. BUG_ON(!base);
  92. /* route all interrupts to ARM */
  93. __raw_writel(0x73ffffff, base + INT2NTSR0);
  94. __raw_writel(0xffffffff, base + INT2NTSR1);
  95. /* unmask all known interrupts in INTCS2 */
  96. __raw_writel(0x08330773, base + INT2SMSKCR0);
  97. __raw_writel(0x00311110, base + INT2SMSKCR1);
  98. iounmap(base);
  99. }
  100. void __init r8a7778_init_irq(void)
  101. {
  102. void __iomem *gic_dist_base;
  103. void __iomem *gic_cpu_base;
  104. gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
  105. gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
  106. BUG_ON(!gic_dist_base || !gic_cpu_base);
  107. /* use GIC to handle interrupts */
  108. gic_init(0, 29, gic_dist_base, gic_cpu_base);
  109. r8a7778_init_irq_common();
  110. }
  111. void __init r8a7778_init_delay(void)
  112. {
  113. shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
  114. }
  115. #ifdef CONFIG_USE_OF
  116. void __init r8a7778_init_irq_dt(void)
  117. {
  118. irqchip_init();
  119. r8a7778_init_irq_common();
  120. }
  121. static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
  122. {},
  123. };
  124. void __init r8a7778_add_standard_devices_dt(void)
  125. {
  126. of_platform_populate(NULL, of_default_bus_match_table,
  127. r8a7778_auxdata_lookup, NULL);
  128. }
  129. static const char *r8a7778_compat_dt[] __initdata = {
  130. "renesas,r8a7778",
  131. NULL,
  132. };
  133. DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
  134. .init_early = r8a7778_init_delay,
  135. .init_irq = r8a7778_init_irq_dt,
  136. .init_machine = r8a7778_add_standard_devices_dt,
  137. .init_time = shmobile_timer_init,
  138. .dt_compat = r8a7778_compat_dt,
  139. MACHINE_END
  140. #endif /* CONFIG_USE_OF */