qeth_core_main.c 129 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_TRACE] = {"qeth_trace",
  33. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_MSG] = {"qeth_msg",
  35. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  36. [QETH_DBF_SENSE] = {"qeth_sense",
  37. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_MISC] = {"qeth_misc",
  39. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_CTRL] = {"qeth_control",
  41. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  42. };
  43. EXPORT_SYMBOL_GPL(qeth_dbf);
  44. struct qeth_card_list_struct qeth_core_card_list;
  45. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  46. struct kmem_cache *qeth_core_header_cache;
  47. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  48. static struct device *qeth_core_root_dev;
  49. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  50. static struct lock_class_key qdio_out_skb_queue_key;
  51. static void qeth_send_control_data_cb(struct qeth_channel *,
  52. struct qeth_cmd_buffer *);
  53. static int qeth_issue_next_read(struct qeth_card *);
  54. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  55. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  56. static void qeth_free_buffer_pool(struct qeth_card *);
  57. static int qeth_qdio_establish(struct qeth_card *);
  58. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  59. struct qdio_buffer *buffer, int is_tso,
  60. int *next_element_to_fill)
  61. {
  62. struct skb_frag_struct *frag;
  63. int fragno;
  64. unsigned long addr;
  65. int element, cnt, dlen;
  66. fragno = skb_shinfo(skb)->nr_frags;
  67. element = *next_element_to_fill;
  68. dlen = 0;
  69. if (is_tso)
  70. buffer->element[element].flags =
  71. SBAL_FLAGS_MIDDLE_FRAG;
  72. else
  73. buffer->element[element].flags =
  74. SBAL_FLAGS_FIRST_FRAG;
  75. dlen = skb->len - skb->data_len;
  76. if (dlen) {
  77. buffer->element[element].addr = skb->data;
  78. buffer->element[element].length = dlen;
  79. element++;
  80. }
  81. for (cnt = 0; cnt < fragno; cnt++) {
  82. frag = &skb_shinfo(skb)->frags[cnt];
  83. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  84. frag->page_offset;
  85. buffer->element[element].addr = (char *)addr;
  86. buffer->element[element].length = frag->size;
  87. if (cnt < (fragno - 1))
  88. buffer->element[element].flags =
  89. SBAL_FLAGS_MIDDLE_FRAG;
  90. else
  91. buffer->element[element].flags =
  92. SBAL_FLAGS_LAST_FRAG;
  93. element++;
  94. }
  95. *next_element_to_fill = element;
  96. }
  97. static inline const char *qeth_get_cardname(struct qeth_card *card)
  98. {
  99. if (card->info.guestlan) {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSAE:
  102. return " Guest LAN QDIO";
  103. case QETH_CARD_TYPE_IQD:
  104. return " Guest LAN Hiper";
  105. default:
  106. return " unknown";
  107. }
  108. } else {
  109. switch (card->info.type) {
  110. case QETH_CARD_TYPE_OSAE:
  111. return " OSD Express";
  112. case QETH_CARD_TYPE_IQD:
  113. return " HiperSockets";
  114. case QETH_CARD_TYPE_OSN:
  115. return " OSN QDIO";
  116. default:
  117. return " unknown";
  118. }
  119. }
  120. return " n/a";
  121. }
  122. /* max length to be returned: 14 */
  123. const char *qeth_get_cardname_short(struct qeth_card *card)
  124. {
  125. if (card->info.guestlan) {
  126. switch (card->info.type) {
  127. case QETH_CARD_TYPE_OSAE:
  128. return "GuestLAN QDIO";
  129. case QETH_CARD_TYPE_IQD:
  130. return "GuestLAN Hiper";
  131. default:
  132. return "unknown";
  133. }
  134. } else {
  135. switch (card->info.type) {
  136. case QETH_CARD_TYPE_OSAE:
  137. switch (card->info.link_type) {
  138. case QETH_LINK_TYPE_FAST_ETH:
  139. return "OSD_100";
  140. case QETH_LINK_TYPE_HSTR:
  141. return "HSTR";
  142. case QETH_LINK_TYPE_GBIT_ETH:
  143. return "OSD_1000";
  144. case QETH_LINK_TYPE_10GBIT_ETH:
  145. return "OSD_10GIG";
  146. case QETH_LINK_TYPE_LANE_ETH100:
  147. return "OSD_FE_LANE";
  148. case QETH_LINK_TYPE_LANE_TR:
  149. return "OSD_TR_LANE";
  150. case QETH_LINK_TYPE_LANE_ETH1000:
  151. return "OSD_GbE_LANE";
  152. case QETH_LINK_TYPE_LANE:
  153. return "OSD_ATM_LANE";
  154. default:
  155. return "OSD_Express";
  156. }
  157. case QETH_CARD_TYPE_IQD:
  158. return "HiperSockets";
  159. case QETH_CARD_TYPE_OSN:
  160. return "OSN";
  161. default:
  162. return "unknown";
  163. }
  164. }
  165. return "n/a";
  166. }
  167. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  168. int clear_start_mask)
  169. {
  170. unsigned long flags;
  171. spin_lock_irqsave(&card->thread_mask_lock, flags);
  172. card->thread_allowed_mask = threads;
  173. if (clear_start_mask)
  174. card->thread_start_mask &= threads;
  175. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  176. wake_up(&card->wait_q);
  177. }
  178. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  179. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  180. {
  181. unsigned long flags;
  182. int rc = 0;
  183. spin_lock_irqsave(&card->thread_mask_lock, flags);
  184. rc = (card->thread_running_mask & threads);
  185. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  186. return rc;
  187. }
  188. EXPORT_SYMBOL_GPL(qeth_threads_running);
  189. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  190. {
  191. return wait_event_interruptible(card->wait_q,
  192. qeth_threads_running(card, threads) == 0);
  193. }
  194. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  195. void qeth_clear_working_pool_list(struct qeth_card *card)
  196. {
  197. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  198. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  199. list_for_each_entry_safe(pool_entry, tmp,
  200. &card->qdio.in_buf_pool.entry_list, list){
  201. list_del(&pool_entry->list);
  202. }
  203. }
  204. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  205. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  206. {
  207. struct qeth_buffer_pool_entry *pool_entry;
  208. void *ptr;
  209. int i, j;
  210. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  211. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  212. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  213. if (!pool_entry) {
  214. qeth_free_buffer_pool(card);
  215. return -ENOMEM;
  216. }
  217. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  218. ptr = (void *) __get_free_page(GFP_KERNEL);
  219. if (!ptr) {
  220. while (j > 0)
  221. free_page((unsigned long)
  222. pool_entry->elements[--j]);
  223. kfree(pool_entry);
  224. qeth_free_buffer_pool(card);
  225. return -ENOMEM;
  226. }
  227. pool_entry->elements[j] = ptr;
  228. }
  229. list_add(&pool_entry->init_list,
  230. &card->qdio.init_pool.entry_list);
  231. }
  232. return 0;
  233. }
  234. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  235. {
  236. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  237. if ((card->state != CARD_STATE_DOWN) &&
  238. (card->state != CARD_STATE_RECOVER))
  239. return -EPERM;
  240. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  241. qeth_clear_working_pool_list(card);
  242. qeth_free_buffer_pool(card);
  243. card->qdio.in_buf_pool.buf_count = bufcnt;
  244. card->qdio.init_pool.buf_count = bufcnt;
  245. return qeth_alloc_buffer_pool(card);
  246. }
  247. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  248. static int qeth_issue_next_read(struct qeth_card *card)
  249. {
  250. int rc;
  251. struct qeth_cmd_buffer *iob;
  252. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  253. if (card->read.state != CH_STATE_UP)
  254. return -EIO;
  255. iob = qeth_get_buffer(&card->read);
  256. if (!iob) {
  257. dev_warn(&card->gdev->dev, "The qeth device driver "
  258. "failed to recover an error on the device\n");
  259. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  260. "available\n", dev_name(&card->gdev->dev));
  261. return -ENOMEM;
  262. }
  263. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  264. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  265. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  266. (addr_t) iob, 0, 0);
  267. if (rc) {
  268. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  269. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  270. atomic_set(&card->read.irq_pending, 0);
  271. qeth_schedule_recovery(card);
  272. wake_up(&card->wait_q);
  273. }
  274. return rc;
  275. }
  276. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  277. {
  278. struct qeth_reply *reply;
  279. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  280. if (reply) {
  281. atomic_set(&reply->refcnt, 1);
  282. atomic_set(&reply->received, 0);
  283. reply->card = card;
  284. };
  285. return reply;
  286. }
  287. static void qeth_get_reply(struct qeth_reply *reply)
  288. {
  289. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  290. atomic_inc(&reply->refcnt);
  291. }
  292. static void qeth_put_reply(struct qeth_reply *reply)
  293. {
  294. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  295. if (atomic_dec_and_test(&reply->refcnt))
  296. kfree(reply);
  297. }
  298. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  299. struct qeth_card *card)
  300. {
  301. char *ipa_name;
  302. int com = cmd->hdr.command;
  303. ipa_name = qeth_get_ipa_cmd_name(com);
  304. if (rc)
  305. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  306. ipa_name, com, QETH_CARD_IFNAME(card),
  307. rc, qeth_get_ipa_msg(rc));
  308. else
  309. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  310. ipa_name, com, QETH_CARD_IFNAME(card));
  311. }
  312. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  313. struct qeth_cmd_buffer *iob)
  314. {
  315. struct qeth_ipa_cmd *cmd = NULL;
  316. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  317. if (IS_IPA(iob->data)) {
  318. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  319. if (IS_IPA_REPLY(cmd)) {
  320. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  321. cmd->hdr.command != IPA_CMD_DELCCID &&
  322. cmd->hdr.command != IPA_CMD_MODCCID &&
  323. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  324. qeth_issue_ipa_msg(cmd,
  325. cmd->hdr.return_code, card);
  326. return cmd;
  327. } else {
  328. switch (cmd->hdr.command) {
  329. case IPA_CMD_STOPLAN:
  330. dev_warn(&card->gdev->dev,
  331. "The link for interface %s on CHPID"
  332. " 0x%X failed\n",
  333. QETH_CARD_IFNAME(card),
  334. card->info.chpid);
  335. card->lan_online = 0;
  336. if (card->dev && netif_carrier_ok(card->dev))
  337. netif_carrier_off(card->dev);
  338. return NULL;
  339. case IPA_CMD_STARTLAN:
  340. dev_info(&card->gdev->dev,
  341. "The link for %s on CHPID 0x%X has"
  342. " been restored\n",
  343. QETH_CARD_IFNAME(card),
  344. card->info.chpid);
  345. netif_carrier_on(card->dev);
  346. card->lan_online = 1;
  347. qeth_schedule_recovery(card);
  348. return NULL;
  349. case IPA_CMD_MODCCID:
  350. return cmd;
  351. case IPA_CMD_REGISTER_LOCAL_ADDR:
  352. QETH_DBF_TEXT(TRACE, 3, "irla");
  353. break;
  354. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  355. QETH_DBF_TEXT(TRACE, 3, "urla");
  356. break;
  357. default:
  358. QETH_DBF_MESSAGE(2, "Received data is IPA "
  359. "but not a reply!\n");
  360. break;
  361. }
  362. }
  363. }
  364. return cmd;
  365. }
  366. void qeth_clear_ipacmd_list(struct qeth_card *card)
  367. {
  368. struct qeth_reply *reply, *r;
  369. unsigned long flags;
  370. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  371. spin_lock_irqsave(&card->lock, flags);
  372. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  373. qeth_get_reply(reply);
  374. reply->rc = -EIO;
  375. atomic_inc(&reply->received);
  376. list_del_init(&reply->list);
  377. wake_up(&reply->wait_q);
  378. qeth_put_reply(reply);
  379. }
  380. spin_unlock_irqrestore(&card->lock, flags);
  381. }
  382. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  383. static int qeth_check_idx_response(unsigned char *buffer)
  384. {
  385. if (!buffer)
  386. return 0;
  387. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  388. if ((buffer[2] & 0xc0) == 0xc0) {
  389. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  390. "with cause code 0x%02x%s\n",
  391. buffer[4],
  392. ((buffer[4] == 0x22) ?
  393. " -- try another portname" : ""));
  394. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  395. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  396. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  397. return -EIO;
  398. }
  399. return 0;
  400. }
  401. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  402. __u32 len)
  403. {
  404. struct qeth_card *card;
  405. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  406. card = CARD_FROM_CDEV(channel->ccwdev);
  407. if (channel == &card->read)
  408. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  409. else
  410. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  411. channel->ccw.count = len;
  412. channel->ccw.cda = (__u32) __pa(iob);
  413. }
  414. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  415. {
  416. __u8 index;
  417. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  418. index = channel->io_buf_no;
  419. do {
  420. if (channel->iob[index].state == BUF_STATE_FREE) {
  421. channel->iob[index].state = BUF_STATE_LOCKED;
  422. channel->io_buf_no = (channel->io_buf_no + 1) %
  423. QETH_CMD_BUFFER_NO;
  424. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  425. return channel->iob + index;
  426. }
  427. index = (index + 1) % QETH_CMD_BUFFER_NO;
  428. } while (index != channel->io_buf_no);
  429. return NULL;
  430. }
  431. void qeth_release_buffer(struct qeth_channel *channel,
  432. struct qeth_cmd_buffer *iob)
  433. {
  434. unsigned long flags;
  435. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  436. spin_lock_irqsave(&channel->iob_lock, flags);
  437. memset(iob->data, 0, QETH_BUFSIZE);
  438. iob->state = BUF_STATE_FREE;
  439. iob->callback = qeth_send_control_data_cb;
  440. iob->rc = 0;
  441. spin_unlock_irqrestore(&channel->iob_lock, flags);
  442. }
  443. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  444. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  445. {
  446. struct qeth_cmd_buffer *buffer = NULL;
  447. unsigned long flags;
  448. spin_lock_irqsave(&channel->iob_lock, flags);
  449. buffer = __qeth_get_buffer(channel);
  450. spin_unlock_irqrestore(&channel->iob_lock, flags);
  451. return buffer;
  452. }
  453. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  454. {
  455. struct qeth_cmd_buffer *buffer;
  456. wait_event(channel->wait_q,
  457. ((buffer = qeth_get_buffer(channel)) != NULL));
  458. return buffer;
  459. }
  460. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  461. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  462. {
  463. int cnt;
  464. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  465. qeth_release_buffer(channel, &channel->iob[cnt]);
  466. channel->buf_no = 0;
  467. channel->io_buf_no = 0;
  468. }
  469. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  470. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  471. struct qeth_cmd_buffer *iob)
  472. {
  473. struct qeth_card *card;
  474. struct qeth_reply *reply, *r;
  475. struct qeth_ipa_cmd *cmd;
  476. unsigned long flags;
  477. int keep_reply;
  478. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  479. card = CARD_FROM_CDEV(channel->ccwdev);
  480. if (qeth_check_idx_response(iob->data)) {
  481. qeth_clear_ipacmd_list(card);
  482. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  483. dev_err(&card->gdev->dev,
  484. "The qeth device is not configured "
  485. "for the OSI layer required by z/VM\n");
  486. else
  487. qeth_schedule_recovery(card);
  488. goto out;
  489. }
  490. cmd = qeth_check_ipa_data(card, iob);
  491. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  492. goto out;
  493. /*in case of OSN : check if cmd is set */
  494. if (card->info.type == QETH_CARD_TYPE_OSN &&
  495. cmd &&
  496. cmd->hdr.command != IPA_CMD_STARTLAN &&
  497. card->osn_info.assist_cb != NULL) {
  498. card->osn_info.assist_cb(card->dev, cmd);
  499. goto out;
  500. }
  501. spin_lock_irqsave(&card->lock, flags);
  502. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  503. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  504. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  505. qeth_get_reply(reply);
  506. list_del_init(&reply->list);
  507. spin_unlock_irqrestore(&card->lock, flags);
  508. keep_reply = 0;
  509. if (reply->callback != NULL) {
  510. if (cmd) {
  511. reply->offset = (__u16)((char *)cmd -
  512. (char *)iob->data);
  513. keep_reply = reply->callback(card,
  514. reply,
  515. (unsigned long)cmd);
  516. } else
  517. keep_reply = reply->callback(card,
  518. reply,
  519. (unsigned long)iob);
  520. }
  521. if (cmd)
  522. reply->rc = (u16) cmd->hdr.return_code;
  523. else if (iob->rc)
  524. reply->rc = iob->rc;
  525. if (keep_reply) {
  526. spin_lock_irqsave(&card->lock, flags);
  527. list_add_tail(&reply->list,
  528. &card->cmd_waiter_list);
  529. spin_unlock_irqrestore(&card->lock, flags);
  530. } else {
  531. atomic_inc(&reply->received);
  532. wake_up(&reply->wait_q);
  533. }
  534. qeth_put_reply(reply);
  535. goto out;
  536. }
  537. }
  538. spin_unlock_irqrestore(&card->lock, flags);
  539. out:
  540. memcpy(&card->seqno.pdu_hdr_ack,
  541. QETH_PDU_HEADER_SEQ_NO(iob->data),
  542. QETH_SEQ_NO_LENGTH);
  543. qeth_release_buffer(channel, iob);
  544. }
  545. static int qeth_setup_channel(struct qeth_channel *channel)
  546. {
  547. int cnt;
  548. QETH_DBF_TEXT(SETUP, 2, "setupch");
  549. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  550. channel->iob[cnt].data = (char *)
  551. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  552. if (channel->iob[cnt].data == NULL)
  553. break;
  554. channel->iob[cnt].state = BUF_STATE_FREE;
  555. channel->iob[cnt].channel = channel;
  556. channel->iob[cnt].callback = qeth_send_control_data_cb;
  557. channel->iob[cnt].rc = 0;
  558. }
  559. if (cnt < QETH_CMD_BUFFER_NO) {
  560. while (cnt-- > 0)
  561. kfree(channel->iob[cnt].data);
  562. return -ENOMEM;
  563. }
  564. channel->buf_no = 0;
  565. channel->io_buf_no = 0;
  566. atomic_set(&channel->irq_pending, 0);
  567. spin_lock_init(&channel->iob_lock);
  568. init_waitqueue_head(&channel->wait_q);
  569. return 0;
  570. }
  571. static int qeth_set_thread_start_bit(struct qeth_card *card,
  572. unsigned long thread)
  573. {
  574. unsigned long flags;
  575. spin_lock_irqsave(&card->thread_mask_lock, flags);
  576. if (!(card->thread_allowed_mask & thread) ||
  577. (card->thread_start_mask & thread)) {
  578. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  579. return -EPERM;
  580. }
  581. card->thread_start_mask |= thread;
  582. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  583. return 0;
  584. }
  585. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  586. {
  587. unsigned long flags;
  588. spin_lock_irqsave(&card->thread_mask_lock, flags);
  589. card->thread_start_mask &= ~thread;
  590. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  591. wake_up(&card->wait_q);
  592. }
  593. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  594. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  595. {
  596. unsigned long flags;
  597. spin_lock_irqsave(&card->thread_mask_lock, flags);
  598. card->thread_running_mask &= ~thread;
  599. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  600. wake_up(&card->wait_q);
  601. }
  602. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  603. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  604. {
  605. unsigned long flags;
  606. int rc = 0;
  607. spin_lock_irqsave(&card->thread_mask_lock, flags);
  608. if (card->thread_start_mask & thread) {
  609. if ((card->thread_allowed_mask & thread) &&
  610. !(card->thread_running_mask & thread)) {
  611. rc = 1;
  612. card->thread_start_mask &= ~thread;
  613. card->thread_running_mask |= thread;
  614. } else
  615. rc = -EPERM;
  616. }
  617. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  618. return rc;
  619. }
  620. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  621. {
  622. int rc = 0;
  623. wait_event(card->wait_q,
  624. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  625. return rc;
  626. }
  627. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  628. void qeth_schedule_recovery(struct qeth_card *card)
  629. {
  630. QETH_DBF_TEXT(TRACE, 2, "startrec");
  631. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  632. schedule_work(&card->kernel_thread_starter);
  633. }
  634. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  635. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  636. {
  637. int dstat, cstat;
  638. char *sense;
  639. sense = (char *) irb->ecw;
  640. cstat = irb->scsw.cmd.cstat;
  641. dstat = irb->scsw.cmd.dstat;
  642. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  643. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  644. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  645. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  646. dev_warn(&cdev->dev, "The qeth device driver "
  647. "failed to recover an error on the device\n");
  648. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  649. dev_name(&cdev->dev), dstat, cstat);
  650. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  651. 16, 1, irb, 64, 1);
  652. return 1;
  653. }
  654. if (dstat & DEV_STAT_UNIT_CHECK) {
  655. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  656. SENSE_RESETTING_EVENT_FLAG) {
  657. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  658. return 1;
  659. }
  660. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  661. SENSE_COMMAND_REJECT_FLAG) {
  662. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  663. return 1;
  664. }
  665. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  666. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  667. return 1;
  668. }
  669. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  670. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  671. return 0;
  672. }
  673. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  674. return 1;
  675. }
  676. return 0;
  677. }
  678. static long __qeth_check_irb_error(struct ccw_device *cdev,
  679. unsigned long intparm, struct irb *irb)
  680. {
  681. if (!IS_ERR(irb))
  682. return 0;
  683. switch (PTR_ERR(irb)) {
  684. case -EIO:
  685. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  686. dev_name(&cdev->dev));
  687. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  688. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  689. break;
  690. case -ETIMEDOUT:
  691. dev_warn(&cdev->dev, "A hardware operation timed out"
  692. " on the device\n");
  693. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  694. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  695. if (intparm == QETH_RCD_PARM) {
  696. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  697. if (card && (card->data.ccwdev == cdev)) {
  698. card->data.state = CH_STATE_DOWN;
  699. wake_up(&card->wait_q);
  700. }
  701. }
  702. break;
  703. default:
  704. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  705. dev_name(&cdev->dev), PTR_ERR(irb));
  706. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  707. QETH_DBF_TEXT(TRACE, 2, " rc???");
  708. }
  709. return PTR_ERR(irb);
  710. }
  711. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  712. struct irb *irb)
  713. {
  714. int rc;
  715. int cstat, dstat;
  716. struct qeth_cmd_buffer *buffer;
  717. struct qeth_channel *channel;
  718. struct qeth_card *card;
  719. struct qeth_cmd_buffer *iob;
  720. __u8 index;
  721. QETH_DBF_TEXT(TRACE, 5, "irq");
  722. if (__qeth_check_irb_error(cdev, intparm, irb))
  723. return;
  724. cstat = irb->scsw.cmd.cstat;
  725. dstat = irb->scsw.cmd.dstat;
  726. card = CARD_FROM_CDEV(cdev);
  727. if (!card)
  728. return;
  729. if (card->read.ccwdev == cdev) {
  730. channel = &card->read;
  731. QETH_DBF_TEXT(TRACE, 5, "read");
  732. } else if (card->write.ccwdev == cdev) {
  733. channel = &card->write;
  734. QETH_DBF_TEXT(TRACE, 5, "write");
  735. } else {
  736. channel = &card->data;
  737. QETH_DBF_TEXT(TRACE, 5, "data");
  738. }
  739. atomic_set(&channel->irq_pending, 0);
  740. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  741. channel->state = CH_STATE_STOPPED;
  742. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  743. channel->state = CH_STATE_HALTED;
  744. /*let's wake up immediately on data channel*/
  745. if ((channel == &card->data) && (intparm != 0) &&
  746. (intparm != QETH_RCD_PARM))
  747. goto out;
  748. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  749. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  750. /* we don't have to handle this further */
  751. intparm = 0;
  752. }
  753. if (intparm == QETH_HALT_CHANNEL_PARM) {
  754. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  755. /* we don't have to handle this further */
  756. intparm = 0;
  757. }
  758. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  759. (dstat & DEV_STAT_UNIT_CHECK) ||
  760. (cstat)) {
  761. if (irb->esw.esw0.erw.cons) {
  762. dev_warn(&channel->ccwdev->dev,
  763. "The qeth device driver failed to recover "
  764. "an error on the device\n");
  765. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  766. "0x%X dstat 0x%X\n",
  767. dev_name(&channel->ccwdev->dev), cstat, dstat);
  768. print_hex_dump(KERN_WARNING, "qeth: irb ",
  769. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  770. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  771. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  772. }
  773. if (intparm == QETH_RCD_PARM) {
  774. channel->state = CH_STATE_DOWN;
  775. goto out;
  776. }
  777. rc = qeth_get_problem(cdev, irb);
  778. if (rc) {
  779. qeth_clear_ipacmd_list(card);
  780. qeth_schedule_recovery(card);
  781. goto out;
  782. }
  783. }
  784. if (intparm == QETH_RCD_PARM) {
  785. channel->state = CH_STATE_RCD_DONE;
  786. goto out;
  787. }
  788. if (intparm) {
  789. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  790. buffer->state = BUF_STATE_PROCESSED;
  791. }
  792. if (channel == &card->data)
  793. return;
  794. if (channel == &card->read &&
  795. channel->state == CH_STATE_UP)
  796. qeth_issue_next_read(card);
  797. iob = channel->iob;
  798. index = channel->buf_no;
  799. while (iob[index].state == BUF_STATE_PROCESSED) {
  800. if (iob[index].callback != NULL)
  801. iob[index].callback(channel, iob + index);
  802. index = (index + 1) % QETH_CMD_BUFFER_NO;
  803. }
  804. channel->buf_no = index;
  805. out:
  806. wake_up(&card->wait_q);
  807. return;
  808. }
  809. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  810. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  811. {
  812. int i;
  813. struct sk_buff *skb;
  814. /* is PCI flag set on buffer? */
  815. if (buf->buffer->element[0].flags & 0x40)
  816. atomic_dec(&queue->set_pci_flags_count);
  817. if (!qeth_skip_skb) {
  818. skb = skb_dequeue(&buf->skb_list);
  819. while (skb) {
  820. atomic_dec(&skb->users);
  821. dev_kfree_skb_any(skb);
  822. skb = skb_dequeue(&buf->skb_list);
  823. }
  824. }
  825. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  826. if (buf->buffer->element[i].addr && buf->is_header[i])
  827. kmem_cache_free(qeth_core_header_cache,
  828. buf->buffer->element[i].addr);
  829. buf->is_header[i] = 0;
  830. buf->buffer->element[i].length = 0;
  831. buf->buffer->element[i].addr = NULL;
  832. buf->buffer->element[i].flags = 0;
  833. }
  834. buf->buffer->element[15].flags = 0;
  835. buf->next_element_to_fill = 0;
  836. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  837. }
  838. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  839. struct qeth_qdio_out_buffer *buf)
  840. {
  841. __qeth_clear_output_buffer(queue, buf, 0);
  842. }
  843. void qeth_clear_qdio_buffers(struct qeth_card *card)
  844. {
  845. int i, j;
  846. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  847. /* clear outbound buffers to free skbs */
  848. for (i = 0; i < card->qdio.no_out_queues; ++i)
  849. if (card->qdio.out_qs[i]) {
  850. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  851. qeth_clear_output_buffer(card->qdio.out_qs[i],
  852. &card->qdio.out_qs[i]->bufs[j]);
  853. }
  854. }
  855. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  856. static void qeth_free_buffer_pool(struct qeth_card *card)
  857. {
  858. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  859. int i = 0;
  860. QETH_DBF_TEXT(TRACE, 5, "freepool");
  861. list_for_each_entry_safe(pool_entry, tmp,
  862. &card->qdio.init_pool.entry_list, init_list){
  863. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  864. free_page((unsigned long)pool_entry->elements[i]);
  865. list_del(&pool_entry->init_list);
  866. kfree(pool_entry);
  867. }
  868. }
  869. static void qeth_free_qdio_buffers(struct qeth_card *card)
  870. {
  871. int i, j;
  872. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  873. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  874. QETH_QDIO_UNINITIALIZED)
  875. return;
  876. kfree(card->qdio.in_q);
  877. card->qdio.in_q = NULL;
  878. /* inbound buffer pool */
  879. qeth_free_buffer_pool(card);
  880. /* free outbound qdio_qs */
  881. if (card->qdio.out_qs) {
  882. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  883. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  884. qeth_clear_output_buffer(card->qdio.out_qs[i],
  885. &card->qdio.out_qs[i]->bufs[j]);
  886. kfree(card->qdio.out_qs[i]);
  887. }
  888. kfree(card->qdio.out_qs);
  889. card->qdio.out_qs = NULL;
  890. }
  891. }
  892. static void qeth_clean_channel(struct qeth_channel *channel)
  893. {
  894. int cnt;
  895. QETH_DBF_TEXT(SETUP, 2, "freech");
  896. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  897. kfree(channel->iob[cnt].data);
  898. }
  899. static int qeth_is_1920_device(struct qeth_card *card)
  900. {
  901. int single_queue = 0;
  902. struct ccw_device *ccwdev;
  903. struct channelPath_dsc {
  904. u8 flags;
  905. u8 lsn;
  906. u8 desc;
  907. u8 chpid;
  908. u8 swla;
  909. u8 zeroes;
  910. u8 chla;
  911. u8 chpp;
  912. } *chp_dsc;
  913. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  914. ccwdev = card->data.ccwdev;
  915. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  916. if (chp_dsc != NULL) {
  917. /* CHPP field bit 6 == 1 -> single queue */
  918. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  919. kfree(chp_dsc);
  920. }
  921. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  922. return single_queue;
  923. }
  924. static void qeth_init_qdio_info(struct qeth_card *card)
  925. {
  926. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  927. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  928. /* inbound */
  929. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  930. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  931. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  932. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  933. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  934. }
  935. static void qeth_set_intial_options(struct qeth_card *card)
  936. {
  937. card->options.route4.type = NO_ROUTER;
  938. card->options.route6.type = NO_ROUTER;
  939. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  940. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  941. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  942. card->options.fake_broadcast = 0;
  943. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  944. card->options.performance_stats = 0;
  945. card->options.rx_sg_cb = QETH_RX_SG_CB;
  946. card->options.isolation = ISOLATION_MODE_NONE;
  947. }
  948. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  949. {
  950. unsigned long flags;
  951. int rc = 0;
  952. spin_lock_irqsave(&card->thread_mask_lock, flags);
  953. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  954. (u8) card->thread_start_mask,
  955. (u8) card->thread_allowed_mask,
  956. (u8) card->thread_running_mask);
  957. rc = (card->thread_start_mask & thread);
  958. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  959. return rc;
  960. }
  961. static void qeth_start_kernel_thread(struct work_struct *work)
  962. {
  963. struct qeth_card *card = container_of(work, struct qeth_card,
  964. kernel_thread_starter);
  965. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  966. if (card->read.state != CH_STATE_UP &&
  967. card->write.state != CH_STATE_UP)
  968. return;
  969. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  970. kthread_run(card->discipline.recover, (void *) card,
  971. "qeth_recover");
  972. }
  973. static int qeth_setup_card(struct qeth_card *card)
  974. {
  975. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  976. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  977. card->read.state = CH_STATE_DOWN;
  978. card->write.state = CH_STATE_DOWN;
  979. card->data.state = CH_STATE_DOWN;
  980. card->state = CARD_STATE_DOWN;
  981. card->lan_online = 0;
  982. card->use_hard_stop = 0;
  983. card->dev = NULL;
  984. spin_lock_init(&card->vlanlock);
  985. spin_lock_init(&card->mclock);
  986. card->vlangrp = NULL;
  987. spin_lock_init(&card->lock);
  988. spin_lock_init(&card->ip_lock);
  989. spin_lock_init(&card->thread_mask_lock);
  990. card->thread_start_mask = 0;
  991. card->thread_allowed_mask = 0;
  992. card->thread_running_mask = 0;
  993. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  994. INIT_LIST_HEAD(&card->ip_list);
  995. INIT_LIST_HEAD(card->ip_tbd_list);
  996. INIT_LIST_HEAD(&card->cmd_waiter_list);
  997. init_waitqueue_head(&card->wait_q);
  998. /* intial options */
  999. qeth_set_intial_options(card);
  1000. /* IP address takeover */
  1001. INIT_LIST_HEAD(&card->ipato.entries);
  1002. card->ipato.enabled = 0;
  1003. card->ipato.invert4 = 0;
  1004. card->ipato.invert6 = 0;
  1005. /* init QDIO stuff */
  1006. qeth_init_qdio_info(card);
  1007. return 0;
  1008. }
  1009. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1010. {
  1011. struct qeth_card *card = container_of(slr, struct qeth_card,
  1012. qeth_service_level);
  1013. if (card->info.mcl_level[0])
  1014. seq_printf(m, "qeth: %s firmware level %s\n",
  1015. CARD_BUS_ID(card), card->info.mcl_level);
  1016. }
  1017. static struct qeth_card *qeth_alloc_card(void)
  1018. {
  1019. struct qeth_card *card;
  1020. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1021. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1022. if (!card)
  1023. goto out;
  1024. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1025. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1026. if (!card->ip_tbd_list) {
  1027. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1028. goto out_card;
  1029. }
  1030. if (qeth_setup_channel(&card->read))
  1031. goto out_ip;
  1032. if (qeth_setup_channel(&card->write))
  1033. goto out_channel;
  1034. card->options.layer2 = -1;
  1035. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1036. register_service_level(&card->qeth_service_level);
  1037. return card;
  1038. out_channel:
  1039. qeth_clean_channel(&card->read);
  1040. out_ip:
  1041. kfree(card->ip_tbd_list);
  1042. out_card:
  1043. kfree(card);
  1044. out:
  1045. return NULL;
  1046. }
  1047. static int qeth_determine_card_type(struct qeth_card *card)
  1048. {
  1049. int i = 0;
  1050. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1051. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1052. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1053. while (known_devices[i][4]) {
  1054. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1055. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1056. card->info.type = known_devices[i][4];
  1057. card->qdio.no_out_queues = known_devices[i][8];
  1058. card->info.is_multicast_different = known_devices[i][9];
  1059. if (qeth_is_1920_device(card)) {
  1060. dev_info(&card->gdev->dev,
  1061. "Priority Queueing not supported\n");
  1062. card->qdio.no_out_queues = 1;
  1063. card->qdio.default_out_queue = 0;
  1064. }
  1065. return 0;
  1066. }
  1067. i++;
  1068. }
  1069. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1070. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1071. "unknown type\n");
  1072. return -ENOENT;
  1073. }
  1074. static int qeth_clear_channel(struct qeth_channel *channel)
  1075. {
  1076. unsigned long flags;
  1077. struct qeth_card *card;
  1078. int rc;
  1079. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1080. card = CARD_FROM_CDEV(channel->ccwdev);
  1081. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1082. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1083. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1084. if (rc)
  1085. return rc;
  1086. rc = wait_event_interruptible_timeout(card->wait_q,
  1087. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1088. if (rc == -ERESTARTSYS)
  1089. return rc;
  1090. if (channel->state != CH_STATE_STOPPED)
  1091. return -ETIME;
  1092. channel->state = CH_STATE_DOWN;
  1093. return 0;
  1094. }
  1095. static int qeth_halt_channel(struct qeth_channel *channel)
  1096. {
  1097. unsigned long flags;
  1098. struct qeth_card *card;
  1099. int rc;
  1100. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1101. card = CARD_FROM_CDEV(channel->ccwdev);
  1102. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1103. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1104. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1105. if (rc)
  1106. return rc;
  1107. rc = wait_event_interruptible_timeout(card->wait_q,
  1108. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1109. if (rc == -ERESTARTSYS)
  1110. return rc;
  1111. if (channel->state != CH_STATE_HALTED)
  1112. return -ETIME;
  1113. return 0;
  1114. }
  1115. static int qeth_halt_channels(struct qeth_card *card)
  1116. {
  1117. int rc1 = 0, rc2 = 0, rc3 = 0;
  1118. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1119. rc1 = qeth_halt_channel(&card->read);
  1120. rc2 = qeth_halt_channel(&card->write);
  1121. rc3 = qeth_halt_channel(&card->data);
  1122. if (rc1)
  1123. return rc1;
  1124. if (rc2)
  1125. return rc2;
  1126. return rc3;
  1127. }
  1128. static int qeth_clear_channels(struct qeth_card *card)
  1129. {
  1130. int rc1 = 0, rc2 = 0, rc3 = 0;
  1131. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1132. rc1 = qeth_clear_channel(&card->read);
  1133. rc2 = qeth_clear_channel(&card->write);
  1134. rc3 = qeth_clear_channel(&card->data);
  1135. if (rc1)
  1136. return rc1;
  1137. if (rc2)
  1138. return rc2;
  1139. return rc3;
  1140. }
  1141. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1142. {
  1143. int rc = 0;
  1144. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1145. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1146. if (halt)
  1147. rc = qeth_halt_channels(card);
  1148. if (rc)
  1149. return rc;
  1150. return qeth_clear_channels(card);
  1151. }
  1152. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1153. {
  1154. int rc = 0;
  1155. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1156. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1157. QETH_QDIO_CLEANING)) {
  1158. case QETH_QDIO_ESTABLISHED:
  1159. if (card->info.type == QETH_CARD_TYPE_IQD)
  1160. rc = qdio_shutdown(CARD_DDEV(card),
  1161. QDIO_FLAG_CLEANUP_USING_HALT);
  1162. else
  1163. rc = qdio_shutdown(CARD_DDEV(card),
  1164. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1165. if (rc)
  1166. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1167. qdio_free(CARD_DDEV(card));
  1168. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1169. break;
  1170. case QETH_QDIO_CLEANING:
  1171. return rc;
  1172. default:
  1173. break;
  1174. }
  1175. rc = qeth_clear_halt_card(card, use_halt);
  1176. if (rc)
  1177. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1178. card->state = CARD_STATE_DOWN;
  1179. return rc;
  1180. }
  1181. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1182. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1183. int *length)
  1184. {
  1185. struct ciw *ciw;
  1186. char *rcd_buf;
  1187. int ret;
  1188. struct qeth_channel *channel = &card->data;
  1189. unsigned long flags;
  1190. /*
  1191. * scan for RCD command in extended SenseID data
  1192. */
  1193. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1194. if (!ciw || ciw->cmd == 0)
  1195. return -EOPNOTSUPP;
  1196. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1197. if (!rcd_buf)
  1198. return -ENOMEM;
  1199. channel->ccw.cmd_code = ciw->cmd;
  1200. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1201. channel->ccw.count = ciw->count;
  1202. channel->ccw.flags = CCW_FLAG_SLI;
  1203. channel->state = CH_STATE_RCD;
  1204. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1205. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1206. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1207. QETH_RCD_TIMEOUT);
  1208. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1209. if (!ret)
  1210. wait_event(card->wait_q,
  1211. (channel->state == CH_STATE_RCD_DONE ||
  1212. channel->state == CH_STATE_DOWN));
  1213. if (channel->state == CH_STATE_DOWN)
  1214. ret = -EIO;
  1215. else
  1216. channel->state = CH_STATE_DOWN;
  1217. if (ret) {
  1218. kfree(rcd_buf);
  1219. *buffer = NULL;
  1220. *length = 0;
  1221. } else {
  1222. *length = ciw->count;
  1223. *buffer = rcd_buf;
  1224. }
  1225. return ret;
  1226. }
  1227. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1228. {
  1229. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1230. card->info.chpid = prcd[30];
  1231. card->info.unit_addr2 = prcd[31];
  1232. card->info.cula = prcd[63];
  1233. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1234. (prcd[0x11] == _ascebc['M']));
  1235. }
  1236. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1237. {
  1238. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1239. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1240. card->info.blkt.time_total = 250;
  1241. card->info.blkt.inter_packet = 5;
  1242. card->info.blkt.inter_packet_jumbo = 15;
  1243. } else {
  1244. card->info.blkt.time_total = 0;
  1245. card->info.blkt.inter_packet = 0;
  1246. card->info.blkt.inter_packet_jumbo = 0;
  1247. }
  1248. }
  1249. static void qeth_init_tokens(struct qeth_card *card)
  1250. {
  1251. card->token.issuer_rm_w = 0x00010103UL;
  1252. card->token.cm_filter_w = 0x00010108UL;
  1253. card->token.cm_connection_w = 0x0001010aUL;
  1254. card->token.ulp_filter_w = 0x0001010bUL;
  1255. card->token.ulp_connection_w = 0x0001010dUL;
  1256. }
  1257. static void qeth_init_func_level(struct qeth_card *card)
  1258. {
  1259. if (card->ipato.enabled) {
  1260. if (card->info.type == QETH_CARD_TYPE_IQD)
  1261. card->info.func_level =
  1262. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1263. else
  1264. card->info.func_level =
  1265. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1266. } else {
  1267. if (card->info.type == QETH_CARD_TYPE_IQD)
  1268. /*FIXME:why do we have same values for dis and ena for
  1269. osae??? */
  1270. card->info.func_level =
  1271. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1272. else
  1273. card->info.func_level =
  1274. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1275. }
  1276. }
  1277. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1278. void (*idx_reply_cb)(struct qeth_channel *,
  1279. struct qeth_cmd_buffer *))
  1280. {
  1281. struct qeth_cmd_buffer *iob;
  1282. unsigned long flags;
  1283. int rc;
  1284. struct qeth_card *card;
  1285. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1286. card = CARD_FROM_CDEV(channel->ccwdev);
  1287. iob = qeth_get_buffer(channel);
  1288. iob->callback = idx_reply_cb;
  1289. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1290. channel->ccw.count = QETH_BUFSIZE;
  1291. channel->ccw.cda = (__u32) __pa(iob->data);
  1292. wait_event(card->wait_q,
  1293. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1294. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1295. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1296. rc = ccw_device_start(channel->ccwdev,
  1297. &channel->ccw, (addr_t) iob, 0, 0);
  1298. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1299. if (rc) {
  1300. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1301. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1302. atomic_set(&channel->irq_pending, 0);
  1303. wake_up(&card->wait_q);
  1304. return rc;
  1305. }
  1306. rc = wait_event_interruptible_timeout(card->wait_q,
  1307. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1308. if (rc == -ERESTARTSYS)
  1309. return rc;
  1310. if (channel->state != CH_STATE_UP) {
  1311. rc = -ETIME;
  1312. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1313. qeth_clear_cmd_buffers(channel);
  1314. } else
  1315. rc = 0;
  1316. return rc;
  1317. }
  1318. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1319. void (*idx_reply_cb)(struct qeth_channel *,
  1320. struct qeth_cmd_buffer *))
  1321. {
  1322. struct qeth_card *card;
  1323. struct qeth_cmd_buffer *iob;
  1324. unsigned long flags;
  1325. __u16 temp;
  1326. __u8 tmp;
  1327. int rc;
  1328. struct ccw_dev_id temp_devid;
  1329. card = CARD_FROM_CDEV(channel->ccwdev);
  1330. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1331. iob = qeth_get_buffer(channel);
  1332. iob->callback = idx_reply_cb;
  1333. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1334. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1335. channel->ccw.cda = (__u32) __pa(iob->data);
  1336. if (channel == &card->write) {
  1337. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1338. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1339. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1340. card->seqno.trans_hdr++;
  1341. } else {
  1342. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1343. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1344. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1345. }
  1346. tmp = ((__u8)card->info.portno) | 0x80;
  1347. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1348. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1349. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1350. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1351. &card->info.func_level, sizeof(__u16));
  1352. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1353. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1354. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1355. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1356. wait_event(card->wait_q,
  1357. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1358. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1359. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1360. rc = ccw_device_start(channel->ccwdev,
  1361. &channel->ccw, (addr_t) iob, 0, 0);
  1362. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1363. if (rc) {
  1364. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1365. rc);
  1366. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1367. atomic_set(&channel->irq_pending, 0);
  1368. wake_up(&card->wait_q);
  1369. return rc;
  1370. }
  1371. rc = wait_event_interruptible_timeout(card->wait_q,
  1372. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1373. if (rc == -ERESTARTSYS)
  1374. return rc;
  1375. if (channel->state != CH_STATE_ACTIVATING) {
  1376. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1377. " failed to recover an error on the device\n");
  1378. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1379. dev_name(&channel->ccwdev->dev));
  1380. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1381. qeth_clear_cmd_buffers(channel);
  1382. return -ETIME;
  1383. }
  1384. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1385. }
  1386. static int qeth_peer_func_level(int level)
  1387. {
  1388. if ((level & 0xff) == 8)
  1389. return (level & 0xff) + 0x400;
  1390. if (((level >> 8) & 3) == 1)
  1391. return (level & 0xff) + 0x200;
  1392. return level;
  1393. }
  1394. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1395. struct qeth_cmd_buffer *iob)
  1396. {
  1397. struct qeth_card *card;
  1398. __u16 temp;
  1399. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1400. if (channel->state == CH_STATE_DOWN) {
  1401. channel->state = CH_STATE_ACTIVATING;
  1402. goto out;
  1403. }
  1404. card = CARD_FROM_CDEV(channel->ccwdev);
  1405. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1406. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1407. dev_err(&card->write.ccwdev->dev,
  1408. "The adapter is used exclusively by another "
  1409. "host\n");
  1410. else
  1411. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1412. " negative reply\n",
  1413. dev_name(&card->write.ccwdev->dev));
  1414. goto out;
  1415. }
  1416. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1417. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1418. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1419. "function level mismatch (sent: 0x%x, received: "
  1420. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1421. card->info.func_level, temp);
  1422. goto out;
  1423. }
  1424. channel->state = CH_STATE_UP;
  1425. out:
  1426. qeth_release_buffer(channel, iob);
  1427. }
  1428. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1429. struct qeth_cmd_buffer *iob)
  1430. {
  1431. struct qeth_card *card;
  1432. __u16 temp;
  1433. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1434. if (channel->state == CH_STATE_DOWN) {
  1435. channel->state = CH_STATE_ACTIVATING;
  1436. goto out;
  1437. }
  1438. card = CARD_FROM_CDEV(channel->ccwdev);
  1439. if (qeth_check_idx_response(iob->data))
  1440. goto out;
  1441. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1442. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1443. dev_err(&card->write.ccwdev->dev,
  1444. "The adapter is used exclusively by another "
  1445. "host\n");
  1446. else
  1447. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1448. " negative reply\n",
  1449. dev_name(&card->read.ccwdev->dev));
  1450. goto out;
  1451. }
  1452. /**
  1453. * temporary fix for microcode bug
  1454. * to revert it,replace OR by AND
  1455. */
  1456. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1457. (card->info.type == QETH_CARD_TYPE_OSAE))
  1458. card->info.portname_required = 1;
  1459. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1460. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1461. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1462. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1463. dev_name(&card->read.ccwdev->dev),
  1464. card->info.func_level, temp);
  1465. goto out;
  1466. }
  1467. memcpy(&card->token.issuer_rm_r,
  1468. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1469. QETH_MPC_TOKEN_LENGTH);
  1470. memcpy(&card->info.mcl_level[0],
  1471. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1472. channel->state = CH_STATE_UP;
  1473. out:
  1474. qeth_release_buffer(channel, iob);
  1475. }
  1476. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1477. struct qeth_cmd_buffer *iob)
  1478. {
  1479. qeth_setup_ccw(&card->write, iob->data, len);
  1480. iob->callback = qeth_release_buffer;
  1481. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1482. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1483. card->seqno.trans_hdr++;
  1484. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1485. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1486. card->seqno.pdu_hdr++;
  1487. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1488. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1489. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1490. }
  1491. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1492. int qeth_send_control_data(struct qeth_card *card, int len,
  1493. struct qeth_cmd_buffer *iob,
  1494. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1495. unsigned long),
  1496. void *reply_param)
  1497. {
  1498. int rc;
  1499. unsigned long flags;
  1500. struct qeth_reply *reply = NULL;
  1501. unsigned long timeout, event_timeout;
  1502. struct qeth_ipa_cmd *cmd;
  1503. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1504. reply = qeth_alloc_reply(card);
  1505. if (!reply) {
  1506. return -ENOMEM;
  1507. }
  1508. reply->callback = reply_cb;
  1509. reply->param = reply_param;
  1510. if (card->state == CARD_STATE_DOWN)
  1511. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1512. else
  1513. reply->seqno = card->seqno.ipa++;
  1514. init_waitqueue_head(&reply->wait_q);
  1515. spin_lock_irqsave(&card->lock, flags);
  1516. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1517. spin_unlock_irqrestore(&card->lock, flags);
  1518. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1519. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1520. qeth_prepare_control_data(card, len, iob);
  1521. if (IS_IPA(iob->data))
  1522. event_timeout = QETH_IPA_TIMEOUT;
  1523. else
  1524. event_timeout = QETH_TIMEOUT;
  1525. timeout = jiffies + event_timeout;
  1526. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1527. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1528. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1529. (addr_t) iob, 0, 0);
  1530. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1531. if (rc) {
  1532. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1533. "ccw_device_start rc = %i\n",
  1534. dev_name(&card->write.ccwdev->dev), rc);
  1535. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1536. spin_lock_irqsave(&card->lock, flags);
  1537. list_del_init(&reply->list);
  1538. qeth_put_reply(reply);
  1539. spin_unlock_irqrestore(&card->lock, flags);
  1540. qeth_release_buffer(iob->channel, iob);
  1541. atomic_set(&card->write.irq_pending, 0);
  1542. wake_up(&card->wait_q);
  1543. return rc;
  1544. }
  1545. /* we have only one long running ipassist, since we can ensure
  1546. process context of this command we can sleep */
  1547. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1548. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1549. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1550. if (!wait_event_timeout(reply->wait_q,
  1551. atomic_read(&reply->received), event_timeout))
  1552. goto time_err;
  1553. } else {
  1554. while (!atomic_read(&reply->received)) {
  1555. if (time_after(jiffies, timeout))
  1556. goto time_err;
  1557. cpu_relax();
  1558. };
  1559. }
  1560. rc = reply->rc;
  1561. qeth_put_reply(reply);
  1562. return rc;
  1563. time_err:
  1564. spin_lock_irqsave(&reply->card->lock, flags);
  1565. list_del_init(&reply->list);
  1566. spin_unlock_irqrestore(&reply->card->lock, flags);
  1567. reply->rc = -ETIME;
  1568. atomic_inc(&reply->received);
  1569. wake_up(&reply->wait_q);
  1570. rc = reply->rc;
  1571. qeth_put_reply(reply);
  1572. return rc;
  1573. }
  1574. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1575. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1576. unsigned long data)
  1577. {
  1578. struct qeth_cmd_buffer *iob;
  1579. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1580. iob = (struct qeth_cmd_buffer *) data;
  1581. memcpy(&card->token.cm_filter_r,
  1582. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1583. QETH_MPC_TOKEN_LENGTH);
  1584. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1585. return 0;
  1586. }
  1587. static int qeth_cm_enable(struct qeth_card *card)
  1588. {
  1589. int rc;
  1590. struct qeth_cmd_buffer *iob;
  1591. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1592. iob = qeth_wait_for_buffer(&card->write);
  1593. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1594. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1595. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1596. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1597. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1598. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1599. qeth_cm_enable_cb, NULL);
  1600. return rc;
  1601. }
  1602. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1603. unsigned long data)
  1604. {
  1605. struct qeth_cmd_buffer *iob;
  1606. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1607. iob = (struct qeth_cmd_buffer *) data;
  1608. memcpy(&card->token.cm_connection_r,
  1609. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1610. QETH_MPC_TOKEN_LENGTH);
  1611. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1612. return 0;
  1613. }
  1614. static int qeth_cm_setup(struct qeth_card *card)
  1615. {
  1616. int rc;
  1617. struct qeth_cmd_buffer *iob;
  1618. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1619. iob = qeth_wait_for_buffer(&card->write);
  1620. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1621. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1622. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1623. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1624. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1625. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1626. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1627. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1628. qeth_cm_setup_cb, NULL);
  1629. return rc;
  1630. }
  1631. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1632. {
  1633. switch (card->info.type) {
  1634. case QETH_CARD_TYPE_UNKNOWN:
  1635. return 1500;
  1636. case QETH_CARD_TYPE_IQD:
  1637. return card->info.max_mtu;
  1638. case QETH_CARD_TYPE_OSAE:
  1639. switch (card->info.link_type) {
  1640. case QETH_LINK_TYPE_HSTR:
  1641. case QETH_LINK_TYPE_LANE_TR:
  1642. return 2000;
  1643. default:
  1644. return 1492;
  1645. }
  1646. default:
  1647. return 1500;
  1648. }
  1649. }
  1650. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1651. {
  1652. switch (cardtype) {
  1653. case QETH_CARD_TYPE_UNKNOWN:
  1654. case QETH_CARD_TYPE_OSAE:
  1655. case QETH_CARD_TYPE_OSN:
  1656. return 61440;
  1657. case QETH_CARD_TYPE_IQD:
  1658. return 57344;
  1659. default:
  1660. return 1500;
  1661. }
  1662. }
  1663. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1664. {
  1665. switch (cardtype) {
  1666. case QETH_CARD_TYPE_IQD:
  1667. return 1;
  1668. default:
  1669. return 0;
  1670. }
  1671. }
  1672. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1673. {
  1674. switch (framesize) {
  1675. case 0x4000:
  1676. return 8192;
  1677. case 0x6000:
  1678. return 16384;
  1679. case 0xa000:
  1680. return 32768;
  1681. case 0xffff:
  1682. return 57344;
  1683. default:
  1684. return 0;
  1685. }
  1686. }
  1687. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1688. {
  1689. switch (card->info.type) {
  1690. case QETH_CARD_TYPE_OSAE:
  1691. return ((mtu >= 576) && (mtu <= 61440));
  1692. case QETH_CARD_TYPE_IQD:
  1693. return ((mtu >= 576) &&
  1694. (mtu <= card->info.max_mtu + 4096 - 32));
  1695. case QETH_CARD_TYPE_OSN:
  1696. case QETH_CARD_TYPE_UNKNOWN:
  1697. default:
  1698. return 1;
  1699. }
  1700. }
  1701. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1702. unsigned long data)
  1703. {
  1704. __u16 mtu, framesize;
  1705. __u16 len;
  1706. __u8 link_type;
  1707. struct qeth_cmd_buffer *iob;
  1708. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1709. iob = (struct qeth_cmd_buffer *) data;
  1710. memcpy(&card->token.ulp_filter_r,
  1711. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1712. QETH_MPC_TOKEN_LENGTH);
  1713. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1714. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1715. mtu = qeth_get_mtu_outof_framesize(framesize);
  1716. if (!mtu) {
  1717. iob->rc = -EINVAL;
  1718. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1719. return 0;
  1720. }
  1721. card->info.max_mtu = mtu;
  1722. card->info.initial_mtu = mtu;
  1723. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1724. } else {
  1725. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1726. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1727. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1728. }
  1729. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1730. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1731. memcpy(&link_type,
  1732. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1733. card->info.link_type = link_type;
  1734. } else
  1735. card->info.link_type = 0;
  1736. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1737. return 0;
  1738. }
  1739. static int qeth_ulp_enable(struct qeth_card *card)
  1740. {
  1741. int rc;
  1742. char prot_type;
  1743. struct qeth_cmd_buffer *iob;
  1744. /*FIXME: trace view callbacks*/
  1745. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1746. iob = qeth_wait_for_buffer(&card->write);
  1747. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1748. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1749. (__u8) card->info.portno;
  1750. if (card->options.layer2)
  1751. if (card->info.type == QETH_CARD_TYPE_OSN)
  1752. prot_type = QETH_PROT_OSN2;
  1753. else
  1754. prot_type = QETH_PROT_LAYER2;
  1755. else
  1756. prot_type = QETH_PROT_TCPIP;
  1757. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1758. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1759. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1760. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1761. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1762. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1763. card->info.portname, 9);
  1764. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1765. qeth_ulp_enable_cb, NULL);
  1766. return rc;
  1767. }
  1768. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1769. unsigned long data)
  1770. {
  1771. struct qeth_cmd_buffer *iob;
  1772. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1773. iob = (struct qeth_cmd_buffer *) data;
  1774. memcpy(&card->token.ulp_connection_r,
  1775. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1776. QETH_MPC_TOKEN_LENGTH);
  1777. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1778. return 0;
  1779. }
  1780. static int qeth_ulp_setup(struct qeth_card *card)
  1781. {
  1782. int rc;
  1783. __u16 temp;
  1784. struct qeth_cmd_buffer *iob;
  1785. struct ccw_dev_id dev_id;
  1786. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1787. iob = qeth_wait_for_buffer(&card->write);
  1788. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1789. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1790. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1791. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1792. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1793. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1794. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1795. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1796. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1797. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1798. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1799. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1800. qeth_ulp_setup_cb, NULL);
  1801. return rc;
  1802. }
  1803. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1804. {
  1805. int i, j;
  1806. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1807. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1808. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1809. return 0;
  1810. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1811. GFP_KERNEL);
  1812. if (!card->qdio.in_q)
  1813. goto out_nomem;
  1814. QETH_DBF_TEXT(SETUP, 2, "inq");
  1815. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1816. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1817. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1818. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1819. card->qdio.in_q->bufs[i].buffer =
  1820. &card->qdio.in_q->qdio_bufs[i];
  1821. /* inbound buffer pool */
  1822. if (qeth_alloc_buffer_pool(card))
  1823. goto out_freeinq;
  1824. /* outbound */
  1825. card->qdio.out_qs =
  1826. kmalloc(card->qdio.no_out_queues *
  1827. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1828. if (!card->qdio.out_qs)
  1829. goto out_freepool;
  1830. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1831. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1832. GFP_KERNEL);
  1833. if (!card->qdio.out_qs[i])
  1834. goto out_freeoutq;
  1835. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1836. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1837. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1838. card->qdio.out_qs[i]->queue_no = i;
  1839. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1840. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1841. card->qdio.out_qs[i]->bufs[j].buffer =
  1842. &card->qdio.out_qs[i]->qdio_bufs[j];
  1843. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1844. skb_list);
  1845. lockdep_set_class(
  1846. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1847. &qdio_out_skb_queue_key);
  1848. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1849. }
  1850. }
  1851. return 0;
  1852. out_freeoutq:
  1853. while (i > 0)
  1854. kfree(card->qdio.out_qs[--i]);
  1855. kfree(card->qdio.out_qs);
  1856. card->qdio.out_qs = NULL;
  1857. out_freepool:
  1858. qeth_free_buffer_pool(card);
  1859. out_freeinq:
  1860. kfree(card->qdio.in_q);
  1861. card->qdio.in_q = NULL;
  1862. out_nomem:
  1863. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1864. return -ENOMEM;
  1865. }
  1866. static void qeth_create_qib_param_field(struct qeth_card *card,
  1867. char *param_field)
  1868. {
  1869. param_field[0] = _ascebc['P'];
  1870. param_field[1] = _ascebc['C'];
  1871. param_field[2] = _ascebc['I'];
  1872. param_field[3] = _ascebc['T'];
  1873. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1874. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1875. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1876. }
  1877. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1878. char *param_field)
  1879. {
  1880. param_field[16] = _ascebc['B'];
  1881. param_field[17] = _ascebc['L'];
  1882. param_field[18] = _ascebc['K'];
  1883. param_field[19] = _ascebc['T'];
  1884. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1885. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1886. *((unsigned int *) (&param_field[28])) =
  1887. card->info.blkt.inter_packet_jumbo;
  1888. }
  1889. static int qeth_qdio_activate(struct qeth_card *card)
  1890. {
  1891. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1892. return qdio_activate(CARD_DDEV(card));
  1893. }
  1894. static int qeth_dm_act(struct qeth_card *card)
  1895. {
  1896. int rc;
  1897. struct qeth_cmd_buffer *iob;
  1898. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1899. iob = qeth_wait_for_buffer(&card->write);
  1900. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1901. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1902. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1903. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1904. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1905. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1906. return rc;
  1907. }
  1908. static int qeth_mpc_initialize(struct qeth_card *card)
  1909. {
  1910. int rc;
  1911. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1912. rc = qeth_issue_next_read(card);
  1913. if (rc) {
  1914. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1915. return rc;
  1916. }
  1917. rc = qeth_cm_enable(card);
  1918. if (rc) {
  1919. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1920. goto out_qdio;
  1921. }
  1922. rc = qeth_cm_setup(card);
  1923. if (rc) {
  1924. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1925. goto out_qdio;
  1926. }
  1927. rc = qeth_ulp_enable(card);
  1928. if (rc) {
  1929. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1930. goto out_qdio;
  1931. }
  1932. rc = qeth_ulp_setup(card);
  1933. if (rc) {
  1934. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1935. goto out_qdio;
  1936. }
  1937. rc = qeth_alloc_qdio_buffers(card);
  1938. if (rc) {
  1939. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1940. goto out_qdio;
  1941. }
  1942. rc = qeth_qdio_establish(card);
  1943. if (rc) {
  1944. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1945. qeth_free_qdio_buffers(card);
  1946. goto out_qdio;
  1947. }
  1948. rc = qeth_qdio_activate(card);
  1949. if (rc) {
  1950. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1951. goto out_qdio;
  1952. }
  1953. rc = qeth_dm_act(card);
  1954. if (rc) {
  1955. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1956. goto out_qdio;
  1957. }
  1958. return 0;
  1959. out_qdio:
  1960. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1961. return rc;
  1962. }
  1963. static void qeth_print_status_with_portname(struct qeth_card *card)
  1964. {
  1965. char dbf_text[15];
  1966. int i;
  1967. sprintf(dbf_text, "%s", card->info.portname + 1);
  1968. for (i = 0; i < 8; i++)
  1969. dbf_text[i] =
  1970. (char) _ebcasc[(__u8) dbf_text[i]];
  1971. dbf_text[8] = 0;
  1972. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1973. "with link type %s (portname: %s)\n",
  1974. qeth_get_cardname(card),
  1975. (card->info.mcl_level[0]) ? " (level: " : "",
  1976. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1977. (card->info.mcl_level[0]) ? ")" : "",
  1978. qeth_get_cardname_short(card),
  1979. dbf_text);
  1980. }
  1981. static void qeth_print_status_no_portname(struct qeth_card *card)
  1982. {
  1983. if (card->info.portname[0])
  1984. dev_info(&card->gdev->dev, "Device is a%s "
  1985. "card%s%s%s\nwith link type %s "
  1986. "(no portname needed by interface).\n",
  1987. qeth_get_cardname(card),
  1988. (card->info.mcl_level[0]) ? " (level: " : "",
  1989. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1990. (card->info.mcl_level[0]) ? ")" : "",
  1991. qeth_get_cardname_short(card));
  1992. else
  1993. dev_info(&card->gdev->dev, "Device is a%s "
  1994. "card%s%s%s\nwith link type %s.\n",
  1995. qeth_get_cardname(card),
  1996. (card->info.mcl_level[0]) ? " (level: " : "",
  1997. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1998. (card->info.mcl_level[0]) ? ")" : "",
  1999. qeth_get_cardname_short(card));
  2000. }
  2001. void qeth_print_status_message(struct qeth_card *card)
  2002. {
  2003. switch (card->info.type) {
  2004. case QETH_CARD_TYPE_OSAE:
  2005. /* VM will use a non-zero first character
  2006. * to indicate a HiperSockets like reporting
  2007. * of the level OSA sets the first character to zero
  2008. * */
  2009. if (!card->info.mcl_level[0]) {
  2010. sprintf(card->info.mcl_level, "%02x%02x",
  2011. card->info.mcl_level[2],
  2012. card->info.mcl_level[3]);
  2013. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2014. break;
  2015. }
  2016. /* fallthrough */
  2017. case QETH_CARD_TYPE_IQD:
  2018. if ((card->info.guestlan) ||
  2019. (card->info.mcl_level[0] & 0x80)) {
  2020. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2021. card->info.mcl_level[0]];
  2022. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2023. card->info.mcl_level[1]];
  2024. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2025. card->info.mcl_level[2]];
  2026. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2027. card->info.mcl_level[3]];
  2028. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2029. }
  2030. break;
  2031. default:
  2032. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2033. }
  2034. if (card->info.portname_required)
  2035. qeth_print_status_with_portname(card);
  2036. else
  2037. qeth_print_status_no_portname(card);
  2038. }
  2039. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2040. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2041. {
  2042. struct qeth_buffer_pool_entry *entry;
  2043. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2044. list_for_each_entry(entry,
  2045. &card->qdio.init_pool.entry_list, init_list) {
  2046. qeth_put_buffer_pool_entry(card, entry);
  2047. }
  2048. }
  2049. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2050. struct qeth_card *card)
  2051. {
  2052. struct list_head *plh;
  2053. struct qeth_buffer_pool_entry *entry;
  2054. int i, free;
  2055. struct page *page;
  2056. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2057. return NULL;
  2058. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2059. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2060. free = 1;
  2061. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2062. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2063. free = 0;
  2064. break;
  2065. }
  2066. }
  2067. if (free) {
  2068. list_del_init(&entry->list);
  2069. return entry;
  2070. }
  2071. }
  2072. /* no free buffer in pool so take first one and swap pages */
  2073. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2074. struct qeth_buffer_pool_entry, list);
  2075. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2076. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2077. page = alloc_page(GFP_ATOMIC);
  2078. if (!page) {
  2079. return NULL;
  2080. } else {
  2081. free_page((unsigned long)entry->elements[i]);
  2082. entry->elements[i] = page_address(page);
  2083. if (card->options.performance_stats)
  2084. card->perf_stats.sg_alloc_page_rx++;
  2085. }
  2086. }
  2087. }
  2088. list_del_init(&entry->list);
  2089. return entry;
  2090. }
  2091. static int qeth_init_input_buffer(struct qeth_card *card,
  2092. struct qeth_qdio_buffer *buf)
  2093. {
  2094. struct qeth_buffer_pool_entry *pool_entry;
  2095. int i;
  2096. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2097. if (!pool_entry)
  2098. return 1;
  2099. /*
  2100. * since the buffer is accessed only from the input_tasklet
  2101. * there shouldn't be a need to synchronize; also, since we use
  2102. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2103. * buffers
  2104. */
  2105. buf->pool_entry = pool_entry;
  2106. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2107. buf->buffer->element[i].length = PAGE_SIZE;
  2108. buf->buffer->element[i].addr = pool_entry->elements[i];
  2109. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2110. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2111. else
  2112. buf->buffer->element[i].flags = 0;
  2113. }
  2114. return 0;
  2115. }
  2116. int qeth_init_qdio_queues(struct qeth_card *card)
  2117. {
  2118. int i, j;
  2119. int rc;
  2120. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2121. /* inbound queue */
  2122. memset(card->qdio.in_q->qdio_bufs, 0,
  2123. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2124. qeth_initialize_working_pool_list(card);
  2125. /*give only as many buffers to hardware as we have buffer pool entries*/
  2126. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2127. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2128. card->qdio.in_q->next_buf_to_init =
  2129. card->qdio.in_buf_pool.buf_count - 1;
  2130. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2131. card->qdio.in_buf_pool.buf_count - 1);
  2132. if (rc) {
  2133. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2134. return rc;
  2135. }
  2136. /* outbound queue */
  2137. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2138. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2139. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2140. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2141. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2142. &card->qdio.out_qs[i]->bufs[j]);
  2143. }
  2144. card->qdio.out_qs[i]->card = card;
  2145. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2146. card->qdio.out_qs[i]->do_pack = 0;
  2147. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2148. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2149. atomic_set(&card->qdio.out_qs[i]->state,
  2150. QETH_OUT_Q_UNLOCKED);
  2151. }
  2152. return 0;
  2153. }
  2154. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2155. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2156. {
  2157. switch (link_type) {
  2158. case QETH_LINK_TYPE_HSTR:
  2159. return 2;
  2160. default:
  2161. return 1;
  2162. }
  2163. }
  2164. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2165. struct qeth_ipa_cmd *cmd, __u8 command,
  2166. enum qeth_prot_versions prot)
  2167. {
  2168. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2169. cmd->hdr.command = command;
  2170. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2171. cmd->hdr.seqno = card->seqno.ipa;
  2172. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2173. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2174. if (card->options.layer2)
  2175. cmd->hdr.prim_version_no = 2;
  2176. else
  2177. cmd->hdr.prim_version_no = 1;
  2178. cmd->hdr.param_count = 1;
  2179. cmd->hdr.prot_version = prot;
  2180. cmd->hdr.ipa_supported = 0;
  2181. cmd->hdr.ipa_enabled = 0;
  2182. }
  2183. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2184. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2185. {
  2186. struct qeth_cmd_buffer *iob;
  2187. struct qeth_ipa_cmd *cmd;
  2188. iob = qeth_wait_for_buffer(&card->write);
  2189. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2190. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2191. return iob;
  2192. }
  2193. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2194. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2195. char prot_type)
  2196. {
  2197. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2198. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2199. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2200. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2201. }
  2202. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2203. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2204. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2205. unsigned long),
  2206. void *reply_param)
  2207. {
  2208. int rc;
  2209. char prot_type;
  2210. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2211. if (card->options.layer2)
  2212. if (card->info.type == QETH_CARD_TYPE_OSN)
  2213. prot_type = QETH_PROT_OSN2;
  2214. else
  2215. prot_type = QETH_PROT_LAYER2;
  2216. else
  2217. prot_type = QETH_PROT_TCPIP;
  2218. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2219. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2220. iob, reply_cb, reply_param);
  2221. return rc;
  2222. }
  2223. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2224. static int qeth_send_startstoplan(struct qeth_card *card,
  2225. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2226. {
  2227. int rc;
  2228. struct qeth_cmd_buffer *iob;
  2229. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2230. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2231. return rc;
  2232. }
  2233. int qeth_send_startlan(struct qeth_card *card)
  2234. {
  2235. int rc;
  2236. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2237. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2238. return rc;
  2239. }
  2240. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2241. int qeth_send_stoplan(struct qeth_card *card)
  2242. {
  2243. int rc = 0;
  2244. /*
  2245. * TODO: according to the IPA format document page 14,
  2246. * TCP/IP (we!) never issue a STOPLAN
  2247. * is this right ?!?
  2248. */
  2249. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2250. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2251. return rc;
  2252. }
  2253. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2254. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2255. struct qeth_reply *reply, unsigned long data)
  2256. {
  2257. struct qeth_ipa_cmd *cmd;
  2258. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2259. cmd = (struct qeth_ipa_cmd *) data;
  2260. if (cmd->hdr.return_code == 0)
  2261. cmd->hdr.return_code =
  2262. cmd->data.setadapterparms.hdr.return_code;
  2263. return 0;
  2264. }
  2265. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2266. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2267. struct qeth_reply *reply, unsigned long data)
  2268. {
  2269. struct qeth_ipa_cmd *cmd;
  2270. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2271. cmd = (struct qeth_ipa_cmd *) data;
  2272. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2273. card->info.link_type =
  2274. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2275. card->options.adp.supported_funcs =
  2276. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2277. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2278. }
  2279. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2280. __u32 command, __u32 cmdlen)
  2281. {
  2282. struct qeth_cmd_buffer *iob;
  2283. struct qeth_ipa_cmd *cmd;
  2284. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2285. QETH_PROT_IPV4);
  2286. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2287. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2288. cmd->data.setadapterparms.hdr.command_code = command;
  2289. cmd->data.setadapterparms.hdr.used_total = 1;
  2290. cmd->data.setadapterparms.hdr.seq_no = 1;
  2291. return iob;
  2292. }
  2293. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2294. int qeth_query_setadapterparms(struct qeth_card *card)
  2295. {
  2296. int rc;
  2297. struct qeth_cmd_buffer *iob;
  2298. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2299. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2300. sizeof(struct qeth_ipacmd_setadpparms));
  2301. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2302. return rc;
  2303. }
  2304. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2305. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2306. unsigned int qdio_error, const char *dbftext)
  2307. {
  2308. if (qdio_error) {
  2309. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2310. QETH_DBF_TEXT(QERR, 2, dbftext);
  2311. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2312. buf->element[15].flags & 0xff);
  2313. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2314. buf->element[14].flags & 0xff);
  2315. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2316. if ((buf->element[15].flags & 0xff) == 0x12) {
  2317. card->stats.rx_dropped++;
  2318. return 0;
  2319. } else
  2320. return 1;
  2321. }
  2322. return 0;
  2323. }
  2324. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2325. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2326. {
  2327. struct qeth_qdio_q *queue = card->qdio.in_q;
  2328. int count;
  2329. int i;
  2330. int rc;
  2331. int newcount = 0;
  2332. count = (index < queue->next_buf_to_init)?
  2333. card->qdio.in_buf_pool.buf_count -
  2334. (queue->next_buf_to_init - index) :
  2335. card->qdio.in_buf_pool.buf_count -
  2336. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2337. /* only requeue at a certain threshold to avoid SIGAs */
  2338. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2339. for (i = queue->next_buf_to_init;
  2340. i < queue->next_buf_to_init + count; ++i) {
  2341. if (qeth_init_input_buffer(card,
  2342. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2343. break;
  2344. } else {
  2345. newcount++;
  2346. }
  2347. }
  2348. if (newcount < count) {
  2349. /* we are in memory shortage so we switch back to
  2350. traditional skb allocation and drop packages */
  2351. atomic_set(&card->force_alloc_skb, 3);
  2352. count = newcount;
  2353. } else {
  2354. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2355. }
  2356. /*
  2357. * according to old code it should be avoided to requeue all
  2358. * 128 buffers in order to benefit from PCI avoidance.
  2359. * this function keeps at least one buffer (the buffer at
  2360. * 'index') un-requeued -> this buffer is the first buffer that
  2361. * will be requeued the next time
  2362. */
  2363. if (card->options.performance_stats) {
  2364. card->perf_stats.inbound_do_qdio_cnt++;
  2365. card->perf_stats.inbound_do_qdio_start_time =
  2366. qeth_get_micros();
  2367. }
  2368. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2369. queue->next_buf_to_init, count);
  2370. if (card->options.performance_stats)
  2371. card->perf_stats.inbound_do_qdio_time +=
  2372. qeth_get_micros() -
  2373. card->perf_stats.inbound_do_qdio_start_time;
  2374. if (rc) {
  2375. dev_warn(&card->gdev->dev,
  2376. "QDIO reported an error, rc=%i\n", rc);
  2377. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2378. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2379. }
  2380. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2381. QDIO_MAX_BUFFERS_PER_Q;
  2382. }
  2383. }
  2384. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2385. static int qeth_handle_send_error(struct qeth_card *card,
  2386. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2387. {
  2388. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2389. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2390. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2391. if (sbalf15 == 0) {
  2392. qdio_err = 0;
  2393. } else {
  2394. qdio_err = 1;
  2395. }
  2396. }
  2397. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2398. if (!qdio_err)
  2399. return QETH_SEND_ERROR_NONE;
  2400. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2401. return QETH_SEND_ERROR_RETRY;
  2402. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2403. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2404. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2405. (u16)qdio_err, (u8)sbalf15);
  2406. return QETH_SEND_ERROR_LINK_FAILURE;
  2407. }
  2408. /*
  2409. * Switched to packing state if the number of used buffers on a queue
  2410. * reaches a certain limit.
  2411. */
  2412. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2413. {
  2414. if (!queue->do_pack) {
  2415. if (atomic_read(&queue->used_buffers)
  2416. >= QETH_HIGH_WATERMARK_PACK){
  2417. /* switch non-PACKING -> PACKING */
  2418. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2419. if (queue->card->options.performance_stats)
  2420. queue->card->perf_stats.sc_dp_p++;
  2421. queue->do_pack = 1;
  2422. }
  2423. }
  2424. }
  2425. /*
  2426. * Switches from packing to non-packing mode. If there is a packing
  2427. * buffer on the queue this buffer will be prepared to be flushed.
  2428. * In that case 1 is returned to inform the caller. If no buffer
  2429. * has to be flushed, zero is returned.
  2430. */
  2431. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2432. {
  2433. struct qeth_qdio_out_buffer *buffer;
  2434. int flush_count = 0;
  2435. if (queue->do_pack) {
  2436. if (atomic_read(&queue->used_buffers)
  2437. <= QETH_LOW_WATERMARK_PACK) {
  2438. /* switch PACKING -> non-PACKING */
  2439. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2440. if (queue->card->options.performance_stats)
  2441. queue->card->perf_stats.sc_p_dp++;
  2442. queue->do_pack = 0;
  2443. /* flush packing buffers */
  2444. buffer = &queue->bufs[queue->next_buf_to_fill];
  2445. if ((atomic_read(&buffer->state) ==
  2446. QETH_QDIO_BUF_EMPTY) &&
  2447. (buffer->next_element_to_fill > 0)) {
  2448. atomic_set(&buffer->state,
  2449. QETH_QDIO_BUF_PRIMED);
  2450. flush_count++;
  2451. queue->next_buf_to_fill =
  2452. (queue->next_buf_to_fill + 1) %
  2453. QDIO_MAX_BUFFERS_PER_Q;
  2454. }
  2455. }
  2456. }
  2457. return flush_count;
  2458. }
  2459. /*
  2460. * Called to flush a packing buffer if no more pci flags are on the queue.
  2461. * Checks if there is a packing buffer and prepares it to be flushed.
  2462. * In that case returns 1, otherwise zero.
  2463. */
  2464. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2465. {
  2466. struct qeth_qdio_out_buffer *buffer;
  2467. buffer = &queue->bufs[queue->next_buf_to_fill];
  2468. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2469. (buffer->next_element_to_fill > 0)) {
  2470. /* it's a packing buffer */
  2471. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2472. queue->next_buf_to_fill =
  2473. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2474. return 1;
  2475. }
  2476. return 0;
  2477. }
  2478. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2479. int count)
  2480. {
  2481. struct qeth_qdio_out_buffer *buf;
  2482. int rc;
  2483. int i;
  2484. unsigned int qdio_flags;
  2485. for (i = index; i < index + count; ++i) {
  2486. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2487. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2488. SBAL_FLAGS_LAST_ENTRY;
  2489. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2490. continue;
  2491. if (!queue->do_pack) {
  2492. if ((atomic_read(&queue->used_buffers) >=
  2493. (QETH_HIGH_WATERMARK_PACK -
  2494. QETH_WATERMARK_PACK_FUZZ)) &&
  2495. !atomic_read(&queue->set_pci_flags_count)) {
  2496. /* it's likely that we'll go to packing
  2497. * mode soon */
  2498. atomic_inc(&queue->set_pci_flags_count);
  2499. buf->buffer->element[0].flags |= 0x40;
  2500. }
  2501. } else {
  2502. if (!atomic_read(&queue->set_pci_flags_count)) {
  2503. /*
  2504. * there's no outstanding PCI any more, so we
  2505. * have to request a PCI to be sure the the PCI
  2506. * will wake at some time in the future then we
  2507. * can flush packed buffers that might still be
  2508. * hanging around, which can happen if no
  2509. * further send was requested by the stack
  2510. */
  2511. atomic_inc(&queue->set_pci_flags_count);
  2512. buf->buffer->element[0].flags |= 0x40;
  2513. }
  2514. }
  2515. }
  2516. queue->sync_iqdio_error = 0;
  2517. queue->card->dev->trans_start = jiffies;
  2518. if (queue->card->options.performance_stats) {
  2519. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2520. queue->card->perf_stats.outbound_do_qdio_start_time =
  2521. qeth_get_micros();
  2522. }
  2523. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2524. if (atomic_read(&queue->set_pci_flags_count))
  2525. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2526. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2527. queue->queue_no, index, count);
  2528. if (queue->card->options.performance_stats)
  2529. queue->card->perf_stats.outbound_do_qdio_time +=
  2530. qeth_get_micros() -
  2531. queue->card->perf_stats.outbound_do_qdio_start_time;
  2532. if (rc > 0) {
  2533. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2534. queue->sync_iqdio_error = rc & 3;
  2535. }
  2536. if (rc) {
  2537. queue->card->stats.tx_errors += count;
  2538. /* ignore temporary SIGA errors without busy condition */
  2539. if (rc == QDIO_ERROR_SIGA_TARGET)
  2540. return;
  2541. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2542. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2543. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2544. /* this must not happen under normal circumstances. if it
  2545. * happens something is really wrong -> recover */
  2546. qeth_schedule_recovery(queue->card);
  2547. return;
  2548. }
  2549. atomic_add(count, &queue->used_buffers);
  2550. if (queue->card->options.performance_stats)
  2551. queue->card->perf_stats.bufs_sent += count;
  2552. }
  2553. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2554. {
  2555. int index;
  2556. int flush_cnt = 0;
  2557. int q_was_packing = 0;
  2558. /*
  2559. * check if weed have to switch to non-packing mode or if
  2560. * we have to get a pci flag out on the queue
  2561. */
  2562. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2563. !atomic_read(&queue->set_pci_flags_count)) {
  2564. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2565. QETH_OUT_Q_UNLOCKED) {
  2566. /*
  2567. * If we get in here, there was no action in
  2568. * do_send_packet. So, we check if there is a
  2569. * packing buffer to be flushed here.
  2570. */
  2571. netif_stop_queue(queue->card->dev);
  2572. index = queue->next_buf_to_fill;
  2573. q_was_packing = queue->do_pack;
  2574. /* queue->do_pack may change */
  2575. barrier();
  2576. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2577. if (!flush_cnt &&
  2578. !atomic_read(&queue->set_pci_flags_count))
  2579. flush_cnt +=
  2580. qeth_flush_buffers_on_no_pci(queue);
  2581. if (queue->card->options.performance_stats &&
  2582. q_was_packing)
  2583. queue->card->perf_stats.bufs_sent_pack +=
  2584. flush_cnt;
  2585. if (flush_cnt)
  2586. qeth_flush_buffers(queue, index, flush_cnt);
  2587. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2588. }
  2589. }
  2590. }
  2591. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2592. unsigned int qdio_error, int __queue, int first_element,
  2593. int count, unsigned long card_ptr)
  2594. {
  2595. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2596. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2597. struct qeth_qdio_out_buffer *buffer;
  2598. int i;
  2599. unsigned qeth_send_err;
  2600. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2601. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2602. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2603. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2604. netif_stop_queue(card->dev);
  2605. qeth_schedule_recovery(card);
  2606. return;
  2607. }
  2608. if (card->options.performance_stats) {
  2609. card->perf_stats.outbound_handler_cnt++;
  2610. card->perf_stats.outbound_handler_start_time =
  2611. qeth_get_micros();
  2612. }
  2613. for (i = first_element; i < (first_element + count); ++i) {
  2614. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2615. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2616. __qeth_clear_output_buffer(queue, buffer,
  2617. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2618. }
  2619. atomic_sub(count, &queue->used_buffers);
  2620. /* check if we need to do something on this outbound queue */
  2621. if (card->info.type != QETH_CARD_TYPE_IQD)
  2622. qeth_check_outbound_queue(queue);
  2623. netif_wake_queue(queue->card->dev);
  2624. if (card->options.performance_stats)
  2625. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2626. card->perf_stats.outbound_handler_start_time;
  2627. }
  2628. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2629. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2630. int ipv, int cast_type)
  2631. {
  2632. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2633. return card->qdio.default_out_queue;
  2634. switch (card->qdio.no_out_queues) {
  2635. case 4:
  2636. if (cast_type && card->info.is_multicast_different)
  2637. return card->info.is_multicast_different &
  2638. (card->qdio.no_out_queues - 1);
  2639. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2640. const u8 tos = ip_hdr(skb)->tos;
  2641. if (card->qdio.do_prio_queueing ==
  2642. QETH_PRIO_Q_ING_TOS) {
  2643. if (tos & IP_TOS_NOTIMPORTANT)
  2644. return 3;
  2645. if (tos & IP_TOS_HIGHRELIABILITY)
  2646. return 2;
  2647. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2648. return 1;
  2649. if (tos & IP_TOS_LOWDELAY)
  2650. return 0;
  2651. }
  2652. if (card->qdio.do_prio_queueing ==
  2653. QETH_PRIO_Q_ING_PREC)
  2654. return 3 - (tos >> 6);
  2655. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2656. /* TODO: IPv6!!! */
  2657. }
  2658. return card->qdio.default_out_queue;
  2659. case 1: /* fallthrough for single-out-queue 1920-device */
  2660. default:
  2661. return card->qdio.default_out_queue;
  2662. }
  2663. }
  2664. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2665. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2666. struct sk_buff *skb, int elems)
  2667. {
  2668. int elements_needed = 0;
  2669. if (skb_shinfo(skb)->nr_frags > 0)
  2670. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2671. if (elements_needed == 0)
  2672. elements_needed = 1 + (((((unsigned long) skb->data) %
  2673. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2674. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2675. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2676. "(Number=%d / Length=%d). Discarded.\n",
  2677. (elements_needed+elems), skb->len);
  2678. return 0;
  2679. }
  2680. return elements_needed;
  2681. }
  2682. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2683. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2684. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2685. int offset)
  2686. {
  2687. int length = skb->len;
  2688. int length_here;
  2689. int element;
  2690. char *data;
  2691. int first_lap ;
  2692. element = *next_element_to_fill;
  2693. data = skb->data;
  2694. first_lap = (is_tso == 0 ? 1 : 0);
  2695. if (offset >= 0) {
  2696. data = skb->data + offset;
  2697. length -= offset;
  2698. first_lap = 0;
  2699. }
  2700. while (length > 0) {
  2701. /* length_here is the remaining amount of data in this page */
  2702. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2703. if (length < length_here)
  2704. length_here = length;
  2705. buffer->element[element].addr = data;
  2706. buffer->element[element].length = length_here;
  2707. length -= length_here;
  2708. if (!length) {
  2709. if (first_lap)
  2710. buffer->element[element].flags = 0;
  2711. else
  2712. buffer->element[element].flags =
  2713. SBAL_FLAGS_LAST_FRAG;
  2714. } else {
  2715. if (first_lap)
  2716. buffer->element[element].flags =
  2717. SBAL_FLAGS_FIRST_FRAG;
  2718. else
  2719. buffer->element[element].flags =
  2720. SBAL_FLAGS_MIDDLE_FRAG;
  2721. }
  2722. data += length_here;
  2723. element++;
  2724. first_lap = 0;
  2725. }
  2726. *next_element_to_fill = element;
  2727. }
  2728. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2729. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2730. struct qeth_hdr *hdr, int offset, int hd_len)
  2731. {
  2732. struct qdio_buffer *buffer;
  2733. int flush_cnt = 0, hdr_len, large_send = 0;
  2734. buffer = buf->buffer;
  2735. atomic_inc(&skb->users);
  2736. skb_queue_tail(&buf->skb_list, skb);
  2737. /*check first on TSO ....*/
  2738. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2739. int element = buf->next_element_to_fill;
  2740. hdr_len = sizeof(struct qeth_hdr_tso) +
  2741. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2742. /*fill first buffer entry only with header information */
  2743. buffer->element[element].addr = skb->data;
  2744. buffer->element[element].length = hdr_len;
  2745. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2746. buf->next_element_to_fill++;
  2747. skb->data += hdr_len;
  2748. skb->len -= hdr_len;
  2749. large_send = 1;
  2750. }
  2751. if (offset >= 0) {
  2752. int element = buf->next_element_to_fill;
  2753. buffer->element[element].addr = hdr;
  2754. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2755. hd_len;
  2756. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2757. buf->is_header[element] = 1;
  2758. buf->next_element_to_fill++;
  2759. }
  2760. if (skb_shinfo(skb)->nr_frags == 0)
  2761. __qeth_fill_buffer(skb, buffer, large_send,
  2762. (int *)&buf->next_element_to_fill, offset);
  2763. else
  2764. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2765. (int *)&buf->next_element_to_fill);
  2766. if (!queue->do_pack) {
  2767. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2768. /* set state to PRIMED -> will be flushed */
  2769. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2770. flush_cnt = 1;
  2771. } else {
  2772. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2773. if (queue->card->options.performance_stats)
  2774. queue->card->perf_stats.skbs_sent_pack++;
  2775. if (buf->next_element_to_fill >=
  2776. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2777. /*
  2778. * packed buffer if full -> set state PRIMED
  2779. * -> will be flushed
  2780. */
  2781. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2782. flush_cnt = 1;
  2783. }
  2784. }
  2785. return flush_cnt;
  2786. }
  2787. int qeth_do_send_packet_fast(struct qeth_card *card,
  2788. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2789. struct qeth_hdr *hdr, int elements_needed,
  2790. int offset, int hd_len)
  2791. {
  2792. struct qeth_qdio_out_buffer *buffer;
  2793. struct sk_buff *skb1;
  2794. struct qeth_skb_data *retry_ctrl;
  2795. int index;
  2796. int rc;
  2797. /* spin until we get the queue ... */
  2798. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2799. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2800. /* ... now we've got the queue */
  2801. index = queue->next_buf_to_fill;
  2802. buffer = &queue->bufs[queue->next_buf_to_fill];
  2803. /*
  2804. * check if buffer is empty to make sure that we do not 'overtake'
  2805. * ourselves and try to fill a buffer that is already primed
  2806. */
  2807. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2808. goto out;
  2809. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2810. QDIO_MAX_BUFFERS_PER_Q;
  2811. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2812. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2813. qeth_flush_buffers(queue, index, 1);
  2814. if (queue->sync_iqdio_error == 2) {
  2815. skb1 = skb_dequeue(&buffer->skb_list);
  2816. while (skb1) {
  2817. atomic_dec(&skb1->users);
  2818. skb1 = skb_dequeue(&buffer->skb_list);
  2819. }
  2820. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2821. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2822. retry_ctrl->magic = QETH_SKB_MAGIC;
  2823. retry_ctrl->count = 0;
  2824. }
  2825. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2826. retry_ctrl->count++;
  2827. rc = dev_queue_xmit(skb);
  2828. } else {
  2829. dev_kfree_skb_any(skb);
  2830. QETH_DBF_TEXT(QERR, 2, "qrdrop");
  2831. }
  2832. }
  2833. return 0;
  2834. out:
  2835. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2836. return -EBUSY;
  2837. }
  2838. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2839. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2840. struct sk_buff *skb, struct qeth_hdr *hdr,
  2841. int elements_needed)
  2842. {
  2843. struct qeth_qdio_out_buffer *buffer;
  2844. int start_index;
  2845. int flush_count = 0;
  2846. int do_pack = 0;
  2847. int tmp;
  2848. int rc = 0;
  2849. /* spin until we get the queue ... */
  2850. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2851. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2852. start_index = queue->next_buf_to_fill;
  2853. buffer = &queue->bufs[queue->next_buf_to_fill];
  2854. /*
  2855. * check if buffer is empty to make sure that we do not 'overtake'
  2856. * ourselves and try to fill a buffer that is already primed
  2857. */
  2858. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2859. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2860. return -EBUSY;
  2861. }
  2862. /* check if we need to switch packing state of this queue */
  2863. qeth_switch_to_packing_if_needed(queue);
  2864. if (queue->do_pack) {
  2865. do_pack = 1;
  2866. /* does packet fit in current buffer? */
  2867. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2868. buffer->next_element_to_fill) < elements_needed) {
  2869. /* ... no -> set state PRIMED */
  2870. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2871. flush_count++;
  2872. queue->next_buf_to_fill =
  2873. (queue->next_buf_to_fill + 1) %
  2874. QDIO_MAX_BUFFERS_PER_Q;
  2875. buffer = &queue->bufs[queue->next_buf_to_fill];
  2876. /* we did a step forward, so check buffer state
  2877. * again */
  2878. if (atomic_read(&buffer->state) !=
  2879. QETH_QDIO_BUF_EMPTY) {
  2880. qeth_flush_buffers(queue, start_index,
  2881. flush_count);
  2882. atomic_set(&queue->state,
  2883. QETH_OUT_Q_UNLOCKED);
  2884. return -EBUSY;
  2885. }
  2886. }
  2887. }
  2888. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2889. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2890. QDIO_MAX_BUFFERS_PER_Q;
  2891. flush_count += tmp;
  2892. if (flush_count)
  2893. qeth_flush_buffers(queue, start_index, flush_count);
  2894. else if (!atomic_read(&queue->set_pci_flags_count))
  2895. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2896. /*
  2897. * queue->state will go from LOCKED -> UNLOCKED or from
  2898. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2899. * (switch packing state or flush buffer to get another pci flag out).
  2900. * In that case we will enter this loop
  2901. */
  2902. while (atomic_dec_return(&queue->state)) {
  2903. flush_count = 0;
  2904. start_index = queue->next_buf_to_fill;
  2905. /* check if we can go back to non-packing state */
  2906. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2907. /*
  2908. * check if we need to flush a packing buffer to get a pci
  2909. * flag out on the queue
  2910. */
  2911. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2912. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2913. if (flush_count)
  2914. qeth_flush_buffers(queue, start_index, flush_count);
  2915. }
  2916. /* at this point the queue is UNLOCKED again */
  2917. if (queue->card->options.performance_stats && do_pack)
  2918. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2919. return rc;
  2920. }
  2921. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2922. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2923. struct qeth_reply *reply, unsigned long data)
  2924. {
  2925. struct qeth_ipa_cmd *cmd;
  2926. struct qeth_ipacmd_setadpparms *setparms;
  2927. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2928. cmd = (struct qeth_ipa_cmd *) data;
  2929. setparms = &(cmd->data.setadapterparms);
  2930. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2931. if (cmd->hdr.return_code) {
  2932. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2933. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2934. }
  2935. card->info.promisc_mode = setparms->data.mode;
  2936. return 0;
  2937. }
  2938. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2939. {
  2940. enum qeth_ipa_promisc_modes mode;
  2941. struct net_device *dev = card->dev;
  2942. struct qeth_cmd_buffer *iob;
  2943. struct qeth_ipa_cmd *cmd;
  2944. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2945. if (((dev->flags & IFF_PROMISC) &&
  2946. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2947. (!(dev->flags & IFF_PROMISC) &&
  2948. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2949. return;
  2950. mode = SET_PROMISC_MODE_OFF;
  2951. if (dev->flags & IFF_PROMISC)
  2952. mode = SET_PROMISC_MODE_ON;
  2953. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2954. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2955. sizeof(struct qeth_ipacmd_setadpparms));
  2956. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2957. cmd->data.setadapterparms.data.mode = mode;
  2958. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2959. }
  2960. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2961. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2962. {
  2963. struct qeth_card *card;
  2964. char dbf_text[15];
  2965. card = dev->ml_priv;
  2966. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2967. sprintf(dbf_text, "%8x", new_mtu);
  2968. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2969. if (new_mtu < 64)
  2970. return -EINVAL;
  2971. if (new_mtu > 65535)
  2972. return -EINVAL;
  2973. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2974. (!qeth_mtu_is_valid(card, new_mtu)))
  2975. return -EINVAL;
  2976. dev->mtu = new_mtu;
  2977. return 0;
  2978. }
  2979. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2980. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2981. {
  2982. struct qeth_card *card;
  2983. card = dev->ml_priv;
  2984. QETH_DBF_TEXT(TRACE, 5, "getstat");
  2985. return &card->stats;
  2986. }
  2987. EXPORT_SYMBOL_GPL(qeth_get_stats);
  2988. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  2989. struct qeth_reply *reply, unsigned long data)
  2990. {
  2991. struct qeth_ipa_cmd *cmd;
  2992. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  2993. cmd = (struct qeth_ipa_cmd *) data;
  2994. if (!card->options.layer2 ||
  2995. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  2996. memcpy(card->dev->dev_addr,
  2997. &cmd->data.setadapterparms.data.change_addr.addr,
  2998. OSA_ADDR_LEN);
  2999. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3000. }
  3001. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3002. return 0;
  3003. }
  3004. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3005. {
  3006. int rc;
  3007. struct qeth_cmd_buffer *iob;
  3008. struct qeth_ipa_cmd *cmd;
  3009. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3010. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3011. sizeof(struct qeth_ipacmd_setadpparms));
  3012. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3013. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3014. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3015. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3016. card->dev->dev_addr, OSA_ADDR_LEN);
  3017. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3018. NULL);
  3019. return rc;
  3020. }
  3021. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3022. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3023. struct qeth_reply *reply, unsigned long data)
  3024. {
  3025. struct qeth_ipa_cmd *cmd;
  3026. struct qeth_set_access_ctrl *access_ctrl_req;
  3027. int rc;
  3028. QETH_DBF_TEXT(TRACE, 4, "setaccb");
  3029. cmd = (struct qeth_ipa_cmd *) data;
  3030. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3031. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3032. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3033. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3034. cmd->data.setadapterparms.hdr.return_code);
  3035. switch (cmd->data.setadapterparms.hdr.return_code) {
  3036. case SET_ACCESS_CTRL_RC_SUCCESS:
  3037. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3038. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3039. {
  3040. card->options.isolation = access_ctrl_req->subcmd_code;
  3041. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3042. dev_info(&card->gdev->dev,
  3043. "QDIO data connection isolation is deactivated\n");
  3044. } else {
  3045. dev_info(&card->gdev->dev,
  3046. "QDIO data connection isolation is activated\n");
  3047. }
  3048. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3049. card->gdev->dev.kobj.name,
  3050. access_ctrl_req->subcmd_code,
  3051. cmd->data.setadapterparms.hdr.return_code);
  3052. rc = 0;
  3053. break;
  3054. }
  3055. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3056. {
  3057. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3058. card->gdev->dev.kobj.name,
  3059. access_ctrl_req->subcmd_code,
  3060. cmd->data.setadapterparms.hdr.return_code);
  3061. dev_err(&card->gdev->dev, "Adapter does not "
  3062. "support QDIO data connection isolation\n");
  3063. /* ensure isolation mode is "none" */
  3064. card->options.isolation = ISOLATION_MODE_NONE;
  3065. rc = -EOPNOTSUPP;
  3066. break;
  3067. }
  3068. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3069. {
  3070. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3071. card->gdev->dev.kobj.name,
  3072. access_ctrl_req->subcmd_code,
  3073. cmd->data.setadapterparms.hdr.return_code);
  3074. dev_err(&card->gdev->dev,
  3075. "Adapter is dedicated. "
  3076. "QDIO data connection isolation not supported\n");
  3077. /* ensure isolation mode is "none" */
  3078. card->options.isolation = ISOLATION_MODE_NONE;
  3079. rc = -EOPNOTSUPP;
  3080. break;
  3081. }
  3082. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3083. {
  3084. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3085. card->gdev->dev.kobj.name,
  3086. access_ctrl_req->subcmd_code,
  3087. cmd->data.setadapterparms.hdr.return_code);
  3088. dev_err(&card->gdev->dev,
  3089. "TSO does not permit QDIO data connection isolation\n");
  3090. /* ensure isolation mode is "none" */
  3091. card->options.isolation = ISOLATION_MODE_NONE;
  3092. rc = -EPERM;
  3093. break;
  3094. }
  3095. default:
  3096. {
  3097. /* this should never happen */
  3098. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3099. "==UNKNOWN\n",
  3100. card->gdev->dev.kobj.name,
  3101. access_ctrl_req->subcmd_code,
  3102. cmd->data.setadapterparms.hdr.return_code);
  3103. /* ensure isolation mode is "none" */
  3104. card->options.isolation = ISOLATION_MODE_NONE;
  3105. rc = 0;
  3106. break;
  3107. }
  3108. }
  3109. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3110. return rc;
  3111. }
  3112. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3113. enum qeth_ipa_isolation_modes isolation)
  3114. {
  3115. int rc;
  3116. struct qeth_cmd_buffer *iob;
  3117. struct qeth_ipa_cmd *cmd;
  3118. struct qeth_set_access_ctrl *access_ctrl_req;
  3119. QETH_DBF_TEXT(TRACE, 4, "setacctl");
  3120. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3121. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3122. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3123. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3124. sizeof(struct qeth_set_access_ctrl));
  3125. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3126. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3127. access_ctrl_req->subcmd_code = isolation;
  3128. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3129. NULL);
  3130. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3131. return rc;
  3132. }
  3133. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3134. {
  3135. int rc = 0;
  3136. QETH_DBF_TEXT(TRACE, 4, "setactlo");
  3137. if (card->info.type == QETH_CARD_TYPE_OSAE &&
  3138. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3139. rc = qeth_setadpparms_set_access_ctrl(card,
  3140. card->options.isolation);
  3141. if (rc) {
  3142. QETH_DBF_MESSAGE(3,
  3143. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed",
  3144. card->gdev->dev.kobj.name,
  3145. rc);
  3146. }
  3147. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3148. card->options.isolation = ISOLATION_MODE_NONE;
  3149. dev_err(&card->gdev->dev, "Adapter does not "
  3150. "support QDIO data connection isolation\n");
  3151. rc = -EOPNOTSUPP;
  3152. }
  3153. return rc;
  3154. }
  3155. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3156. void qeth_tx_timeout(struct net_device *dev)
  3157. {
  3158. struct qeth_card *card;
  3159. QETH_DBF_TEXT(TRACE, 4, "txtimeo");
  3160. card = dev->ml_priv;
  3161. card->stats.tx_errors++;
  3162. qeth_schedule_recovery(card);
  3163. }
  3164. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3165. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3166. {
  3167. struct qeth_card *card = dev->ml_priv;
  3168. int rc = 0;
  3169. switch (regnum) {
  3170. case MII_BMCR: /* Basic mode control register */
  3171. rc = BMCR_FULLDPLX;
  3172. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3173. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3174. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3175. rc |= BMCR_SPEED100;
  3176. break;
  3177. case MII_BMSR: /* Basic mode status register */
  3178. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3179. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3180. BMSR_100BASE4;
  3181. break;
  3182. case MII_PHYSID1: /* PHYS ID 1 */
  3183. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3184. dev->dev_addr[2];
  3185. rc = (rc >> 5) & 0xFFFF;
  3186. break;
  3187. case MII_PHYSID2: /* PHYS ID 2 */
  3188. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3189. break;
  3190. case MII_ADVERTISE: /* Advertisement control reg */
  3191. rc = ADVERTISE_ALL;
  3192. break;
  3193. case MII_LPA: /* Link partner ability reg */
  3194. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3195. LPA_100BASE4 | LPA_LPACK;
  3196. break;
  3197. case MII_EXPANSION: /* Expansion register */
  3198. break;
  3199. case MII_DCOUNTER: /* disconnect counter */
  3200. break;
  3201. case MII_FCSCOUNTER: /* false carrier counter */
  3202. break;
  3203. case MII_NWAYTEST: /* N-way auto-neg test register */
  3204. break;
  3205. case MII_RERRCOUNTER: /* rx error counter */
  3206. rc = card->stats.rx_errors;
  3207. break;
  3208. case MII_SREVISION: /* silicon revision */
  3209. break;
  3210. case MII_RESV1: /* reserved 1 */
  3211. break;
  3212. case MII_LBRERROR: /* loopback, rx, bypass error */
  3213. break;
  3214. case MII_PHYADDR: /* physical address */
  3215. break;
  3216. case MII_RESV2: /* reserved 2 */
  3217. break;
  3218. case MII_TPISTATUS: /* TPI status for 10mbps */
  3219. break;
  3220. case MII_NCONFIG: /* network interface config */
  3221. break;
  3222. default:
  3223. break;
  3224. }
  3225. return rc;
  3226. }
  3227. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3228. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3229. struct qeth_cmd_buffer *iob, int len,
  3230. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3231. unsigned long),
  3232. void *reply_param)
  3233. {
  3234. u16 s1, s2;
  3235. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3236. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3237. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3238. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3239. /* adjust PDU length fields in IPA_PDU_HEADER */
  3240. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3241. s2 = (u32) len;
  3242. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3243. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3244. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3245. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3246. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3247. reply_cb, reply_param);
  3248. }
  3249. static int qeth_snmp_command_cb(struct qeth_card *card,
  3250. struct qeth_reply *reply, unsigned long sdata)
  3251. {
  3252. struct qeth_ipa_cmd *cmd;
  3253. struct qeth_arp_query_info *qinfo;
  3254. struct qeth_snmp_cmd *snmp;
  3255. unsigned char *data;
  3256. __u16 data_len;
  3257. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3258. cmd = (struct qeth_ipa_cmd *) sdata;
  3259. data = (unsigned char *)((char *)cmd - reply->offset);
  3260. qinfo = (struct qeth_arp_query_info *) reply->param;
  3261. snmp = &cmd->data.setadapterparms.data.snmp;
  3262. if (cmd->hdr.return_code) {
  3263. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3264. return 0;
  3265. }
  3266. if (cmd->data.setadapterparms.hdr.return_code) {
  3267. cmd->hdr.return_code =
  3268. cmd->data.setadapterparms.hdr.return_code;
  3269. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3270. return 0;
  3271. }
  3272. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3273. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3274. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3275. else
  3276. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3277. /* check if there is enough room in userspace */
  3278. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3279. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3280. cmd->hdr.return_code = -ENOMEM;
  3281. return 0;
  3282. }
  3283. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3284. cmd->data.setadapterparms.hdr.used_total);
  3285. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3286. cmd->data.setadapterparms.hdr.seq_no);
  3287. /*copy entries to user buffer*/
  3288. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3289. memcpy(qinfo->udata + qinfo->udata_offset,
  3290. (char *)snmp,
  3291. data_len + offsetof(struct qeth_snmp_cmd, data));
  3292. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3293. } else {
  3294. memcpy(qinfo->udata + qinfo->udata_offset,
  3295. (char *)&snmp->request, data_len);
  3296. }
  3297. qinfo->udata_offset += data_len;
  3298. /* check if all replies received ... */
  3299. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3300. cmd->data.setadapterparms.hdr.used_total);
  3301. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3302. cmd->data.setadapterparms.hdr.seq_no);
  3303. if (cmd->data.setadapterparms.hdr.seq_no <
  3304. cmd->data.setadapterparms.hdr.used_total)
  3305. return 1;
  3306. return 0;
  3307. }
  3308. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3309. {
  3310. struct qeth_cmd_buffer *iob;
  3311. struct qeth_ipa_cmd *cmd;
  3312. struct qeth_snmp_ureq *ureq;
  3313. int req_len;
  3314. struct qeth_arp_query_info qinfo = {0, };
  3315. int rc = 0;
  3316. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3317. if (card->info.guestlan)
  3318. return -EOPNOTSUPP;
  3319. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3320. (!card->options.layer2)) {
  3321. return -EOPNOTSUPP;
  3322. }
  3323. /* skip 4 bytes (data_len struct member) to get req_len */
  3324. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3325. return -EFAULT;
  3326. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3327. if (!ureq) {
  3328. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3329. return -ENOMEM;
  3330. }
  3331. if (copy_from_user(ureq, udata,
  3332. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3333. kfree(ureq);
  3334. return -EFAULT;
  3335. }
  3336. qinfo.udata_len = ureq->hdr.data_len;
  3337. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3338. if (!qinfo.udata) {
  3339. kfree(ureq);
  3340. return -ENOMEM;
  3341. }
  3342. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3343. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3344. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3345. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3346. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3347. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3348. qeth_snmp_command_cb, (void *)&qinfo);
  3349. if (rc)
  3350. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3351. QETH_CARD_IFNAME(card), rc);
  3352. else {
  3353. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3354. rc = -EFAULT;
  3355. }
  3356. kfree(ureq);
  3357. kfree(qinfo.udata);
  3358. return rc;
  3359. }
  3360. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3361. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3362. {
  3363. switch (card->info.type) {
  3364. case QETH_CARD_TYPE_IQD:
  3365. return 2;
  3366. default:
  3367. return 0;
  3368. }
  3369. }
  3370. static int qeth_qdio_establish(struct qeth_card *card)
  3371. {
  3372. struct qdio_initialize init_data;
  3373. char *qib_param_field;
  3374. struct qdio_buffer **in_sbal_ptrs;
  3375. struct qdio_buffer **out_sbal_ptrs;
  3376. int i, j, k;
  3377. int rc = 0;
  3378. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3379. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3380. GFP_KERNEL);
  3381. if (!qib_param_field)
  3382. return -ENOMEM;
  3383. qeth_create_qib_param_field(card, qib_param_field);
  3384. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3385. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3386. GFP_KERNEL);
  3387. if (!in_sbal_ptrs) {
  3388. kfree(qib_param_field);
  3389. return -ENOMEM;
  3390. }
  3391. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3392. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3393. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3394. out_sbal_ptrs =
  3395. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3396. sizeof(void *), GFP_KERNEL);
  3397. if (!out_sbal_ptrs) {
  3398. kfree(in_sbal_ptrs);
  3399. kfree(qib_param_field);
  3400. return -ENOMEM;
  3401. }
  3402. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3403. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3404. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3405. card->qdio.out_qs[i]->bufs[j].buffer);
  3406. }
  3407. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3408. init_data.cdev = CARD_DDEV(card);
  3409. init_data.q_format = qeth_get_qdio_q_format(card);
  3410. init_data.qib_param_field_format = 0;
  3411. init_data.qib_param_field = qib_param_field;
  3412. init_data.no_input_qs = 1;
  3413. init_data.no_output_qs = card->qdio.no_out_queues;
  3414. init_data.input_handler = card->discipline.input_handler;
  3415. init_data.output_handler = card->discipline.output_handler;
  3416. init_data.int_parm = (unsigned long) card;
  3417. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3418. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3419. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3420. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3421. rc = qdio_allocate(&init_data);
  3422. if (rc) {
  3423. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3424. goto out;
  3425. }
  3426. rc = qdio_establish(&init_data);
  3427. if (rc) {
  3428. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3429. qdio_free(CARD_DDEV(card));
  3430. }
  3431. }
  3432. out:
  3433. kfree(out_sbal_ptrs);
  3434. kfree(in_sbal_ptrs);
  3435. kfree(qib_param_field);
  3436. return rc;
  3437. }
  3438. static void qeth_core_free_card(struct qeth_card *card)
  3439. {
  3440. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3441. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3442. qeth_clean_channel(&card->read);
  3443. qeth_clean_channel(&card->write);
  3444. if (card->dev)
  3445. free_netdev(card->dev);
  3446. kfree(card->ip_tbd_list);
  3447. qeth_free_qdio_buffers(card);
  3448. unregister_service_level(&card->qeth_service_level);
  3449. kfree(card);
  3450. }
  3451. static struct ccw_device_id qeth_ids[] = {
  3452. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3453. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3454. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3455. {},
  3456. };
  3457. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3458. static struct ccw_driver qeth_ccw_driver = {
  3459. .name = "qeth",
  3460. .ids = qeth_ids,
  3461. .probe = ccwgroup_probe_ccwdev,
  3462. .remove = ccwgroup_remove_ccwdev,
  3463. };
  3464. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3465. unsigned long driver_id)
  3466. {
  3467. return ccwgroup_create_from_string(root_dev, driver_id,
  3468. &qeth_ccw_driver, 3, buf);
  3469. }
  3470. int qeth_core_hardsetup_card(struct qeth_card *card)
  3471. {
  3472. int retries = 0;
  3473. int rc;
  3474. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3475. atomic_set(&card->force_alloc_skb, 0);
  3476. retry:
  3477. if (retries)
  3478. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3479. dev_name(&card->gdev->dev));
  3480. ccw_device_set_offline(CARD_DDEV(card));
  3481. ccw_device_set_offline(CARD_WDEV(card));
  3482. ccw_device_set_offline(CARD_RDEV(card));
  3483. rc = ccw_device_set_online(CARD_RDEV(card));
  3484. if (rc)
  3485. goto retriable;
  3486. rc = ccw_device_set_online(CARD_WDEV(card));
  3487. if (rc)
  3488. goto retriable;
  3489. rc = ccw_device_set_online(CARD_DDEV(card));
  3490. if (rc)
  3491. goto retriable;
  3492. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3493. retriable:
  3494. if (rc == -ERESTARTSYS) {
  3495. QETH_DBF_TEXT(SETUP, 2, "break1");
  3496. return rc;
  3497. } else if (rc) {
  3498. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3499. if (++retries > 3)
  3500. goto out;
  3501. else
  3502. goto retry;
  3503. }
  3504. qeth_init_tokens(card);
  3505. qeth_init_func_level(card);
  3506. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3507. if (rc == -ERESTARTSYS) {
  3508. QETH_DBF_TEXT(SETUP, 2, "break2");
  3509. return rc;
  3510. } else if (rc) {
  3511. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3512. if (--retries < 0)
  3513. goto out;
  3514. else
  3515. goto retry;
  3516. }
  3517. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3518. if (rc == -ERESTARTSYS) {
  3519. QETH_DBF_TEXT(SETUP, 2, "break3");
  3520. return rc;
  3521. } else if (rc) {
  3522. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3523. if (--retries < 0)
  3524. goto out;
  3525. else
  3526. goto retry;
  3527. }
  3528. rc = qeth_mpc_initialize(card);
  3529. if (rc) {
  3530. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3531. goto out;
  3532. }
  3533. return 0;
  3534. out:
  3535. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3536. "an error on the device\n");
  3537. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3538. dev_name(&card->gdev->dev), rc);
  3539. return rc;
  3540. }
  3541. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3542. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3543. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3544. {
  3545. struct page *page = virt_to_page(element->addr);
  3546. if (*pskb == NULL) {
  3547. /* the upper protocol layers assume that there is data in the
  3548. * skb itself. Copy a small amount (64 bytes) to make them
  3549. * happy. */
  3550. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3551. if (!(*pskb))
  3552. return -ENOMEM;
  3553. skb_reserve(*pskb, ETH_HLEN);
  3554. if (data_len <= 64) {
  3555. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3556. data_len);
  3557. } else {
  3558. get_page(page);
  3559. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3560. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3561. data_len - 64);
  3562. (*pskb)->data_len += data_len - 64;
  3563. (*pskb)->len += data_len - 64;
  3564. (*pskb)->truesize += data_len - 64;
  3565. (*pfrag)++;
  3566. }
  3567. } else {
  3568. get_page(page);
  3569. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3570. (*pskb)->data_len += data_len;
  3571. (*pskb)->len += data_len;
  3572. (*pskb)->truesize += data_len;
  3573. (*pfrag)++;
  3574. }
  3575. return 0;
  3576. }
  3577. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3578. struct qdio_buffer *buffer,
  3579. struct qdio_buffer_element **__element, int *__offset,
  3580. struct qeth_hdr **hdr)
  3581. {
  3582. struct qdio_buffer_element *element = *__element;
  3583. int offset = *__offset;
  3584. struct sk_buff *skb = NULL;
  3585. int skb_len = 0;
  3586. void *data_ptr;
  3587. int data_len;
  3588. int headroom = 0;
  3589. int use_rx_sg = 0;
  3590. int frag = 0;
  3591. /* qeth_hdr must not cross element boundaries */
  3592. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3593. if (qeth_is_last_sbale(element))
  3594. return NULL;
  3595. element++;
  3596. offset = 0;
  3597. if (element->length < sizeof(struct qeth_hdr))
  3598. return NULL;
  3599. }
  3600. *hdr = element->addr + offset;
  3601. offset += sizeof(struct qeth_hdr);
  3602. switch ((*hdr)->hdr.l2.id) {
  3603. case QETH_HEADER_TYPE_LAYER2:
  3604. skb_len = (*hdr)->hdr.l2.pkt_length;
  3605. break;
  3606. case QETH_HEADER_TYPE_LAYER3:
  3607. skb_len = (*hdr)->hdr.l3.length;
  3608. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3609. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3610. headroom = TR_HLEN;
  3611. else
  3612. headroom = ETH_HLEN;
  3613. break;
  3614. case QETH_HEADER_TYPE_OSN:
  3615. skb_len = (*hdr)->hdr.osn.pdu_length;
  3616. headroom = sizeof(struct qeth_hdr);
  3617. break;
  3618. default:
  3619. break;
  3620. }
  3621. if (!skb_len)
  3622. return NULL;
  3623. if ((skb_len >= card->options.rx_sg_cb) &&
  3624. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3625. (!atomic_read(&card->force_alloc_skb))) {
  3626. use_rx_sg = 1;
  3627. } else {
  3628. skb = dev_alloc_skb(skb_len + headroom);
  3629. if (!skb)
  3630. goto no_mem;
  3631. if (headroom)
  3632. skb_reserve(skb, headroom);
  3633. }
  3634. data_ptr = element->addr + offset;
  3635. while (skb_len) {
  3636. data_len = min(skb_len, (int)(element->length - offset));
  3637. if (data_len) {
  3638. if (use_rx_sg) {
  3639. if (qeth_create_skb_frag(element, &skb, offset,
  3640. &frag, data_len))
  3641. goto no_mem;
  3642. } else {
  3643. memcpy(skb_put(skb, data_len), data_ptr,
  3644. data_len);
  3645. }
  3646. }
  3647. skb_len -= data_len;
  3648. if (skb_len) {
  3649. if (qeth_is_last_sbale(element)) {
  3650. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3651. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3652. CARD_BUS_ID(card));
  3653. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3654. QETH_DBF_TEXT_(QERR, 2, "%s",
  3655. CARD_BUS_ID(card));
  3656. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3657. dev_kfree_skb_any(skb);
  3658. card->stats.rx_errors++;
  3659. return NULL;
  3660. }
  3661. element++;
  3662. offset = 0;
  3663. data_ptr = element->addr;
  3664. } else {
  3665. offset += data_len;
  3666. }
  3667. }
  3668. *__element = element;
  3669. *__offset = offset;
  3670. if (use_rx_sg && card->options.performance_stats) {
  3671. card->perf_stats.sg_skbs_rx++;
  3672. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3673. }
  3674. return skb;
  3675. no_mem:
  3676. if (net_ratelimit()) {
  3677. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3678. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3679. }
  3680. card->stats.rx_dropped++;
  3681. return NULL;
  3682. }
  3683. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3684. static void qeth_unregister_dbf_views(void)
  3685. {
  3686. int x;
  3687. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3688. debug_unregister(qeth_dbf[x].id);
  3689. qeth_dbf[x].id = NULL;
  3690. }
  3691. }
  3692. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3693. {
  3694. char dbf_txt_buf[32];
  3695. va_list args;
  3696. if (level > (qeth_dbf[dbf_nix].id)->level)
  3697. return;
  3698. va_start(args, fmt);
  3699. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3700. va_end(args);
  3701. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3702. }
  3703. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3704. static int qeth_register_dbf_views(void)
  3705. {
  3706. int ret;
  3707. int x;
  3708. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3709. /* register the areas */
  3710. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3711. qeth_dbf[x].pages,
  3712. qeth_dbf[x].areas,
  3713. qeth_dbf[x].len);
  3714. if (qeth_dbf[x].id == NULL) {
  3715. qeth_unregister_dbf_views();
  3716. return -ENOMEM;
  3717. }
  3718. /* register a view */
  3719. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3720. if (ret) {
  3721. qeth_unregister_dbf_views();
  3722. return ret;
  3723. }
  3724. /* set a passing level */
  3725. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3726. }
  3727. return 0;
  3728. }
  3729. int qeth_core_load_discipline(struct qeth_card *card,
  3730. enum qeth_discipline_id discipline)
  3731. {
  3732. int rc = 0;
  3733. switch (discipline) {
  3734. case QETH_DISCIPLINE_LAYER3:
  3735. card->discipline.ccwgdriver = try_then_request_module(
  3736. symbol_get(qeth_l3_ccwgroup_driver),
  3737. "qeth_l3");
  3738. break;
  3739. case QETH_DISCIPLINE_LAYER2:
  3740. card->discipline.ccwgdriver = try_then_request_module(
  3741. symbol_get(qeth_l2_ccwgroup_driver),
  3742. "qeth_l2");
  3743. break;
  3744. }
  3745. if (!card->discipline.ccwgdriver) {
  3746. dev_err(&card->gdev->dev, "There is no kernel module to "
  3747. "support discipline %d\n", discipline);
  3748. rc = -EINVAL;
  3749. }
  3750. return rc;
  3751. }
  3752. void qeth_core_free_discipline(struct qeth_card *card)
  3753. {
  3754. if (card->options.layer2)
  3755. symbol_put(qeth_l2_ccwgroup_driver);
  3756. else
  3757. symbol_put(qeth_l3_ccwgroup_driver);
  3758. card->discipline.ccwgdriver = NULL;
  3759. }
  3760. static void qeth_determine_capabilities(struct qeth_card *card)
  3761. {
  3762. int rc;
  3763. int length;
  3764. char *prcd;
  3765. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3766. rc = ccw_device_set_online(CARD_DDEV(card));
  3767. if (rc) {
  3768. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3769. goto out;
  3770. }
  3771. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3772. if (rc) {
  3773. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3774. dev_name(&card->gdev->dev), rc);
  3775. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3776. goto out_offline;
  3777. }
  3778. qeth_configure_unitaddr(card, prcd);
  3779. qeth_configure_blkt_default(card, prcd);
  3780. kfree(prcd);
  3781. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3782. if (rc)
  3783. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3784. out_offline:
  3785. ccw_device_set_offline(CARD_DDEV(card));
  3786. out:
  3787. return;
  3788. }
  3789. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3790. {
  3791. struct qeth_card *card;
  3792. struct device *dev;
  3793. int rc;
  3794. unsigned long flags;
  3795. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3796. dev = &gdev->dev;
  3797. if (!get_device(dev))
  3798. return -ENODEV;
  3799. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3800. card = qeth_alloc_card();
  3801. if (!card) {
  3802. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3803. rc = -ENOMEM;
  3804. goto err_dev;
  3805. }
  3806. card->read.ccwdev = gdev->cdev[0];
  3807. card->write.ccwdev = gdev->cdev[1];
  3808. card->data.ccwdev = gdev->cdev[2];
  3809. dev_set_drvdata(&gdev->dev, card);
  3810. card->gdev = gdev;
  3811. gdev->cdev[0]->handler = qeth_irq;
  3812. gdev->cdev[1]->handler = qeth_irq;
  3813. gdev->cdev[2]->handler = qeth_irq;
  3814. rc = qeth_determine_card_type(card);
  3815. if (rc) {
  3816. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3817. goto err_card;
  3818. }
  3819. rc = qeth_setup_card(card);
  3820. if (rc) {
  3821. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3822. goto err_card;
  3823. }
  3824. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3825. rc = qeth_core_create_osn_attributes(dev);
  3826. if (rc)
  3827. goto err_card;
  3828. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3829. if (rc) {
  3830. qeth_core_remove_osn_attributes(dev);
  3831. goto err_card;
  3832. }
  3833. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3834. if (rc) {
  3835. qeth_core_free_discipline(card);
  3836. qeth_core_remove_osn_attributes(dev);
  3837. goto err_card;
  3838. }
  3839. } else {
  3840. rc = qeth_core_create_device_attributes(dev);
  3841. if (rc)
  3842. goto err_card;
  3843. }
  3844. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3845. list_add_tail(&card->list, &qeth_core_card_list.list);
  3846. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3847. qeth_determine_capabilities(card);
  3848. return 0;
  3849. err_card:
  3850. qeth_core_free_card(card);
  3851. err_dev:
  3852. put_device(dev);
  3853. return rc;
  3854. }
  3855. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3856. {
  3857. unsigned long flags;
  3858. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3859. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3860. if (card->discipline.ccwgdriver) {
  3861. card->discipline.ccwgdriver->remove(gdev);
  3862. qeth_core_free_discipline(card);
  3863. }
  3864. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3865. qeth_core_remove_osn_attributes(&gdev->dev);
  3866. } else {
  3867. qeth_core_remove_device_attributes(&gdev->dev);
  3868. }
  3869. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3870. list_del(&card->list);
  3871. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3872. qeth_core_free_card(card);
  3873. dev_set_drvdata(&gdev->dev, NULL);
  3874. put_device(&gdev->dev);
  3875. return;
  3876. }
  3877. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3878. {
  3879. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3880. int rc = 0;
  3881. int def_discipline;
  3882. if (!card->discipline.ccwgdriver) {
  3883. if (card->info.type == QETH_CARD_TYPE_IQD)
  3884. def_discipline = QETH_DISCIPLINE_LAYER3;
  3885. else
  3886. def_discipline = QETH_DISCIPLINE_LAYER2;
  3887. rc = qeth_core_load_discipline(card, def_discipline);
  3888. if (rc)
  3889. goto err;
  3890. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3891. if (rc)
  3892. goto err;
  3893. }
  3894. rc = card->discipline.ccwgdriver->set_online(gdev);
  3895. err:
  3896. return rc;
  3897. }
  3898. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3899. {
  3900. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3901. return card->discipline.ccwgdriver->set_offline(gdev);
  3902. }
  3903. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3904. {
  3905. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3906. if (card->discipline.ccwgdriver &&
  3907. card->discipline.ccwgdriver->shutdown)
  3908. card->discipline.ccwgdriver->shutdown(gdev);
  3909. }
  3910. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3911. {
  3912. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3913. if (card->discipline.ccwgdriver &&
  3914. card->discipline.ccwgdriver->prepare)
  3915. return card->discipline.ccwgdriver->prepare(gdev);
  3916. return 0;
  3917. }
  3918. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3919. {
  3920. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3921. if (card->discipline.ccwgdriver &&
  3922. card->discipline.ccwgdriver->complete)
  3923. card->discipline.ccwgdriver->complete(gdev);
  3924. }
  3925. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3926. {
  3927. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3928. if (card->discipline.ccwgdriver &&
  3929. card->discipline.ccwgdriver->freeze)
  3930. return card->discipline.ccwgdriver->freeze(gdev);
  3931. return 0;
  3932. }
  3933. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3934. {
  3935. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3936. if (card->discipline.ccwgdriver &&
  3937. card->discipline.ccwgdriver->thaw)
  3938. return card->discipline.ccwgdriver->thaw(gdev);
  3939. return 0;
  3940. }
  3941. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3942. {
  3943. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3944. if (card->discipline.ccwgdriver &&
  3945. card->discipline.ccwgdriver->restore)
  3946. return card->discipline.ccwgdriver->restore(gdev);
  3947. return 0;
  3948. }
  3949. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3950. .owner = THIS_MODULE,
  3951. .name = "qeth",
  3952. .driver_id = 0xD8C5E3C8,
  3953. .probe = qeth_core_probe_device,
  3954. .remove = qeth_core_remove_device,
  3955. .set_online = qeth_core_set_online,
  3956. .set_offline = qeth_core_set_offline,
  3957. .shutdown = qeth_core_shutdown,
  3958. .prepare = qeth_core_prepare,
  3959. .complete = qeth_core_complete,
  3960. .freeze = qeth_core_freeze,
  3961. .thaw = qeth_core_thaw,
  3962. .restore = qeth_core_restore,
  3963. };
  3964. static ssize_t
  3965. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3966. size_t count)
  3967. {
  3968. int err;
  3969. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3970. qeth_core_ccwgroup_driver.driver_id);
  3971. if (err)
  3972. return err;
  3973. else
  3974. return count;
  3975. }
  3976. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3977. static struct {
  3978. const char str[ETH_GSTRING_LEN];
  3979. } qeth_ethtool_stats_keys[] = {
  3980. /* 0 */{"rx skbs"},
  3981. {"rx buffers"},
  3982. {"tx skbs"},
  3983. {"tx buffers"},
  3984. {"tx skbs no packing"},
  3985. {"tx buffers no packing"},
  3986. {"tx skbs packing"},
  3987. {"tx buffers packing"},
  3988. {"tx sg skbs"},
  3989. {"tx sg frags"},
  3990. /* 10 */{"rx sg skbs"},
  3991. {"rx sg frags"},
  3992. {"rx sg page allocs"},
  3993. {"tx large kbytes"},
  3994. {"tx large count"},
  3995. {"tx pk state ch n->p"},
  3996. {"tx pk state ch p->n"},
  3997. {"tx pk watermark low"},
  3998. {"tx pk watermark high"},
  3999. {"queue 0 buffer usage"},
  4000. /* 20 */{"queue 1 buffer usage"},
  4001. {"queue 2 buffer usage"},
  4002. {"queue 3 buffer usage"},
  4003. {"rx handler time"},
  4004. {"rx handler count"},
  4005. {"rx do_QDIO time"},
  4006. {"rx do_QDIO count"},
  4007. {"tx handler time"},
  4008. {"tx handler count"},
  4009. {"tx time"},
  4010. /* 30 */{"tx count"},
  4011. {"tx do_QDIO time"},
  4012. {"tx do_QDIO count"},
  4013. {"tx csum"},
  4014. {"tx lin"},
  4015. };
  4016. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4017. {
  4018. switch (stringset) {
  4019. case ETH_SS_STATS:
  4020. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4021. default:
  4022. return -EINVAL;
  4023. }
  4024. }
  4025. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4026. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4027. struct ethtool_stats *stats, u64 *data)
  4028. {
  4029. struct qeth_card *card = dev->ml_priv;
  4030. data[0] = card->stats.rx_packets -
  4031. card->perf_stats.initial_rx_packets;
  4032. data[1] = card->perf_stats.bufs_rec;
  4033. data[2] = card->stats.tx_packets -
  4034. card->perf_stats.initial_tx_packets;
  4035. data[3] = card->perf_stats.bufs_sent;
  4036. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4037. - card->perf_stats.skbs_sent_pack;
  4038. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4039. data[6] = card->perf_stats.skbs_sent_pack;
  4040. data[7] = card->perf_stats.bufs_sent_pack;
  4041. data[8] = card->perf_stats.sg_skbs_sent;
  4042. data[9] = card->perf_stats.sg_frags_sent;
  4043. data[10] = card->perf_stats.sg_skbs_rx;
  4044. data[11] = card->perf_stats.sg_frags_rx;
  4045. data[12] = card->perf_stats.sg_alloc_page_rx;
  4046. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4047. data[14] = card->perf_stats.large_send_cnt;
  4048. data[15] = card->perf_stats.sc_dp_p;
  4049. data[16] = card->perf_stats.sc_p_dp;
  4050. data[17] = QETH_LOW_WATERMARK_PACK;
  4051. data[18] = QETH_HIGH_WATERMARK_PACK;
  4052. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4053. data[20] = (card->qdio.no_out_queues > 1) ?
  4054. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4055. data[21] = (card->qdio.no_out_queues > 2) ?
  4056. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4057. data[22] = (card->qdio.no_out_queues > 3) ?
  4058. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4059. data[23] = card->perf_stats.inbound_time;
  4060. data[24] = card->perf_stats.inbound_cnt;
  4061. data[25] = card->perf_stats.inbound_do_qdio_time;
  4062. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4063. data[27] = card->perf_stats.outbound_handler_time;
  4064. data[28] = card->perf_stats.outbound_handler_cnt;
  4065. data[29] = card->perf_stats.outbound_time;
  4066. data[30] = card->perf_stats.outbound_cnt;
  4067. data[31] = card->perf_stats.outbound_do_qdio_time;
  4068. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4069. data[33] = card->perf_stats.tx_csum;
  4070. data[34] = card->perf_stats.tx_lin;
  4071. }
  4072. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4073. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4074. {
  4075. switch (stringset) {
  4076. case ETH_SS_STATS:
  4077. memcpy(data, &qeth_ethtool_stats_keys,
  4078. sizeof(qeth_ethtool_stats_keys));
  4079. break;
  4080. default:
  4081. WARN_ON(1);
  4082. break;
  4083. }
  4084. }
  4085. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4086. void qeth_core_get_drvinfo(struct net_device *dev,
  4087. struct ethtool_drvinfo *info)
  4088. {
  4089. struct qeth_card *card = dev->ml_priv;
  4090. if (card->options.layer2)
  4091. strcpy(info->driver, "qeth_l2");
  4092. else
  4093. strcpy(info->driver, "qeth_l3");
  4094. strcpy(info->version, "1.0");
  4095. strcpy(info->fw_version, card->info.mcl_level);
  4096. sprintf(info->bus_info, "%s/%s/%s",
  4097. CARD_RDEV_ID(card),
  4098. CARD_WDEV_ID(card),
  4099. CARD_DDEV_ID(card));
  4100. }
  4101. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4102. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4103. struct ethtool_cmd *ecmd)
  4104. {
  4105. struct qeth_card *card = netdev->ml_priv;
  4106. enum qeth_link_types link_type;
  4107. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4108. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4109. else
  4110. link_type = card->info.link_type;
  4111. ecmd->transceiver = XCVR_INTERNAL;
  4112. ecmd->supported = SUPPORTED_Autoneg;
  4113. ecmd->advertising = ADVERTISED_Autoneg;
  4114. ecmd->duplex = DUPLEX_FULL;
  4115. ecmd->autoneg = AUTONEG_ENABLE;
  4116. switch (link_type) {
  4117. case QETH_LINK_TYPE_FAST_ETH:
  4118. case QETH_LINK_TYPE_LANE_ETH100:
  4119. ecmd->supported |= SUPPORTED_10baseT_Half |
  4120. SUPPORTED_10baseT_Full |
  4121. SUPPORTED_100baseT_Half |
  4122. SUPPORTED_100baseT_Full |
  4123. SUPPORTED_TP;
  4124. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4125. ADVERTISED_10baseT_Full |
  4126. ADVERTISED_100baseT_Half |
  4127. ADVERTISED_100baseT_Full |
  4128. ADVERTISED_TP;
  4129. ecmd->speed = SPEED_100;
  4130. ecmd->port = PORT_TP;
  4131. break;
  4132. case QETH_LINK_TYPE_GBIT_ETH:
  4133. case QETH_LINK_TYPE_LANE_ETH1000:
  4134. ecmd->supported |= SUPPORTED_10baseT_Half |
  4135. SUPPORTED_10baseT_Full |
  4136. SUPPORTED_100baseT_Half |
  4137. SUPPORTED_100baseT_Full |
  4138. SUPPORTED_1000baseT_Half |
  4139. SUPPORTED_1000baseT_Full |
  4140. SUPPORTED_FIBRE;
  4141. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4142. ADVERTISED_10baseT_Full |
  4143. ADVERTISED_100baseT_Half |
  4144. ADVERTISED_100baseT_Full |
  4145. ADVERTISED_1000baseT_Half |
  4146. ADVERTISED_1000baseT_Full |
  4147. ADVERTISED_FIBRE;
  4148. ecmd->speed = SPEED_1000;
  4149. ecmd->port = PORT_FIBRE;
  4150. break;
  4151. case QETH_LINK_TYPE_10GBIT_ETH:
  4152. ecmd->supported |= SUPPORTED_10baseT_Half |
  4153. SUPPORTED_10baseT_Full |
  4154. SUPPORTED_100baseT_Half |
  4155. SUPPORTED_100baseT_Full |
  4156. SUPPORTED_1000baseT_Half |
  4157. SUPPORTED_1000baseT_Full |
  4158. SUPPORTED_10000baseT_Full |
  4159. SUPPORTED_FIBRE;
  4160. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4161. ADVERTISED_10baseT_Full |
  4162. ADVERTISED_100baseT_Half |
  4163. ADVERTISED_100baseT_Full |
  4164. ADVERTISED_1000baseT_Half |
  4165. ADVERTISED_1000baseT_Full |
  4166. ADVERTISED_10000baseT_Full |
  4167. ADVERTISED_FIBRE;
  4168. ecmd->speed = SPEED_10000;
  4169. ecmd->port = PORT_FIBRE;
  4170. break;
  4171. default:
  4172. ecmd->supported |= SUPPORTED_10baseT_Half |
  4173. SUPPORTED_10baseT_Full |
  4174. SUPPORTED_TP;
  4175. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4176. ADVERTISED_10baseT_Full |
  4177. ADVERTISED_TP;
  4178. ecmd->speed = SPEED_10;
  4179. ecmd->port = PORT_TP;
  4180. }
  4181. return 0;
  4182. }
  4183. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4184. static int __init qeth_core_init(void)
  4185. {
  4186. int rc;
  4187. pr_info("loading core functions\n");
  4188. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4189. rwlock_init(&qeth_core_card_list.rwlock);
  4190. rc = qeth_register_dbf_views();
  4191. if (rc)
  4192. goto out_err;
  4193. rc = ccw_driver_register(&qeth_ccw_driver);
  4194. if (rc)
  4195. goto ccw_err;
  4196. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4197. if (rc)
  4198. goto ccwgroup_err;
  4199. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4200. &driver_attr_group);
  4201. if (rc)
  4202. goto driver_err;
  4203. qeth_core_root_dev = root_device_register("qeth");
  4204. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4205. if (rc)
  4206. goto register_err;
  4207. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4208. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4209. if (!qeth_core_header_cache) {
  4210. rc = -ENOMEM;
  4211. goto slab_err;
  4212. }
  4213. return 0;
  4214. slab_err:
  4215. root_device_unregister(qeth_core_root_dev);
  4216. register_err:
  4217. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4218. &driver_attr_group);
  4219. driver_err:
  4220. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4221. ccwgroup_err:
  4222. ccw_driver_unregister(&qeth_ccw_driver);
  4223. ccw_err:
  4224. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4225. qeth_unregister_dbf_views();
  4226. out_err:
  4227. pr_err("Initializing the qeth device driver failed\n");
  4228. return rc;
  4229. }
  4230. static void __exit qeth_core_exit(void)
  4231. {
  4232. root_device_unregister(qeth_core_root_dev);
  4233. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4234. &driver_attr_group);
  4235. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4236. ccw_driver_unregister(&qeth_ccw_driver);
  4237. kmem_cache_destroy(qeth_core_header_cache);
  4238. qeth_unregister_dbf_views();
  4239. pr_info("core functions removed\n");
  4240. }
  4241. module_init(qeth_core_init);
  4242. module_exit(qeth_core_exit);
  4243. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4244. MODULE_DESCRIPTION("qeth core functions");
  4245. MODULE_LICENSE("GPL");