sun5i-a10s.dtsi 7.7 KB

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  1. /*
  2. * Copyright 2013 Maxime Ripard
  3. *
  4. * Maxime Ripard <maxime.ripard@free-electrons.com>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /include/ "skeleton.dtsi"
  14. / {
  15. interrupt-parent = <&intc>;
  16. cpus {
  17. cpu@0 {
  18. compatible = "arm,cortex-a8";
  19. };
  20. };
  21. memory {
  22. reg = <0x40000000 0x20000000>;
  23. };
  24. clocks {
  25. #address-cells = <1>;
  26. #size-cells = <1>;
  27. ranges;
  28. /*
  29. * This is a dummy clock, to be used as placeholder on
  30. * other mux clocks when a specific parent clock is not
  31. * yet implemented. It should be dropped when the driver
  32. * is complete.
  33. */
  34. dummy: dummy {
  35. #clock-cells = <0>;
  36. compatible = "fixed-clock";
  37. clock-frequency = <0>;
  38. };
  39. osc24M: osc24M@01c20050 {
  40. #clock-cells = <0>;
  41. compatible = "allwinner,sun4i-osc-clk";
  42. reg = <0x01c20050 0x4>;
  43. clock-frequency = <24000000>;
  44. };
  45. osc32k: osc32k {
  46. #clock-cells = <0>;
  47. compatible = "fixed-clock";
  48. clock-frequency = <32768>;
  49. };
  50. pll1: pll1@01c20000 {
  51. #clock-cells = <0>;
  52. compatible = "allwinner,sun4i-pll1-clk";
  53. reg = <0x01c20000 0x4>;
  54. clocks = <&osc24M>;
  55. };
  56. /* dummy is 200M */
  57. cpu: cpu@01c20054 {
  58. #clock-cells = <0>;
  59. compatible = "allwinner,sun4i-cpu-clk";
  60. reg = <0x01c20054 0x4>;
  61. clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  62. };
  63. axi: axi@01c20054 {
  64. #clock-cells = <0>;
  65. compatible = "allwinner,sun4i-axi-clk";
  66. reg = <0x01c20054 0x4>;
  67. clocks = <&cpu>;
  68. };
  69. axi_gates: axi_gates@01c2005c {
  70. #clock-cells = <1>;
  71. compatible = "allwinner,sun4i-axi-gates-clk";
  72. reg = <0x01c2005c 0x4>;
  73. clocks = <&axi>;
  74. clock-output-names = "axi_dram";
  75. };
  76. ahb: ahb@01c20054 {
  77. #clock-cells = <0>;
  78. compatible = "allwinner,sun4i-ahb-clk";
  79. reg = <0x01c20054 0x4>;
  80. clocks = <&axi>;
  81. };
  82. ahb_gates: ahb_gates@01c20060 {
  83. #clock-cells = <1>;
  84. compatible = "allwinner,sun4i-ahb-gates-clk";
  85. reg = <0x01c20060 0x8>;
  86. clocks = <&ahb>;
  87. clock-output-names = "ahb_usb0", "ahb_ehci0",
  88. "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
  89. "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
  90. "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
  91. "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
  92. "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
  93. "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
  94. "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
  95. "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
  96. "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
  97. "ahb_de_fe1", "ahb_mp", "ahb_mali400";
  98. };
  99. apb0: apb0@01c20054 {
  100. #clock-cells = <0>;
  101. compatible = "allwinner,sun4i-apb0-clk";
  102. reg = <0x01c20054 0x4>;
  103. clocks = <&ahb>;
  104. };
  105. apb0_gates: apb0_gates@01c20068 {
  106. #clock-cells = <1>;
  107. compatible = "allwinner,sun4i-apb0-gates-clk";
  108. reg = <0x01c20068 0x4>;
  109. clocks = <&apb0>;
  110. clock-output-names = "apb0_codec", "apb0_spdif",
  111. "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
  112. "apb0_ir1", "apb0_keypad";
  113. };
  114. /* dummy is pll62 */
  115. apb1_mux: apb1_mux@01c20058 {
  116. #clock-cells = <0>;
  117. compatible = "allwinner,sun4i-apb1-mux-clk";
  118. reg = <0x01c20058 0x4>;
  119. clocks = <&osc24M>, <&dummy>, <&osc32k>;
  120. };
  121. apb1: apb1@01c20058 {
  122. #clock-cells = <0>;
  123. compatible = "allwinner,sun4i-apb1-clk";
  124. reg = <0x01c20058 0x4>;
  125. clocks = <&apb1_mux>;
  126. };
  127. apb1_gates: apb1_gates@01c2006c {
  128. #clock-cells = <1>;
  129. compatible = "allwinner,sun4i-apb1-gates-clk";
  130. reg = <0x01c2006c 0x4>;
  131. clocks = <&apb1>;
  132. clock-output-names = "apb1_i2c0", "apb1_i2c1",
  133. "apb1_i2c2", "apb1_can", "apb1_scr",
  134. "apb1_ps20", "apb1_ps21", "apb1_uart0",
  135. "apb1_uart1", "apb1_uart2", "apb1_uart3",
  136. "apb1_uart4", "apb1_uart5", "apb1_uart6",
  137. "apb1_uart7";
  138. };
  139. };
  140. soc@01c00000 {
  141. compatible = "simple-bus";
  142. #address-cells = <1>;
  143. #size-cells = <1>;
  144. ranges;
  145. emac: ethernet@01c0b000 {
  146. compatible = "allwinner,sun4i-emac";
  147. reg = <0x01c0b000 0x1000>;
  148. interrupts = <55>;
  149. clocks = <&ahb_gates 17>;
  150. status = "disabled";
  151. };
  152. mdio@01c0b080 {
  153. compatible = "allwinner,sun4i-mdio";
  154. reg = <0x01c0b080 0x14>;
  155. status = "disabled";
  156. #address-cells = <1>;
  157. #size-cells = <0>;
  158. };
  159. intc: interrupt-controller@01c20400 {
  160. compatible = "allwinner,sun4i-ic";
  161. reg = <0x01c20400 0x400>;
  162. interrupt-controller;
  163. #interrupt-cells = <1>;
  164. };
  165. pio: pinctrl@01c20800 {
  166. compatible = "allwinner,sun5i-a10s-pinctrl";
  167. reg = <0x01c20800 0x400>;
  168. interrupts = <28>;
  169. clocks = <&apb0_gates 5>;
  170. gpio-controller;
  171. interrupt-controller;
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. #gpio-cells = <3>;
  175. uart0_pins_a: uart0@0 {
  176. allwinner,pins = "PB19", "PB20";
  177. allwinner,function = "uart0";
  178. allwinner,drive = <0>;
  179. allwinner,pull = <0>;
  180. };
  181. uart2_pins_a: uart2@0 {
  182. allwinner,pins = "PC18", "PC19";
  183. allwinner,function = "uart2";
  184. allwinner,drive = <0>;
  185. allwinner,pull = <0>;
  186. };
  187. uart3_pins_a: uart3@0 {
  188. allwinner,pins = "PG9", "PG10";
  189. allwinner,function = "uart3";
  190. allwinner,drive = <0>;
  191. allwinner,pull = <0>;
  192. };
  193. emac_pins_a: emac0@0 {
  194. allwinner,pins = "PA0", "PA1", "PA2",
  195. "PA3", "PA4", "PA5", "PA6",
  196. "PA7", "PA8", "PA9", "PA10",
  197. "PA11", "PA12", "PA13", "PA14",
  198. "PA15", "PA16";
  199. allwinner,function = "emac";
  200. allwinner,drive = <0>;
  201. allwinner,pull = <0>;
  202. };
  203. i2c0_pins_a: i2c0@0 {
  204. allwinner,pins = "PB0", "PB1";
  205. allwinner,function = "i2c0";
  206. allwinner,drive = <0>;
  207. allwinner,pull = <0>;
  208. };
  209. i2c1_pins_a: i2c1@0 {
  210. allwinner,pins = "PB15", "PB16";
  211. allwinner,function = "i2c1";
  212. allwinner,drive = <0>;
  213. allwinner,pull = <0>;
  214. };
  215. i2c2_pins_a: i2c2@0 {
  216. allwinner,pins = "PB17", "PB18";
  217. allwinner,function = "i2c2";
  218. allwinner,drive = <0>;
  219. allwinner,pull = <0>;
  220. };
  221. };
  222. timer@01c20c00 {
  223. compatible = "allwinner,sun4i-timer";
  224. reg = <0x01c20c00 0x90>;
  225. interrupts = <22>;
  226. clocks = <&osc24M>;
  227. };
  228. wdt: watchdog@01c20c90 {
  229. compatible = "allwinner,sun4i-wdt";
  230. reg = <0x01c20c90 0x10>;
  231. };
  232. uart0: serial@01c28000 {
  233. compatible = "snps,dw-apb-uart";
  234. reg = <0x01c28000 0x400>;
  235. interrupts = <1>;
  236. reg-shift = <2>;
  237. reg-io-width = <4>;
  238. clocks = <&apb1_gates 16>;
  239. status = "disabled";
  240. };
  241. uart1: serial@01c28400 {
  242. compatible = "snps,dw-apb-uart";
  243. reg = <0x01c28400 0x400>;
  244. interrupts = <2>;
  245. reg-shift = <2>;
  246. reg-io-width = <4>;
  247. clocks = <&apb1_gates 17>;
  248. status = "disabled";
  249. };
  250. uart2: serial@01c28800 {
  251. compatible = "snps,dw-apb-uart";
  252. reg = <0x01c28800 0x400>;
  253. interrupts = <3>;
  254. reg-shift = <2>;
  255. reg-io-width = <4>;
  256. clocks = <&apb1_gates 18>;
  257. status = "disabled";
  258. };
  259. uart3: serial@01c28c00 {
  260. compatible = "snps,dw-apb-uart";
  261. reg = <0x01c28c00 0x400>;
  262. interrupts = <4>;
  263. reg-shift = <2>;
  264. reg-io-width = <4>;
  265. clocks = <&apb1_gates 19>;
  266. status = "disabled";
  267. };
  268. i2c0: i2c@01c2ac00 {
  269. #address-cells = <1>;
  270. #size-cells = <0>;
  271. compatible = "allwinner,sun4i-i2c";
  272. reg = <0x01c2ac00 0x400>;
  273. interrupts = <7>;
  274. clocks = <&apb1_gates 0>;
  275. clock-frequency = <100000>;
  276. status = "disabled";
  277. };
  278. i2c1: i2c@01c2b000 {
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. compatible = "allwinner,sun4i-i2c";
  282. reg = <0x01c2b000 0x400>;
  283. interrupts = <8>;
  284. clocks = <&apb1_gates 1>;
  285. clock-frequency = <100000>;
  286. status = "disabled";
  287. };
  288. i2c2: i2c@01c2b400 {
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. compatible = "allwinner,sun4i-i2c";
  292. reg = <0x01c2b400 0x400>;
  293. interrupts = <9>;
  294. clocks = <&apb1_gates 2>;
  295. clock-frequency = <100000>;
  296. status = "disabled";
  297. };
  298. };
  299. };