r8a7740.dtsi 3.1 KB

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  1. /*
  2. * Device Tree Source for the r8a7740 SoC
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "renesas,r8a7740";
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. compatible = "arm,cortex-a9";
  18. device_type = "cpu";
  19. reg = <0x0>;
  20. };
  21. };
  22. gic: interrupt-controller@c2800000 {
  23. compatible = "arm,cortex-a9-gic";
  24. #interrupt-cells = <3>;
  25. #address-cells = <1>;
  26. interrupt-controller;
  27. reg = <0xc2800000 0x1000>,
  28. <0xc2000000 0x1000>;
  29. };
  30. /* irqpin0: IRQ0 - IRQ7 */
  31. irqpin0: irqpin@e6900000 {
  32. compatible = "renesas,intc-irqpin";
  33. #interrupt-cells = <2>;
  34. interrupt-controller;
  35. reg = <0xe6900000 4>,
  36. <0xe6900010 4>,
  37. <0xe6900020 1>,
  38. <0xe6900040 1>,
  39. <0xe6900060 1>;
  40. interrupt-parent = <&gic>;
  41. interrupts = <0 149 0x4
  42. 0 149 0x4
  43. 0 149 0x4
  44. 0 149 0x4
  45. 0 149 0x4
  46. 0 149 0x4
  47. 0 149 0x4
  48. 0 149 0x4>;
  49. };
  50. /* irqpin1: IRQ8 - IRQ15 */
  51. irqpin1: irqpin@e6900004 {
  52. compatible = "renesas,intc-irqpin";
  53. #interrupt-cells = <2>;
  54. interrupt-controller;
  55. reg = <0xe6900004 4>,
  56. <0xe6900014 4>,
  57. <0xe6900024 1>,
  58. <0xe6900044 1>,
  59. <0xe6900064 1>;
  60. interrupt-parent = <&gic>;
  61. interrupts = <0 149 0x4
  62. 0 149 0x4
  63. 0 149 0x4
  64. 0 149 0x4
  65. 0 149 0x4
  66. 0 149 0x4
  67. 0 149 0x4
  68. 0 149 0x4>;
  69. };
  70. /* irqpin2: IRQ16 - IRQ23 */
  71. irqpin2: irqpin@e6900008 {
  72. compatible = "renesas,intc-irqpin";
  73. #interrupt-cells = <2>;
  74. interrupt-controller;
  75. reg = <0xe6900008 4>,
  76. <0xe6900018 4>,
  77. <0xe6900028 1>,
  78. <0xe6900048 1>,
  79. <0xe6900068 1>;
  80. interrupt-parent = <&gic>;
  81. interrupts = <0 149 0x4
  82. 0 149 0x4
  83. 0 149 0x4
  84. 0 149 0x4
  85. 0 149 0x4
  86. 0 149 0x4
  87. 0 149 0x4
  88. 0 149 0x4>;
  89. };
  90. /* irqpin3: IRQ24 - IRQ31 */
  91. irqpin3: irqpin@e690000c {
  92. compatible = "renesas,intc-irqpin";
  93. #interrupt-cells = <2>;
  94. interrupt-controller;
  95. reg = <0xe690000c 4>,
  96. <0xe690001c 4>,
  97. <0xe690002c 1>,
  98. <0xe690004c 1>,
  99. <0xe690006c 1>;
  100. interrupt-parent = <&gic>;
  101. interrupts = <0 149 0x4
  102. 0 149 0x4
  103. 0 149 0x4
  104. 0 149 0x4
  105. 0 149 0x4
  106. 0 149 0x4
  107. 0 149 0x4
  108. 0 149 0x4>;
  109. };
  110. i2c0: i2c@fff20000 {
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. compatible = "renesas,rmobile-iic";
  114. reg = <0xfff20000 0x425>;
  115. interrupt-parent = <&gic>;
  116. interrupts = <0 201 0x4
  117. 0 202 0x4
  118. 0 203 0x4
  119. 0 204 0x4>;
  120. };
  121. i2c1: i2c@e6c20000 {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. compatible = "renesas,rmobile-iic";
  125. reg = <0xe6c20000 0x425>;
  126. interrupt-parent = <&gic>;
  127. interrupts = <0 70 0x4
  128. 0 71 0x4
  129. 0 72 0x4
  130. 0 73 0x4>;
  131. };
  132. pfc: pfc@e6050000 {
  133. compatible = "renesas,pfc-r8a7740";
  134. reg = <0xe6050000 0x8000>,
  135. <0xe605800c 0x20>;
  136. gpio-controller;
  137. #gpio-cells = <2>;
  138. };
  139. };