exynos5250.dtsi 14 KB

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  1. /*
  2. * SAMSUNG EXYNOS5250 SoC device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
  8. * EXYNOS5250 based board files can include this file and provide
  9. * values for board specfic bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13. * additional nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. #include "exynos5.dtsi"
  20. #include "exynos5250-pinctrl.dtsi"
  21. #include <dt-bindings/clk/exynos-audss-clk.h>
  22. / {
  23. compatible = "samsung,exynos5250";
  24. aliases {
  25. spi0 = &spi_0;
  26. spi1 = &spi_1;
  27. spi2 = &spi_2;
  28. gsc0 = &gsc_0;
  29. gsc1 = &gsc_1;
  30. gsc2 = &gsc_2;
  31. gsc3 = &gsc_3;
  32. mshc0 = &dwmmc_0;
  33. mshc1 = &dwmmc_1;
  34. mshc2 = &dwmmc_2;
  35. mshc3 = &dwmmc_3;
  36. i2c0 = &i2c_0;
  37. i2c1 = &i2c_1;
  38. i2c2 = &i2c_2;
  39. i2c3 = &i2c_3;
  40. i2c4 = &i2c_4;
  41. i2c5 = &i2c_5;
  42. i2c6 = &i2c_6;
  43. i2c7 = &i2c_7;
  44. i2c8 = &i2c_8;
  45. pinctrl0 = &pinctrl_0;
  46. pinctrl1 = &pinctrl_1;
  47. pinctrl2 = &pinctrl_2;
  48. pinctrl3 = &pinctrl_3;
  49. };
  50. cpus {
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. cpu@0 {
  54. device_type = "cpu";
  55. compatible = "arm,cortex-a15";
  56. reg = <0>;
  57. };
  58. cpu@1 {
  59. device_type = "cpu";
  60. compatible = "arm,cortex-a15";
  61. reg = <1>;
  62. };
  63. };
  64. pd_gsc: gsc-power-domain@10044000 {
  65. compatible = "samsung,exynos4210-pd";
  66. reg = <0x10044000 0x20>;
  67. };
  68. pd_mfc: mfc-power-domain@10044040 {
  69. compatible = "samsung,exynos4210-pd";
  70. reg = <0x10044040 0x20>;
  71. };
  72. clock: clock-controller@10010000 {
  73. compatible = "samsung,exynos5250-clock";
  74. reg = <0x10010000 0x30000>;
  75. #clock-cells = <1>;
  76. };
  77. clock_audss: audss-clock-controller@3810000 {
  78. compatible = "samsung,exynos5250-audss-clock";
  79. reg = <0x03810000 0x0C>;
  80. #clock-cells = <1>;
  81. };
  82. timer {
  83. compatible = "arm,armv7-timer";
  84. interrupts = <1 13 0xf08>,
  85. <1 14 0xf08>,
  86. <1 11 0xf08>,
  87. <1 10 0xf08>;
  88. };
  89. mct@101C0000 {
  90. compatible = "samsung,exynos4210-mct";
  91. reg = <0x101C0000 0x800>;
  92. interrupt-controller;
  93. #interrups-cells = <2>;
  94. interrupt-parent = <&mct_map>;
  95. interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
  96. <4 0>, <5 0>;
  97. clocks = <&clock 1>, <&clock 335>;
  98. clock-names = "fin_pll", "mct";
  99. mct_map: mct-map {
  100. #interrupt-cells = <2>;
  101. #address-cells = <0>;
  102. #size-cells = <0>;
  103. interrupt-map = <0x0 0 &combiner 23 3>,
  104. <0x1 0 &combiner 23 4>,
  105. <0x2 0 &combiner 25 2>,
  106. <0x3 0 &combiner 25 3>,
  107. <0x4 0 &gic 0 120 0>,
  108. <0x5 0 &gic 0 121 0>;
  109. };
  110. };
  111. pmu {
  112. compatible = "arm,cortex-a15-pmu";
  113. interrupt-parent = <&combiner>;
  114. interrupts = <1 2>, <22 4>;
  115. };
  116. pinctrl_0: pinctrl@11400000 {
  117. compatible = "samsung,exynos5250-pinctrl";
  118. reg = <0x11400000 0x1000>;
  119. interrupts = <0 46 0>;
  120. wakup_eint: wakeup-interrupt-controller {
  121. compatible = "samsung,exynos4210-wakeup-eint";
  122. interrupt-parent = <&gic>;
  123. interrupts = <0 32 0>;
  124. };
  125. };
  126. pinctrl_1: pinctrl@13400000 {
  127. compatible = "samsung,exynos5250-pinctrl";
  128. reg = <0x13400000 0x1000>;
  129. interrupts = <0 45 0>;
  130. };
  131. pinctrl_2: pinctrl@10d10000 {
  132. compatible = "samsung,exynos5250-pinctrl";
  133. reg = <0x10d10000 0x1000>;
  134. interrupts = <0 50 0>;
  135. };
  136. pinctrl_3: pinctrl@03860000 {
  137. compatible = "samsung,exynos5250-pinctrl";
  138. reg = <0x03860000 0x1000>;
  139. interrupts = <0 47 0>;
  140. };
  141. watchdog {
  142. clocks = <&clock 336>;
  143. clock-names = "watchdog";
  144. };
  145. g2d@10850000 {
  146. compatible = "samsung,exynos5250-g2d";
  147. reg = <0x10850000 0x1000>;
  148. interrupts = <0 91 0>;
  149. clocks = <&clock 345>;
  150. clock-names = "fimg2d";
  151. };
  152. codec@11000000 {
  153. compatible = "samsung,mfc-v6";
  154. reg = <0x11000000 0x10000>;
  155. interrupts = <0 96 0>;
  156. samsung,power-domain = <&pd_mfc>;
  157. clocks = <&clock 266>;
  158. clock-names = "mfc";
  159. };
  160. rtc {
  161. clocks = <&clock 337>;
  162. clock-names = "rtc";
  163. };
  164. tmu@10060000 {
  165. compatible = "samsung,exynos5250-tmu";
  166. reg = <0x10060000 0x100>;
  167. interrupts = <0 65 0>;
  168. clocks = <&clock 338>;
  169. clock-names = "tmu_apbif";
  170. };
  171. serial@12C00000 {
  172. clocks = <&clock 289>, <&clock 146>;
  173. clock-names = "uart", "clk_uart_baud0";
  174. };
  175. serial@12C10000 {
  176. clocks = <&clock 290>, <&clock 147>;
  177. clock-names = "uart", "clk_uart_baud0";
  178. };
  179. serial@12C20000 {
  180. clocks = <&clock 291>, <&clock 148>;
  181. clock-names = "uart", "clk_uart_baud0";
  182. };
  183. serial@12C30000 {
  184. clocks = <&clock 292>, <&clock 149>;
  185. clock-names = "uart", "clk_uart_baud0";
  186. };
  187. sata@122F0000 {
  188. compatible = "samsung,exynos5-sata-ahci";
  189. reg = <0x122F0000 0x1ff>;
  190. interrupts = <0 115 0>;
  191. clocks = <&clock 277>, <&clock 143>;
  192. clock-names = "sata", "sclk_sata";
  193. };
  194. sata-phy@12170000 {
  195. compatible = "samsung,exynos5-sata-phy";
  196. reg = <0x12170000 0x1ff>;
  197. };
  198. i2c_0: i2c@12C60000 {
  199. compatible = "samsung,s3c2440-i2c";
  200. reg = <0x12C60000 0x100>;
  201. interrupts = <0 56 0>;
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. clocks = <&clock 294>;
  205. clock-names = "i2c";
  206. pinctrl-names = "default";
  207. pinctrl-0 = <&i2c0_bus>;
  208. };
  209. i2c_1: i2c@12C70000 {
  210. compatible = "samsung,s3c2440-i2c";
  211. reg = <0x12C70000 0x100>;
  212. interrupts = <0 57 0>;
  213. #address-cells = <1>;
  214. #size-cells = <0>;
  215. clocks = <&clock 295>;
  216. clock-names = "i2c";
  217. pinctrl-names = "default";
  218. pinctrl-0 = <&i2c1_bus>;
  219. };
  220. i2c_2: i2c@12C80000 {
  221. compatible = "samsung,s3c2440-i2c";
  222. reg = <0x12C80000 0x100>;
  223. interrupts = <0 58 0>;
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. clocks = <&clock 296>;
  227. clock-names = "i2c";
  228. pinctrl-names = "default";
  229. pinctrl-0 = <&i2c2_bus>;
  230. };
  231. i2c_3: i2c@12C90000 {
  232. compatible = "samsung,s3c2440-i2c";
  233. reg = <0x12C90000 0x100>;
  234. interrupts = <0 59 0>;
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. clocks = <&clock 297>;
  238. clock-names = "i2c";
  239. pinctrl-names = "default";
  240. pinctrl-0 = <&i2c3_bus>;
  241. };
  242. i2c_4: i2c@12CA0000 {
  243. compatible = "samsung,s3c2440-i2c";
  244. reg = <0x12CA0000 0x100>;
  245. interrupts = <0 60 0>;
  246. #address-cells = <1>;
  247. #size-cells = <0>;
  248. clocks = <&clock 298>;
  249. clock-names = "i2c";
  250. pinctrl-names = "default";
  251. pinctrl-0 = <&i2c4_bus>;
  252. };
  253. i2c_5: i2c@12CB0000 {
  254. compatible = "samsung,s3c2440-i2c";
  255. reg = <0x12CB0000 0x100>;
  256. interrupts = <0 61 0>;
  257. #address-cells = <1>;
  258. #size-cells = <0>;
  259. clocks = <&clock 299>;
  260. clock-names = "i2c";
  261. pinctrl-names = "default";
  262. pinctrl-0 = <&i2c5_bus>;
  263. };
  264. i2c_6: i2c@12CC0000 {
  265. compatible = "samsung,s3c2440-i2c";
  266. reg = <0x12CC0000 0x100>;
  267. interrupts = <0 62 0>;
  268. #address-cells = <1>;
  269. #size-cells = <0>;
  270. clocks = <&clock 300>;
  271. clock-names = "i2c";
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&i2c6_bus>;
  274. };
  275. i2c_7: i2c@12CD0000 {
  276. compatible = "samsung,s3c2440-i2c";
  277. reg = <0x12CD0000 0x100>;
  278. interrupts = <0 63 0>;
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. clocks = <&clock 301>;
  282. clock-names = "i2c";
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&i2c7_bus>;
  285. };
  286. i2c_8: i2c@12CE0000 {
  287. compatible = "samsung,s3c2440-hdmiphy-i2c";
  288. reg = <0x12CE0000 0x1000>;
  289. interrupts = <0 64 0>;
  290. #address-cells = <1>;
  291. #size-cells = <0>;
  292. clocks = <&clock 302>;
  293. clock-names = "i2c";
  294. };
  295. i2c@121D0000 {
  296. compatible = "samsung,exynos5-sata-phy-i2c";
  297. reg = <0x121D0000 0x100>;
  298. #address-cells = <1>;
  299. #size-cells = <0>;
  300. clocks = <&clock 288>;
  301. clock-names = "i2c";
  302. };
  303. spi_0: spi@12d20000 {
  304. compatible = "samsung,exynos4210-spi";
  305. reg = <0x12d20000 0x100>;
  306. interrupts = <0 66 0>;
  307. dmas = <&pdma0 5
  308. &pdma0 4>;
  309. dma-names = "tx", "rx";
  310. #address-cells = <1>;
  311. #size-cells = <0>;
  312. clocks = <&clock 304>, <&clock 154>;
  313. clock-names = "spi", "spi_busclk0";
  314. pinctrl-names = "default";
  315. pinctrl-0 = <&spi0_bus>;
  316. };
  317. spi_1: spi@12d30000 {
  318. compatible = "samsung,exynos4210-spi";
  319. reg = <0x12d30000 0x100>;
  320. interrupts = <0 67 0>;
  321. dmas = <&pdma1 5
  322. &pdma1 4>;
  323. dma-names = "tx", "rx";
  324. #address-cells = <1>;
  325. #size-cells = <0>;
  326. clocks = <&clock 305>, <&clock 155>;
  327. clock-names = "spi", "spi_busclk0";
  328. pinctrl-names = "default";
  329. pinctrl-0 = <&spi1_bus>;
  330. };
  331. spi_2: spi@12d40000 {
  332. compatible = "samsung,exynos4210-spi";
  333. reg = <0x12d40000 0x100>;
  334. interrupts = <0 68 0>;
  335. dmas = <&pdma0 7
  336. &pdma0 6>;
  337. dma-names = "tx", "rx";
  338. #address-cells = <1>;
  339. #size-cells = <0>;
  340. clocks = <&clock 306>, <&clock 156>;
  341. clock-names = "spi", "spi_busclk0";
  342. pinctrl-names = "default";
  343. pinctrl-0 = <&spi2_bus>;
  344. };
  345. dwmmc_0: dwmmc0@12200000 {
  346. reg = <0x12200000 0x1000>;
  347. clocks = <&clock 280>, <&clock 139>;
  348. clock-names = "biu", "ciu";
  349. };
  350. dwmmc_1: dwmmc1@12210000 {
  351. reg = <0x12210000 0x1000>;
  352. clocks = <&clock 281>, <&clock 140>;
  353. clock-names = "biu", "ciu";
  354. };
  355. dwmmc_2: dwmmc2@12220000 {
  356. reg = <0x12220000 0x1000>;
  357. clocks = <&clock 282>, <&clock 141>;
  358. clock-names = "biu", "ciu";
  359. };
  360. dwmmc_3: dwmmc3@12230000 {
  361. compatible = "samsung,exynos5250-dw-mshc";
  362. reg = <0x12230000 0x1000>;
  363. interrupts = <0 78 0>;
  364. #address-cells = <1>;
  365. #size-cells = <0>;
  366. clocks = <&clock 283>, <&clock 142>;
  367. clock-names = "biu", "ciu";
  368. };
  369. i2s0: i2s@03830000 {
  370. compatible = "samsung,s5pv210-i2s";
  371. reg = <0x03830000 0x100>;
  372. dmas = <&pdma0 10
  373. &pdma0 9
  374. &pdma0 8>;
  375. dma-names = "tx", "rx", "tx-sec";
  376. clocks = <&clock_audss EXYNOS_I2S_BUS>,
  377. <&clock_audss EXYNOS_I2S_BUS>,
  378. <&clock_audss EXYNOS_SCLK_I2S>;
  379. clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
  380. samsung,idma-addr = <0x03000000>;
  381. pinctrl-names = "default";
  382. pinctrl-0 = <&i2s0_bus>;
  383. };
  384. i2s1: i2s@12D60000 {
  385. compatible = "samsung,s3c6410-i2s";
  386. reg = <0x12D60000 0x100>;
  387. dmas = <&pdma1 12
  388. &pdma1 11>;
  389. dma-names = "tx", "rx";
  390. clocks = <&clock 307>, <&clock 157>;
  391. clock-names = "iis", "i2s_opclk0";
  392. pinctrl-names = "default";
  393. pinctrl-0 = <&i2s1_bus>;
  394. };
  395. i2s2: i2s@12D70000 {
  396. compatible = "samsung,s3c6410-i2s";
  397. reg = <0x12D70000 0x100>;
  398. dmas = <&pdma0 12
  399. &pdma0 11>;
  400. dma-names = "tx", "rx";
  401. clocks = <&clock 308>, <&clock 158>;
  402. clock-names = "iis", "i2s_opclk0";
  403. pinctrl-names = "default";
  404. pinctrl-0 = <&i2s2_bus>;
  405. };
  406. usb@12000000 {
  407. compatible = "samsung,exynos5250-dwusb3";
  408. clocks = <&clock 286>;
  409. clock-names = "usbdrd30";
  410. #address-cells = <1>;
  411. #size-cells = <1>;
  412. ranges;
  413. dwc3 {
  414. compatible = "synopsys,dwc3";
  415. reg = <0x12000000 0x10000>;
  416. interrupts = <0 72 0>;
  417. usb-phy = <&usb2_phy &usb3_phy>;
  418. };
  419. };
  420. usb3_phy: usbphy@12100000 {
  421. compatible = "samsung,exynos5250-usb3phy";
  422. reg = <0x12100000 0x100>;
  423. clocks = <&clock 1>, <&clock 286>;
  424. clock-names = "ext_xtal", "usbdrd30";
  425. #address-cells = <1>;
  426. #size-cells = <1>;
  427. ranges;
  428. usbphy-sys {
  429. reg = <0x10040704 0x8>;
  430. };
  431. };
  432. usb@12110000 {
  433. compatible = "samsung,exynos4210-ehci";
  434. reg = <0x12110000 0x100>;
  435. interrupts = <0 71 0>;
  436. clocks = <&clock 285>;
  437. clock-names = "usbhost";
  438. };
  439. usb@12120000 {
  440. compatible = "samsung,exynos4210-ohci";
  441. reg = <0x12120000 0x100>;
  442. interrupts = <0 71 0>;
  443. clocks = <&clock 285>;
  444. clock-names = "usbhost";
  445. };
  446. usb2_phy: usbphy@12130000 {
  447. compatible = "samsung,exynos5250-usb2phy";
  448. reg = <0x12130000 0x100>;
  449. clocks = <&clock 1>, <&clock 285>;
  450. clock-names = "ext_xtal", "usbhost";
  451. #address-cells = <1>;
  452. #size-cells = <1>;
  453. ranges;
  454. usbphy-sys {
  455. reg = <0x10040704 0x8>,
  456. <0x10050230 0x4>;
  457. };
  458. };
  459. amba {
  460. #address-cells = <1>;
  461. #size-cells = <1>;
  462. compatible = "arm,amba-bus";
  463. interrupt-parent = <&gic>;
  464. ranges;
  465. pdma0: pdma@121A0000 {
  466. compatible = "arm,pl330", "arm,primecell";
  467. reg = <0x121A0000 0x1000>;
  468. interrupts = <0 34 0>;
  469. clocks = <&clock 275>;
  470. clock-names = "apb_pclk";
  471. #dma-cells = <1>;
  472. #dma-channels = <8>;
  473. #dma-requests = <32>;
  474. };
  475. pdma1: pdma@121B0000 {
  476. compatible = "arm,pl330", "arm,primecell";
  477. reg = <0x121B0000 0x1000>;
  478. interrupts = <0 35 0>;
  479. clocks = <&clock 276>;
  480. clock-names = "apb_pclk";
  481. #dma-cells = <1>;
  482. #dma-channels = <8>;
  483. #dma-requests = <32>;
  484. };
  485. mdma0: mdma@10800000 {
  486. compatible = "arm,pl330", "arm,primecell";
  487. reg = <0x10800000 0x1000>;
  488. interrupts = <0 33 0>;
  489. clocks = <&clock 271>;
  490. clock-names = "apb_pclk";
  491. #dma-cells = <1>;
  492. #dma-channels = <8>;
  493. #dma-requests = <1>;
  494. };
  495. mdma1: mdma@11C10000 {
  496. compatible = "arm,pl330", "arm,primecell";
  497. reg = <0x11C10000 0x1000>;
  498. interrupts = <0 124 0>;
  499. clocks = <&clock 271>;
  500. clock-names = "apb_pclk";
  501. #dma-cells = <1>;
  502. #dma-channels = <8>;
  503. #dma-requests = <1>;
  504. };
  505. };
  506. gsc_0: gsc@13e00000 {
  507. compatible = "samsung,exynos5-gsc";
  508. reg = <0x13e00000 0x1000>;
  509. interrupts = <0 85 0>;
  510. samsung,power-domain = <&pd_gsc>;
  511. clocks = <&clock 256>;
  512. clock-names = "gscl";
  513. };
  514. gsc_1: gsc@13e10000 {
  515. compatible = "samsung,exynos5-gsc";
  516. reg = <0x13e10000 0x1000>;
  517. interrupts = <0 86 0>;
  518. samsung,power-domain = <&pd_gsc>;
  519. clocks = <&clock 257>;
  520. clock-names = "gscl";
  521. };
  522. gsc_2: gsc@13e20000 {
  523. compatible = "samsung,exynos5-gsc";
  524. reg = <0x13e20000 0x1000>;
  525. interrupts = <0 87 0>;
  526. samsung,power-domain = <&pd_gsc>;
  527. clocks = <&clock 258>;
  528. clock-names = "gscl";
  529. };
  530. gsc_3: gsc@13e30000 {
  531. compatible = "samsung,exynos5-gsc";
  532. reg = <0x13e30000 0x1000>;
  533. interrupts = <0 88 0>;
  534. samsung,power-domain = <&pd_gsc>;
  535. clocks = <&clock 259>;
  536. clock-names = "gscl";
  537. };
  538. hdmi {
  539. compatible = "samsung,exynos4212-hdmi";
  540. reg = <0x14530000 0x70000>;
  541. interrupts = <0 95 0>;
  542. clocks = <&clock 333>, <&clock 136>, <&clock 137>,
  543. <&clock 333>, <&clock 333>;
  544. clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
  545. "sclk_hdmiphy", "hdmiphy";
  546. };
  547. mixer {
  548. compatible = "samsung,exynos5250-mixer";
  549. reg = <0x14450000 0x10000>;
  550. interrupts = <0 94 0>;
  551. };
  552. dp_phy: video-phy@10040720 {
  553. compatible = "samsung,exynos5250-dp-video-phy";
  554. reg = <0x10040720 4>;
  555. #phy-cells = <0>;
  556. };
  557. dp-controller@145B0000 {
  558. clocks = <&clock 342>;
  559. clock-names = "dp";
  560. phys = <&dp_phy>;
  561. phy-names = "dp";
  562. };
  563. fimd@14400000 {
  564. clocks = <&clock 133>, <&clock 339>;
  565. clock-names = "sclk_fimd", "fimd";
  566. };
  567. };