emev2.dtsi 2.6 KB

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  1. /*
  2. * Device Tree Source for the EMEV2 SoC
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "renesas,emev2";
  13. interrupt-parent = <&gic>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. device_type = "cpu";
  26. compatible = "arm,cortex-a9";
  27. reg = <0>;
  28. };
  29. cpu@1 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a9";
  32. reg = <1>;
  33. };
  34. };
  35. gic: interrupt-controller@e0020000 {
  36. compatible = "arm,cortex-a9-gic";
  37. interrupt-controller;
  38. #interrupt-cells = <3>;
  39. reg = <0xe0028000 0x1000>,
  40. <0xe0020000 0x0100>;
  41. };
  42. sti@e0180000 {
  43. compatible = "renesas,em-sti";
  44. reg = <0xe0180000 0x54>;
  45. interrupts = <0 125 0>;
  46. };
  47. uart@e1020000 {
  48. compatible = "renesas,em-uart";
  49. reg = <0xe1020000 0x38>;
  50. interrupts = <0 8 0>;
  51. };
  52. uart@e1030000 {
  53. compatible = "renesas,em-uart";
  54. reg = <0xe1030000 0x38>;
  55. interrupts = <0 9 0>;
  56. };
  57. uart@e1040000 {
  58. compatible = "renesas,em-uart";
  59. reg = <0xe1040000 0x38>;
  60. interrupts = <0 10 0>;
  61. };
  62. uart@e1050000 {
  63. compatible = "renesas,em-uart";
  64. reg = <0xe1050000 0x38>;
  65. interrupts = <0 11 0>;
  66. };
  67. gpio0: gpio@e0050000 {
  68. compatible = "renesas,em-gio";
  69. reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
  70. interrupts = <0 67 0>, <0 68 0>;
  71. gpio-controller;
  72. #gpio-cells = <2>;
  73. ngpios = <32>;
  74. interrupt-controller;
  75. #interrupt-cells = <2>;
  76. };
  77. gpio1: gpio@e0050080 {
  78. compatible = "renesas,em-gio";
  79. reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
  80. interrupts = <0 69 0>, <0 70 0>;
  81. gpio-controller;
  82. #gpio-cells = <2>;
  83. ngpios = <32>;
  84. interrupt-controller;
  85. #interrupt-cells = <2>;
  86. };
  87. gpio2: gpio@e0050100 {
  88. compatible = "renesas,em-gio";
  89. reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
  90. interrupts = <0 71 0>, <0 72 0>;
  91. gpio-controller;
  92. #gpio-cells = <2>;
  93. ngpios = <32>;
  94. interrupt-controller;
  95. #interrupt-cells = <2>;
  96. };
  97. gpio3: gpio@e0050180 {
  98. compatible = "renesas,em-gio";
  99. reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
  100. interrupts = <0 73 0>, <0 74 0>;
  101. gpio-controller;
  102. #gpio-cells = <2>;
  103. ngpios = <32>;
  104. interrupt-controller;
  105. #interrupt-cells = <2>;
  106. };
  107. gpio4: gpio@e0050200 {
  108. compatible = "renesas,em-gio";
  109. reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
  110. interrupts = <0 75 0>, <0 76 0>;
  111. gpio-controller;
  112. #gpio-cells = <2>;
  113. ngpios = <31>;
  114. interrupt-controller;
  115. #interrupt-cells = <2>;
  116. };
  117. };