marvell.txt 16 KB

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  1. Marvell Discovery mv64[345]6x System Controller chips
  2. ===========================================================
  3. The Marvell mv64[345]60 series of system controller chips contain
  4. many of the peripherals needed to implement a complete computer
  5. system. In this section, we define device tree nodes to describe
  6. the system controller chip itself and each of the peripherals
  7. which it contains. Compatible string values for each node are
  8. prefixed with the string "marvell,", for Marvell Technology Group Ltd.
  9. 1) The /system-controller node
  10. This node is used to represent the system-controller and must be
  11. present when the system uses a system controller chip. The top-level
  12. system-controller node contains information that is global to all
  13. devices within the system controller chip. The node name begins
  14. with "system-controller" followed by the unit address, which is
  15. the base address of the memory-mapped register set for the system
  16. controller chip.
  17. Required properties:
  18. - ranges : Describes the translation of system controller addresses
  19. for memory mapped registers.
  20. - clock-frequency: Contains the main clock frequency for the system
  21. controller chip.
  22. - reg : This property defines the address and size of the
  23. memory-mapped registers contained within the system controller
  24. chip. The address specified in the "reg" property should match
  25. the unit address of the system-controller node.
  26. - #address-cells : Address representation for system controller
  27. devices. This field represents the number of cells needed to
  28. represent the address of the memory-mapped registers of devices
  29. within the system controller chip.
  30. - #size-cells : Size representation for the memory-mapped
  31. registers within the system controller chip.
  32. - #interrupt-cells : Defines the width of cells used to represent
  33. interrupts.
  34. Optional properties:
  35. - model : The specific model of the system controller chip. Such
  36. as, "mv64360", "mv64460", or "mv64560".
  37. - compatible : A string identifying the compatibility identifiers
  38. of the system controller chip.
  39. The system-controller node contains child nodes for each system
  40. controller device that the platform uses. Nodes should not be created
  41. for devices which exist on the system controller chip but are not used
  42. Example Marvell Discovery mv64360 system-controller node:
  43. system-controller@f1000000 { /* Marvell Discovery mv64360 */
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. model = "mv64360"; /* Default */
  47. compatible = "marvell,mv64360";
  48. clock-frequency = <133333333>;
  49. reg = <0xf1000000 0x10000>;
  50. virtual-reg = <0xf1000000>;
  51. ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
  52. 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
  53. 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
  54. 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
  55. 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
  56. [ child node definitions... ]
  57. }
  58. 2) Child nodes of /system-controller
  59. a) Marvell Discovery MDIO bus
  60. The MDIO is a bus to which the PHY devices are connected. For each
  61. device that exists on this bus, a child node should be created. See
  62. the definition of the PHY node below for an example of how to define
  63. a PHY.
  64. Required properties:
  65. - #address-cells : Should be <1>
  66. - #size-cells : Should be <0>
  67. - device_type : Should be "mdio"
  68. - compatible : Should be "marvell,mv64360-mdio"
  69. Example:
  70. mdio {
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. device_type = "mdio";
  74. compatible = "marvell,mv64360-mdio";
  75. ethernet-phy@0 {
  76. ......
  77. };
  78. };
  79. b) Marvell Discovery ethernet controller
  80. The Discover ethernet controller is described with two levels
  81. of nodes. The first level describes an ethernet silicon block
  82. and the second level describes up to 3 ethernet nodes within
  83. that block. The reason for the multiple levels is that the
  84. registers for the node are interleaved within a single set
  85. of registers. The "ethernet-block" level describes the
  86. shared register set, and the "ethernet" nodes describe ethernet
  87. port-specific properties.
  88. Ethernet block node
  89. Required properties:
  90. - #address-cells : <1>
  91. - #size-cells : <0>
  92. - compatible : "marvell,mv64360-eth-block"
  93. - reg : Offset and length of the register set for this block
  94. Optional properties:
  95. - clocks : Phandle to the clock control device and gate bit
  96. Example Discovery Ethernet block node:
  97. ethernet-block@2000 {
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. compatible = "marvell,mv64360-eth-block";
  101. reg = <0x2000 0x2000>;
  102. ethernet@0 {
  103. .......
  104. };
  105. };
  106. Ethernet port node
  107. Required properties:
  108. - device_type : Should be "network".
  109. - compatible : Should be "marvell,mv64360-eth".
  110. - reg : Should be <0>, <1>, or <2>, according to which registers
  111. within the silicon block the device uses.
  112. - interrupts : <a> where a is the interrupt number for the port.
  113. - interrupt-parent : the phandle for the interrupt controller
  114. that services interrupts for this device.
  115. - phy : the phandle for the PHY connected to this ethernet
  116. controller.
  117. - local-mac-address : 6 bytes, MAC address
  118. Example Discovery Ethernet port node:
  119. ethernet@0 {
  120. device_type = "network";
  121. compatible = "marvell,mv64360-eth";
  122. reg = <0>;
  123. interrupts = <32>;
  124. interrupt-parent = <&PIC>;
  125. phy = <&PHY0>;
  126. local-mac-address = [ 00 00 00 00 00 00 ];
  127. };
  128. c) Marvell Discovery PHY nodes
  129. Required properties:
  130. - device_type : Should be "ethernet-phy"
  131. - interrupts : <a> where a is the interrupt number for this phy.
  132. - interrupt-parent : the phandle for the interrupt controller that
  133. services interrupts for this device.
  134. - reg : The ID number for the phy, usually a small integer
  135. Example Discovery PHY node:
  136. ethernet-phy@1 {
  137. device_type = "ethernet-phy";
  138. compatible = "broadcom,bcm5421";
  139. interrupts = <76>; /* GPP 12 */
  140. interrupt-parent = <&PIC>;
  141. reg = <1>;
  142. };
  143. d) Marvell Discovery SDMA nodes
  144. Represent DMA hardware associated with the MPSC (multiprotocol
  145. serial controllers).
  146. Required properties:
  147. - compatible : "marvell,mv64360-sdma"
  148. - reg : Offset and length of the register set for this device
  149. - interrupts : <a> where a is the interrupt number for the DMA
  150. device.
  151. - interrupt-parent : the phandle for the interrupt controller
  152. that services interrupts for this device.
  153. Example Discovery SDMA node:
  154. sdma@4000 {
  155. compatible = "marvell,mv64360-sdma";
  156. reg = <0x4000 0xc18>;
  157. virtual-reg = <0xf1004000>;
  158. interrupts = <36>;
  159. interrupt-parent = <&PIC>;
  160. };
  161. e) Marvell Discovery BRG nodes
  162. Represent baud rate generator hardware associated with the MPSC
  163. (multiprotocol serial controllers).
  164. Required properties:
  165. - compatible : "marvell,mv64360-brg"
  166. - reg : Offset and length of the register set for this device
  167. - clock-src : A value from 0 to 15 which selects the clock
  168. source for the baud rate generator. This value corresponds
  169. to the CLKS value in the BRGx configuration register. See
  170. the mv64x60 User's Manual.
  171. - clock-frequence : The frequency (in Hz) of the baud rate
  172. generator's input clock.
  173. - current-speed : The current speed setting (presumably by
  174. firmware) of the baud rate generator.
  175. Example Discovery BRG node:
  176. brg@b200 {
  177. compatible = "marvell,mv64360-brg";
  178. reg = <0xb200 0x8>;
  179. clock-src = <8>;
  180. clock-frequency = <133333333>;
  181. current-speed = <9600>;
  182. };
  183. f) Marvell Discovery CUNIT nodes
  184. Represent the Serial Communications Unit device hardware.
  185. Required properties:
  186. - reg : Offset and length of the register set for this device
  187. Example Discovery CUNIT node:
  188. cunit@f200 {
  189. reg = <0xf200 0x200>;
  190. };
  191. g) Marvell Discovery MPSCROUTING nodes
  192. Represent the Discovery's MPSC routing hardware
  193. Required properties:
  194. - reg : Offset and length of the register set for this device
  195. Example Discovery CUNIT node:
  196. mpscrouting@b500 {
  197. reg = <0xb400 0xc>;
  198. };
  199. h) Marvell Discovery MPSCINTR nodes
  200. Represent the Discovery's MPSC DMA interrupt hardware registers
  201. (SDMA cause and mask registers).
  202. Required properties:
  203. - reg : Offset and length of the register set for this device
  204. Example Discovery MPSCINTR node:
  205. mpsintr@b800 {
  206. reg = <0xb800 0x100>;
  207. };
  208. i) Marvell Discovery MPSC nodes
  209. Represent the Discovery's MPSC (Multiprotocol Serial Controller)
  210. serial port.
  211. Required properties:
  212. - device_type : "serial"
  213. - compatible : "marvell,mv64360-mpsc"
  214. - reg : Offset and length of the register set for this device
  215. - sdma : the phandle for the SDMA node used by this port
  216. - brg : the phandle for the BRG node used by this port
  217. - cunit : the phandle for the CUNIT node used by this port
  218. - mpscrouting : the phandle for the MPSCROUTING node used by this port
  219. - mpscintr : the phandle for the MPSCINTR node used by this port
  220. - cell-index : the hardware index of this cell in the MPSC core
  221. - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
  222. register
  223. - interrupts : <a> where a is the interrupt number for the MPSC.
  224. - interrupt-parent : the phandle for the interrupt controller
  225. that services interrupts for this device.
  226. Example Discovery MPSCINTR node:
  227. mpsc@8000 {
  228. device_type = "serial";
  229. compatible = "marvell,mv64360-mpsc";
  230. reg = <0x8000 0x38>;
  231. virtual-reg = <0xf1008000>;
  232. sdma = <&SDMA0>;
  233. brg = <&BRG0>;
  234. cunit = <&CUNIT>;
  235. mpscrouting = <&MPSCROUTING>;
  236. mpscintr = <&MPSCINTR>;
  237. cell-index = <0>;
  238. max_idle = <40>;
  239. interrupts = <40>;
  240. interrupt-parent = <&PIC>;
  241. };
  242. j) Marvell Discovery Watch Dog Timer nodes
  243. Represent the Discovery's watchdog timer hardware
  244. Required properties:
  245. - compatible : "marvell,mv64360-wdt"
  246. - reg : Offset and length of the register set for this device
  247. Example Discovery Watch Dog Timer node:
  248. wdt@b410 {
  249. compatible = "marvell,mv64360-wdt";
  250. reg = <0xb410 0x8>;
  251. };
  252. k) Marvell Discovery I2C nodes
  253. Represent the Discovery's I2C hardware
  254. Required properties:
  255. - device_type : "i2c"
  256. - compatible : "marvell,mv64360-i2c"
  257. - reg : Offset and length of the register set for this device
  258. - interrupts : <a> where a is the interrupt number for the I2C.
  259. - interrupt-parent : the phandle for the interrupt controller
  260. that services interrupts for this device.
  261. Example Discovery I2C node:
  262. compatible = "marvell,mv64360-i2c";
  263. reg = <0xc000 0x20>;
  264. virtual-reg = <0xf100c000>;
  265. interrupts = <37>;
  266. interrupt-parent = <&PIC>;
  267. };
  268. l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
  269. Represent the Discovery's PIC hardware
  270. Required properties:
  271. - #interrupt-cells : <1>
  272. - #address-cells : <0>
  273. - compatible : "marvell,mv64360-pic"
  274. - reg : Offset and length of the register set for this device
  275. - interrupt-controller
  276. Example Discovery PIC node:
  277. pic {
  278. #interrupt-cells = <1>;
  279. #address-cells = <0>;
  280. compatible = "marvell,mv64360-pic";
  281. reg = <0x0 0x88>;
  282. interrupt-controller;
  283. };
  284. m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
  285. Represent the Discovery's MPP hardware
  286. Required properties:
  287. - compatible : "marvell,mv64360-mpp"
  288. - reg : Offset and length of the register set for this device
  289. Example Discovery MPP node:
  290. mpp@f000 {
  291. compatible = "marvell,mv64360-mpp";
  292. reg = <0xf000 0x10>;
  293. };
  294. n) Marvell Discovery GPP (General Purpose Pins) nodes
  295. Represent the Discovery's GPP hardware
  296. Required properties:
  297. - compatible : "marvell,mv64360-gpp"
  298. - reg : Offset and length of the register set for this device
  299. Example Discovery GPP node:
  300. gpp@f000 {
  301. compatible = "marvell,mv64360-gpp";
  302. reg = <0xf100 0x20>;
  303. };
  304. o) Marvell Discovery PCI host bridge node
  305. Represents the Discovery's PCI host bridge device. The properties
  306. for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
  307. 1275-1994. A typical value for the compatible property is
  308. "marvell,mv64360-pci".
  309. Example Discovery PCI host bridge node
  310. pci@80000000 {
  311. #address-cells = <3>;
  312. #size-cells = <2>;
  313. #interrupt-cells = <1>;
  314. device_type = "pci";
  315. compatible = "marvell,mv64360-pci";
  316. reg = <0xcf8 0x8>;
  317. ranges = <0x01000000 0x0 0x0
  318. 0x88000000 0x0 0x01000000
  319. 0x02000000 0x0 0x80000000
  320. 0x80000000 0x0 0x08000000>;
  321. bus-range = <0 255>;
  322. clock-frequency = <66000000>;
  323. interrupt-parent = <&PIC>;
  324. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  325. interrupt-map = <
  326. /* IDSEL 0x0a */
  327. 0x5000 0 0 1 &PIC 80
  328. 0x5000 0 0 2 &PIC 81
  329. 0x5000 0 0 3 &PIC 91
  330. 0x5000 0 0 4 &PIC 93
  331. /* IDSEL 0x0b */
  332. 0x5800 0 0 1 &PIC 91
  333. 0x5800 0 0 2 &PIC 93
  334. 0x5800 0 0 3 &PIC 80
  335. 0x5800 0 0 4 &PIC 81
  336. /* IDSEL 0x0c */
  337. 0x6000 0 0 1 &PIC 91
  338. 0x6000 0 0 2 &PIC 93
  339. 0x6000 0 0 3 &PIC 80
  340. 0x6000 0 0 4 &PIC 81
  341. /* IDSEL 0x0d */
  342. 0x6800 0 0 1 &PIC 93
  343. 0x6800 0 0 2 &PIC 80
  344. 0x6800 0 0 3 &PIC 81
  345. 0x6800 0 0 4 &PIC 91
  346. >;
  347. };
  348. p) Marvell Discovery CPU Error nodes
  349. Represent the Discovery's CPU error handler device.
  350. Required properties:
  351. - compatible : "marvell,mv64360-cpu-error"
  352. - reg : Offset and length of the register set for this device
  353. - interrupts : the interrupt number for this device
  354. - interrupt-parent : the phandle for the interrupt controller
  355. that services interrupts for this device.
  356. Example Discovery CPU Error node:
  357. cpu-error@0070 {
  358. compatible = "marvell,mv64360-cpu-error";
  359. reg = <0x70 0x10 0x128 0x28>;
  360. interrupts = <3>;
  361. interrupt-parent = <&PIC>;
  362. };
  363. q) Marvell Discovery SRAM Controller nodes
  364. Represent the Discovery's SRAM controller device.
  365. Required properties:
  366. - compatible : "marvell,mv64360-sram-ctrl"
  367. - reg : Offset and length of the register set for this device
  368. - interrupts : the interrupt number for this device
  369. - interrupt-parent : the phandle for the interrupt controller
  370. that services interrupts for this device.
  371. Example Discovery SRAM Controller node:
  372. sram-ctrl@0380 {
  373. compatible = "marvell,mv64360-sram-ctrl";
  374. reg = <0x380 0x80>;
  375. interrupts = <13>;
  376. interrupt-parent = <&PIC>;
  377. };
  378. r) Marvell Discovery PCI Error Handler nodes
  379. Represent the Discovery's PCI error handler device.
  380. Required properties:
  381. - compatible : "marvell,mv64360-pci-error"
  382. - reg : Offset and length of the register set for this device
  383. - interrupts : the interrupt number for this device
  384. - interrupt-parent : the phandle for the interrupt controller
  385. that services interrupts for this device.
  386. Example Discovery PCI Error Handler node:
  387. pci-error@1d40 {
  388. compatible = "marvell,mv64360-pci-error";
  389. reg = <0x1d40 0x40 0xc28 0x4>;
  390. interrupts = <12>;
  391. interrupt-parent = <&PIC>;
  392. };
  393. s) Marvell Discovery Memory Controller nodes
  394. Represent the Discovery's memory controller device.
  395. Required properties:
  396. - compatible : "marvell,mv64360-mem-ctrl"
  397. - reg : Offset and length of the register set for this device
  398. - interrupts : the interrupt number for this device
  399. - interrupt-parent : the phandle for the interrupt controller
  400. that services interrupts for this device.
  401. Example Discovery Memory Controller node:
  402. mem-ctrl@1400 {
  403. compatible = "marvell,mv64360-mem-ctrl";
  404. reg = <0x1400 0x60>;
  405. interrupts = <17>;
  406. interrupt-parent = <&PIC>;
  407. };