qib_rc.c 61 KB

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  1. /*
  2. * Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved.
  3. * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/io.h>
  34. #include "qib.h"
  35. /* cut down ridiculously long IB macro names */
  36. #define OP(x) IB_OPCODE_RC_##x
  37. static void rc_timeout(unsigned long arg);
  38. static u32 restart_sge(struct qib_sge_state *ss, struct qib_swqe *wqe,
  39. u32 psn, u32 pmtu)
  40. {
  41. u32 len;
  42. len = ((psn - wqe->psn) & QIB_PSN_MASK) * pmtu;
  43. ss->sge = wqe->sg_list[0];
  44. ss->sg_list = wqe->sg_list + 1;
  45. ss->num_sge = wqe->wr.num_sge;
  46. ss->total_len = wqe->length;
  47. qib_skip_sge(ss, len, 0);
  48. return wqe->length - len;
  49. }
  50. static void start_timer(struct qib_qp *qp)
  51. {
  52. qp->s_flags |= QIB_S_TIMER;
  53. qp->s_timer.function = rc_timeout;
  54. /* 4.096 usec. * (1 << qp->timeout) */
  55. qp->s_timer.expires = jiffies +
  56. usecs_to_jiffies((4096UL * (1UL << qp->timeout)) / 1000UL);
  57. add_timer(&qp->s_timer);
  58. }
  59. /**
  60. * qib_make_rc_ack - construct a response packet (ACK, NAK, or RDMA read)
  61. * @dev: the device for this QP
  62. * @qp: a pointer to the QP
  63. * @ohdr: a pointer to the IB header being constructed
  64. * @pmtu: the path MTU
  65. *
  66. * Return 1 if constructed; otherwise, return 0.
  67. * Note that we are in the responder's side of the QP context.
  68. * Note the QP s_lock must be held.
  69. */
  70. static int qib_make_rc_ack(struct qib_ibdev *dev, struct qib_qp *qp,
  71. struct qib_other_headers *ohdr, u32 pmtu)
  72. {
  73. struct qib_ack_entry *e;
  74. u32 hwords;
  75. u32 len;
  76. u32 bth0;
  77. u32 bth2;
  78. /* Don't send an ACK if we aren't supposed to. */
  79. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK))
  80. goto bail;
  81. /* header size in 32-bit words LRH+BTH = (8+12)/4. */
  82. hwords = 5;
  83. switch (qp->s_ack_state) {
  84. case OP(RDMA_READ_RESPONSE_LAST):
  85. case OP(RDMA_READ_RESPONSE_ONLY):
  86. e = &qp->s_ack_queue[qp->s_tail_ack_queue];
  87. if (e->rdma_sge.mr) {
  88. atomic_dec(&e->rdma_sge.mr->refcount);
  89. e->rdma_sge.mr = NULL;
  90. }
  91. /* FALLTHROUGH */
  92. case OP(ATOMIC_ACKNOWLEDGE):
  93. /*
  94. * We can increment the tail pointer now that the last
  95. * response has been sent instead of only being
  96. * constructed.
  97. */
  98. if (++qp->s_tail_ack_queue > QIB_MAX_RDMA_ATOMIC)
  99. qp->s_tail_ack_queue = 0;
  100. /* FALLTHROUGH */
  101. case OP(SEND_ONLY):
  102. case OP(ACKNOWLEDGE):
  103. /* Check for no next entry in the queue. */
  104. if (qp->r_head_ack_queue == qp->s_tail_ack_queue) {
  105. if (qp->s_flags & QIB_S_ACK_PENDING)
  106. goto normal;
  107. goto bail;
  108. }
  109. e = &qp->s_ack_queue[qp->s_tail_ack_queue];
  110. if (e->opcode == OP(RDMA_READ_REQUEST)) {
  111. /*
  112. * If a RDMA read response is being resent and
  113. * we haven't seen the duplicate request yet,
  114. * then stop sending the remaining responses the
  115. * responder has seen until the requester resends it.
  116. */
  117. len = e->rdma_sge.sge_length;
  118. if (len && !e->rdma_sge.mr) {
  119. qp->s_tail_ack_queue = qp->r_head_ack_queue;
  120. goto bail;
  121. }
  122. /* Copy SGE state in case we need to resend */
  123. qp->s_rdma_mr = e->rdma_sge.mr;
  124. if (qp->s_rdma_mr)
  125. atomic_inc(&qp->s_rdma_mr->refcount);
  126. qp->s_ack_rdma_sge.sge = e->rdma_sge;
  127. qp->s_ack_rdma_sge.num_sge = 1;
  128. qp->s_cur_sge = &qp->s_ack_rdma_sge;
  129. if (len > pmtu) {
  130. len = pmtu;
  131. qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
  132. } else {
  133. qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY);
  134. e->sent = 1;
  135. }
  136. ohdr->u.aeth = qib_compute_aeth(qp);
  137. hwords++;
  138. qp->s_ack_rdma_psn = e->psn;
  139. bth2 = qp->s_ack_rdma_psn++ & QIB_PSN_MASK;
  140. } else {
  141. /* COMPARE_SWAP or FETCH_ADD */
  142. qp->s_cur_sge = NULL;
  143. len = 0;
  144. qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
  145. ohdr->u.at.aeth = qib_compute_aeth(qp);
  146. ohdr->u.at.atomic_ack_eth[0] =
  147. cpu_to_be32(e->atomic_data >> 32);
  148. ohdr->u.at.atomic_ack_eth[1] =
  149. cpu_to_be32(e->atomic_data);
  150. hwords += sizeof(ohdr->u.at) / sizeof(u32);
  151. bth2 = e->psn & QIB_PSN_MASK;
  152. e->sent = 1;
  153. }
  154. bth0 = qp->s_ack_state << 24;
  155. break;
  156. case OP(RDMA_READ_RESPONSE_FIRST):
  157. qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
  158. /* FALLTHROUGH */
  159. case OP(RDMA_READ_RESPONSE_MIDDLE):
  160. qp->s_cur_sge = &qp->s_ack_rdma_sge;
  161. qp->s_rdma_mr = qp->s_ack_rdma_sge.sge.mr;
  162. if (qp->s_rdma_mr)
  163. atomic_inc(&qp->s_rdma_mr->refcount);
  164. len = qp->s_ack_rdma_sge.sge.sge_length;
  165. if (len > pmtu)
  166. len = pmtu;
  167. else {
  168. ohdr->u.aeth = qib_compute_aeth(qp);
  169. hwords++;
  170. qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
  171. e = &qp->s_ack_queue[qp->s_tail_ack_queue];
  172. e->sent = 1;
  173. }
  174. bth0 = qp->s_ack_state << 24;
  175. bth2 = qp->s_ack_rdma_psn++ & QIB_PSN_MASK;
  176. break;
  177. default:
  178. normal:
  179. /*
  180. * Send a regular ACK.
  181. * Set the s_ack_state so we wait until after sending
  182. * the ACK before setting s_ack_state to ACKNOWLEDGE
  183. * (see above).
  184. */
  185. qp->s_ack_state = OP(SEND_ONLY);
  186. qp->s_flags &= ~QIB_S_ACK_PENDING;
  187. qp->s_cur_sge = NULL;
  188. if (qp->s_nak_state)
  189. ohdr->u.aeth =
  190. cpu_to_be32((qp->r_msn & QIB_MSN_MASK) |
  191. (qp->s_nak_state <<
  192. QIB_AETH_CREDIT_SHIFT));
  193. else
  194. ohdr->u.aeth = qib_compute_aeth(qp);
  195. hwords++;
  196. len = 0;
  197. bth0 = OP(ACKNOWLEDGE) << 24;
  198. bth2 = qp->s_ack_psn & QIB_PSN_MASK;
  199. }
  200. qp->s_rdma_ack_cnt++;
  201. qp->s_hdrwords = hwords;
  202. qp->s_cur_size = len;
  203. qib_make_ruc_header(qp, ohdr, bth0, bth2);
  204. return 1;
  205. bail:
  206. qp->s_ack_state = OP(ACKNOWLEDGE);
  207. qp->s_flags &= ~(QIB_S_RESP_PENDING | QIB_S_ACK_PENDING);
  208. return 0;
  209. }
  210. /**
  211. * qib_make_rc_req - construct a request packet (SEND, RDMA r/w, ATOMIC)
  212. * @qp: a pointer to the QP
  213. *
  214. * Return 1 if constructed; otherwise, return 0.
  215. */
  216. int qib_make_rc_req(struct qib_qp *qp)
  217. {
  218. struct qib_ibdev *dev = to_idev(qp->ibqp.device);
  219. struct qib_other_headers *ohdr;
  220. struct qib_sge_state *ss;
  221. struct qib_swqe *wqe;
  222. u32 hwords;
  223. u32 len;
  224. u32 bth0;
  225. u32 bth2;
  226. u32 pmtu = qp->pmtu;
  227. char newreq;
  228. unsigned long flags;
  229. int ret = 0;
  230. int delta;
  231. ohdr = &qp->s_hdr.u.oth;
  232. if (qp->remote_ah_attr.ah_flags & IB_AH_GRH)
  233. ohdr = &qp->s_hdr.u.l.oth;
  234. /*
  235. * The lock is needed to synchronize between the sending tasklet,
  236. * the receive interrupt handler, and timeout resends.
  237. */
  238. spin_lock_irqsave(&qp->s_lock, flags);
  239. /* Sending responses has higher priority over sending requests. */
  240. if ((qp->s_flags & QIB_S_RESP_PENDING) &&
  241. qib_make_rc_ack(dev, qp, ohdr, pmtu))
  242. goto done;
  243. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_SEND_OK)) {
  244. if (!(ib_qib_state_ops[qp->state] & QIB_FLUSH_SEND))
  245. goto bail;
  246. /* We are in the error state, flush the work request. */
  247. if (qp->s_last == qp->s_head)
  248. goto bail;
  249. /* If DMAs are in progress, we can't flush immediately. */
  250. if (atomic_read(&qp->s_dma_busy)) {
  251. qp->s_flags |= QIB_S_WAIT_DMA;
  252. goto bail;
  253. }
  254. wqe = get_swqe_ptr(qp, qp->s_last);
  255. while (qp->s_last != qp->s_acked) {
  256. qib_send_complete(qp, wqe, IB_WC_SUCCESS);
  257. if (++qp->s_last >= qp->s_size)
  258. qp->s_last = 0;
  259. wqe = get_swqe_ptr(qp, qp->s_last);
  260. }
  261. qib_send_complete(qp, wqe, IB_WC_WR_FLUSH_ERR);
  262. goto done;
  263. }
  264. if (qp->s_flags & (QIB_S_WAIT_RNR | QIB_S_WAIT_ACK))
  265. goto bail;
  266. if (qib_cmp24(qp->s_psn, qp->s_sending_hpsn) <= 0) {
  267. if (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0) {
  268. qp->s_flags |= QIB_S_WAIT_PSN;
  269. goto bail;
  270. }
  271. qp->s_sending_psn = qp->s_psn;
  272. qp->s_sending_hpsn = qp->s_psn - 1;
  273. }
  274. /* header size in 32-bit words LRH+BTH = (8+12)/4. */
  275. hwords = 5;
  276. bth0 = 0;
  277. /* Send a request. */
  278. wqe = get_swqe_ptr(qp, qp->s_cur);
  279. switch (qp->s_state) {
  280. default:
  281. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_NEXT_SEND_OK))
  282. goto bail;
  283. /*
  284. * Resend an old request or start a new one.
  285. *
  286. * We keep track of the current SWQE so that
  287. * we don't reset the "furthest progress" state
  288. * if we need to back up.
  289. */
  290. newreq = 0;
  291. if (qp->s_cur == qp->s_tail) {
  292. /* Check if send work queue is empty. */
  293. if (qp->s_tail == qp->s_head)
  294. goto bail;
  295. /*
  296. * If a fence is requested, wait for previous
  297. * RDMA read and atomic operations to finish.
  298. */
  299. if ((wqe->wr.send_flags & IB_SEND_FENCE) &&
  300. qp->s_num_rd_atomic) {
  301. qp->s_flags |= QIB_S_WAIT_FENCE;
  302. goto bail;
  303. }
  304. wqe->psn = qp->s_next_psn;
  305. newreq = 1;
  306. }
  307. /*
  308. * Note that we have to be careful not to modify the
  309. * original work request since we may need to resend
  310. * it.
  311. */
  312. len = wqe->length;
  313. ss = &qp->s_sge;
  314. bth2 = qp->s_psn & QIB_PSN_MASK;
  315. switch (wqe->wr.opcode) {
  316. case IB_WR_SEND:
  317. case IB_WR_SEND_WITH_IMM:
  318. /* If no credit, return. */
  319. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT) &&
  320. qib_cmp24(wqe->ssn, qp->s_lsn + 1) > 0) {
  321. qp->s_flags |= QIB_S_WAIT_SSN_CREDIT;
  322. goto bail;
  323. }
  324. wqe->lpsn = wqe->psn;
  325. if (len > pmtu) {
  326. wqe->lpsn += (len - 1) / pmtu;
  327. qp->s_state = OP(SEND_FIRST);
  328. len = pmtu;
  329. break;
  330. }
  331. if (wqe->wr.opcode == IB_WR_SEND)
  332. qp->s_state = OP(SEND_ONLY);
  333. else {
  334. qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE);
  335. /* Immediate data comes after the BTH */
  336. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  337. hwords += 1;
  338. }
  339. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  340. bth0 |= IB_BTH_SOLICITED;
  341. bth2 |= IB_BTH_REQ_ACK;
  342. if (++qp->s_cur == qp->s_size)
  343. qp->s_cur = 0;
  344. break;
  345. case IB_WR_RDMA_WRITE:
  346. if (newreq && !(qp->s_flags & QIB_S_UNLIMITED_CREDIT))
  347. qp->s_lsn++;
  348. /* FALLTHROUGH */
  349. case IB_WR_RDMA_WRITE_WITH_IMM:
  350. /* If no credit, return. */
  351. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT) &&
  352. qib_cmp24(wqe->ssn, qp->s_lsn + 1) > 0) {
  353. qp->s_flags |= QIB_S_WAIT_SSN_CREDIT;
  354. goto bail;
  355. }
  356. ohdr->u.rc.reth.vaddr =
  357. cpu_to_be64(wqe->wr.wr.rdma.remote_addr);
  358. ohdr->u.rc.reth.rkey =
  359. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  360. ohdr->u.rc.reth.length = cpu_to_be32(len);
  361. hwords += sizeof(struct ib_reth) / sizeof(u32);
  362. wqe->lpsn = wqe->psn;
  363. if (len > pmtu) {
  364. wqe->lpsn += (len - 1) / pmtu;
  365. qp->s_state = OP(RDMA_WRITE_FIRST);
  366. len = pmtu;
  367. break;
  368. }
  369. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  370. qp->s_state = OP(RDMA_WRITE_ONLY);
  371. else {
  372. qp->s_state =
  373. OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
  374. /* Immediate data comes after RETH */
  375. ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
  376. hwords += 1;
  377. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  378. bth0 |= IB_BTH_SOLICITED;
  379. }
  380. bth2 |= IB_BTH_REQ_ACK;
  381. if (++qp->s_cur == qp->s_size)
  382. qp->s_cur = 0;
  383. break;
  384. case IB_WR_RDMA_READ:
  385. /*
  386. * Don't allow more operations to be started
  387. * than the QP limits allow.
  388. */
  389. if (newreq) {
  390. if (qp->s_num_rd_atomic >=
  391. qp->s_max_rd_atomic) {
  392. qp->s_flags |= QIB_S_WAIT_RDMAR;
  393. goto bail;
  394. }
  395. qp->s_num_rd_atomic++;
  396. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT))
  397. qp->s_lsn++;
  398. /*
  399. * Adjust s_next_psn to count the
  400. * expected number of responses.
  401. */
  402. if (len > pmtu)
  403. qp->s_next_psn += (len - 1) / pmtu;
  404. wqe->lpsn = qp->s_next_psn++;
  405. }
  406. ohdr->u.rc.reth.vaddr =
  407. cpu_to_be64(wqe->wr.wr.rdma.remote_addr);
  408. ohdr->u.rc.reth.rkey =
  409. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  410. ohdr->u.rc.reth.length = cpu_to_be32(len);
  411. qp->s_state = OP(RDMA_READ_REQUEST);
  412. hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
  413. ss = NULL;
  414. len = 0;
  415. bth2 |= IB_BTH_REQ_ACK;
  416. if (++qp->s_cur == qp->s_size)
  417. qp->s_cur = 0;
  418. break;
  419. case IB_WR_ATOMIC_CMP_AND_SWP:
  420. case IB_WR_ATOMIC_FETCH_AND_ADD:
  421. /*
  422. * Don't allow more operations to be started
  423. * than the QP limits allow.
  424. */
  425. if (newreq) {
  426. if (qp->s_num_rd_atomic >=
  427. qp->s_max_rd_atomic) {
  428. qp->s_flags |= QIB_S_WAIT_RDMAR;
  429. goto bail;
  430. }
  431. qp->s_num_rd_atomic++;
  432. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT))
  433. qp->s_lsn++;
  434. wqe->lpsn = wqe->psn;
  435. }
  436. if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
  437. qp->s_state = OP(COMPARE_SWAP);
  438. ohdr->u.atomic_eth.swap_data = cpu_to_be64(
  439. wqe->wr.wr.atomic.swap);
  440. ohdr->u.atomic_eth.compare_data = cpu_to_be64(
  441. wqe->wr.wr.atomic.compare_add);
  442. } else {
  443. qp->s_state = OP(FETCH_ADD);
  444. ohdr->u.atomic_eth.swap_data = cpu_to_be64(
  445. wqe->wr.wr.atomic.compare_add);
  446. ohdr->u.atomic_eth.compare_data = 0;
  447. }
  448. ohdr->u.atomic_eth.vaddr[0] = cpu_to_be32(
  449. wqe->wr.wr.atomic.remote_addr >> 32);
  450. ohdr->u.atomic_eth.vaddr[1] = cpu_to_be32(
  451. wqe->wr.wr.atomic.remote_addr);
  452. ohdr->u.atomic_eth.rkey = cpu_to_be32(
  453. wqe->wr.wr.atomic.rkey);
  454. hwords += sizeof(struct ib_atomic_eth) / sizeof(u32);
  455. ss = NULL;
  456. len = 0;
  457. bth2 |= IB_BTH_REQ_ACK;
  458. if (++qp->s_cur == qp->s_size)
  459. qp->s_cur = 0;
  460. break;
  461. default:
  462. goto bail;
  463. }
  464. qp->s_sge.sge = wqe->sg_list[0];
  465. qp->s_sge.sg_list = wqe->sg_list + 1;
  466. qp->s_sge.num_sge = wqe->wr.num_sge;
  467. qp->s_sge.total_len = wqe->length;
  468. qp->s_len = wqe->length;
  469. if (newreq) {
  470. qp->s_tail++;
  471. if (qp->s_tail >= qp->s_size)
  472. qp->s_tail = 0;
  473. }
  474. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  475. qp->s_psn = wqe->lpsn + 1;
  476. else {
  477. qp->s_psn++;
  478. if (qib_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  479. qp->s_next_psn = qp->s_psn;
  480. }
  481. break;
  482. case OP(RDMA_READ_RESPONSE_FIRST):
  483. /*
  484. * qp->s_state is normally set to the opcode of the
  485. * last packet constructed for new requests and therefore
  486. * is never set to RDMA read response.
  487. * RDMA_READ_RESPONSE_FIRST is used by the ACK processing
  488. * thread to indicate a SEND needs to be restarted from an
  489. * earlier PSN without interferring with the sending thread.
  490. * See qib_restart_rc().
  491. */
  492. qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
  493. /* FALLTHROUGH */
  494. case OP(SEND_FIRST):
  495. qp->s_state = OP(SEND_MIDDLE);
  496. /* FALLTHROUGH */
  497. case OP(SEND_MIDDLE):
  498. bth2 = qp->s_psn++ & QIB_PSN_MASK;
  499. if (qib_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  500. qp->s_next_psn = qp->s_psn;
  501. ss = &qp->s_sge;
  502. len = qp->s_len;
  503. if (len > pmtu) {
  504. len = pmtu;
  505. break;
  506. }
  507. if (wqe->wr.opcode == IB_WR_SEND)
  508. qp->s_state = OP(SEND_LAST);
  509. else {
  510. qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
  511. /* Immediate data comes after the BTH */
  512. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  513. hwords += 1;
  514. }
  515. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  516. bth0 |= IB_BTH_SOLICITED;
  517. bth2 |= IB_BTH_REQ_ACK;
  518. qp->s_cur++;
  519. if (qp->s_cur >= qp->s_size)
  520. qp->s_cur = 0;
  521. break;
  522. case OP(RDMA_READ_RESPONSE_LAST):
  523. /*
  524. * qp->s_state is normally set to the opcode of the
  525. * last packet constructed for new requests and therefore
  526. * is never set to RDMA read response.
  527. * RDMA_READ_RESPONSE_LAST is used by the ACK processing
  528. * thread to indicate a RDMA write needs to be restarted from
  529. * an earlier PSN without interferring with the sending thread.
  530. * See qib_restart_rc().
  531. */
  532. qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
  533. /* FALLTHROUGH */
  534. case OP(RDMA_WRITE_FIRST):
  535. qp->s_state = OP(RDMA_WRITE_MIDDLE);
  536. /* FALLTHROUGH */
  537. case OP(RDMA_WRITE_MIDDLE):
  538. bth2 = qp->s_psn++ & QIB_PSN_MASK;
  539. if (qib_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  540. qp->s_next_psn = qp->s_psn;
  541. ss = &qp->s_sge;
  542. len = qp->s_len;
  543. if (len > pmtu) {
  544. len = pmtu;
  545. break;
  546. }
  547. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  548. qp->s_state = OP(RDMA_WRITE_LAST);
  549. else {
  550. qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
  551. /* Immediate data comes after the BTH */
  552. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  553. hwords += 1;
  554. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  555. bth0 |= IB_BTH_SOLICITED;
  556. }
  557. bth2 |= IB_BTH_REQ_ACK;
  558. qp->s_cur++;
  559. if (qp->s_cur >= qp->s_size)
  560. qp->s_cur = 0;
  561. break;
  562. case OP(RDMA_READ_RESPONSE_MIDDLE):
  563. /*
  564. * qp->s_state is normally set to the opcode of the
  565. * last packet constructed for new requests and therefore
  566. * is never set to RDMA read response.
  567. * RDMA_READ_RESPONSE_MIDDLE is used by the ACK processing
  568. * thread to indicate a RDMA read needs to be restarted from
  569. * an earlier PSN without interferring with the sending thread.
  570. * See qib_restart_rc().
  571. */
  572. len = ((qp->s_psn - wqe->psn) & QIB_PSN_MASK) * pmtu;
  573. ohdr->u.rc.reth.vaddr =
  574. cpu_to_be64(wqe->wr.wr.rdma.remote_addr + len);
  575. ohdr->u.rc.reth.rkey =
  576. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  577. ohdr->u.rc.reth.length = cpu_to_be32(wqe->length - len);
  578. qp->s_state = OP(RDMA_READ_REQUEST);
  579. hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
  580. bth2 = (qp->s_psn & QIB_PSN_MASK) | IB_BTH_REQ_ACK;
  581. qp->s_psn = wqe->lpsn + 1;
  582. ss = NULL;
  583. len = 0;
  584. qp->s_cur++;
  585. if (qp->s_cur == qp->s_size)
  586. qp->s_cur = 0;
  587. break;
  588. }
  589. qp->s_sending_hpsn = bth2;
  590. delta = (((int) bth2 - (int) wqe->psn) << 8) >> 8;
  591. if (delta && delta % QIB_PSN_CREDIT == 0)
  592. bth2 |= IB_BTH_REQ_ACK;
  593. if (qp->s_flags & QIB_S_SEND_ONE) {
  594. qp->s_flags &= ~QIB_S_SEND_ONE;
  595. qp->s_flags |= QIB_S_WAIT_ACK;
  596. bth2 |= IB_BTH_REQ_ACK;
  597. }
  598. qp->s_len -= len;
  599. qp->s_hdrwords = hwords;
  600. qp->s_cur_sge = ss;
  601. qp->s_cur_size = len;
  602. qib_make_ruc_header(qp, ohdr, bth0 | (qp->s_state << 24), bth2);
  603. done:
  604. ret = 1;
  605. goto unlock;
  606. bail:
  607. qp->s_flags &= ~QIB_S_BUSY;
  608. unlock:
  609. spin_unlock_irqrestore(&qp->s_lock, flags);
  610. return ret;
  611. }
  612. /**
  613. * qib_send_rc_ack - Construct an ACK packet and send it
  614. * @qp: a pointer to the QP
  615. *
  616. * This is called from qib_rc_rcv() and qib_kreceive().
  617. * Note that RDMA reads and atomics are handled in the
  618. * send side QP state and tasklet.
  619. */
  620. void qib_send_rc_ack(struct qib_qp *qp)
  621. {
  622. struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
  623. struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
  624. struct qib_pportdata *ppd = ppd_from_ibp(ibp);
  625. u64 pbc;
  626. u16 lrh0;
  627. u32 bth0;
  628. u32 hwords;
  629. u32 pbufn;
  630. u32 __iomem *piobuf;
  631. struct qib_ib_header hdr;
  632. struct qib_other_headers *ohdr;
  633. u32 control;
  634. unsigned long flags;
  635. spin_lock_irqsave(&qp->s_lock, flags);
  636. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK))
  637. goto unlock;
  638. /* Don't send ACK or NAK if a RDMA read or atomic is pending. */
  639. if ((qp->s_flags & QIB_S_RESP_PENDING) || qp->s_rdma_ack_cnt)
  640. goto queue_ack;
  641. /* Construct the header with s_lock held so APM doesn't change it. */
  642. ohdr = &hdr.u.oth;
  643. lrh0 = QIB_LRH_BTH;
  644. /* header size in 32-bit words LRH+BTH+AETH = (8+12+4)/4. */
  645. hwords = 6;
  646. if (unlikely(qp->remote_ah_attr.ah_flags & IB_AH_GRH)) {
  647. hwords += qib_make_grh(ibp, &hdr.u.l.grh,
  648. &qp->remote_ah_attr.grh, hwords, 0);
  649. ohdr = &hdr.u.l.oth;
  650. lrh0 = QIB_LRH_GRH;
  651. }
  652. /* read pkey_index w/o lock (its atomic) */
  653. bth0 = qib_get_pkey(ibp, qp->s_pkey_index) | (OP(ACKNOWLEDGE) << 24);
  654. if (qp->s_mig_state == IB_MIG_MIGRATED)
  655. bth0 |= IB_BTH_MIG_REQ;
  656. if (qp->r_nak_state)
  657. ohdr->u.aeth = cpu_to_be32((qp->r_msn & QIB_MSN_MASK) |
  658. (qp->r_nak_state <<
  659. QIB_AETH_CREDIT_SHIFT));
  660. else
  661. ohdr->u.aeth = qib_compute_aeth(qp);
  662. lrh0 |= ibp->sl_to_vl[qp->remote_ah_attr.sl] << 12 |
  663. qp->remote_ah_attr.sl << 4;
  664. hdr.lrh[0] = cpu_to_be16(lrh0);
  665. hdr.lrh[1] = cpu_to_be16(qp->remote_ah_attr.dlid);
  666. hdr.lrh[2] = cpu_to_be16(hwords + SIZE_OF_CRC);
  667. hdr.lrh[3] = cpu_to_be16(ppd->lid | qp->remote_ah_attr.src_path_bits);
  668. ohdr->bth[0] = cpu_to_be32(bth0);
  669. ohdr->bth[1] = cpu_to_be32(qp->remote_qpn);
  670. ohdr->bth[2] = cpu_to_be32(qp->r_ack_psn & QIB_PSN_MASK);
  671. spin_unlock_irqrestore(&qp->s_lock, flags);
  672. /* Don't try to send ACKs if the link isn't ACTIVE */
  673. if (!(ppd->lflags & QIBL_LINKACTIVE))
  674. goto done;
  675. control = dd->f_setpbc_control(ppd, hwords + SIZE_OF_CRC,
  676. qp->s_srate, lrh0 >> 12);
  677. /* length is + 1 for the control dword */
  678. pbc = ((u64) control << 32) | (hwords + 1);
  679. piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
  680. if (!piobuf) {
  681. /*
  682. * We are out of PIO buffers at the moment.
  683. * Pass responsibility for sending the ACK to the
  684. * send tasklet so that when a PIO buffer becomes
  685. * available, the ACK is sent ahead of other outgoing
  686. * packets.
  687. */
  688. spin_lock_irqsave(&qp->s_lock, flags);
  689. goto queue_ack;
  690. }
  691. /*
  692. * Write the pbc.
  693. * We have to flush after the PBC for correctness
  694. * on some cpus or WC buffer can be written out of order.
  695. */
  696. writeq(pbc, piobuf);
  697. if (dd->flags & QIB_PIO_FLUSH_WC) {
  698. u32 *hdrp = (u32 *) &hdr;
  699. qib_flush_wc();
  700. qib_pio_copy(piobuf + 2, hdrp, hwords - 1);
  701. qib_flush_wc();
  702. __raw_writel(hdrp[hwords - 1], piobuf + hwords + 1);
  703. } else
  704. qib_pio_copy(piobuf + 2, (u32 *) &hdr, hwords);
  705. if (dd->flags & QIB_USE_SPCL_TRIG) {
  706. u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
  707. qib_flush_wc();
  708. __raw_writel(0xaebecede, piobuf + spcl_off);
  709. }
  710. qib_flush_wc();
  711. qib_sendbuf_done(dd, pbufn);
  712. ibp->n_unicast_xmit++;
  713. goto done;
  714. queue_ack:
  715. if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
  716. ibp->n_rc_qacks++;
  717. qp->s_flags |= QIB_S_ACK_PENDING | QIB_S_RESP_PENDING;
  718. qp->s_nak_state = qp->r_nak_state;
  719. qp->s_ack_psn = qp->r_ack_psn;
  720. /* Schedule the send tasklet. */
  721. qib_schedule_send(qp);
  722. }
  723. unlock:
  724. spin_unlock_irqrestore(&qp->s_lock, flags);
  725. done:
  726. return;
  727. }
  728. /**
  729. * reset_psn - reset the QP state to send starting from PSN
  730. * @qp: the QP
  731. * @psn: the packet sequence number to restart at
  732. *
  733. * This is called from qib_rc_rcv() to process an incoming RC ACK
  734. * for the given QP.
  735. * Called at interrupt level with the QP s_lock held.
  736. */
  737. static void reset_psn(struct qib_qp *qp, u32 psn)
  738. {
  739. u32 n = qp->s_acked;
  740. struct qib_swqe *wqe = get_swqe_ptr(qp, n);
  741. u32 opcode;
  742. qp->s_cur = n;
  743. /*
  744. * If we are starting the request from the beginning,
  745. * let the normal send code handle initialization.
  746. */
  747. if (qib_cmp24(psn, wqe->psn) <= 0) {
  748. qp->s_state = OP(SEND_LAST);
  749. goto done;
  750. }
  751. /* Find the work request opcode corresponding to the given PSN. */
  752. opcode = wqe->wr.opcode;
  753. for (;;) {
  754. int diff;
  755. if (++n == qp->s_size)
  756. n = 0;
  757. if (n == qp->s_tail)
  758. break;
  759. wqe = get_swqe_ptr(qp, n);
  760. diff = qib_cmp24(psn, wqe->psn);
  761. if (diff < 0)
  762. break;
  763. qp->s_cur = n;
  764. /*
  765. * If we are starting the request from the beginning,
  766. * let the normal send code handle initialization.
  767. */
  768. if (diff == 0) {
  769. qp->s_state = OP(SEND_LAST);
  770. goto done;
  771. }
  772. opcode = wqe->wr.opcode;
  773. }
  774. /*
  775. * Set the state to restart in the middle of a request.
  776. * Don't change the s_sge, s_cur_sge, or s_cur_size.
  777. * See qib_make_rc_req().
  778. */
  779. switch (opcode) {
  780. case IB_WR_SEND:
  781. case IB_WR_SEND_WITH_IMM:
  782. qp->s_state = OP(RDMA_READ_RESPONSE_FIRST);
  783. break;
  784. case IB_WR_RDMA_WRITE:
  785. case IB_WR_RDMA_WRITE_WITH_IMM:
  786. qp->s_state = OP(RDMA_READ_RESPONSE_LAST);
  787. break;
  788. case IB_WR_RDMA_READ:
  789. qp->s_state = OP(RDMA_READ_RESPONSE_MIDDLE);
  790. break;
  791. default:
  792. /*
  793. * This case shouldn't happen since its only
  794. * one PSN per req.
  795. */
  796. qp->s_state = OP(SEND_LAST);
  797. }
  798. done:
  799. qp->s_psn = psn;
  800. /*
  801. * Set QIB_S_WAIT_PSN as qib_rc_complete() may start the timer
  802. * asynchronously before the send tasklet can get scheduled.
  803. * Doing it in qib_make_rc_req() is too late.
  804. */
  805. if ((qib_cmp24(qp->s_psn, qp->s_sending_hpsn) <= 0) &&
  806. (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0))
  807. qp->s_flags |= QIB_S_WAIT_PSN;
  808. }
  809. /*
  810. * Back up requester to resend the last un-ACKed request.
  811. * The QP r_lock and s_lock should be held and interrupts disabled.
  812. */
  813. static void qib_restart_rc(struct qib_qp *qp, u32 psn, int wait)
  814. {
  815. struct qib_swqe *wqe = get_swqe_ptr(qp, qp->s_acked);
  816. struct qib_ibport *ibp;
  817. if (qp->s_retry == 0) {
  818. if (qp->s_mig_state == IB_MIG_ARMED) {
  819. qib_migrate_qp(qp);
  820. qp->s_retry = qp->s_retry_cnt;
  821. } else if (qp->s_last == qp->s_acked) {
  822. qib_send_complete(qp, wqe, IB_WC_RETRY_EXC_ERR);
  823. qib_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  824. return;
  825. } else /* XXX need to handle delayed completion */
  826. return;
  827. } else
  828. qp->s_retry--;
  829. ibp = to_iport(qp->ibqp.device, qp->port_num);
  830. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  831. ibp->n_rc_resends++;
  832. else
  833. ibp->n_rc_resends += (qp->s_psn - psn) & QIB_PSN_MASK;
  834. qp->s_flags &= ~(QIB_S_WAIT_FENCE | QIB_S_WAIT_RDMAR |
  835. QIB_S_WAIT_SSN_CREDIT | QIB_S_WAIT_PSN |
  836. QIB_S_WAIT_ACK);
  837. if (wait)
  838. qp->s_flags |= QIB_S_SEND_ONE;
  839. reset_psn(qp, psn);
  840. }
  841. /*
  842. * This is called from s_timer for missing responses.
  843. */
  844. static void rc_timeout(unsigned long arg)
  845. {
  846. struct qib_qp *qp = (struct qib_qp *)arg;
  847. struct qib_ibport *ibp;
  848. unsigned long flags;
  849. spin_lock_irqsave(&qp->r_lock, flags);
  850. spin_lock(&qp->s_lock);
  851. if (qp->s_flags & QIB_S_TIMER) {
  852. ibp = to_iport(qp->ibqp.device, qp->port_num);
  853. ibp->n_rc_timeouts++;
  854. qp->s_flags &= ~QIB_S_TIMER;
  855. del_timer(&qp->s_timer);
  856. qib_restart_rc(qp, qp->s_last_psn + 1, 1);
  857. qib_schedule_send(qp);
  858. }
  859. spin_unlock(&qp->s_lock);
  860. spin_unlock_irqrestore(&qp->r_lock, flags);
  861. }
  862. /*
  863. * This is called from s_timer for RNR timeouts.
  864. */
  865. void qib_rc_rnr_retry(unsigned long arg)
  866. {
  867. struct qib_qp *qp = (struct qib_qp *)arg;
  868. unsigned long flags;
  869. spin_lock_irqsave(&qp->s_lock, flags);
  870. if (qp->s_flags & QIB_S_WAIT_RNR) {
  871. qp->s_flags &= ~QIB_S_WAIT_RNR;
  872. del_timer(&qp->s_timer);
  873. qib_schedule_send(qp);
  874. }
  875. spin_unlock_irqrestore(&qp->s_lock, flags);
  876. }
  877. /*
  878. * Set qp->s_sending_psn to the next PSN after the given one.
  879. * This would be psn+1 except when RDMA reads are present.
  880. */
  881. static void reset_sending_psn(struct qib_qp *qp, u32 psn)
  882. {
  883. struct qib_swqe *wqe;
  884. u32 n = qp->s_last;
  885. /* Find the work request corresponding to the given PSN. */
  886. for (;;) {
  887. wqe = get_swqe_ptr(qp, n);
  888. if (qib_cmp24(psn, wqe->lpsn) <= 0) {
  889. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  890. qp->s_sending_psn = wqe->lpsn + 1;
  891. else
  892. qp->s_sending_psn = psn + 1;
  893. break;
  894. }
  895. if (++n == qp->s_size)
  896. n = 0;
  897. if (n == qp->s_tail)
  898. break;
  899. }
  900. }
  901. /*
  902. * This should be called with the QP s_lock held and interrupts disabled.
  903. */
  904. void qib_rc_send_complete(struct qib_qp *qp, struct qib_ib_header *hdr)
  905. {
  906. struct qib_other_headers *ohdr;
  907. struct qib_swqe *wqe;
  908. struct ib_wc wc;
  909. unsigned i;
  910. u32 opcode;
  911. u32 psn;
  912. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_OR_FLUSH_SEND))
  913. return;
  914. /* Find out where the BTH is */
  915. if ((be16_to_cpu(hdr->lrh[0]) & 3) == QIB_LRH_BTH)
  916. ohdr = &hdr->u.oth;
  917. else
  918. ohdr = &hdr->u.l.oth;
  919. opcode = be32_to_cpu(ohdr->bth[0]) >> 24;
  920. if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
  921. opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
  922. WARN_ON(!qp->s_rdma_ack_cnt);
  923. qp->s_rdma_ack_cnt--;
  924. return;
  925. }
  926. psn = be32_to_cpu(ohdr->bth[2]);
  927. reset_sending_psn(qp, psn);
  928. /*
  929. * Start timer after a packet requesting an ACK has been sent and
  930. * there are still requests that haven't been acked.
  931. */
  932. if ((psn & IB_BTH_REQ_ACK) && qp->s_acked != qp->s_tail &&
  933. !(qp->s_flags & (QIB_S_TIMER | QIB_S_WAIT_RNR | QIB_S_WAIT_PSN)) &&
  934. (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK))
  935. start_timer(qp);
  936. while (qp->s_last != qp->s_acked) {
  937. wqe = get_swqe_ptr(qp, qp->s_last);
  938. if (qib_cmp24(wqe->lpsn, qp->s_sending_psn) >= 0 &&
  939. qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)
  940. break;
  941. for (i = 0; i < wqe->wr.num_sge; i++) {
  942. struct qib_sge *sge = &wqe->sg_list[i];
  943. atomic_dec(&sge->mr->refcount);
  944. }
  945. /* Post a send completion queue entry if requested. */
  946. if (!(qp->s_flags & QIB_S_SIGNAL_REQ_WR) ||
  947. (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
  948. memset(&wc, 0, sizeof wc);
  949. wc.wr_id = wqe->wr.wr_id;
  950. wc.status = IB_WC_SUCCESS;
  951. wc.opcode = ib_qib_wc_opcode[wqe->wr.opcode];
  952. wc.byte_len = wqe->length;
  953. wc.qp = &qp->ibqp;
  954. qib_cq_enter(to_icq(qp->ibqp.send_cq), &wc, 0);
  955. }
  956. if (++qp->s_last >= qp->s_size)
  957. qp->s_last = 0;
  958. }
  959. /*
  960. * If we were waiting for sends to complete before resending,
  961. * and they are now complete, restart sending.
  962. */
  963. if (qp->s_flags & QIB_S_WAIT_PSN &&
  964. qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
  965. qp->s_flags &= ~QIB_S_WAIT_PSN;
  966. qp->s_sending_psn = qp->s_psn;
  967. qp->s_sending_hpsn = qp->s_psn - 1;
  968. qib_schedule_send(qp);
  969. }
  970. }
  971. static inline void update_last_psn(struct qib_qp *qp, u32 psn)
  972. {
  973. qp->s_last_psn = psn;
  974. }
  975. /*
  976. * Generate a SWQE completion.
  977. * This is similar to qib_send_complete but has to check to be sure
  978. * that the SGEs are not being referenced if the SWQE is being resent.
  979. */
  980. static struct qib_swqe *do_rc_completion(struct qib_qp *qp,
  981. struct qib_swqe *wqe,
  982. struct qib_ibport *ibp)
  983. {
  984. struct ib_wc wc;
  985. unsigned i;
  986. /*
  987. * Don't decrement refcount and don't generate a
  988. * completion if the SWQE is being resent until the send
  989. * is finished.
  990. */
  991. if (qib_cmp24(wqe->lpsn, qp->s_sending_psn) < 0 ||
  992. qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
  993. for (i = 0; i < wqe->wr.num_sge; i++) {
  994. struct qib_sge *sge = &wqe->sg_list[i];
  995. atomic_dec(&sge->mr->refcount);
  996. }
  997. /* Post a send completion queue entry if requested. */
  998. if (!(qp->s_flags & QIB_S_SIGNAL_REQ_WR) ||
  999. (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
  1000. memset(&wc, 0, sizeof wc);
  1001. wc.wr_id = wqe->wr.wr_id;
  1002. wc.status = IB_WC_SUCCESS;
  1003. wc.opcode = ib_qib_wc_opcode[wqe->wr.opcode];
  1004. wc.byte_len = wqe->length;
  1005. wc.qp = &qp->ibqp;
  1006. qib_cq_enter(to_icq(qp->ibqp.send_cq), &wc, 0);
  1007. }
  1008. if (++qp->s_last >= qp->s_size)
  1009. qp->s_last = 0;
  1010. } else
  1011. ibp->n_rc_delayed_comp++;
  1012. qp->s_retry = qp->s_retry_cnt;
  1013. update_last_psn(qp, wqe->lpsn);
  1014. /*
  1015. * If we are completing a request which is in the process of
  1016. * being resent, we can stop resending it since we know the
  1017. * responder has already seen it.
  1018. */
  1019. if (qp->s_acked == qp->s_cur) {
  1020. if (++qp->s_cur >= qp->s_size)
  1021. qp->s_cur = 0;
  1022. qp->s_acked = qp->s_cur;
  1023. wqe = get_swqe_ptr(qp, qp->s_cur);
  1024. if (qp->s_acked != qp->s_tail) {
  1025. qp->s_state = OP(SEND_LAST);
  1026. qp->s_psn = wqe->psn;
  1027. }
  1028. } else {
  1029. if (++qp->s_acked >= qp->s_size)
  1030. qp->s_acked = 0;
  1031. if (qp->state == IB_QPS_SQD && qp->s_acked == qp->s_cur)
  1032. qp->s_draining = 0;
  1033. wqe = get_swqe_ptr(qp, qp->s_acked);
  1034. }
  1035. return wqe;
  1036. }
  1037. /**
  1038. * do_rc_ack - process an incoming RC ACK
  1039. * @qp: the QP the ACK came in on
  1040. * @psn: the packet sequence number of the ACK
  1041. * @opcode: the opcode of the request that resulted in the ACK
  1042. *
  1043. * This is called from qib_rc_rcv_resp() to process an incoming RC ACK
  1044. * for the given QP.
  1045. * Called at interrupt level with the QP s_lock held.
  1046. * Returns 1 if OK, 0 if current operation should be aborted (NAK).
  1047. */
  1048. static int do_rc_ack(struct qib_qp *qp, u32 aeth, u32 psn, int opcode,
  1049. u64 val, struct qib_ctxtdata *rcd)
  1050. {
  1051. struct qib_ibport *ibp;
  1052. enum ib_wc_status status;
  1053. struct qib_swqe *wqe;
  1054. int ret = 0;
  1055. u32 ack_psn;
  1056. int diff;
  1057. /* Remove QP from retry timer */
  1058. if (qp->s_flags & (QIB_S_TIMER | QIB_S_WAIT_RNR)) {
  1059. qp->s_flags &= ~(QIB_S_TIMER | QIB_S_WAIT_RNR);
  1060. del_timer(&qp->s_timer);
  1061. }
  1062. /*
  1063. * Note that NAKs implicitly ACK outstanding SEND and RDMA write
  1064. * requests and implicitly NAK RDMA read and atomic requests issued
  1065. * before the NAK'ed request. The MSN won't include the NAK'ed
  1066. * request but will include an ACK'ed request(s).
  1067. */
  1068. ack_psn = psn;
  1069. if (aeth >> 29)
  1070. ack_psn--;
  1071. wqe = get_swqe_ptr(qp, qp->s_acked);
  1072. ibp = to_iport(qp->ibqp.device, qp->port_num);
  1073. /*
  1074. * The MSN might be for a later WQE than the PSN indicates so
  1075. * only complete WQEs that the PSN finishes.
  1076. */
  1077. while ((diff = qib_cmp24(ack_psn, wqe->lpsn)) >= 0) {
  1078. /*
  1079. * RDMA_READ_RESPONSE_ONLY is a special case since
  1080. * we want to generate completion events for everything
  1081. * before the RDMA read, copy the data, then generate
  1082. * the completion for the read.
  1083. */
  1084. if (wqe->wr.opcode == IB_WR_RDMA_READ &&
  1085. opcode == OP(RDMA_READ_RESPONSE_ONLY) &&
  1086. diff == 0) {
  1087. ret = 1;
  1088. goto bail;
  1089. }
  1090. /*
  1091. * If this request is a RDMA read or atomic, and the ACK is
  1092. * for a later operation, this ACK NAKs the RDMA read or
  1093. * atomic. In other words, only a RDMA_READ_LAST or ONLY
  1094. * can ACK a RDMA read and likewise for atomic ops. Note
  1095. * that the NAK case can only happen if relaxed ordering is
  1096. * used and requests are sent after an RDMA read or atomic
  1097. * is sent but before the response is received.
  1098. */
  1099. if ((wqe->wr.opcode == IB_WR_RDMA_READ &&
  1100. (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) ||
  1101. ((wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1102. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) &&
  1103. (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0))) {
  1104. /* Retry this request. */
  1105. if (!(qp->r_flags & QIB_R_RDMAR_SEQ)) {
  1106. qp->r_flags |= QIB_R_RDMAR_SEQ;
  1107. qib_restart_rc(qp, qp->s_last_psn + 1, 0);
  1108. if (list_empty(&qp->rspwait)) {
  1109. qp->r_flags |= QIB_R_RSP_SEND;
  1110. atomic_inc(&qp->refcount);
  1111. list_add_tail(&qp->rspwait,
  1112. &rcd->qp_wait_list);
  1113. }
  1114. }
  1115. /*
  1116. * No need to process the ACK/NAK since we are
  1117. * restarting an earlier request.
  1118. */
  1119. goto bail;
  1120. }
  1121. if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1122. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
  1123. u64 *vaddr = wqe->sg_list[0].vaddr;
  1124. *vaddr = val;
  1125. }
  1126. if (qp->s_num_rd_atomic &&
  1127. (wqe->wr.opcode == IB_WR_RDMA_READ ||
  1128. wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1129. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)) {
  1130. qp->s_num_rd_atomic--;
  1131. /* Restart sending task if fence is complete */
  1132. if ((qp->s_flags & QIB_S_WAIT_FENCE) &&
  1133. !qp->s_num_rd_atomic) {
  1134. qp->s_flags &= ~(QIB_S_WAIT_FENCE |
  1135. QIB_S_WAIT_ACK);
  1136. qib_schedule_send(qp);
  1137. } else if (qp->s_flags & QIB_S_WAIT_RDMAR) {
  1138. qp->s_flags &= ~(QIB_S_WAIT_RDMAR |
  1139. QIB_S_WAIT_ACK);
  1140. qib_schedule_send(qp);
  1141. }
  1142. }
  1143. wqe = do_rc_completion(qp, wqe, ibp);
  1144. if (qp->s_acked == qp->s_tail)
  1145. break;
  1146. }
  1147. switch (aeth >> 29) {
  1148. case 0: /* ACK */
  1149. ibp->n_rc_acks++;
  1150. if (qp->s_acked != qp->s_tail) {
  1151. /*
  1152. * We are expecting more ACKs so
  1153. * reset the retransmit timer.
  1154. */
  1155. start_timer(qp);
  1156. /*
  1157. * We can stop resending the earlier packets and
  1158. * continue with the next packet the receiver wants.
  1159. */
  1160. if (qib_cmp24(qp->s_psn, psn) <= 0)
  1161. reset_psn(qp, psn + 1);
  1162. } else if (qib_cmp24(qp->s_psn, psn) <= 0) {
  1163. qp->s_state = OP(SEND_LAST);
  1164. qp->s_psn = psn + 1;
  1165. }
  1166. if (qp->s_flags & QIB_S_WAIT_ACK) {
  1167. qp->s_flags &= ~QIB_S_WAIT_ACK;
  1168. qib_schedule_send(qp);
  1169. }
  1170. qib_get_credit(qp, aeth);
  1171. qp->s_rnr_retry = qp->s_rnr_retry_cnt;
  1172. qp->s_retry = qp->s_retry_cnt;
  1173. update_last_psn(qp, psn);
  1174. ret = 1;
  1175. goto bail;
  1176. case 1: /* RNR NAK */
  1177. ibp->n_rnr_naks++;
  1178. if (qp->s_acked == qp->s_tail)
  1179. goto bail;
  1180. if (qp->s_flags & QIB_S_WAIT_RNR)
  1181. goto bail;
  1182. if (qp->s_rnr_retry == 0) {
  1183. status = IB_WC_RNR_RETRY_EXC_ERR;
  1184. goto class_b;
  1185. }
  1186. if (qp->s_rnr_retry_cnt < 7)
  1187. qp->s_rnr_retry--;
  1188. /* The last valid PSN is the previous PSN. */
  1189. update_last_psn(qp, psn - 1);
  1190. ibp->n_rc_resends += (qp->s_psn - psn) & QIB_PSN_MASK;
  1191. reset_psn(qp, psn);
  1192. qp->s_flags &= ~(QIB_S_WAIT_SSN_CREDIT | QIB_S_WAIT_ACK);
  1193. qp->s_flags |= QIB_S_WAIT_RNR;
  1194. qp->s_timer.function = qib_rc_rnr_retry;
  1195. qp->s_timer.expires = jiffies + usecs_to_jiffies(
  1196. ib_qib_rnr_table[(aeth >> QIB_AETH_CREDIT_SHIFT) &
  1197. QIB_AETH_CREDIT_MASK]);
  1198. add_timer(&qp->s_timer);
  1199. goto bail;
  1200. case 3: /* NAK */
  1201. if (qp->s_acked == qp->s_tail)
  1202. goto bail;
  1203. /* The last valid PSN is the previous PSN. */
  1204. update_last_psn(qp, psn - 1);
  1205. switch ((aeth >> QIB_AETH_CREDIT_SHIFT) &
  1206. QIB_AETH_CREDIT_MASK) {
  1207. case 0: /* PSN sequence error */
  1208. ibp->n_seq_naks++;
  1209. /*
  1210. * Back up to the responder's expected PSN.
  1211. * Note that we might get a NAK in the middle of an
  1212. * RDMA READ response which terminates the RDMA
  1213. * READ.
  1214. */
  1215. qib_restart_rc(qp, psn, 0);
  1216. qib_schedule_send(qp);
  1217. break;
  1218. case 1: /* Invalid Request */
  1219. status = IB_WC_REM_INV_REQ_ERR;
  1220. ibp->n_other_naks++;
  1221. goto class_b;
  1222. case 2: /* Remote Access Error */
  1223. status = IB_WC_REM_ACCESS_ERR;
  1224. ibp->n_other_naks++;
  1225. goto class_b;
  1226. case 3: /* Remote Operation Error */
  1227. status = IB_WC_REM_OP_ERR;
  1228. ibp->n_other_naks++;
  1229. class_b:
  1230. if (qp->s_last == qp->s_acked) {
  1231. qib_send_complete(qp, wqe, status);
  1232. qib_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  1233. }
  1234. break;
  1235. default:
  1236. /* Ignore other reserved NAK error codes */
  1237. goto reserved;
  1238. }
  1239. qp->s_retry = qp->s_retry_cnt;
  1240. qp->s_rnr_retry = qp->s_rnr_retry_cnt;
  1241. goto bail;
  1242. default: /* 2: reserved */
  1243. reserved:
  1244. /* Ignore reserved NAK codes. */
  1245. goto bail;
  1246. }
  1247. bail:
  1248. return ret;
  1249. }
  1250. /*
  1251. * We have seen an out of sequence RDMA read middle or last packet.
  1252. * This ACKs SENDs and RDMA writes up to the first RDMA read or atomic SWQE.
  1253. */
  1254. static void rdma_seq_err(struct qib_qp *qp, struct qib_ibport *ibp, u32 psn,
  1255. struct qib_ctxtdata *rcd)
  1256. {
  1257. struct qib_swqe *wqe;
  1258. /* Remove QP from retry timer */
  1259. if (qp->s_flags & (QIB_S_TIMER | QIB_S_WAIT_RNR)) {
  1260. qp->s_flags &= ~(QIB_S_TIMER | QIB_S_WAIT_RNR);
  1261. del_timer(&qp->s_timer);
  1262. }
  1263. wqe = get_swqe_ptr(qp, qp->s_acked);
  1264. while (qib_cmp24(psn, wqe->lpsn) > 0) {
  1265. if (wqe->wr.opcode == IB_WR_RDMA_READ ||
  1266. wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1267. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
  1268. break;
  1269. wqe = do_rc_completion(qp, wqe, ibp);
  1270. }
  1271. ibp->n_rdma_seq++;
  1272. qp->r_flags |= QIB_R_RDMAR_SEQ;
  1273. qib_restart_rc(qp, qp->s_last_psn + 1, 0);
  1274. if (list_empty(&qp->rspwait)) {
  1275. qp->r_flags |= QIB_R_RSP_SEND;
  1276. atomic_inc(&qp->refcount);
  1277. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  1278. }
  1279. }
  1280. /**
  1281. * qib_rc_rcv_resp - process an incoming RC response packet
  1282. * @ibp: the port this packet came in on
  1283. * @ohdr: the other headers for this packet
  1284. * @data: the packet data
  1285. * @tlen: the packet length
  1286. * @qp: the QP for this packet
  1287. * @opcode: the opcode for this packet
  1288. * @psn: the packet sequence number for this packet
  1289. * @hdrsize: the header length
  1290. * @pmtu: the path MTU
  1291. *
  1292. * This is called from qib_rc_rcv() to process an incoming RC response
  1293. * packet for the given QP.
  1294. * Called at interrupt level.
  1295. */
  1296. static void qib_rc_rcv_resp(struct qib_ibport *ibp,
  1297. struct qib_other_headers *ohdr,
  1298. void *data, u32 tlen,
  1299. struct qib_qp *qp,
  1300. u32 opcode,
  1301. u32 psn, u32 hdrsize, u32 pmtu,
  1302. struct qib_ctxtdata *rcd)
  1303. {
  1304. struct qib_swqe *wqe;
  1305. struct qib_pportdata *ppd = ppd_from_ibp(ibp);
  1306. enum ib_wc_status status;
  1307. unsigned long flags;
  1308. int diff;
  1309. u32 pad;
  1310. u32 aeth;
  1311. u64 val;
  1312. if (opcode != OP(RDMA_READ_RESPONSE_MIDDLE)) {
  1313. /*
  1314. * If ACK'd PSN on SDMA busy list try to make progress to
  1315. * reclaim SDMA credits.
  1316. */
  1317. if ((qib_cmp24(psn, qp->s_sending_psn) >= 0) &&
  1318. (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)) {
  1319. /*
  1320. * If send tasklet not running attempt to progress
  1321. * SDMA queue.
  1322. */
  1323. if (!(qp->s_flags & QIB_S_BUSY)) {
  1324. /* Acquire SDMA Lock */
  1325. spin_lock_irqsave(&ppd->sdma_lock, flags);
  1326. /* Invoke sdma make progress */
  1327. qib_sdma_make_progress(ppd);
  1328. /* Release SDMA Lock */
  1329. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1330. }
  1331. }
  1332. }
  1333. spin_lock_irqsave(&qp->s_lock, flags);
  1334. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK))
  1335. goto ack_done;
  1336. /* Ignore invalid responses. */
  1337. if (qib_cmp24(psn, qp->s_next_psn) >= 0)
  1338. goto ack_done;
  1339. /* Ignore duplicate responses. */
  1340. diff = qib_cmp24(psn, qp->s_last_psn);
  1341. if (unlikely(diff <= 0)) {
  1342. /* Update credits for "ghost" ACKs */
  1343. if (diff == 0 && opcode == OP(ACKNOWLEDGE)) {
  1344. aeth = be32_to_cpu(ohdr->u.aeth);
  1345. if ((aeth >> 29) == 0)
  1346. qib_get_credit(qp, aeth);
  1347. }
  1348. goto ack_done;
  1349. }
  1350. /*
  1351. * Skip everything other than the PSN we expect, if we are waiting
  1352. * for a reply to a restarted RDMA read or atomic op.
  1353. */
  1354. if (qp->r_flags & QIB_R_RDMAR_SEQ) {
  1355. if (qib_cmp24(psn, qp->s_last_psn + 1) != 0)
  1356. goto ack_done;
  1357. qp->r_flags &= ~QIB_R_RDMAR_SEQ;
  1358. }
  1359. if (unlikely(qp->s_acked == qp->s_tail))
  1360. goto ack_done;
  1361. wqe = get_swqe_ptr(qp, qp->s_acked);
  1362. status = IB_WC_SUCCESS;
  1363. switch (opcode) {
  1364. case OP(ACKNOWLEDGE):
  1365. case OP(ATOMIC_ACKNOWLEDGE):
  1366. case OP(RDMA_READ_RESPONSE_FIRST):
  1367. aeth = be32_to_cpu(ohdr->u.aeth);
  1368. if (opcode == OP(ATOMIC_ACKNOWLEDGE)) {
  1369. __be32 *p = ohdr->u.at.atomic_ack_eth;
  1370. val = ((u64) be32_to_cpu(p[0]) << 32) |
  1371. be32_to_cpu(p[1]);
  1372. } else
  1373. val = 0;
  1374. if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) ||
  1375. opcode != OP(RDMA_READ_RESPONSE_FIRST))
  1376. goto ack_done;
  1377. hdrsize += 4;
  1378. wqe = get_swqe_ptr(qp, qp->s_acked);
  1379. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1380. goto ack_op_err;
  1381. /*
  1382. * If this is a response to a resent RDMA read, we
  1383. * have to be careful to copy the data to the right
  1384. * location.
  1385. */
  1386. qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
  1387. wqe, psn, pmtu);
  1388. goto read_middle;
  1389. case OP(RDMA_READ_RESPONSE_MIDDLE):
  1390. /* no AETH, no ACK */
  1391. if (unlikely(qib_cmp24(psn, qp->s_last_psn + 1)))
  1392. goto ack_seq_err;
  1393. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1394. goto ack_op_err;
  1395. read_middle:
  1396. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  1397. goto ack_len_err;
  1398. if (unlikely(pmtu >= qp->s_rdma_read_len))
  1399. goto ack_len_err;
  1400. /*
  1401. * We got a response so update the timeout.
  1402. * 4.096 usec. * (1 << qp->timeout)
  1403. */
  1404. qp->s_flags |= QIB_S_TIMER;
  1405. mod_timer(&qp->s_timer, jiffies +
  1406. usecs_to_jiffies((4096UL * (1UL << qp->timeout)) /
  1407. 1000UL));
  1408. if (qp->s_flags & QIB_S_WAIT_ACK) {
  1409. qp->s_flags &= ~QIB_S_WAIT_ACK;
  1410. qib_schedule_send(qp);
  1411. }
  1412. if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE))
  1413. qp->s_retry = qp->s_retry_cnt;
  1414. /*
  1415. * Update the RDMA receive state but do the copy w/o
  1416. * holding the locks and blocking interrupts.
  1417. */
  1418. qp->s_rdma_read_len -= pmtu;
  1419. update_last_psn(qp, psn);
  1420. spin_unlock_irqrestore(&qp->s_lock, flags);
  1421. qib_copy_sge(&qp->s_rdma_read_sge, data, pmtu, 0);
  1422. goto bail;
  1423. case OP(RDMA_READ_RESPONSE_ONLY):
  1424. aeth = be32_to_cpu(ohdr->u.aeth);
  1425. if (!do_rc_ack(qp, aeth, psn, opcode, 0, rcd))
  1426. goto ack_done;
  1427. /* Get the number of bytes the message was padded by. */
  1428. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1429. /*
  1430. * Check that the data size is >= 0 && <= pmtu.
  1431. * Remember to account for the AETH header (4) and
  1432. * ICRC (4).
  1433. */
  1434. if (unlikely(tlen < (hdrsize + pad + 8)))
  1435. goto ack_len_err;
  1436. /*
  1437. * If this is a response to a resent RDMA read, we
  1438. * have to be careful to copy the data to the right
  1439. * location.
  1440. */
  1441. wqe = get_swqe_ptr(qp, qp->s_acked);
  1442. qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
  1443. wqe, psn, pmtu);
  1444. goto read_last;
  1445. case OP(RDMA_READ_RESPONSE_LAST):
  1446. /* ACKs READ req. */
  1447. if (unlikely(qib_cmp24(psn, qp->s_last_psn + 1)))
  1448. goto ack_seq_err;
  1449. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1450. goto ack_op_err;
  1451. /* Get the number of bytes the message was padded by. */
  1452. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1453. /*
  1454. * Check that the data size is >= 1 && <= pmtu.
  1455. * Remember to account for the AETH header (4) and
  1456. * ICRC (4).
  1457. */
  1458. if (unlikely(tlen <= (hdrsize + pad + 8)))
  1459. goto ack_len_err;
  1460. read_last:
  1461. tlen -= hdrsize + pad + 8;
  1462. if (unlikely(tlen != qp->s_rdma_read_len))
  1463. goto ack_len_err;
  1464. aeth = be32_to_cpu(ohdr->u.aeth);
  1465. qib_copy_sge(&qp->s_rdma_read_sge, data, tlen, 0);
  1466. WARN_ON(qp->s_rdma_read_sge.num_sge);
  1467. (void) do_rc_ack(qp, aeth, psn,
  1468. OP(RDMA_READ_RESPONSE_LAST), 0, rcd);
  1469. goto ack_done;
  1470. }
  1471. ack_op_err:
  1472. status = IB_WC_LOC_QP_OP_ERR;
  1473. goto ack_err;
  1474. ack_seq_err:
  1475. rdma_seq_err(qp, ibp, psn, rcd);
  1476. goto ack_done;
  1477. ack_len_err:
  1478. status = IB_WC_LOC_LEN_ERR;
  1479. ack_err:
  1480. if (qp->s_last == qp->s_acked) {
  1481. qib_send_complete(qp, wqe, status);
  1482. qib_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  1483. }
  1484. ack_done:
  1485. spin_unlock_irqrestore(&qp->s_lock, flags);
  1486. bail:
  1487. return;
  1488. }
  1489. /**
  1490. * qib_rc_rcv_error - process an incoming duplicate or error RC packet
  1491. * @ohdr: the other headers for this packet
  1492. * @data: the packet data
  1493. * @qp: the QP for this packet
  1494. * @opcode: the opcode for this packet
  1495. * @psn: the packet sequence number for this packet
  1496. * @diff: the difference between the PSN and the expected PSN
  1497. *
  1498. * This is called from qib_rc_rcv() to process an unexpected
  1499. * incoming RC packet for the given QP.
  1500. * Called at interrupt level.
  1501. * Return 1 if no more processing is needed; otherwise return 0 to
  1502. * schedule a response to be sent.
  1503. */
  1504. static int qib_rc_rcv_error(struct qib_other_headers *ohdr,
  1505. void *data,
  1506. struct qib_qp *qp,
  1507. u32 opcode,
  1508. u32 psn,
  1509. int diff,
  1510. struct qib_ctxtdata *rcd)
  1511. {
  1512. struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
  1513. struct qib_ack_entry *e;
  1514. unsigned long flags;
  1515. u8 i, prev;
  1516. int old_req;
  1517. if (diff > 0) {
  1518. /*
  1519. * Packet sequence error.
  1520. * A NAK will ACK earlier sends and RDMA writes.
  1521. * Don't queue the NAK if we already sent one.
  1522. */
  1523. if (!qp->r_nak_state) {
  1524. ibp->n_rc_seqnak++;
  1525. qp->r_nak_state = IB_NAK_PSN_ERROR;
  1526. /* Use the expected PSN. */
  1527. qp->r_ack_psn = qp->r_psn;
  1528. /*
  1529. * Wait to send the sequence NAK until all packets
  1530. * in the receive queue have been processed.
  1531. * Otherwise, we end up propagating congestion.
  1532. */
  1533. if (list_empty(&qp->rspwait)) {
  1534. qp->r_flags |= QIB_R_RSP_NAK;
  1535. atomic_inc(&qp->refcount);
  1536. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  1537. }
  1538. }
  1539. goto done;
  1540. }
  1541. /*
  1542. * Handle a duplicate request. Don't re-execute SEND, RDMA
  1543. * write or atomic op. Don't NAK errors, just silently drop
  1544. * the duplicate request. Note that r_sge, r_len, and
  1545. * r_rcv_len may be in use so don't modify them.
  1546. *
  1547. * We are supposed to ACK the earliest duplicate PSN but we
  1548. * can coalesce an outstanding duplicate ACK. We have to
  1549. * send the earliest so that RDMA reads can be restarted at
  1550. * the requester's expected PSN.
  1551. *
  1552. * First, find where this duplicate PSN falls within the
  1553. * ACKs previously sent.
  1554. * old_req is true if there is an older response that is scheduled
  1555. * to be sent before sending this one.
  1556. */
  1557. e = NULL;
  1558. old_req = 1;
  1559. ibp->n_rc_dupreq++;
  1560. spin_lock_irqsave(&qp->s_lock, flags);
  1561. for (i = qp->r_head_ack_queue; ; i = prev) {
  1562. if (i == qp->s_tail_ack_queue)
  1563. old_req = 0;
  1564. if (i)
  1565. prev = i - 1;
  1566. else
  1567. prev = QIB_MAX_RDMA_ATOMIC;
  1568. if (prev == qp->r_head_ack_queue) {
  1569. e = NULL;
  1570. break;
  1571. }
  1572. e = &qp->s_ack_queue[prev];
  1573. if (!e->opcode) {
  1574. e = NULL;
  1575. break;
  1576. }
  1577. if (qib_cmp24(psn, e->psn) >= 0) {
  1578. if (prev == qp->s_tail_ack_queue &&
  1579. qib_cmp24(psn, e->lpsn) <= 0)
  1580. old_req = 0;
  1581. break;
  1582. }
  1583. }
  1584. switch (opcode) {
  1585. case OP(RDMA_READ_REQUEST): {
  1586. struct ib_reth *reth;
  1587. u32 offset;
  1588. u32 len;
  1589. /*
  1590. * If we didn't find the RDMA read request in the ack queue,
  1591. * we can ignore this request.
  1592. */
  1593. if (!e || e->opcode != OP(RDMA_READ_REQUEST))
  1594. goto unlock_done;
  1595. /* RETH comes after BTH */
  1596. reth = &ohdr->u.rc.reth;
  1597. /*
  1598. * Address range must be a subset of the original
  1599. * request and start on pmtu boundaries.
  1600. * We reuse the old ack_queue slot since the requester
  1601. * should not back up and request an earlier PSN for the
  1602. * same request.
  1603. */
  1604. offset = ((psn - e->psn) & QIB_PSN_MASK) *
  1605. qp->pmtu;
  1606. len = be32_to_cpu(reth->length);
  1607. if (unlikely(offset + len != e->rdma_sge.sge_length))
  1608. goto unlock_done;
  1609. if (e->rdma_sge.mr) {
  1610. atomic_dec(&e->rdma_sge.mr->refcount);
  1611. e->rdma_sge.mr = NULL;
  1612. }
  1613. if (len != 0) {
  1614. u32 rkey = be32_to_cpu(reth->rkey);
  1615. u64 vaddr = be64_to_cpu(reth->vaddr);
  1616. int ok;
  1617. ok = qib_rkey_ok(qp, &e->rdma_sge, len, vaddr, rkey,
  1618. IB_ACCESS_REMOTE_READ);
  1619. if (unlikely(!ok))
  1620. goto unlock_done;
  1621. } else {
  1622. e->rdma_sge.vaddr = NULL;
  1623. e->rdma_sge.length = 0;
  1624. e->rdma_sge.sge_length = 0;
  1625. }
  1626. e->psn = psn;
  1627. if (old_req)
  1628. goto unlock_done;
  1629. qp->s_tail_ack_queue = prev;
  1630. break;
  1631. }
  1632. case OP(COMPARE_SWAP):
  1633. case OP(FETCH_ADD): {
  1634. /*
  1635. * If we didn't find the atomic request in the ack queue
  1636. * or the send tasklet is already backed up to send an
  1637. * earlier entry, we can ignore this request.
  1638. */
  1639. if (!e || e->opcode != (u8) opcode || old_req)
  1640. goto unlock_done;
  1641. qp->s_tail_ack_queue = prev;
  1642. break;
  1643. }
  1644. default:
  1645. /*
  1646. * Ignore this operation if it doesn't request an ACK
  1647. * or an earlier RDMA read or atomic is going to be resent.
  1648. */
  1649. if (!(psn & IB_BTH_REQ_ACK) || old_req)
  1650. goto unlock_done;
  1651. /*
  1652. * Resend the most recent ACK if this request is
  1653. * after all the previous RDMA reads and atomics.
  1654. */
  1655. if (i == qp->r_head_ack_queue) {
  1656. spin_unlock_irqrestore(&qp->s_lock, flags);
  1657. qp->r_nak_state = 0;
  1658. qp->r_ack_psn = qp->r_psn - 1;
  1659. goto send_ack;
  1660. }
  1661. /*
  1662. * Try to send a simple ACK to work around a Mellanox bug
  1663. * which doesn't accept a RDMA read response or atomic
  1664. * response as an ACK for earlier SENDs or RDMA writes.
  1665. */
  1666. if (!(qp->s_flags & QIB_S_RESP_PENDING)) {
  1667. spin_unlock_irqrestore(&qp->s_lock, flags);
  1668. qp->r_nak_state = 0;
  1669. qp->r_ack_psn = qp->s_ack_queue[i].psn - 1;
  1670. goto send_ack;
  1671. }
  1672. /*
  1673. * Resend the RDMA read or atomic op which
  1674. * ACKs this duplicate request.
  1675. */
  1676. qp->s_tail_ack_queue = i;
  1677. break;
  1678. }
  1679. qp->s_ack_state = OP(ACKNOWLEDGE);
  1680. qp->s_flags |= QIB_S_RESP_PENDING;
  1681. qp->r_nak_state = 0;
  1682. qib_schedule_send(qp);
  1683. unlock_done:
  1684. spin_unlock_irqrestore(&qp->s_lock, flags);
  1685. done:
  1686. return 1;
  1687. send_ack:
  1688. return 0;
  1689. }
  1690. void qib_rc_error(struct qib_qp *qp, enum ib_wc_status err)
  1691. {
  1692. unsigned long flags;
  1693. int lastwqe;
  1694. spin_lock_irqsave(&qp->s_lock, flags);
  1695. lastwqe = qib_error_qp(qp, err);
  1696. spin_unlock_irqrestore(&qp->s_lock, flags);
  1697. if (lastwqe) {
  1698. struct ib_event ev;
  1699. ev.device = qp->ibqp.device;
  1700. ev.element.qp = &qp->ibqp;
  1701. ev.event = IB_EVENT_QP_LAST_WQE_REACHED;
  1702. qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
  1703. }
  1704. }
  1705. static inline void qib_update_ack_queue(struct qib_qp *qp, unsigned n)
  1706. {
  1707. unsigned next;
  1708. next = n + 1;
  1709. if (next > QIB_MAX_RDMA_ATOMIC)
  1710. next = 0;
  1711. qp->s_tail_ack_queue = next;
  1712. qp->s_ack_state = OP(ACKNOWLEDGE);
  1713. }
  1714. /**
  1715. * qib_rc_rcv - process an incoming RC packet
  1716. * @rcd: the context pointer
  1717. * @hdr: the header of this packet
  1718. * @has_grh: true if the header has a GRH
  1719. * @data: the packet data
  1720. * @tlen: the packet length
  1721. * @qp: the QP for this packet
  1722. *
  1723. * This is called from qib_qp_rcv() to process an incoming RC packet
  1724. * for the given QP.
  1725. * Called at interrupt level.
  1726. */
  1727. void qib_rc_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
  1728. int has_grh, void *data, u32 tlen, struct qib_qp *qp)
  1729. {
  1730. struct qib_ibport *ibp = &rcd->ppd->ibport_data;
  1731. struct qib_other_headers *ohdr;
  1732. u32 opcode;
  1733. u32 hdrsize;
  1734. u32 psn;
  1735. u32 pad;
  1736. struct ib_wc wc;
  1737. u32 pmtu = qp->pmtu;
  1738. int diff;
  1739. struct ib_reth *reth;
  1740. unsigned long flags;
  1741. int ret;
  1742. /* Check for GRH */
  1743. if (!has_grh) {
  1744. ohdr = &hdr->u.oth;
  1745. hdrsize = 8 + 12; /* LRH + BTH */
  1746. } else {
  1747. ohdr = &hdr->u.l.oth;
  1748. hdrsize = 8 + 40 + 12; /* LRH + GRH + BTH */
  1749. }
  1750. opcode = be32_to_cpu(ohdr->bth[0]);
  1751. spin_lock_irqsave(&qp->s_lock, flags);
  1752. if (qib_ruc_check_hdr(ibp, hdr, has_grh, qp, opcode))
  1753. goto sunlock;
  1754. spin_unlock_irqrestore(&qp->s_lock, flags);
  1755. psn = be32_to_cpu(ohdr->bth[2]);
  1756. opcode >>= 24;
  1757. /*
  1758. * Process responses (ACKs) before anything else. Note that the
  1759. * packet sequence number will be for something in the send work
  1760. * queue rather than the expected receive packet sequence number.
  1761. * In other words, this QP is the requester.
  1762. */
  1763. if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
  1764. opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
  1765. qib_rc_rcv_resp(ibp, ohdr, data, tlen, qp, opcode, psn,
  1766. hdrsize, pmtu, rcd);
  1767. return;
  1768. }
  1769. /* Compute 24 bits worth of difference. */
  1770. diff = qib_cmp24(psn, qp->r_psn);
  1771. if (unlikely(diff)) {
  1772. if (qib_rc_rcv_error(ohdr, data, qp, opcode, psn, diff, rcd))
  1773. return;
  1774. goto send_ack;
  1775. }
  1776. /* Check for opcode sequence errors. */
  1777. switch (qp->r_state) {
  1778. case OP(SEND_FIRST):
  1779. case OP(SEND_MIDDLE):
  1780. if (opcode == OP(SEND_MIDDLE) ||
  1781. opcode == OP(SEND_LAST) ||
  1782. opcode == OP(SEND_LAST_WITH_IMMEDIATE))
  1783. break;
  1784. goto nack_inv;
  1785. case OP(RDMA_WRITE_FIRST):
  1786. case OP(RDMA_WRITE_MIDDLE):
  1787. if (opcode == OP(RDMA_WRITE_MIDDLE) ||
  1788. opcode == OP(RDMA_WRITE_LAST) ||
  1789. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  1790. break;
  1791. goto nack_inv;
  1792. default:
  1793. if (opcode == OP(SEND_MIDDLE) ||
  1794. opcode == OP(SEND_LAST) ||
  1795. opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
  1796. opcode == OP(RDMA_WRITE_MIDDLE) ||
  1797. opcode == OP(RDMA_WRITE_LAST) ||
  1798. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  1799. goto nack_inv;
  1800. /*
  1801. * Note that it is up to the requester to not send a new
  1802. * RDMA read or atomic operation before receiving an ACK
  1803. * for the previous operation.
  1804. */
  1805. break;
  1806. }
  1807. if (qp->state == IB_QPS_RTR && !(qp->r_flags & QIB_R_COMM_EST)) {
  1808. qp->r_flags |= QIB_R_COMM_EST;
  1809. if (qp->ibqp.event_handler) {
  1810. struct ib_event ev;
  1811. ev.device = qp->ibqp.device;
  1812. ev.element.qp = &qp->ibqp;
  1813. ev.event = IB_EVENT_COMM_EST;
  1814. qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
  1815. }
  1816. }
  1817. /* OK, process the packet. */
  1818. switch (opcode) {
  1819. case OP(SEND_FIRST):
  1820. ret = qib_get_rwqe(qp, 0);
  1821. if (ret < 0)
  1822. goto nack_op_err;
  1823. if (!ret)
  1824. goto rnr_nak;
  1825. qp->r_rcv_len = 0;
  1826. /* FALLTHROUGH */
  1827. case OP(SEND_MIDDLE):
  1828. case OP(RDMA_WRITE_MIDDLE):
  1829. send_middle:
  1830. /* Check for invalid length PMTU or posted rwqe len. */
  1831. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  1832. goto nack_inv;
  1833. qp->r_rcv_len += pmtu;
  1834. if (unlikely(qp->r_rcv_len > qp->r_len))
  1835. goto nack_inv;
  1836. qib_copy_sge(&qp->r_sge, data, pmtu, 1);
  1837. break;
  1838. case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
  1839. /* consume RWQE */
  1840. ret = qib_get_rwqe(qp, 1);
  1841. if (ret < 0)
  1842. goto nack_op_err;
  1843. if (!ret)
  1844. goto rnr_nak;
  1845. goto send_last_imm;
  1846. case OP(SEND_ONLY):
  1847. case OP(SEND_ONLY_WITH_IMMEDIATE):
  1848. ret = qib_get_rwqe(qp, 0);
  1849. if (ret < 0)
  1850. goto nack_op_err;
  1851. if (!ret)
  1852. goto rnr_nak;
  1853. qp->r_rcv_len = 0;
  1854. if (opcode == OP(SEND_ONLY))
  1855. goto no_immediate_data;
  1856. /* FALLTHROUGH for SEND_ONLY_WITH_IMMEDIATE */
  1857. case OP(SEND_LAST_WITH_IMMEDIATE):
  1858. send_last_imm:
  1859. wc.ex.imm_data = ohdr->u.imm_data;
  1860. hdrsize += 4;
  1861. wc.wc_flags = IB_WC_WITH_IMM;
  1862. goto send_last;
  1863. case OP(SEND_LAST):
  1864. case OP(RDMA_WRITE_LAST):
  1865. no_immediate_data:
  1866. wc.wc_flags = 0;
  1867. wc.ex.imm_data = 0;
  1868. send_last:
  1869. /* Get the number of bytes the message was padded by. */
  1870. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1871. /* Check for invalid length. */
  1872. /* XXX LAST len should be >= 1 */
  1873. if (unlikely(tlen < (hdrsize + pad + 4)))
  1874. goto nack_inv;
  1875. /* Don't count the CRC. */
  1876. tlen -= (hdrsize + pad + 4);
  1877. wc.byte_len = tlen + qp->r_rcv_len;
  1878. if (unlikely(wc.byte_len > qp->r_len))
  1879. goto nack_inv;
  1880. qib_copy_sge(&qp->r_sge, data, tlen, 1);
  1881. while (qp->r_sge.num_sge) {
  1882. atomic_dec(&qp->r_sge.sge.mr->refcount);
  1883. if (--qp->r_sge.num_sge)
  1884. qp->r_sge.sge = *qp->r_sge.sg_list++;
  1885. }
  1886. qp->r_msn++;
  1887. if (!test_and_clear_bit(QIB_R_WRID_VALID, &qp->r_aflags))
  1888. break;
  1889. wc.wr_id = qp->r_wr_id;
  1890. wc.status = IB_WC_SUCCESS;
  1891. if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) ||
  1892. opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
  1893. wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
  1894. else
  1895. wc.opcode = IB_WC_RECV;
  1896. wc.qp = &qp->ibqp;
  1897. wc.src_qp = qp->remote_qpn;
  1898. wc.slid = qp->remote_ah_attr.dlid;
  1899. wc.sl = qp->remote_ah_attr.sl;
  1900. /* zero fields that are N/A */
  1901. wc.vendor_err = 0;
  1902. wc.pkey_index = 0;
  1903. wc.dlid_path_bits = 0;
  1904. wc.port_num = 0;
  1905. wc.csum_ok = 0;
  1906. /* Signal completion event if the solicited bit is set. */
  1907. qib_cq_enter(to_icq(qp->ibqp.recv_cq), &wc,
  1908. (ohdr->bth[0] &
  1909. cpu_to_be32(IB_BTH_SOLICITED)) != 0);
  1910. break;
  1911. case OP(RDMA_WRITE_FIRST):
  1912. case OP(RDMA_WRITE_ONLY):
  1913. case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
  1914. if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_WRITE)))
  1915. goto nack_inv;
  1916. /* consume RWQE */
  1917. reth = &ohdr->u.rc.reth;
  1918. hdrsize += sizeof(*reth);
  1919. qp->r_len = be32_to_cpu(reth->length);
  1920. qp->r_rcv_len = 0;
  1921. qp->r_sge.sg_list = NULL;
  1922. if (qp->r_len != 0) {
  1923. u32 rkey = be32_to_cpu(reth->rkey);
  1924. u64 vaddr = be64_to_cpu(reth->vaddr);
  1925. int ok;
  1926. /* Check rkey & NAK */
  1927. ok = qib_rkey_ok(qp, &qp->r_sge.sge, qp->r_len, vaddr,
  1928. rkey, IB_ACCESS_REMOTE_WRITE);
  1929. if (unlikely(!ok))
  1930. goto nack_acc;
  1931. qp->r_sge.num_sge = 1;
  1932. } else {
  1933. qp->r_sge.num_sge = 0;
  1934. qp->r_sge.sge.mr = NULL;
  1935. qp->r_sge.sge.vaddr = NULL;
  1936. qp->r_sge.sge.length = 0;
  1937. qp->r_sge.sge.sge_length = 0;
  1938. }
  1939. if (opcode == OP(RDMA_WRITE_FIRST))
  1940. goto send_middle;
  1941. else if (opcode == OP(RDMA_WRITE_ONLY))
  1942. goto no_immediate_data;
  1943. ret = qib_get_rwqe(qp, 1);
  1944. if (ret < 0)
  1945. goto nack_op_err;
  1946. if (!ret)
  1947. goto rnr_nak;
  1948. wc.ex.imm_data = ohdr->u.rc.imm_data;
  1949. hdrsize += 4;
  1950. wc.wc_flags = IB_WC_WITH_IMM;
  1951. goto send_last;
  1952. case OP(RDMA_READ_REQUEST): {
  1953. struct qib_ack_entry *e;
  1954. u32 len;
  1955. u8 next;
  1956. if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_READ)))
  1957. goto nack_inv;
  1958. next = qp->r_head_ack_queue + 1;
  1959. /* s_ack_queue is size QIB_MAX_RDMA_ATOMIC+1 so use > not >= */
  1960. if (next > QIB_MAX_RDMA_ATOMIC)
  1961. next = 0;
  1962. spin_lock_irqsave(&qp->s_lock, flags);
  1963. if (unlikely(next == qp->s_tail_ack_queue)) {
  1964. if (!qp->s_ack_queue[next].sent)
  1965. goto nack_inv_unlck;
  1966. qib_update_ack_queue(qp, next);
  1967. }
  1968. e = &qp->s_ack_queue[qp->r_head_ack_queue];
  1969. if (e->opcode == OP(RDMA_READ_REQUEST) && e->rdma_sge.mr) {
  1970. atomic_dec(&e->rdma_sge.mr->refcount);
  1971. e->rdma_sge.mr = NULL;
  1972. }
  1973. reth = &ohdr->u.rc.reth;
  1974. len = be32_to_cpu(reth->length);
  1975. if (len) {
  1976. u32 rkey = be32_to_cpu(reth->rkey);
  1977. u64 vaddr = be64_to_cpu(reth->vaddr);
  1978. int ok;
  1979. /* Check rkey & NAK */
  1980. ok = qib_rkey_ok(qp, &e->rdma_sge, len, vaddr,
  1981. rkey, IB_ACCESS_REMOTE_READ);
  1982. if (unlikely(!ok))
  1983. goto nack_acc_unlck;
  1984. /*
  1985. * Update the next expected PSN. We add 1 later
  1986. * below, so only add the remainder here.
  1987. */
  1988. if (len > pmtu)
  1989. qp->r_psn += (len - 1) / pmtu;
  1990. } else {
  1991. e->rdma_sge.mr = NULL;
  1992. e->rdma_sge.vaddr = NULL;
  1993. e->rdma_sge.length = 0;
  1994. e->rdma_sge.sge_length = 0;
  1995. }
  1996. e->opcode = opcode;
  1997. e->sent = 0;
  1998. e->psn = psn;
  1999. e->lpsn = qp->r_psn;
  2000. /*
  2001. * We need to increment the MSN here instead of when we
  2002. * finish sending the result since a duplicate request would
  2003. * increment it more than once.
  2004. */
  2005. qp->r_msn++;
  2006. qp->r_psn++;
  2007. qp->r_state = opcode;
  2008. qp->r_nak_state = 0;
  2009. qp->r_head_ack_queue = next;
  2010. /* Schedule the send tasklet. */
  2011. qp->s_flags |= QIB_S_RESP_PENDING;
  2012. qib_schedule_send(qp);
  2013. goto sunlock;
  2014. }
  2015. case OP(COMPARE_SWAP):
  2016. case OP(FETCH_ADD): {
  2017. struct ib_atomic_eth *ateth;
  2018. struct qib_ack_entry *e;
  2019. u64 vaddr;
  2020. atomic64_t *maddr;
  2021. u64 sdata;
  2022. u32 rkey;
  2023. u8 next;
  2024. if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)))
  2025. goto nack_inv;
  2026. next = qp->r_head_ack_queue + 1;
  2027. if (next > QIB_MAX_RDMA_ATOMIC)
  2028. next = 0;
  2029. spin_lock_irqsave(&qp->s_lock, flags);
  2030. if (unlikely(next == qp->s_tail_ack_queue)) {
  2031. if (!qp->s_ack_queue[next].sent)
  2032. goto nack_inv_unlck;
  2033. qib_update_ack_queue(qp, next);
  2034. }
  2035. e = &qp->s_ack_queue[qp->r_head_ack_queue];
  2036. if (e->opcode == OP(RDMA_READ_REQUEST) && e->rdma_sge.mr) {
  2037. atomic_dec(&e->rdma_sge.mr->refcount);
  2038. e->rdma_sge.mr = NULL;
  2039. }
  2040. ateth = &ohdr->u.atomic_eth;
  2041. vaddr = ((u64) be32_to_cpu(ateth->vaddr[0]) << 32) |
  2042. be32_to_cpu(ateth->vaddr[1]);
  2043. if (unlikely(vaddr & (sizeof(u64) - 1)))
  2044. goto nack_inv_unlck;
  2045. rkey = be32_to_cpu(ateth->rkey);
  2046. /* Check rkey & NAK */
  2047. if (unlikely(!qib_rkey_ok(qp, &qp->r_sge.sge, sizeof(u64),
  2048. vaddr, rkey,
  2049. IB_ACCESS_REMOTE_ATOMIC)))
  2050. goto nack_acc_unlck;
  2051. /* Perform atomic OP and save result. */
  2052. maddr = (atomic64_t *) qp->r_sge.sge.vaddr;
  2053. sdata = be64_to_cpu(ateth->swap_data);
  2054. e->atomic_data = (opcode == OP(FETCH_ADD)) ?
  2055. (u64) atomic64_add_return(sdata, maddr) - sdata :
  2056. (u64) cmpxchg((u64 *) qp->r_sge.sge.vaddr,
  2057. be64_to_cpu(ateth->compare_data),
  2058. sdata);
  2059. atomic_dec(&qp->r_sge.sge.mr->refcount);
  2060. qp->r_sge.num_sge = 0;
  2061. e->opcode = opcode;
  2062. e->sent = 0;
  2063. e->psn = psn;
  2064. e->lpsn = psn;
  2065. qp->r_msn++;
  2066. qp->r_psn++;
  2067. qp->r_state = opcode;
  2068. qp->r_nak_state = 0;
  2069. qp->r_head_ack_queue = next;
  2070. /* Schedule the send tasklet. */
  2071. qp->s_flags |= QIB_S_RESP_PENDING;
  2072. qib_schedule_send(qp);
  2073. goto sunlock;
  2074. }
  2075. default:
  2076. /* NAK unknown opcodes. */
  2077. goto nack_inv;
  2078. }
  2079. qp->r_psn++;
  2080. qp->r_state = opcode;
  2081. qp->r_ack_psn = psn;
  2082. qp->r_nak_state = 0;
  2083. /* Send an ACK if requested or required. */
  2084. if (psn & (1 << 31))
  2085. goto send_ack;
  2086. return;
  2087. rnr_nak:
  2088. qp->r_nak_state = IB_RNR_NAK | qp->r_min_rnr_timer;
  2089. qp->r_ack_psn = qp->r_psn;
  2090. /* Queue RNR NAK for later */
  2091. if (list_empty(&qp->rspwait)) {
  2092. qp->r_flags |= QIB_R_RSP_NAK;
  2093. atomic_inc(&qp->refcount);
  2094. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  2095. }
  2096. return;
  2097. nack_op_err:
  2098. qib_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
  2099. qp->r_nak_state = IB_NAK_REMOTE_OPERATIONAL_ERROR;
  2100. qp->r_ack_psn = qp->r_psn;
  2101. /* Queue NAK for later */
  2102. if (list_empty(&qp->rspwait)) {
  2103. qp->r_flags |= QIB_R_RSP_NAK;
  2104. atomic_inc(&qp->refcount);
  2105. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  2106. }
  2107. return;
  2108. nack_inv_unlck:
  2109. spin_unlock_irqrestore(&qp->s_lock, flags);
  2110. nack_inv:
  2111. qib_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
  2112. qp->r_nak_state = IB_NAK_INVALID_REQUEST;
  2113. qp->r_ack_psn = qp->r_psn;
  2114. /* Queue NAK for later */
  2115. if (list_empty(&qp->rspwait)) {
  2116. qp->r_flags |= QIB_R_RSP_NAK;
  2117. atomic_inc(&qp->refcount);
  2118. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  2119. }
  2120. return;
  2121. nack_acc_unlck:
  2122. spin_unlock_irqrestore(&qp->s_lock, flags);
  2123. nack_acc:
  2124. qib_rc_error(qp, IB_WC_LOC_PROT_ERR);
  2125. qp->r_nak_state = IB_NAK_REMOTE_ACCESS_ERROR;
  2126. qp->r_ack_psn = qp->r_psn;
  2127. send_ack:
  2128. qib_send_rc_ack(qp);
  2129. return;
  2130. sunlock:
  2131. spin_unlock_irqrestore(&qp->s_lock, flags);
  2132. }