i387.h 16 KB

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  1. /*
  2. * Copyright (C) 1994 Linus Torvalds
  3. *
  4. * Pentium III FXSR, SSE support
  5. * General FPU state handling cleanups
  6. * Gareth Hughes <gareth@valinux.com>, May 2000
  7. * x86-64 work by Andi Kleen 2002
  8. */
  9. #ifndef _ASM_X86_I387_H
  10. #define _ASM_X86_I387_H
  11. #ifndef __ASSEMBLY__
  12. #include <linux/sched.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/regset.h>
  15. #include <linux/hardirq.h>
  16. #include <linux/slab.h>
  17. #include <asm/asm.h>
  18. #include <asm/cpufeature.h>
  19. #include <asm/processor.h>
  20. #include <asm/sigcontext.h>
  21. #include <asm/user.h>
  22. #include <asm/uaccess.h>
  23. #include <asm/xsave.h>
  24. extern unsigned int sig_xstate_size;
  25. extern void fpu_init(void);
  26. extern void mxcsr_feature_mask_init(void);
  27. extern int init_fpu(struct task_struct *child);
  28. extern void math_state_restore(void);
  29. extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
  30. DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
  31. extern user_regset_active_fn fpregs_active, xfpregs_active;
  32. extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
  33. xstateregs_get;
  34. extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
  35. xstateregs_set;
  36. /*
  37. * xstateregs_active == fpregs_active. Please refer to the comment
  38. * at the definition of fpregs_active.
  39. */
  40. #define xstateregs_active fpregs_active
  41. extern struct _fpx_sw_bytes fx_sw_reserved;
  42. #ifdef CONFIG_IA32_EMULATION
  43. extern unsigned int sig_xstate_ia32_size;
  44. extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
  45. struct _fpstate_ia32;
  46. struct _xstate_ia32;
  47. extern int save_i387_xstate_ia32(void __user *buf);
  48. extern int restore_i387_xstate_ia32(void __user *buf);
  49. #endif
  50. #ifdef CONFIG_MATH_EMULATION
  51. extern void finit_soft_fpu(struct i387_soft_struct *soft);
  52. #else
  53. static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
  54. #endif
  55. #define X87_FSW_ES (1 << 7) /* Exception Summary */
  56. static __always_inline __pure bool use_xsaveopt(void)
  57. {
  58. return static_cpu_has(X86_FEATURE_XSAVEOPT);
  59. }
  60. static __always_inline __pure bool use_xsave(void)
  61. {
  62. return static_cpu_has(X86_FEATURE_XSAVE);
  63. }
  64. static __always_inline __pure bool use_fxsr(void)
  65. {
  66. return static_cpu_has(X86_FEATURE_FXSR);
  67. }
  68. extern void __sanitize_i387_state(struct task_struct *);
  69. static inline void sanitize_i387_state(struct task_struct *tsk)
  70. {
  71. if (!use_xsaveopt())
  72. return;
  73. __sanitize_i387_state(tsk);
  74. }
  75. #ifdef CONFIG_X86_64
  76. static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  77. {
  78. int err;
  79. /* See comment in fxsave() below. */
  80. #ifdef CONFIG_AS_FXSAVEQ
  81. asm volatile("1: fxrstorq %[fx]\n\t"
  82. "2:\n"
  83. ".section .fixup,\"ax\"\n"
  84. "3: movl $-1,%[err]\n"
  85. " jmp 2b\n"
  86. ".previous\n"
  87. _ASM_EXTABLE(1b, 3b)
  88. : [err] "=r" (err)
  89. : [fx] "m" (*fx), "0" (0));
  90. #else
  91. asm volatile("1: rex64/fxrstor (%[fx])\n\t"
  92. "2:\n"
  93. ".section .fixup,\"ax\"\n"
  94. "3: movl $-1,%[err]\n"
  95. " jmp 2b\n"
  96. ".previous\n"
  97. _ASM_EXTABLE(1b, 3b)
  98. : [err] "=r" (err)
  99. : [fx] "R" (fx), "m" (*fx), "0" (0));
  100. #endif
  101. return err;
  102. }
  103. static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
  104. {
  105. int err;
  106. /*
  107. * Clear the bytes not touched by the fxsave and reserved
  108. * for the SW usage.
  109. */
  110. err = __clear_user(&fx->sw_reserved,
  111. sizeof(struct _fpx_sw_bytes));
  112. if (unlikely(err))
  113. return -EFAULT;
  114. /* See comment in fxsave() below. */
  115. #ifdef CONFIG_AS_FXSAVEQ
  116. asm volatile("1: fxsaveq %[fx]\n\t"
  117. "2:\n"
  118. ".section .fixup,\"ax\"\n"
  119. "3: movl $-1,%[err]\n"
  120. " jmp 2b\n"
  121. ".previous\n"
  122. _ASM_EXTABLE(1b, 3b)
  123. : [err] "=r" (err), [fx] "=m" (*fx)
  124. : "0" (0));
  125. #else
  126. asm volatile("1: rex64/fxsave (%[fx])\n\t"
  127. "2:\n"
  128. ".section .fixup,\"ax\"\n"
  129. "3: movl $-1,%[err]\n"
  130. " jmp 2b\n"
  131. ".previous\n"
  132. _ASM_EXTABLE(1b, 3b)
  133. : [err] "=r" (err), "=m" (*fx)
  134. : [fx] "R" (fx), "0" (0));
  135. #endif
  136. if (unlikely(err) &&
  137. __clear_user(fx, sizeof(struct i387_fxsave_struct)))
  138. err = -EFAULT;
  139. /* No need to clear here because the caller clears USED_MATH */
  140. return err;
  141. }
  142. static inline void fpu_fxsave(struct fpu *fpu)
  143. {
  144. /* Using "rex64; fxsave %0" is broken because, if the memory operand
  145. uses any extended registers for addressing, a second REX prefix
  146. will be generated (to the assembler, rex64 followed by semicolon
  147. is a separate instruction), and hence the 64-bitness is lost. */
  148. #ifdef CONFIG_AS_FXSAVEQ
  149. /* Using "fxsaveq %0" would be the ideal choice, but is only supported
  150. starting with gas 2.16. */
  151. __asm__ __volatile__("fxsaveq %0"
  152. : "=m" (fpu->state->fxsave));
  153. #else
  154. /* Using, as a workaround, the properly prefixed form below isn't
  155. accepted by any binutils version so far released, complaining that
  156. the same type of prefix is used twice if an extended register is
  157. needed for addressing (fix submitted to mainline 2005-11-21).
  158. asm volatile("rex64/fxsave %0"
  159. : "=m" (fpu->state->fxsave));
  160. This, however, we can work around by forcing the compiler to select
  161. an addressing mode that doesn't require extended registers. */
  162. asm volatile("rex64/fxsave (%[fx])"
  163. : "=m" (fpu->state->fxsave)
  164. : [fx] "R" (&fpu->state->fxsave));
  165. #endif
  166. }
  167. #else /* CONFIG_X86_32 */
  168. /* perform fxrstor iff the processor has extended states, otherwise frstor */
  169. static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  170. {
  171. /*
  172. * The "nop" is needed to make the instructions the same
  173. * length.
  174. */
  175. alternative_input(
  176. "nop ; frstor %1",
  177. "fxrstor %1",
  178. X86_FEATURE_FXSR,
  179. "m" (*fx));
  180. return 0;
  181. }
  182. static inline void fpu_fxsave(struct fpu *fpu)
  183. {
  184. asm volatile("fxsave %[fx]"
  185. : [fx] "=m" (fpu->state->fxsave));
  186. }
  187. #endif /* CONFIG_X86_64 */
  188. /*
  189. * These must be called with preempt disabled. Returns
  190. * 'true' if the FPU state is still intact.
  191. */
  192. static inline int fpu_save_init(struct fpu *fpu)
  193. {
  194. if (use_xsave()) {
  195. fpu_xsave(fpu);
  196. /*
  197. * xsave header may indicate the init state of the FP.
  198. */
  199. if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
  200. return 1;
  201. } else if (use_fxsr()) {
  202. fpu_fxsave(fpu);
  203. } else {
  204. asm volatile("fnsave %[fx]; fwait"
  205. : [fx] "=m" (fpu->state->fsave));
  206. return 0;
  207. }
  208. /*
  209. * If exceptions are pending, we need to clear them so
  210. * that we don't randomly get exceptions later.
  211. *
  212. * FIXME! Is this perhaps only true for the old-style
  213. * irq13 case? Maybe we could leave the x87 state
  214. * intact otherwise?
  215. */
  216. if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
  217. asm volatile("fnclex");
  218. return 0;
  219. }
  220. return 1;
  221. }
  222. static inline int __save_init_fpu(struct task_struct *tsk)
  223. {
  224. return fpu_save_init(&tsk->thread.fpu);
  225. }
  226. static inline int fpu_fxrstor_checking(struct fpu *fpu)
  227. {
  228. return fxrstor_checking(&fpu->state->fxsave);
  229. }
  230. static inline int fpu_restore_checking(struct fpu *fpu)
  231. {
  232. if (use_xsave())
  233. return fpu_xrstor_checking(fpu);
  234. else
  235. return fpu_fxrstor_checking(fpu);
  236. }
  237. static inline int restore_fpu_checking(struct task_struct *tsk)
  238. {
  239. /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
  240. is pending. Clear the x87 state here by setting it to fixed
  241. values. "m" is a random variable that should be in L1 */
  242. alternative_input(
  243. ASM_NOP8 ASM_NOP2,
  244. "emms\n\t" /* clear stack tags */
  245. "fildl %P[addr]", /* set F?P to defined value */
  246. X86_FEATURE_FXSAVE_LEAK,
  247. [addr] "m" (tsk->thread.fpu.has_fpu));
  248. return fpu_restore_checking(&tsk->thread.fpu);
  249. }
  250. /*
  251. * Software FPU state helpers. Careful: these need to
  252. * be preemption protection *and* they need to be
  253. * properly paired with the CR0.TS changes!
  254. */
  255. static inline int __thread_has_fpu(struct task_struct *tsk)
  256. {
  257. return tsk->thread.fpu.has_fpu;
  258. }
  259. /* Must be paired with an 'stts' after! */
  260. static inline void __thread_clear_has_fpu(struct task_struct *tsk)
  261. {
  262. tsk->thread.fpu.has_fpu = 0;
  263. percpu_write(fpu_owner_task, NULL);
  264. }
  265. /* Must be paired with a 'clts' before! */
  266. static inline void __thread_set_has_fpu(struct task_struct *tsk)
  267. {
  268. tsk->thread.fpu.has_fpu = 1;
  269. percpu_write(fpu_owner_task, tsk);
  270. }
  271. /*
  272. * Encapsulate the CR0.TS handling together with the
  273. * software flag.
  274. *
  275. * These generally need preemption protection to work,
  276. * do try to avoid using these on their own.
  277. */
  278. static inline void __thread_fpu_end(struct task_struct *tsk)
  279. {
  280. __thread_clear_has_fpu(tsk);
  281. stts();
  282. }
  283. static inline void __thread_fpu_begin(struct task_struct *tsk)
  284. {
  285. clts();
  286. __thread_set_has_fpu(tsk);
  287. }
  288. /*
  289. * FPU state switching for scheduling.
  290. *
  291. * This is a two-stage process:
  292. *
  293. * - switch_fpu_prepare() saves the old state and
  294. * sets the new state of the CR0.TS bit. This is
  295. * done within the context of the old process.
  296. *
  297. * - switch_fpu_finish() restores the new state as
  298. * necessary.
  299. */
  300. typedef struct { int preload; } fpu_switch_t;
  301. /*
  302. * FIXME! We could do a totally lazy restore, but we need to
  303. * add a per-cpu "this was the task that last touched the FPU
  304. * on this CPU" variable, and the task needs to have a "I last
  305. * touched the FPU on this CPU" and check them.
  306. *
  307. * We don't do that yet, so "fpu_lazy_restore()" always returns
  308. * false, but some day..
  309. */
  310. static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
  311. {
  312. return new == percpu_read_stable(fpu_owner_task) &&
  313. cpu == new->thread.fpu.last_cpu;
  314. }
  315. static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
  316. {
  317. fpu_switch_t fpu;
  318. fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
  319. if (__thread_has_fpu(old)) {
  320. if (!__save_init_fpu(old))
  321. cpu = ~0;
  322. old->thread.fpu.last_cpu = cpu;
  323. old->thread.fpu.has_fpu = 0; /* But leave fpu_owner_task! */
  324. /* Don't change CR0.TS if we just switch! */
  325. if (fpu.preload) {
  326. new->fpu_counter++;
  327. __thread_set_has_fpu(new);
  328. prefetch(new->thread.fpu.state);
  329. } else
  330. stts();
  331. } else {
  332. old->fpu_counter = 0;
  333. old->thread.fpu.last_cpu = ~0;
  334. if (fpu.preload) {
  335. new->fpu_counter++;
  336. if (fpu_lazy_restore(new, cpu))
  337. fpu.preload = 0;
  338. else
  339. prefetch(new->thread.fpu.state);
  340. __thread_fpu_begin(new);
  341. }
  342. }
  343. return fpu;
  344. }
  345. /*
  346. * By the time this gets called, we've already cleared CR0.TS and
  347. * given the process the FPU if we are going to preload the FPU
  348. * state - all we need to do is to conditionally restore the register
  349. * state itself.
  350. */
  351. static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
  352. {
  353. if (fpu.preload) {
  354. if (unlikely(restore_fpu_checking(new)))
  355. __thread_fpu_end(new);
  356. }
  357. }
  358. /*
  359. * Signal frame handlers...
  360. */
  361. extern int save_i387_xstate(void __user *buf);
  362. extern int restore_i387_xstate(void __user *buf);
  363. static inline void __clear_fpu(struct task_struct *tsk)
  364. {
  365. if (__thread_has_fpu(tsk)) {
  366. /* Ignore delayed exceptions from user space */
  367. asm volatile("1: fwait\n"
  368. "2:\n"
  369. _ASM_EXTABLE(1b, 2b));
  370. __thread_fpu_end(tsk);
  371. }
  372. }
  373. /*
  374. * Were we in an interrupt that interrupted kernel mode?
  375. *
  376. * We can do a kernel_fpu_begin/end() pair *ONLY* if that
  377. * pair does nothing at all: the thread must not have fpu (so
  378. * that we don't try to save the FPU state), and TS must
  379. * be set (so that the clts/stts pair does nothing that is
  380. * visible in the interrupted kernel thread).
  381. */
  382. static inline bool interrupted_kernel_fpu_idle(void)
  383. {
  384. return !__thread_has_fpu(current) &&
  385. (read_cr0() & X86_CR0_TS);
  386. }
  387. /*
  388. * Were we in user mode (or vm86 mode) when we were
  389. * interrupted?
  390. *
  391. * Doing kernel_fpu_begin/end() is ok if we are running
  392. * in an interrupt context from user mode - we'll just
  393. * save the FPU state as required.
  394. */
  395. static inline bool interrupted_user_mode(void)
  396. {
  397. struct pt_regs *regs = get_irq_regs();
  398. return regs && user_mode_vm(regs);
  399. }
  400. /*
  401. * Can we use the FPU in kernel mode with the
  402. * whole "kernel_fpu_begin/end()" sequence?
  403. *
  404. * It's always ok in process context (ie "not interrupt")
  405. * but it is sometimes ok even from an irq.
  406. */
  407. static inline bool irq_fpu_usable(void)
  408. {
  409. return !in_interrupt() ||
  410. interrupted_user_mode() ||
  411. interrupted_kernel_fpu_idle();
  412. }
  413. static inline void kernel_fpu_begin(void)
  414. {
  415. struct task_struct *me = current;
  416. WARN_ON_ONCE(!irq_fpu_usable());
  417. preempt_disable();
  418. if (__thread_has_fpu(me)) {
  419. __save_init_fpu(me);
  420. __thread_clear_has_fpu(me);
  421. /* We do 'stts()' in kernel_fpu_end() */
  422. } else {
  423. percpu_write(fpu_owner_task, NULL);
  424. clts();
  425. }
  426. }
  427. static inline void kernel_fpu_end(void)
  428. {
  429. stts();
  430. preempt_enable();
  431. }
  432. /*
  433. * Some instructions like VIA's padlock instructions generate a spurious
  434. * DNA fault but don't modify SSE registers. And these instructions
  435. * get used from interrupt context as well. To prevent these kernel instructions
  436. * in interrupt context interacting wrongly with other user/kernel fpu usage, we
  437. * should use them only in the context of irq_ts_save/restore()
  438. */
  439. static inline int irq_ts_save(void)
  440. {
  441. /*
  442. * If in process context and not atomic, we can take a spurious DNA fault.
  443. * Otherwise, doing clts() in process context requires disabling preemption
  444. * or some heavy lifting like kernel_fpu_begin()
  445. */
  446. if (!in_atomic())
  447. return 0;
  448. if (read_cr0() & X86_CR0_TS) {
  449. clts();
  450. return 1;
  451. }
  452. return 0;
  453. }
  454. static inline void irq_ts_restore(int TS_state)
  455. {
  456. if (TS_state)
  457. stts();
  458. }
  459. /*
  460. * The question "does this thread have fpu access?"
  461. * is slightly racy, since preemption could come in
  462. * and revoke it immediately after the test.
  463. *
  464. * However, even in that very unlikely scenario,
  465. * we can just assume we have FPU access - typically
  466. * to save the FP state - we'll just take a #NM
  467. * fault and get the FPU access back.
  468. *
  469. * The actual user_fpu_begin/end() functions
  470. * need to be preemption-safe, though.
  471. *
  472. * NOTE! user_fpu_end() must be used only after you
  473. * have saved the FP state, and user_fpu_begin() must
  474. * be used only immediately before restoring it.
  475. * These functions do not do any save/restore on
  476. * their own.
  477. */
  478. static inline int user_has_fpu(void)
  479. {
  480. return __thread_has_fpu(current);
  481. }
  482. static inline void user_fpu_end(void)
  483. {
  484. preempt_disable();
  485. __thread_fpu_end(current);
  486. preempt_enable();
  487. }
  488. static inline void user_fpu_begin(void)
  489. {
  490. preempt_disable();
  491. if (!user_has_fpu())
  492. __thread_fpu_begin(current);
  493. preempt_enable();
  494. }
  495. /*
  496. * These disable preemption on their own and are safe
  497. */
  498. static inline void save_init_fpu(struct task_struct *tsk)
  499. {
  500. WARN_ON_ONCE(!__thread_has_fpu(tsk));
  501. preempt_disable();
  502. __save_init_fpu(tsk);
  503. __thread_fpu_end(tsk);
  504. preempt_enable();
  505. }
  506. static inline void unlazy_fpu(struct task_struct *tsk)
  507. {
  508. preempt_disable();
  509. if (__thread_has_fpu(tsk)) {
  510. __save_init_fpu(tsk);
  511. __thread_fpu_end(tsk);
  512. } else
  513. tsk->fpu_counter = 0;
  514. preempt_enable();
  515. }
  516. static inline void clear_fpu(struct task_struct *tsk)
  517. {
  518. preempt_disable();
  519. __clear_fpu(tsk);
  520. preempt_enable();
  521. }
  522. /*
  523. * i387 state interaction
  524. */
  525. static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
  526. {
  527. if (cpu_has_fxsr) {
  528. return tsk->thread.fpu.state->fxsave.cwd;
  529. } else {
  530. return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
  531. }
  532. }
  533. static inline unsigned short get_fpu_swd(struct task_struct *tsk)
  534. {
  535. if (cpu_has_fxsr) {
  536. return tsk->thread.fpu.state->fxsave.swd;
  537. } else {
  538. return (unsigned short)tsk->thread.fpu.state->fsave.swd;
  539. }
  540. }
  541. static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
  542. {
  543. if (cpu_has_xmm) {
  544. return tsk->thread.fpu.state->fxsave.mxcsr;
  545. } else {
  546. return MXCSR_DEFAULT;
  547. }
  548. }
  549. static bool fpu_allocated(struct fpu *fpu)
  550. {
  551. return fpu->state != NULL;
  552. }
  553. static inline int fpu_alloc(struct fpu *fpu)
  554. {
  555. if (fpu_allocated(fpu))
  556. return 0;
  557. fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
  558. if (!fpu->state)
  559. return -ENOMEM;
  560. WARN_ON((unsigned long)fpu->state & 15);
  561. return 0;
  562. }
  563. static inline void fpu_free(struct fpu *fpu)
  564. {
  565. if (fpu->state) {
  566. kmem_cache_free(task_xstate_cachep, fpu->state);
  567. fpu->state = NULL;
  568. }
  569. }
  570. static inline void fpu_copy(struct fpu *dst, struct fpu *src)
  571. {
  572. memcpy(dst->state, src->state, xstate_size);
  573. }
  574. extern void fpu_finit(struct fpu *fpu);
  575. #endif /* __ASSEMBLY__ */
  576. #endif /* _ASM_X86_I387_H */