si.c 169 KB

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  1. /*
  2. * Copyright 2011 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <linux/firmware.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/slab.h>
  27. #include <linux/module.h>
  28. #include <drm/drmP.h>
  29. #include "radeon.h"
  30. #include "radeon_asic.h"
  31. #include <drm/radeon_drm.h>
  32. #include "sid.h"
  33. #include "atom.h"
  34. #include "si_blit_shaders.h"
  35. #define SI_PFP_UCODE_SIZE 2144
  36. #define SI_PM4_UCODE_SIZE 2144
  37. #define SI_CE_UCODE_SIZE 2144
  38. #define SI_RLC_UCODE_SIZE 2048
  39. #define SI_MC_UCODE_SIZE 7769
  40. #define OLAND_MC_UCODE_SIZE 7863
  41. MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
  42. MODULE_FIRMWARE("radeon/TAHITI_me.bin");
  43. MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
  44. MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
  45. MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
  46. MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
  47. MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
  48. MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
  49. MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
  50. MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
  51. MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
  52. MODULE_FIRMWARE("radeon/VERDE_me.bin");
  53. MODULE_FIRMWARE("radeon/VERDE_ce.bin");
  54. MODULE_FIRMWARE("radeon/VERDE_mc.bin");
  55. MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
  56. MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
  57. MODULE_FIRMWARE("radeon/OLAND_me.bin");
  58. MODULE_FIRMWARE("radeon/OLAND_ce.bin");
  59. MODULE_FIRMWARE("radeon/OLAND_mc.bin");
  60. MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
  61. MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
  62. MODULE_FIRMWARE("radeon/HAINAN_me.bin");
  63. MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
  64. MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
  65. MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
  66. extern int r600_ih_ring_alloc(struct radeon_device *rdev);
  67. extern void r600_ih_ring_fini(struct radeon_device *rdev);
  68. extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  69. extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  70. extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  71. extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
  72. extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
  73. extern bool evergreen_is_display_hung(struct radeon_device *rdev);
  74. static const u32 tahiti_golden_rlc_registers[] =
  75. {
  76. 0xc424, 0xffffffff, 0x00601005,
  77. 0xc47c, 0xffffffff, 0x10104040,
  78. 0xc488, 0xffffffff, 0x0100000a,
  79. 0xc314, 0xffffffff, 0x00000800,
  80. 0xc30c, 0xffffffff, 0x800000f4,
  81. 0xf4a8, 0xffffffff, 0x00000000
  82. };
  83. static const u32 tahiti_golden_registers[] =
  84. {
  85. 0x9a10, 0x00010000, 0x00018208,
  86. 0x9830, 0xffffffff, 0x00000000,
  87. 0x9834, 0xf00fffff, 0x00000400,
  88. 0x9838, 0x0002021c, 0x00020200,
  89. 0xc78, 0x00000080, 0x00000000,
  90. 0xd030, 0x000300c0, 0x00800040,
  91. 0xd830, 0x000300c0, 0x00800040,
  92. 0x5bb0, 0x000000f0, 0x00000070,
  93. 0x5bc0, 0x00200000, 0x50100000,
  94. 0x7030, 0x31000311, 0x00000011,
  95. 0x277c, 0x00000003, 0x000007ff,
  96. 0x240c, 0x000007ff, 0x00000000,
  97. 0x8a14, 0xf000001f, 0x00000007,
  98. 0x8b24, 0xffffffff, 0x00ffffff,
  99. 0x8b10, 0x0000ff0f, 0x00000000,
  100. 0x28a4c, 0x07ffffff, 0x4e000000,
  101. 0x28350, 0x3f3f3fff, 0x2a00126a,
  102. 0x30, 0x000000ff, 0x0040,
  103. 0x34, 0x00000040, 0x00004040,
  104. 0x9100, 0x07ffffff, 0x03000000,
  105. 0x8e88, 0x01ff1f3f, 0x00000000,
  106. 0x8e84, 0x01ff1f3f, 0x00000000,
  107. 0x9060, 0x0000007f, 0x00000020,
  108. 0x9508, 0x00010000, 0x00010000,
  109. 0xac14, 0x00000200, 0x000002fb,
  110. 0xac10, 0xffffffff, 0x0000543b,
  111. 0xac0c, 0xffffffff, 0xa9210876,
  112. 0x88d0, 0xffffffff, 0x000fff40,
  113. 0x88d4, 0x0000001f, 0x00000010,
  114. 0x1410, 0x20000000, 0x20fffed8,
  115. 0x15c0, 0x000c0fc0, 0x000c0400
  116. };
  117. static const u32 tahiti_golden_registers2[] =
  118. {
  119. 0xc64, 0x00000001, 0x00000001
  120. };
  121. static const u32 pitcairn_golden_rlc_registers[] =
  122. {
  123. 0xc424, 0xffffffff, 0x00601004,
  124. 0xc47c, 0xffffffff, 0x10102020,
  125. 0xc488, 0xffffffff, 0x01000020,
  126. 0xc314, 0xffffffff, 0x00000800,
  127. 0xc30c, 0xffffffff, 0x800000a4
  128. };
  129. static const u32 pitcairn_golden_registers[] =
  130. {
  131. 0x9a10, 0x00010000, 0x00018208,
  132. 0x9830, 0xffffffff, 0x00000000,
  133. 0x9834, 0xf00fffff, 0x00000400,
  134. 0x9838, 0x0002021c, 0x00020200,
  135. 0xc78, 0x00000080, 0x00000000,
  136. 0xd030, 0x000300c0, 0x00800040,
  137. 0xd830, 0x000300c0, 0x00800040,
  138. 0x5bb0, 0x000000f0, 0x00000070,
  139. 0x5bc0, 0x00200000, 0x50100000,
  140. 0x7030, 0x31000311, 0x00000011,
  141. 0x2ae4, 0x00073ffe, 0x000022a2,
  142. 0x240c, 0x000007ff, 0x00000000,
  143. 0x8a14, 0xf000001f, 0x00000007,
  144. 0x8b24, 0xffffffff, 0x00ffffff,
  145. 0x8b10, 0x0000ff0f, 0x00000000,
  146. 0x28a4c, 0x07ffffff, 0x4e000000,
  147. 0x28350, 0x3f3f3fff, 0x2a00126a,
  148. 0x30, 0x000000ff, 0x0040,
  149. 0x34, 0x00000040, 0x00004040,
  150. 0x9100, 0x07ffffff, 0x03000000,
  151. 0x9060, 0x0000007f, 0x00000020,
  152. 0x9508, 0x00010000, 0x00010000,
  153. 0xac14, 0x000003ff, 0x000000f7,
  154. 0xac10, 0xffffffff, 0x00000000,
  155. 0xac0c, 0xffffffff, 0x32761054,
  156. 0x88d4, 0x0000001f, 0x00000010,
  157. 0x15c0, 0x000c0fc0, 0x000c0400
  158. };
  159. static const u32 verde_golden_rlc_registers[] =
  160. {
  161. 0xc424, 0xffffffff, 0x033f1005,
  162. 0xc47c, 0xffffffff, 0x10808020,
  163. 0xc488, 0xffffffff, 0x00800008,
  164. 0xc314, 0xffffffff, 0x00001000,
  165. 0xc30c, 0xffffffff, 0x80010014
  166. };
  167. static const u32 verde_golden_registers[] =
  168. {
  169. 0x9a10, 0x00010000, 0x00018208,
  170. 0x9830, 0xffffffff, 0x00000000,
  171. 0x9834, 0xf00fffff, 0x00000400,
  172. 0x9838, 0x0002021c, 0x00020200,
  173. 0xc78, 0x00000080, 0x00000000,
  174. 0xd030, 0x000300c0, 0x00800040,
  175. 0xd030, 0x000300c0, 0x00800040,
  176. 0xd830, 0x000300c0, 0x00800040,
  177. 0xd830, 0x000300c0, 0x00800040,
  178. 0x5bb0, 0x000000f0, 0x00000070,
  179. 0x5bc0, 0x00200000, 0x50100000,
  180. 0x7030, 0x31000311, 0x00000011,
  181. 0x2ae4, 0x00073ffe, 0x000022a2,
  182. 0x2ae4, 0x00073ffe, 0x000022a2,
  183. 0x2ae4, 0x00073ffe, 0x000022a2,
  184. 0x240c, 0x000007ff, 0x00000000,
  185. 0x240c, 0x000007ff, 0x00000000,
  186. 0x240c, 0x000007ff, 0x00000000,
  187. 0x8a14, 0xf000001f, 0x00000007,
  188. 0x8a14, 0xf000001f, 0x00000007,
  189. 0x8a14, 0xf000001f, 0x00000007,
  190. 0x8b24, 0xffffffff, 0x00ffffff,
  191. 0x8b10, 0x0000ff0f, 0x00000000,
  192. 0x28a4c, 0x07ffffff, 0x4e000000,
  193. 0x28350, 0x3f3f3fff, 0x0000124a,
  194. 0x28350, 0x3f3f3fff, 0x0000124a,
  195. 0x28350, 0x3f3f3fff, 0x0000124a,
  196. 0x30, 0x000000ff, 0x0040,
  197. 0x34, 0x00000040, 0x00004040,
  198. 0x9100, 0x07ffffff, 0x03000000,
  199. 0x9100, 0x07ffffff, 0x03000000,
  200. 0x8e88, 0x01ff1f3f, 0x00000000,
  201. 0x8e88, 0x01ff1f3f, 0x00000000,
  202. 0x8e88, 0x01ff1f3f, 0x00000000,
  203. 0x8e84, 0x01ff1f3f, 0x00000000,
  204. 0x8e84, 0x01ff1f3f, 0x00000000,
  205. 0x8e84, 0x01ff1f3f, 0x00000000,
  206. 0x9060, 0x0000007f, 0x00000020,
  207. 0x9508, 0x00010000, 0x00010000,
  208. 0xac14, 0x000003ff, 0x00000003,
  209. 0xac14, 0x000003ff, 0x00000003,
  210. 0xac14, 0x000003ff, 0x00000003,
  211. 0xac10, 0xffffffff, 0x00000000,
  212. 0xac10, 0xffffffff, 0x00000000,
  213. 0xac10, 0xffffffff, 0x00000000,
  214. 0xac0c, 0xffffffff, 0x00001032,
  215. 0xac0c, 0xffffffff, 0x00001032,
  216. 0xac0c, 0xffffffff, 0x00001032,
  217. 0x88d4, 0x0000001f, 0x00000010,
  218. 0x88d4, 0x0000001f, 0x00000010,
  219. 0x88d4, 0x0000001f, 0x00000010,
  220. 0x15c0, 0x000c0fc0, 0x000c0400
  221. };
  222. static const u32 oland_golden_rlc_registers[] =
  223. {
  224. 0xc424, 0xffffffff, 0x00601005,
  225. 0xc47c, 0xffffffff, 0x10104040,
  226. 0xc488, 0xffffffff, 0x0100000a,
  227. 0xc314, 0xffffffff, 0x00000800,
  228. 0xc30c, 0xffffffff, 0x800000f4
  229. };
  230. static const u32 oland_golden_registers[] =
  231. {
  232. 0x9a10, 0x00010000, 0x00018208,
  233. 0x9830, 0xffffffff, 0x00000000,
  234. 0x9834, 0xf00fffff, 0x00000400,
  235. 0x9838, 0x0002021c, 0x00020200,
  236. 0xc78, 0x00000080, 0x00000000,
  237. 0xd030, 0x000300c0, 0x00800040,
  238. 0xd830, 0x000300c0, 0x00800040,
  239. 0x5bb0, 0x000000f0, 0x00000070,
  240. 0x5bc0, 0x00200000, 0x50100000,
  241. 0x7030, 0x31000311, 0x00000011,
  242. 0x2ae4, 0x00073ffe, 0x000022a2,
  243. 0x240c, 0x000007ff, 0x00000000,
  244. 0x8a14, 0xf000001f, 0x00000007,
  245. 0x8b24, 0xffffffff, 0x00ffffff,
  246. 0x8b10, 0x0000ff0f, 0x00000000,
  247. 0x28a4c, 0x07ffffff, 0x4e000000,
  248. 0x28350, 0x3f3f3fff, 0x00000082,
  249. 0x30, 0x000000ff, 0x0040,
  250. 0x34, 0x00000040, 0x00004040,
  251. 0x9100, 0x07ffffff, 0x03000000,
  252. 0x9060, 0x0000007f, 0x00000020,
  253. 0x9508, 0x00010000, 0x00010000,
  254. 0xac14, 0x000003ff, 0x000000f3,
  255. 0xac10, 0xffffffff, 0x00000000,
  256. 0xac0c, 0xffffffff, 0x00003210,
  257. 0x88d4, 0x0000001f, 0x00000010,
  258. 0x15c0, 0x000c0fc0, 0x000c0400
  259. };
  260. static const u32 hainan_golden_registers[] =
  261. {
  262. 0x9a10, 0x00010000, 0x00018208,
  263. 0x9830, 0xffffffff, 0x00000000,
  264. 0x9834, 0xf00fffff, 0x00000400,
  265. 0x9838, 0x0002021c, 0x00020200,
  266. 0xd0c0, 0xff000fff, 0x00000100,
  267. 0xd030, 0x000300c0, 0x00800040,
  268. 0xd8c0, 0xff000fff, 0x00000100,
  269. 0xd830, 0x000300c0, 0x00800040,
  270. 0x2ae4, 0x00073ffe, 0x000022a2,
  271. 0x240c, 0x000007ff, 0x00000000,
  272. 0x8a14, 0xf000001f, 0x00000007,
  273. 0x8b24, 0xffffffff, 0x00ffffff,
  274. 0x8b10, 0x0000ff0f, 0x00000000,
  275. 0x28a4c, 0x07ffffff, 0x4e000000,
  276. 0x28350, 0x3f3f3fff, 0x00000000,
  277. 0x30, 0x000000ff, 0x0040,
  278. 0x34, 0x00000040, 0x00004040,
  279. 0x9100, 0x03e00000, 0x03600000,
  280. 0x9060, 0x0000007f, 0x00000020,
  281. 0x9508, 0x00010000, 0x00010000,
  282. 0xac14, 0x000003ff, 0x000000f1,
  283. 0xac10, 0xffffffff, 0x00000000,
  284. 0xac0c, 0xffffffff, 0x00003210,
  285. 0x88d4, 0x0000001f, 0x00000010,
  286. 0x15c0, 0x000c0fc0, 0x000c0400
  287. };
  288. static const u32 hainan_golden_registers2[] =
  289. {
  290. 0x98f8, 0xffffffff, 0x02010001
  291. };
  292. static const u32 tahiti_mgcg_cgcg_init[] =
  293. {
  294. 0xc400, 0xffffffff, 0xfffffffc,
  295. 0x802c, 0xffffffff, 0xe0000000,
  296. 0x9a60, 0xffffffff, 0x00000100,
  297. 0x92a4, 0xffffffff, 0x00000100,
  298. 0xc164, 0xffffffff, 0x00000100,
  299. 0x9774, 0xffffffff, 0x00000100,
  300. 0x8984, 0xffffffff, 0x06000100,
  301. 0x8a18, 0xffffffff, 0x00000100,
  302. 0x92a0, 0xffffffff, 0x00000100,
  303. 0xc380, 0xffffffff, 0x00000100,
  304. 0x8b28, 0xffffffff, 0x00000100,
  305. 0x9144, 0xffffffff, 0x00000100,
  306. 0x8d88, 0xffffffff, 0x00000100,
  307. 0x8d8c, 0xffffffff, 0x00000100,
  308. 0x9030, 0xffffffff, 0x00000100,
  309. 0x9034, 0xffffffff, 0x00000100,
  310. 0x9038, 0xffffffff, 0x00000100,
  311. 0x903c, 0xffffffff, 0x00000100,
  312. 0xad80, 0xffffffff, 0x00000100,
  313. 0xac54, 0xffffffff, 0x00000100,
  314. 0x897c, 0xffffffff, 0x06000100,
  315. 0x9868, 0xffffffff, 0x00000100,
  316. 0x9510, 0xffffffff, 0x00000100,
  317. 0xaf04, 0xffffffff, 0x00000100,
  318. 0xae04, 0xffffffff, 0x00000100,
  319. 0x949c, 0xffffffff, 0x00000100,
  320. 0x802c, 0xffffffff, 0xe0000000,
  321. 0x9160, 0xffffffff, 0x00010000,
  322. 0x9164, 0xffffffff, 0x00030002,
  323. 0x9168, 0xffffffff, 0x00040007,
  324. 0x916c, 0xffffffff, 0x00060005,
  325. 0x9170, 0xffffffff, 0x00090008,
  326. 0x9174, 0xffffffff, 0x00020001,
  327. 0x9178, 0xffffffff, 0x00040003,
  328. 0x917c, 0xffffffff, 0x00000007,
  329. 0x9180, 0xffffffff, 0x00060005,
  330. 0x9184, 0xffffffff, 0x00090008,
  331. 0x9188, 0xffffffff, 0x00030002,
  332. 0x918c, 0xffffffff, 0x00050004,
  333. 0x9190, 0xffffffff, 0x00000008,
  334. 0x9194, 0xffffffff, 0x00070006,
  335. 0x9198, 0xffffffff, 0x000a0009,
  336. 0x919c, 0xffffffff, 0x00040003,
  337. 0x91a0, 0xffffffff, 0x00060005,
  338. 0x91a4, 0xffffffff, 0x00000009,
  339. 0x91a8, 0xffffffff, 0x00080007,
  340. 0x91ac, 0xffffffff, 0x000b000a,
  341. 0x91b0, 0xffffffff, 0x00050004,
  342. 0x91b4, 0xffffffff, 0x00070006,
  343. 0x91b8, 0xffffffff, 0x0008000b,
  344. 0x91bc, 0xffffffff, 0x000a0009,
  345. 0x91c0, 0xffffffff, 0x000d000c,
  346. 0x91c4, 0xffffffff, 0x00060005,
  347. 0x91c8, 0xffffffff, 0x00080007,
  348. 0x91cc, 0xffffffff, 0x0000000b,
  349. 0x91d0, 0xffffffff, 0x000a0009,
  350. 0x91d4, 0xffffffff, 0x000d000c,
  351. 0x91d8, 0xffffffff, 0x00070006,
  352. 0x91dc, 0xffffffff, 0x00090008,
  353. 0x91e0, 0xffffffff, 0x0000000c,
  354. 0x91e4, 0xffffffff, 0x000b000a,
  355. 0x91e8, 0xffffffff, 0x000e000d,
  356. 0x91ec, 0xffffffff, 0x00080007,
  357. 0x91f0, 0xffffffff, 0x000a0009,
  358. 0x91f4, 0xffffffff, 0x0000000d,
  359. 0x91f8, 0xffffffff, 0x000c000b,
  360. 0x91fc, 0xffffffff, 0x000f000e,
  361. 0x9200, 0xffffffff, 0x00090008,
  362. 0x9204, 0xffffffff, 0x000b000a,
  363. 0x9208, 0xffffffff, 0x000c000f,
  364. 0x920c, 0xffffffff, 0x000e000d,
  365. 0x9210, 0xffffffff, 0x00110010,
  366. 0x9214, 0xffffffff, 0x000a0009,
  367. 0x9218, 0xffffffff, 0x000c000b,
  368. 0x921c, 0xffffffff, 0x0000000f,
  369. 0x9220, 0xffffffff, 0x000e000d,
  370. 0x9224, 0xffffffff, 0x00110010,
  371. 0x9228, 0xffffffff, 0x000b000a,
  372. 0x922c, 0xffffffff, 0x000d000c,
  373. 0x9230, 0xffffffff, 0x00000010,
  374. 0x9234, 0xffffffff, 0x000f000e,
  375. 0x9238, 0xffffffff, 0x00120011,
  376. 0x923c, 0xffffffff, 0x000c000b,
  377. 0x9240, 0xffffffff, 0x000e000d,
  378. 0x9244, 0xffffffff, 0x00000011,
  379. 0x9248, 0xffffffff, 0x0010000f,
  380. 0x924c, 0xffffffff, 0x00130012,
  381. 0x9250, 0xffffffff, 0x000d000c,
  382. 0x9254, 0xffffffff, 0x000f000e,
  383. 0x9258, 0xffffffff, 0x00100013,
  384. 0x925c, 0xffffffff, 0x00120011,
  385. 0x9260, 0xffffffff, 0x00150014,
  386. 0x9264, 0xffffffff, 0x000e000d,
  387. 0x9268, 0xffffffff, 0x0010000f,
  388. 0x926c, 0xffffffff, 0x00000013,
  389. 0x9270, 0xffffffff, 0x00120011,
  390. 0x9274, 0xffffffff, 0x00150014,
  391. 0x9278, 0xffffffff, 0x000f000e,
  392. 0x927c, 0xffffffff, 0x00110010,
  393. 0x9280, 0xffffffff, 0x00000014,
  394. 0x9284, 0xffffffff, 0x00130012,
  395. 0x9288, 0xffffffff, 0x00160015,
  396. 0x928c, 0xffffffff, 0x0010000f,
  397. 0x9290, 0xffffffff, 0x00120011,
  398. 0x9294, 0xffffffff, 0x00000015,
  399. 0x9298, 0xffffffff, 0x00140013,
  400. 0x929c, 0xffffffff, 0x00170016,
  401. 0x9150, 0xffffffff, 0x96940200,
  402. 0x8708, 0xffffffff, 0x00900100,
  403. 0xc478, 0xffffffff, 0x00000080,
  404. 0xc404, 0xffffffff, 0x0020003f,
  405. 0x30, 0xffffffff, 0x0000001c,
  406. 0x34, 0x000f0000, 0x000f0000,
  407. 0x160c, 0xffffffff, 0x00000100,
  408. 0x1024, 0xffffffff, 0x00000100,
  409. 0x102c, 0x00000101, 0x00000000,
  410. 0x20a8, 0xffffffff, 0x00000104,
  411. 0x264c, 0x000c0000, 0x000c0000,
  412. 0x2648, 0x000c0000, 0x000c0000,
  413. 0x55e4, 0xff000fff, 0x00000100,
  414. 0x55e8, 0x00000001, 0x00000001,
  415. 0x2f50, 0x00000001, 0x00000001,
  416. 0x30cc, 0xc0000fff, 0x00000104,
  417. 0xc1e4, 0x00000001, 0x00000001,
  418. 0xd0c0, 0xfffffff0, 0x00000100,
  419. 0xd8c0, 0xfffffff0, 0x00000100
  420. };
  421. static const u32 pitcairn_mgcg_cgcg_init[] =
  422. {
  423. 0xc400, 0xffffffff, 0xfffffffc,
  424. 0x802c, 0xffffffff, 0xe0000000,
  425. 0x9a60, 0xffffffff, 0x00000100,
  426. 0x92a4, 0xffffffff, 0x00000100,
  427. 0xc164, 0xffffffff, 0x00000100,
  428. 0x9774, 0xffffffff, 0x00000100,
  429. 0x8984, 0xffffffff, 0x06000100,
  430. 0x8a18, 0xffffffff, 0x00000100,
  431. 0x92a0, 0xffffffff, 0x00000100,
  432. 0xc380, 0xffffffff, 0x00000100,
  433. 0x8b28, 0xffffffff, 0x00000100,
  434. 0x9144, 0xffffffff, 0x00000100,
  435. 0x8d88, 0xffffffff, 0x00000100,
  436. 0x8d8c, 0xffffffff, 0x00000100,
  437. 0x9030, 0xffffffff, 0x00000100,
  438. 0x9034, 0xffffffff, 0x00000100,
  439. 0x9038, 0xffffffff, 0x00000100,
  440. 0x903c, 0xffffffff, 0x00000100,
  441. 0xad80, 0xffffffff, 0x00000100,
  442. 0xac54, 0xffffffff, 0x00000100,
  443. 0x897c, 0xffffffff, 0x06000100,
  444. 0x9868, 0xffffffff, 0x00000100,
  445. 0x9510, 0xffffffff, 0x00000100,
  446. 0xaf04, 0xffffffff, 0x00000100,
  447. 0xae04, 0xffffffff, 0x00000100,
  448. 0x949c, 0xffffffff, 0x00000100,
  449. 0x802c, 0xffffffff, 0xe0000000,
  450. 0x9160, 0xffffffff, 0x00010000,
  451. 0x9164, 0xffffffff, 0x00030002,
  452. 0x9168, 0xffffffff, 0x00040007,
  453. 0x916c, 0xffffffff, 0x00060005,
  454. 0x9170, 0xffffffff, 0x00090008,
  455. 0x9174, 0xffffffff, 0x00020001,
  456. 0x9178, 0xffffffff, 0x00040003,
  457. 0x917c, 0xffffffff, 0x00000007,
  458. 0x9180, 0xffffffff, 0x00060005,
  459. 0x9184, 0xffffffff, 0x00090008,
  460. 0x9188, 0xffffffff, 0x00030002,
  461. 0x918c, 0xffffffff, 0x00050004,
  462. 0x9190, 0xffffffff, 0x00000008,
  463. 0x9194, 0xffffffff, 0x00070006,
  464. 0x9198, 0xffffffff, 0x000a0009,
  465. 0x919c, 0xffffffff, 0x00040003,
  466. 0x91a0, 0xffffffff, 0x00060005,
  467. 0x91a4, 0xffffffff, 0x00000009,
  468. 0x91a8, 0xffffffff, 0x00080007,
  469. 0x91ac, 0xffffffff, 0x000b000a,
  470. 0x91b0, 0xffffffff, 0x00050004,
  471. 0x91b4, 0xffffffff, 0x00070006,
  472. 0x91b8, 0xffffffff, 0x0008000b,
  473. 0x91bc, 0xffffffff, 0x000a0009,
  474. 0x91c0, 0xffffffff, 0x000d000c,
  475. 0x9200, 0xffffffff, 0x00090008,
  476. 0x9204, 0xffffffff, 0x000b000a,
  477. 0x9208, 0xffffffff, 0x000c000f,
  478. 0x920c, 0xffffffff, 0x000e000d,
  479. 0x9210, 0xffffffff, 0x00110010,
  480. 0x9214, 0xffffffff, 0x000a0009,
  481. 0x9218, 0xffffffff, 0x000c000b,
  482. 0x921c, 0xffffffff, 0x0000000f,
  483. 0x9220, 0xffffffff, 0x000e000d,
  484. 0x9224, 0xffffffff, 0x00110010,
  485. 0x9228, 0xffffffff, 0x000b000a,
  486. 0x922c, 0xffffffff, 0x000d000c,
  487. 0x9230, 0xffffffff, 0x00000010,
  488. 0x9234, 0xffffffff, 0x000f000e,
  489. 0x9238, 0xffffffff, 0x00120011,
  490. 0x923c, 0xffffffff, 0x000c000b,
  491. 0x9240, 0xffffffff, 0x000e000d,
  492. 0x9244, 0xffffffff, 0x00000011,
  493. 0x9248, 0xffffffff, 0x0010000f,
  494. 0x924c, 0xffffffff, 0x00130012,
  495. 0x9250, 0xffffffff, 0x000d000c,
  496. 0x9254, 0xffffffff, 0x000f000e,
  497. 0x9258, 0xffffffff, 0x00100013,
  498. 0x925c, 0xffffffff, 0x00120011,
  499. 0x9260, 0xffffffff, 0x00150014,
  500. 0x9150, 0xffffffff, 0x96940200,
  501. 0x8708, 0xffffffff, 0x00900100,
  502. 0xc478, 0xffffffff, 0x00000080,
  503. 0xc404, 0xffffffff, 0x0020003f,
  504. 0x30, 0xffffffff, 0x0000001c,
  505. 0x34, 0x000f0000, 0x000f0000,
  506. 0x160c, 0xffffffff, 0x00000100,
  507. 0x1024, 0xffffffff, 0x00000100,
  508. 0x102c, 0x00000101, 0x00000000,
  509. 0x20a8, 0xffffffff, 0x00000104,
  510. 0x55e4, 0xff000fff, 0x00000100,
  511. 0x55e8, 0x00000001, 0x00000001,
  512. 0x2f50, 0x00000001, 0x00000001,
  513. 0x30cc, 0xc0000fff, 0x00000104,
  514. 0xc1e4, 0x00000001, 0x00000001,
  515. 0xd0c0, 0xfffffff0, 0x00000100,
  516. 0xd8c0, 0xfffffff0, 0x00000100
  517. };
  518. static const u32 verde_mgcg_cgcg_init[] =
  519. {
  520. 0xc400, 0xffffffff, 0xfffffffc,
  521. 0x802c, 0xffffffff, 0xe0000000,
  522. 0x9a60, 0xffffffff, 0x00000100,
  523. 0x92a4, 0xffffffff, 0x00000100,
  524. 0xc164, 0xffffffff, 0x00000100,
  525. 0x9774, 0xffffffff, 0x00000100,
  526. 0x8984, 0xffffffff, 0x06000100,
  527. 0x8a18, 0xffffffff, 0x00000100,
  528. 0x92a0, 0xffffffff, 0x00000100,
  529. 0xc380, 0xffffffff, 0x00000100,
  530. 0x8b28, 0xffffffff, 0x00000100,
  531. 0x9144, 0xffffffff, 0x00000100,
  532. 0x8d88, 0xffffffff, 0x00000100,
  533. 0x8d8c, 0xffffffff, 0x00000100,
  534. 0x9030, 0xffffffff, 0x00000100,
  535. 0x9034, 0xffffffff, 0x00000100,
  536. 0x9038, 0xffffffff, 0x00000100,
  537. 0x903c, 0xffffffff, 0x00000100,
  538. 0xad80, 0xffffffff, 0x00000100,
  539. 0xac54, 0xffffffff, 0x00000100,
  540. 0x897c, 0xffffffff, 0x06000100,
  541. 0x9868, 0xffffffff, 0x00000100,
  542. 0x9510, 0xffffffff, 0x00000100,
  543. 0xaf04, 0xffffffff, 0x00000100,
  544. 0xae04, 0xffffffff, 0x00000100,
  545. 0x949c, 0xffffffff, 0x00000100,
  546. 0x802c, 0xffffffff, 0xe0000000,
  547. 0x9160, 0xffffffff, 0x00010000,
  548. 0x9164, 0xffffffff, 0x00030002,
  549. 0x9168, 0xffffffff, 0x00040007,
  550. 0x916c, 0xffffffff, 0x00060005,
  551. 0x9170, 0xffffffff, 0x00090008,
  552. 0x9174, 0xffffffff, 0x00020001,
  553. 0x9178, 0xffffffff, 0x00040003,
  554. 0x917c, 0xffffffff, 0x00000007,
  555. 0x9180, 0xffffffff, 0x00060005,
  556. 0x9184, 0xffffffff, 0x00090008,
  557. 0x9188, 0xffffffff, 0x00030002,
  558. 0x918c, 0xffffffff, 0x00050004,
  559. 0x9190, 0xffffffff, 0x00000008,
  560. 0x9194, 0xffffffff, 0x00070006,
  561. 0x9198, 0xffffffff, 0x000a0009,
  562. 0x919c, 0xffffffff, 0x00040003,
  563. 0x91a0, 0xffffffff, 0x00060005,
  564. 0x91a4, 0xffffffff, 0x00000009,
  565. 0x91a8, 0xffffffff, 0x00080007,
  566. 0x91ac, 0xffffffff, 0x000b000a,
  567. 0x91b0, 0xffffffff, 0x00050004,
  568. 0x91b4, 0xffffffff, 0x00070006,
  569. 0x91b8, 0xffffffff, 0x0008000b,
  570. 0x91bc, 0xffffffff, 0x000a0009,
  571. 0x91c0, 0xffffffff, 0x000d000c,
  572. 0x9200, 0xffffffff, 0x00090008,
  573. 0x9204, 0xffffffff, 0x000b000a,
  574. 0x9208, 0xffffffff, 0x000c000f,
  575. 0x920c, 0xffffffff, 0x000e000d,
  576. 0x9210, 0xffffffff, 0x00110010,
  577. 0x9214, 0xffffffff, 0x000a0009,
  578. 0x9218, 0xffffffff, 0x000c000b,
  579. 0x921c, 0xffffffff, 0x0000000f,
  580. 0x9220, 0xffffffff, 0x000e000d,
  581. 0x9224, 0xffffffff, 0x00110010,
  582. 0x9228, 0xffffffff, 0x000b000a,
  583. 0x922c, 0xffffffff, 0x000d000c,
  584. 0x9230, 0xffffffff, 0x00000010,
  585. 0x9234, 0xffffffff, 0x000f000e,
  586. 0x9238, 0xffffffff, 0x00120011,
  587. 0x923c, 0xffffffff, 0x000c000b,
  588. 0x9240, 0xffffffff, 0x000e000d,
  589. 0x9244, 0xffffffff, 0x00000011,
  590. 0x9248, 0xffffffff, 0x0010000f,
  591. 0x924c, 0xffffffff, 0x00130012,
  592. 0x9250, 0xffffffff, 0x000d000c,
  593. 0x9254, 0xffffffff, 0x000f000e,
  594. 0x9258, 0xffffffff, 0x00100013,
  595. 0x925c, 0xffffffff, 0x00120011,
  596. 0x9260, 0xffffffff, 0x00150014,
  597. 0x9150, 0xffffffff, 0x96940200,
  598. 0x8708, 0xffffffff, 0x00900100,
  599. 0xc478, 0xffffffff, 0x00000080,
  600. 0xc404, 0xffffffff, 0x0020003f,
  601. 0x30, 0xffffffff, 0x0000001c,
  602. 0x34, 0x000f0000, 0x000f0000,
  603. 0x160c, 0xffffffff, 0x00000100,
  604. 0x1024, 0xffffffff, 0x00000100,
  605. 0x102c, 0x00000101, 0x00000000,
  606. 0x20a8, 0xffffffff, 0x00000104,
  607. 0x264c, 0x000c0000, 0x000c0000,
  608. 0x2648, 0x000c0000, 0x000c0000,
  609. 0x55e4, 0xff000fff, 0x00000100,
  610. 0x55e8, 0x00000001, 0x00000001,
  611. 0x2f50, 0x00000001, 0x00000001,
  612. 0x30cc, 0xc0000fff, 0x00000104,
  613. 0xc1e4, 0x00000001, 0x00000001,
  614. 0xd0c0, 0xfffffff0, 0x00000100,
  615. 0xd8c0, 0xfffffff0, 0x00000100
  616. };
  617. static const u32 oland_mgcg_cgcg_init[] =
  618. {
  619. 0xc400, 0xffffffff, 0xfffffffc,
  620. 0x802c, 0xffffffff, 0xe0000000,
  621. 0x9a60, 0xffffffff, 0x00000100,
  622. 0x92a4, 0xffffffff, 0x00000100,
  623. 0xc164, 0xffffffff, 0x00000100,
  624. 0x9774, 0xffffffff, 0x00000100,
  625. 0x8984, 0xffffffff, 0x06000100,
  626. 0x8a18, 0xffffffff, 0x00000100,
  627. 0x92a0, 0xffffffff, 0x00000100,
  628. 0xc380, 0xffffffff, 0x00000100,
  629. 0x8b28, 0xffffffff, 0x00000100,
  630. 0x9144, 0xffffffff, 0x00000100,
  631. 0x8d88, 0xffffffff, 0x00000100,
  632. 0x8d8c, 0xffffffff, 0x00000100,
  633. 0x9030, 0xffffffff, 0x00000100,
  634. 0x9034, 0xffffffff, 0x00000100,
  635. 0x9038, 0xffffffff, 0x00000100,
  636. 0x903c, 0xffffffff, 0x00000100,
  637. 0xad80, 0xffffffff, 0x00000100,
  638. 0xac54, 0xffffffff, 0x00000100,
  639. 0x897c, 0xffffffff, 0x06000100,
  640. 0x9868, 0xffffffff, 0x00000100,
  641. 0x9510, 0xffffffff, 0x00000100,
  642. 0xaf04, 0xffffffff, 0x00000100,
  643. 0xae04, 0xffffffff, 0x00000100,
  644. 0x949c, 0xffffffff, 0x00000100,
  645. 0x802c, 0xffffffff, 0xe0000000,
  646. 0x9160, 0xffffffff, 0x00010000,
  647. 0x9164, 0xffffffff, 0x00030002,
  648. 0x9168, 0xffffffff, 0x00040007,
  649. 0x916c, 0xffffffff, 0x00060005,
  650. 0x9170, 0xffffffff, 0x00090008,
  651. 0x9174, 0xffffffff, 0x00020001,
  652. 0x9178, 0xffffffff, 0x00040003,
  653. 0x917c, 0xffffffff, 0x00000007,
  654. 0x9180, 0xffffffff, 0x00060005,
  655. 0x9184, 0xffffffff, 0x00090008,
  656. 0x9188, 0xffffffff, 0x00030002,
  657. 0x918c, 0xffffffff, 0x00050004,
  658. 0x9190, 0xffffffff, 0x00000008,
  659. 0x9194, 0xffffffff, 0x00070006,
  660. 0x9198, 0xffffffff, 0x000a0009,
  661. 0x919c, 0xffffffff, 0x00040003,
  662. 0x91a0, 0xffffffff, 0x00060005,
  663. 0x91a4, 0xffffffff, 0x00000009,
  664. 0x91a8, 0xffffffff, 0x00080007,
  665. 0x91ac, 0xffffffff, 0x000b000a,
  666. 0x91b0, 0xffffffff, 0x00050004,
  667. 0x91b4, 0xffffffff, 0x00070006,
  668. 0x91b8, 0xffffffff, 0x0008000b,
  669. 0x91bc, 0xffffffff, 0x000a0009,
  670. 0x91c0, 0xffffffff, 0x000d000c,
  671. 0x91c4, 0xffffffff, 0x00060005,
  672. 0x91c8, 0xffffffff, 0x00080007,
  673. 0x91cc, 0xffffffff, 0x0000000b,
  674. 0x91d0, 0xffffffff, 0x000a0009,
  675. 0x91d4, 0xffffffff, 0x000d000c,
  676. 0x9150, 0xffffffff, 0x96940200,
  677. 0x8708, 0xffffffff, 0x00900100,
  678. 0xc478, 0xffffffff, 0x00000080,
  679. 0xc404, 0xffffffff, 0x0020003f,
  680. 0x30, 0xffffffff, 0x0000001c,
  681. 0x34, 0x000f0000, 0x000f0000,
  682. 0x160c, 0xffffffff, 0x00000100,
  683. 0x1024, 0xffffffff, 0x00000100,
  684. 0x102c, 0x00000101, 0x00000000,
  685. 0x20a8, 0xffffffff, 0x00000104,
  686. 0x264c, 0x000c0000, 0x000c0000,
  687. 0x2648, 0x000c0000, 0x000c0000,
  688. 0x55e4, 0xff000fff, 0x00000100,
  689. 0x55e8, 0x00000001, 0x00000001,
  690. 0x2f50, 0x00000001, 0x00000001,
  691. 0x30cc, 0xc0000fff, 0x00000104,
  692. 0xc1e4, 0x00000001, 0x00000001,
  693. 0xd0c0, 0xfffffff0, 0x00000100,
  694. 0xd8c0, 0xfffffff0, 0x00000100
  695. };
  696. static const u32 hainan_mgcg_cgcg_init[] =
  697. {
  698. 0xc400, 0xffffffff, 0xfffffffc,
  699. 0x802c, 0xffffffff, 0xe0000000,
  700. 0x9a60, 0xffffffff, 0x00000100,
  701. 0x92a4, 0xffffffff, 0x00000100,
  702. 0xc164, 0xffffffff, 0x00000100,
  703. 0x9774, 0xffffffff, 0x00000100,
  704. 0x8984, 0xffffffff, 0x06000100,
  705. 0x8a18, 0xffffffff, 0x00000100,
  706. 0x92a0, 0xffffffff, 0x00000100,
  707. 0xc380, 0xffffffff, 0x00000100,
  708. 0x8b28, 0xffffffff, 0x00000100,
  709. 0x9144, 0xffffffff, 0x00000100,
  710. 0x8d88, 0xffffffff, 0x00000100,
  711. 0x8d8c, 0xffffffff, 0x00000100,
  712. 0x9030, 0xffffffff, 0x00000100,
  713. 0x9034, 0xffffffff, 0x00000100,
  714. 0x9038, 0xffffffff, 0x00000100,
  715. 0x903c, 0xffffffff, 0x00000100,
  716. 0xad80, 0xffffffff, 0x00000100,
  717. 0xac54, 0xffffffff, 0x00000100,
  718. 0x897c, 0xffffffff, 0x06000100,
  719. 0x9868, 0xffffffff, 0x00000100,
  720. 0x9510, 0xffffffff, 0x00000100,
  721. 0xaf04, 0xffffffff, 0x00000100,
  722. 0xae04, 0xffffffff, 0x00000100,
  723. 0x949c, 0xffffffff, 0x00000100,
  724. 0x802c, 0xffffffff, 0xe0000000,
  725. 0x9160, 0xffffffff, 0x00010000,
  726. 0x9164, 0xffffffff, 0x00030002,
  727. 0x9168, 0xffffffff, 0x00040007,
  728. 0x916c, 0xffffffff, 0x00060005,
  729. 0x9170, 0xffffffff, 0x00090008,
  730. 0x9174, 0xffffffff, 0x00020001,
  731. 0x9178, 0xffffffff, 0x00040003,
  732. 0x917c, 0xffffffff, 0x00000007,
  733. 0x9180, 0xffffffff, 0x00060005,
  734. 0x9184, 0xffffffff, 0x00090008,
  735. 0x9188, 0xffffffff, 0x00030002,
  736. 0x918c, 0xffffffff, 0x00050004,
  737. 0x9190, 0xffffffff, 0x00000008,
  738. 0x9194, 0xffffffff, 0x00070006,
  739. 0x9198, 0xffffffff, 0x000a0009,
  740. 0x919c, 0xffffffff, 0x00040003,
  741. 0x91a0, 0xffffffff, 0x00060005,
  742. 0x91a4, 0xffffffff, 0x00000009,
  743. 0x91a8, 0xffffffff, 0x00080007,
  744. 0x91ac, 0xffffffff, 0x000b000a,
  745. 0x91b0, 0xffffffff, 0x00050004,
  746. 0x91b4, 0xffffffff, 0x00070006,
  747. 0x91b8, 0xffffffff, 0x0008000b,
  748. 0x91bc, 0xffffffff, 0x000a0009,
  749. 0x91c0, 0xffffffff, 0x000d000c,
  750. 0x91c4, 0xffffffff, 0x00060005,
  751. 0x91c8, 0xffffffff, 0x00080007,
  752. 0x91cc, 0xffffffff, 0x0000000b,
  753. 0x91d0, 0xffffffff, 0x000a0009,
  754. 0x91d4, 0xffffffff, 0x000d000c,
  755. 0x9150, 0xffffffff, 0x96940200,
  756. 0x8708, 0xffffffff, 0x00900100,
  757. 0xc478, 0xffffffff, 0x00000080,
  758. 0xc404, 0xffffffff, 0x0020003f,
  759. 0x30, 0xffffffff, 0x0000001c,
  760. 0x34, 0x000f0000, 0x000f0000,
  761. 0x160c, 0xffffffff, 0x00000100,
  762. 0x1024, 0xffffffff, 0x00000100,
  763. 0x20a8, 0xffffffff, 0x00000104,
  764. 0x264c, 0x000c0000, 0x000c0000,
  765. 0x2648, 0x000c0000, 0x000c0000,
  766. 0x2f50, 0x00000001, 0x00000001,
  767. 0x30cc, 0xc0000fff, 0x00000104,
  768. 0xc1e4, 0x00000001, 0x00000001,
  769. 0xd0c0, 0xfffffff0, 0x00000100,
  770. 0xd8c0, 0xfffffff0, 0x00000100
  771. };
  772. static u32 verde_pg_init[] =
  773. {
  774. 0x353c, 0xffffffff, 0x40000,
  775. 0x3538, 0xffffffff, 0x200010ff,
  776. 0x353c, 0xffffffff, 0x0,
  777. 0x353c, 0xffffffff, 0x0,
  778. 0x353c, 0xffffffff, 0x0,
  779. 0x353c, 0xffffffff, 0x0,
  780. 0x353c, 0xffffffff, 0x0,
  781. 0x353c, 0xffffffff, 0x7007,
  782. 0x3538, 0xffffffff, 0x300010ff,
  783. 0x353c, 0xffffffff, 0x0,
  784. 0x353c, 0xffffffff, 0x0,
  785. 0x353c, 0xffffffff, 0x0,
  786. 0x353c, 0xffffffff, 0x0,
  787. 0x353c, 0xffffffff, 0x0,
  788. 0x353c, 0xffffffff, 0x400000,
  789. 0x3538, 0xffffffff, 0x100010ff,
  790. 0x353c, 0xffffffff, 0x0,
  791. 0x353c, 0xffffffff, 0x0,
  792. 0x353c, 0xffffffff, 0x0,
  793. 0x353c, 0xffffffff, 0x0,
  794. 0x353c, 0xffffffff, 0x0,
  795. 0x353c, 0xffffffff, 0x120200,
  796. 0x3538, 0xffffffff, 0x500010ff,
  797. 0x353c, 0xffffffff, 0x0,
  798. 0x353c, 0xffffffff, 0x0,
  799. 0x353c, 0xffffffff, 0x0,
  800. 0x353c, 0xffffffff, 0x0,
  801. 0x353c, 0xffffffff, 0x0,
  802. 0x353c, 0xffffffff, 0x1e1e16,
  803. 0x3538, 0xffffffff, 0x600010ff,
  804. 0x353c, 0xffffffff, 0x0,
  805. 0x353c, 0xffffffff, 0x0,
  806. 0x353c, 0xffffffff, 0x0,
  807. 0x353c, 0xffffffff, 0x0,
  808. 0x353c, 0xffffffff, 0x0,
  809. 0x353c, 0xffffffff, 0x171f1e,
  810. 0x3538, 0xffffffff, 0x700010ff,
  811. 0x353c, 0xffffffff, 0x0,
  812. 0x353c, 0xffffffff, 0x0,
  813. 0x353c, 0xffffffff, 0x0,
  814. 0x353c, 0xffffffff, 0x0,
  815. 0x353c, 0xffffffff, 0x0,
  816. 0x353c, 0xffffffff, 0x0,
  817. 0x3538, 0xffffffff, 0x9ff,
  818. 0x3500, 0xffffffff, 0x0,
  819. 0x3504, 0xffffffff, 0x10000800,
  820. 0x3504, 0xffffffff, 0xf,
  821. 0x3504, 0xffffffff, 0xf,
  822. 0x3500, 0xffffffff, 0x4,
  823. 0x3504, 0xffffffff, 0x1000051e,
  824. 0x3504, 0xffffffff, 0xffff,
  825. 0x3504, 0xffffffff, 0xffff,
  826. 0x3500, 0xffffffff, 0x8,
  827. 0x3504, 0xffffffff, 0x80500,
  828. 0x3500, 0xffffffff, 0x12,
  829. 0x3504, 0xffffffff, 0x9050c,
  830. 0x3500, 0xffffffff, 0x1d,
  831. 0x3504, 0xffffffff, 0xb052c,
  832. 0x3500, 0xffffffff, 0x2a,
  833. 0x3504, 0xffffffff, 0x1053e,
  834. 0x3500, 0xffffffff, 0x2d,
  835. 0x3504, 0xffffffff, 0x10546,
  836. 0x3500, 0xffffffff, 0x30,
  837. 0x3504, 0xffffffff, 0xa054e,
  838. 0x3500, 0xffffffff, 0x3c,
  839. 0x3504, 0xffffffff, 0x1055f,
  840. 0x3500, 0xffffffff, 0x3f,
  841. 0x3504, 0xffffffff, 0x10567,
  842. 0x3500, 0xffffffff, 0x42,
  843. 0x3504, 0xffffffff, 0x1056f,
  844. 0x3500, 0xffffffff, 0x45,
  845. 0x3504, 0xffffffff, 0x10572,
  846. 0x3500, 0xffffffff, 0x48,
  847. 0x3504, 0xffffffff, 0x20575,
  848. 0x3500, 0xffffffff, 0x4c,
  849. 0x3504, 0xffffffff, 0x190801,
  850. 0x3500, 0xffffffff, 0x67,
  851. 0x3504, 0xffffffff, 0x1082a,
  852. 0x3500, 0xffffffff, 0x6a,
  853. 0x3504, 0xffffffff, 0x1b082d,
  854. 0x3500, 0xffffffff, 0x87,
  855. 0x3504, 0xffffffff, 0x310851,
  856. 0x3500, 0xffffffff, 0xba,
  857. 0x3504, 0xffffffff, 0x891,
  858. 0x3500, 0xffffffff, 0xbc,
  859. 0x3504, 0xffffffff, 0x893,
  860. 0x3500, 0xffffffff, 0xbe,
  861. 0x3504, 0xffffffff, 0x20895,
  862. 0x3500, 0xffffffff, 0xc2,
  863. 0x3504, 0xffffffff, 0x20899,
  864. 0x3500, 0xffffffff, 0xc6,
  865. 0x3504, 0xffffffff, 0x2089d,
  866. 0x3500, 0xffffffff, 0xca,
  867. 0x3504, 0xffffffff, 0x8a1,
  868. 0x3500, 0xffffffff, 0xcc,
  869. 0x3504, 0xffffffff, 0x8a3,
  870. 0x3500, 0xffffffff, 0xce,
  871. 0x3504, 0xffffffff, 0x308a5,
  872. 0x3500, 0xffffffff, 0xd3,
  873. 0x3504, 0xffffffff, 0x6d08cd,
  874. 0x3500, 0xffffffff, 0x142,
  875. 0x3504, 0xffffffff, 0x2000095a,
  876. 0x3504, 0xffffffff, 0x1,
  877. 0x3500, 0xffffffff, 0x144,
  878. 0x3504, 0xffffffff, 0x301f095b,
  879. 0x3500, 0xffffffff, 0x165,
  880. 0x3504, 0xffffffff, 0xc094d,
  881. 0x3500, 0xffffffff, 0x173,
  882. 0x3504, 0xffffffff, 0xf096d,
  883. 0x3500, 0xffffffff, 0x184,
  884. 0x3504, 0xffffffff, 0x15097f,
  885. 0x3500, 0xffffffff, 0x19b,
  886. 0x3504, 0xffffffff, 0xc0998,
  887. 0x3500, 0xffffffff, 0x1a9,
  888. 0x3504, 0xffffffff, 0x409a7,
  889. 0x3500, 0xffffffff, 0x1af,
  890. 0x3504, 0xffffffff, 0xcdc,
  891. 0x3500, 0xffffffff, 0x1b1,
  892. 0x3504, 0xffffffff, 0x800,
  893. 0x3508, 0xffffffff, 0x6c9b2000,
  894. 0x3510, 0xfc00, 0x2000,
  895. 0x3544, 0xffffffff, 0xfc0,
  896. 0x28d4, 0x00000100, 0x100
  897. };
  898. static void si_init_golden_registers(struct radeon_device *rdev)
  899. {
  900. switch (rdev->family) {
  901. case CHIP_TAHITI:
  902. radeon_program_register_sequence(rdev,
  903. tahiti_golden_registers,
  904. (const u32)ARRAY_SIZE(tahiti_golden_registers));
  905. radeon_program_register_sequence(rdev,
  906. tahiti_golden_rlc_registers,
  907. (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
  908. radeon_program_register_sequence(rdev,
  909. tahiti_mgcg_cgcg_init,
  910. (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
  911. radeon_program_register_sequence(rdev,
  912. tahiti_golden_registers2,
  913. (const u32)ARRAY_SIZE(tahiti_golden_registers2));
  914. break;
  915. case CHIP_PITCAIRN:
  916. radeon_program_register_sequence(rdev,
  917. pitcairn_golden_registers,
  918. (const u32)ARRAY_SIZE(pitcairn_golden_registers));
  919. radeon_program_register_sequence(rdev,
  920. pitcairn_golden_rlc_registers,
  921. (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
  922. radeon_program_register_sequence(rdev,
  923. pitcairn_mgcg_cgcg_init,
  924. (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
  925. break;
  926. case CHIP_VERDE:
  927. radeon_program_register_sequence(rdev,
  928. verde_golden_registers,
  929. (const u32)ARRAY_SIZE(verde_golden_registers));
  930. radeon_program_register_sequence(rdev,
  931. verde_golden_rlc_registers,
  932. (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
  933. radeon_program_register_sequence(rdev,
  934. verde_mgcg_cgcg_init,
  935. (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
  936. radeon_program_register_sequence(rdev,
  937. verde_pg_init,
  938. (const u32)ARRAY_SIZE(verde_pg_init));
  939. break;
  940. case CHIP_OLAND:
  941. radeon_program_register_sequence(rdev,
  942. oland_golden_registers,
  943. (const u32)ARRAY_SIZE(oland_golden_registers));
  944. radeon_program_register_sequence(rdev,
  945. oland_golden_rlc_registers,
  946. (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
  947. radeon_program_register_sequence(rdev,
  948. oland_mgcg_cgcg_init,
  949. (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
  950. break;
  951. case CHIP_HAINAN:
  952. radeon_program_register_sequence(rdev,
  953. hainan_golden_registers,
  954. (const u32)ARRAY_SIZE(hainan_golden_registers));
  955. radeon_program_register_sequence(rdev,
  956. hainan_golden_registers2,
  957. (const u32)ARRAY_SIZE(hainan_golden_registers2));
  958. radeon_program_register_sequence(rdev,
  959. hainan_mgcg_cgcg_init,
  960. (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
  961. break;
  962. default:
  963. break;
  964. }
  965. }
  966. #define PCIE_BUS_CLK 10000
  967. #define TCLK (PCIE_BUS_CLK / 10)
  968. /**
  969. * si_get_xclk - get the xclk
  970. *
  971. * @rdev: radeon_device pointer
  972. *
  973. * Returns the reference clock used by the gfx engine
  974. * (SI).
  975. */
  976. u32 si_get_xclk(struct radeon_device *rdev)
  977. {
  978. u32 reference_clock = rdev->clock.spll.reference_freq;
  979. u32 tmp;
  980. tmp = RREG32(CG_CLKPIN_CNTL_2);
  981. if (tmp & MUX_TCLK_TO_XCLK)
  982. return TCLK;
  983. tmp = RREG32(CG_CLKPIN_CNTL);
  984. if (tmp & XTALIN_DIVIDE)
  985. return reference_clock / 4;
  986. return reference_clock;
  987. }
  988. /* get temperature in millidegrees */
  989. int si_get_temp(struct radeon_device *rdev)
  990. {
  991. u32 temp;
  992. int actual_temp = 0;
  993. temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
  994. CTF_TEMP_SHIFT;
  995. if (temp & 0x200)
  996. actual_temp = 255;
  997. else
  998. actual_temp = temp & 0x1ff;
  999. actual_temp = (actual_temp * 1000);
  1000. return actual_temp;
  1001. }
  1002. #define TAHITI_IO_MC_REGS_SIZE 36
  1003. static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1004. {0x0000006f, 0x03044000},
  1005. {0x00000070, 0x0480c018},
  1006. {0x00000071, 0x00000040},
  1007. {0x00000072, 0x01000000},
  1008. {0x00000074, 0x000000ff},
  1009. {0x00000075, 0x00143400},
  1010. {0x00000076, 0x08ec0800},
  1011. {0x00000077, 0x040000cc},
  1012. {0x00000079, 0x00000000},
  1013. {0x0000007a, 0x21000409},
  1014. {0x0000007c, 0x00000000},
  1015. {0x0000007d, 0xe8000000},
  1016. {0x0000007e, 0x044408a8},
  1017. {0x0000007f, 0x00000003},
  1018. {0x00000080, 0x00000000},
  1019. {0x00000081, 0x01000000},
  1020. {0x00000082, 0x02000000},
  1021. {0x00000083, 0x00000000},
  1022. {0x00000084, 0xe3f3e4f4},
  1023. {0x00000085, 0x00052024},
  1024. {0x00000087, 0x00000000},
  1025. {0x00000088, 0x66036603},
  1026. {0x00000089, 0x01000000},
  1027. {0x0000008b, 0x1c0a0000},
  1028. {0x0000008c, 0xff010000},
  1029. {0x0000008e, 0xffffefff},
  1030. {0x0000008f, 0xfff3efff},
  1031. {0x00000090, 0xfff3efbf},
  1032. {0x00000094, 0x00101101},
  1033. {0x00000095, 0x00000fff},
  1034. {0x00000096, 0x00116fff},
  1035. {0x00000097, 0x60010000},
  1036. {0x00000098, 0x10010000},
  1037. {0x00000099, 0x00006000},
  1038. {0x0000009a, 0x00001000},
  1039. {0x0000009f, 0x00a77400}
  1040. };
  1041. static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1042. {0x0000006f, 0x03044000},
  1043. {0x00000070, 0x0480c018},
  1044. {0x00000071, 0x00000040},
  1045. {0x00000072, 0x01000000},
  1046. {0x00000074, 0x000000ff},
  1047. {0x00000075, 0x00143400},
  1048. {0x00000076, 0x08ec0800},
  1049. {0x00000077, 0x040000cc},
  1050. {0x00000079, 0x00000000},
  1051. {0x0000007a, 0x21000409},
  1052. {0x0000007c, 0x00000000},
  1053. {0x0000007d, 0xe8000000},
  1054. {0x0000007e, 0x044408a8},
  1055. {0x0000007f, 0x00000003},
  1056. {0x00000080, 0x00000000},
  1057. {0x00000081, 0x01000000},
  1058. {0x00000082, 0x02000000},
  1059. {0x00000083, 0x00000000},
  1060. {0x00000084, 0xe3f3e4f4},
  1061. {0x00000085, 0x00052024},
  1062. {0x00000087, 0x00000000},
  1063. {0x00000088, 0x66036603},
  1064. {0x00000089, 0x01000000},
  1065. {0x0000008b, 0x1c0a0000},
  1066. {0x0000008c, 0xff010000},
  1067. {0x0000008e, 0xffffefff},
  1068. {0x0000008f, 0xfff3efff},
  1069. {0x00000090, 0xfff3efbf},
  1070. {0x00000094, 0x00101101},
  1071. {0x00000095, 0x00000fff},
  1072. {0x00000096, 0x00116fff},
  1073. {0x00000097, 0x60010000},
  1074. {0x00000098, 0x10010000},
  1075. {0x00000099, 0x00006000},
  1076. {0x0000009a, 0x00001000},
  1077. {0x0000009f, 0x00a47400}
  1078. };
  1079. static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1080. {0x0000006f, 0x03044000},
  1081. {0x00000070, 0x0480c018},
  1082. {0x00000071, 0x00000040},
  1083. {0x00000072, 0x01000000},
  1084. {0x00000074, 0x000000ff},
  1085. {0x00000075, 0x00143400},
  1086. {0x00000076, 0x08ec0800},
  1087. {0x00000077, 0x040000cc},
  1088. {0x00000079, 0x00000000},
  1089. {0x0000007a, 0x21000409},
  1090. {0x0000007c, 0x00000000},
  1091. {0x0000007d, 0xe8000000},
  1092. {0x0000007e, 0x044408a8},
  1093. {0x0000007f, 0x00000003},
  1094. {0x00000080, 0x00000000},
  1095. {0x00000081, 0x01000000},
  1096. {0x00000082, 0x02000000},
  1097. {0x00000083, 0x00000000},
  1098. {0x00000084, 0xe3f3e4f4},
  1099. {0x00000085, 0x00052024},
  1100. {0x00000087, 0x00000000},
  1101. {0x00000088, 0x66036603},
  1102. {0x00000089, 0x01000000},
  1103. {0x0000008b, 0x1c0a0000},
  1104. {0x0000008c, 0xff010000},
  1105. {0x0000008e, 0xffffefff},
  1106. {0x0000008f, 0xfff3efff},
  1107. {0x00000090, 0xfff3efbf},
  1108. {0x00000094, 0x00101101},
  1109. {0x00000095, 0x00000fff},
  1110. {0x00000096, 0x00116fff},
  1111. {0x00000097, 0x60010000},
  1112. {0x00000098, 0x10010000},
  1113. {0x00000099, 0x00006000},
  1114. {0x0000009a, 0x00001000},
  1115. {0x0000009f, 0x00a37400}
  1116. };
  1117. static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1118. {0x0000006f, 0x03044000},
  1119. {0x00000070, 0x0480c018},
  1120. {0x00000071, 0x00000040},
  1121. {0x00000072, 0x01000000},
  1122. {0x00000074, 0x000000ff},
  1123. {0x00000075, 0x00143400},
  1124. {0x00000076, 0x08ec0800},
  1125. {0x00000077, 0x040000cc},
  1126. {0x00000079, 0x00000000},
  1127. {0x0000007a, 0x21000409},
  1128. {0x0000007c, 0x00000000},
  1129. {0x0000007d, 0xe8000000},
  1130. {0x0000007e, 0x044408a8},
  1131. {0x0000007f, 0x00000003},
  1132. {0x00000080, 0x00000000},
  1133. {0x00000081, 0x01000000},
  1134. {0x00000082, 0x02000000},
  1135. {0x00000083, 0x00000000},
  1136. {0x00000084, 0xe3f3e4f4},
  1137. {0x00000085, 0x00052024},
  1138. {0x00000087, 0x00000000},
  1139. {0x00000088, 0x66036603},
  1140. {0x00000089, 0x01000000},
  1141. {0x0000008b, 0x1c0a0000},
  1142. {0x0000008c, 0xff010000},
  1143. {0x0000008e, 0xffffefff},
  1144. {0x0000008f, 0xfff3efff},
  1145. {0x00000090, 0xfff3efbf},
  1146. {0x00000094, 0x00101101},
  1147. {0x00000095, 0x00000fff},
  1148. {0x00000096, 0x00116fff},
  1149. {0x00000097, 0x60010000},
  1150. {0x00000098, 0x10010000},
  1151. {0x00000099, 0x00006000},
  1152. {0x0000009a, 0x00001000},
  1153. {0x0000009f, 0x00a17730}
  1154. };
  1155. static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  1156. {0x0000006f, 0x03044000},
  1157. {0x00000070, 0x0480c018},
  1158. {0x00000071, 0x00000040},
  1159. {0x00000072, 0x01000000},
  1160. {0x00000074, 0x000000ff},
  1161. {0x00000075, 0x00143400},
  1162. {0x00000076, 0x08ec0800},
  1163. {0x00000077, 0x040000cc},
  1164. {0x00000079, 0x00000000},
  1165. {0x0000007a, 0x21000409},
  1166. {0x0000007c, 0x00000000},
  1167. {0x0000007d, 0xe8000000},
  1168. {0x0000007e, 0x044408a8},
  1169. {0x0000007f, 0x00000003},
  1170. {0x00000080, 0x00000000},
  1171. {0x00000081, 0x01000000},
  1172. {0x00000082, 0x02000000},
  1173. {0x00000083, 0x00000000},
  1174. {0x00000084, 0xe3f3e4f4},
  1175. {0x00000085, 0x00052024},
  1176. {0x00000087, 0x00000000},
  1177. {0x00000088, 0x66036603},
  1178. {0x00000089, 0x01000000},
  1179. {0x0000008b, 0x1c0a0000},
  1180. {0x0000008c, 0xff010000},
  1181. {0x0000008e, 0xffffefff},
  1182. {0x0000008f, 0xfff3efff},
  1183. {0x00000090, 0xfff3efbf},
  1184. {0x00000094, 0x00101101},
  1185. {0x00000095, 0x00000fff},
  1186. {0x00000096, 0x00116fff},
  1187. {0x00000097, 0x60010000},
  1188. {0x00000098, 0x10010000},
  1189. {0x00000099, 0x00006000},
  1190. {0x0000009a, 0x00001000},
  1191. {0x0000009f, 0x00a07730}
  1192. };
  1193. /* ucode loading */
  1194. static int si_mc_load_microcode(struct radeon_device *rdev)
  1195. {
  1196. const __be32 *fw_data;
  1197. u32 running, blackout = 0;
  1198. u32 *io_mc_regs;
  1199. int i, ucode_size, regs_size;
  1200. if (!rdev->mc_fw)
  1201. return -EINVAL;
  1202. switch (rdev->family) {
  1203. case CHIP_TAHITI:
  1204. io_mc_regs = (u32 *)&tahiti_io_mc_regs;
  1205. ucode_size = SI_MC_UCODE_SIZE;
  1206. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1207. break;
  1208. case CHIP_PITCAIRN:
  1209. io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
  1210. ucode_size = SI_MC_UCODE_SIZE;
  1211. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1212. break;
  1213. case CHIP_VERDE:
  1214. default:
  1215. io_mc_regs = (u32 *)&verde_io_mc_regs;
  1216. ucode_size = SI_MC_UCODE_SIZE;
  1217. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1218. break;
  1219. case CHIP_OLAND:
  1220. io_mc_regs = (u32 *)&oland_io_mc_regs;
  1221. ucode_size = OLAND_MC_UCODE_SIZE;
  1222. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1223. break;
  1224. case CHIP_HAINAN:
  1225. io_mc_regs = (u32 *)&hainan_io_mc_regs;
  1226. ucode_size = OLAND_MC_UCODE_SIZE;
  1227. regs_size = TAHITI_IO_MC_REGS_SIZE;
  1228. break;
  1229. }
  1230. running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
  1231. if (running == 0) {
  1232. if (running) {
  1233. blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
  1234. WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
  1235. }
  1236. /* reset the engine and set to writable */
  1237. WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
  1238. WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
  1239. /* load mc io regs */
  1240. for (i = 0; i < regs_size; i++) {
  1241. WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
  1242. WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
  1243. }
  1244. /* load the MC ucode */
  1245. fw_data = (const __be32 *)rdev->mc_fw->data;
  1246. for (i = 0; i < ucode_size; i++)
  1247. WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
  1248. /* put the engine back into the active state */
  1249. WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
  1250. WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
  1251. WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
  1252. /* wait for training to complete */
  1253. for (i = 0; i < rdev->usec_timeout; i++) {
  1254. if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
  1255. break;
  1256. udelay(1);
  1257. }
  1258. for (i = 0; i < rdev->usec_timeout; i++) {
  1259. if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
  1260. break;
  1261. udelay(1);
  1262. }
  1263. if (running)
  1264. WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
  1265. }
  1266. return 0;
  1267. }
  1268. static int si_init_microcode(struct radeon_device *rdev)
  1269. {
  1270. struct platform_device *pdev;
  1271. const char *chip_name;
  1272. const char *rlc_chip_name;
  1273. size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
  1274. char fw_name[30];
  1275. int err;
  1276. DRM_DEBUG("\n");
  1277. pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
  1278. err = IS_ERR(pdev);
  1279. if (err) {
  1280. printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
  1281. return -EINVAL;
  1282. }
  1283. switch (rdev->family) {
  1284. case CHIP_TAHITI:
  1285. chip_name = "TAHITI";
  1286. rlc_chip_name = "TAHITI";
  1287. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1288. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1289. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1290. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1291. mc_req_size = SI_MC_UCODE_SIZE * 4;
  1292. break;
  1293. case CHIP_PITCAIRN:
  1294. chip_name = "PITCAIRN";
  1295. rlc_chip_name = "PITCAIRN";
  1296. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1297. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1298. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1299. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1300. mc_req_size = SI_MC_UCODE_SIZE * 4;
  1301. break;
  1302. case CHIP_VERDE:
  1303. chip_name = "VERDE";
  1304. rlc_chip_name = "VERDE";
  1305. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1306. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1307. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1308. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1309. mc_req_size = SI_MC_UCODE_SIZE * 4;
  1310. break;
  1311. case CHIP_OLAND:
  1312. chip_name = "OLAND";
  1313. rlc_chip_name = "OLAND";
  1314. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1315. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1316. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1317. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1318. mc_req_size = OLAND_MC_UCODE_SIZE * 4;
  1319. break;
  1320. case CHIP_HAINAN:
  1321. chip_name = "HAINAN";
  1322. rlc_chip_name = "HAINAN";
  1323. pfp_req_size = SI_PFP_UCODE_SIZE * 4;
  1324. me_req_size = SI_PM4_UCODE_SIZE * 4;
  1325. ce_req_size = SI_CE_UCODE_SIZE * 4;
  1326. rlc_req_size = SI_RLC_UCODE_SIZE * 4;
  1327. mc_req_size = OLAND_MC_UCODE_SIZE * 4;
  1328. break;
  1329. default: BUG();
  1330. }
  1331. DRM_INFO("Loading %s Microcode\n", chip_name);
  1332. snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
  1333. err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
  1334. if (err)
  1335. goto out;
  1336. if (rdev->pfp_fw->size != pfp_req_size) {
  1337. printk(KERN_ERR
  1338. "si_cp: Bogus length %zu in firmware \"%s\"\n",
  1339. rdev->pfp_fw->size, fw_name);
  1340. err = -EINVAL;
  1341. goto out;
  1342. }
  1343. snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
  1344. err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
  1345. if (err)
  1346. goto out;
  1347. if (rdev->me_fw->size != me_req_size) {
  1348. printk(KERN_ERR
  1349. "si_cp: Bogus length %zu in firmware \"%s\"\n",
  1350. rdev->me_fw->size, fw_name);
  1351. err = -EINVAL;
  1352. }
  1353. snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
  1354. err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
  1355. if (err)
  1356. goto out;
  1357. if (rdev->ce_fw->size != ce_req_size) {
  1358. printk(KERN_ERR
  1359. "si_cp: Bogus length %zu in firmware \"%s\"\n",
  1360. rdev->ce_fw->size, fw_name);
  1361. err = -EINVAL;
  1362. }
  1363. snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
  1364. err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
  1365. if (err)
  1366. goto out;
  1367. if (rdev->rlc_fw->size != rlc_req_size) {
  1368. printk(KERN_ERR
  1369. "si_rlc: Bogus length %zu in firmware \"%s\"\n",
  1370. rdev->rlc_fw->size, fw_name);
  1371. err = -EINVAL;
  1372. }
  1373. snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
  1374. err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
  1375. if (err)
  1376. goto out;
  1377. if (rdev->mc_fw->size != mc_req_size) {
  1378. printk(KERN_ERR
  1379. "si_mc: Bogus length %zu in firmware \"%s\"\n",
  1380. rdev->mc_fw->size, fw_name);
  1381. err = -EINVAL;
  1382. }
  1383. out:
  1384. platform_device_unregister(pdev);
  1385. if (err) {
  1386. if (err != -EINVAL)
  1387. printk(KERN_ERR
  1388. "si_cp: Failed to load firmware \"%s\"\n",
  1389. fw_name);
  1390. release_firmware(rdev->pfp_fw);
  1391. rdev->pfp_fw = NULL;
  1392. release_firmware(rdev->me_fw);
  1393. rdev->me_fw = NULL;
  1394. release_firmware(rdev->ce_fw);
  1395. rdev->ce_fw = NULL;
  1396. release_firmware(rdev->rlc_fw);
  1397. rdev->rlc_fw = NULL;
  1398. release_firmware(rdev->mc_fw);
  1399. rdev->mc_fw = NULL;
  1400. }
  1401. return err;
  1402. }
  1403. /* watermark setup */
  1404. static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
  1405. struct radeon_crtc *radeon_crtc,
  1406. struct drm_display_mode *mode,
  1407. struct drm_display_mode *other_mode)
  1408. {
  1409. u32 tmp;
  1410. /*
  1411. * Line Buffer Setup
  1412. * There are 3 line buffers, each one shared by 2 display controllers.
  1413. * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
  1414. * the display controllers. The paritioning is done via one of four
  1415. * preset allocations specified in bits 21:20:
  1416. * 0 - half lb
  1417. * 2 - whole lb, other crtc must be disabled
  1418. */
  1419. /* this can get tricky if we have two large displays on a paired group
  1420. * of crtcs. Ideally for multiple large displays we'd assign them to
  1421. * non-linked crtcs for maximum line buffer allocation.
  1422. */
  1423. if (radeon_crtc->base.enabled && mode) {
  1424. if (other_mode)
  1425. tmp = 0; /* 1/2 */
  1426. else
  1427. tmp = 2; /* whole */
  1428. } else
  1429. tmp = 0;
  1430. WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
  1431. DC_LB_MEMORY_CONFIG(tmp));
  1432. if (radeon_crtc->base.enabled && mode) {
  1433. switch (tmp) {
  1434. case 0:
  1435. default:
  1436. return 4096 * 2;
  1437. case 2:
  1438. return 8192 * 2;
  1439. }
  1440. }
  1441. /* controller not enabled, so no lb used */
  1442. return 0;
  1443. }
  1444. static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
  1445. {
  1446. u32 tmp = RREG32(MC_SHARED_CHMAP);
  1447. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  1448. case 0:
  1449. default:
  1450. return 1;
  1451. case 1:
  1452. return 2;
  1453. case 2:
  1454. return 4;
  1455. case 3:
  1456. return 8;
  1457. case 4:
  1458. return 3;
  1459. case 5:
  1460. return 6;
  1461. case 6:
  1462. return 10;
  1463. case 7:
  1464. return 12;
  1465. case 8:
  1466. return 16;
  1467. }
  1468. }
  1469. struct dce6_wm_params {
  1470. u32 dram_channels; /* number of dram channels */
  1471. u32 yclk; /* bandwidth per dram data pin in kHz */
  1472. u32 sclk; /* engine clock in kHz */
  1473. u32 disp_clk; /* display clock in kHz */
  1474. u32 src_width; /* viewport width */
  1475. u32 active_time; /* active display time in ns */
  1476. u32 blank_time; /* blank time in ns */
  1477. bool interlaced; /* mode is interlaced */
  1478. fixed20_12 vsc; /* vertical scale ratio */
  1479. u32 num_heads; /* number of active crtcs */
  1480. u32 bytes_per_pixel; /* bytes per pixel display + overlay */
  1481. u32 lb_size; /* line buffer allocated to pipe */
  1482. u32 vtaps; /* vertical scaler taps */
  1483. };
  1484. static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
  1485. {
  1486. /* Calculate raw DRAM Bandwidth */
  1487. fixed20_12 dram_efficiency; /* 0.7 */
  1488. fixed20_12 yclk, dram_channels, bandwidth;
  1489. fixed20_12 a;
  1490. a.full = dfixed_const(1000);
  1491. yclk.full = dfixed_const(wm->yclk);
  1492. yclk.full = dfixed_div(yclk, a);
  1493. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  1494. a.full = dfixed_const(10);
  1495. dram_efficiency.full = dfixed_const(7);
  1496. dram_efficiency.full = dfixed_div(dram_efficiency, a);
  1497. bandwidth.full = dfixed_mul(dram_channels, yclk);
  1498. bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
  1499. return dfixed_trunc(bandwidth);
  1500. }
  1501. static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
  1502. {
  1503. /* Calculate DRAM Bandwidth and the part allocated to display. */
  1504. fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
  1505. fixed20_12 yclk, dram_channels, bandwidth;
  1506. fixed20_12 a;
  1507. a.full = dfixed_const(1000);
  1508. yclk.full = dfixed_const(wm->yclk);
  1509. yclk.full = dfixed_div(yclk, a);
  1510. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  1511. a.full = dfixed_const(10);
  1512. disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
  1513. disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
  1514. bandwidth.full = dfixed_mul(dram_channels, yclk);
  1515. bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
  1516. return dfixed_trunc(bandwidth);
  1517. }
  1518. static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
  1519. {
  1520. /* Calculate the display Data return Bandwidth */
  1521. fixed20_12 return_efficiency; /* 0.8 */
  1522. fixed20_12 sclk, bandwidth;
  1523. fixed20_12 a;
  1524. a.full = dfixed_const(1000);
  1525. sclk.full = dfixed_const(wm->sclk);
  1526. sclk.full = dfixed_div(sclk, a);
  1527. a.full = dfixed_const(10);
  1528. return_efficiency.full = dfixed_const(8);
  1529. return_efficiency.full = dfixed_div(return_efficiency, a);
  1530. a.full = dfixed_const(32);
  1531. bandwidth.full = dfixed_mul(a, sclk);
  1532. bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
  1533. return dfixed_trunc(bandwidth);
  1534. }
  1535. static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
  1536. {
  1537. return 32;
  1538. }
  1539. static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
  1540. {
  1541. /* Calculate the DMIF Request Bandwidth */
  1542. fixed20_12 disp_clk_request_efficiency; /* 0.8 */
  1543. fixed20_12 disp_clk, sclk, bandwidth;
  1544. fixed20_12 a, b1, b2;
  1545. u32 min_bandwidth;
  1546. a.full = dfixed_const(1000);
  1547. disp_clk.full = dfixed_const(wm->disp_clk);
  1548. disp_clk.full = dfixed_div(disp_clk, a);
  1549. a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
  1550. b1.full = dfixed_mul(a, disp_clk);
  1551. a.full = dfixed_const(1000);
  1552. sclk.full = dfixed_const(wm->sclk);
  1553. sclk.full = dfixed_div(sclk, a);
  1554. a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
  1555. b2.full = dfixed_mul(a, sclk);
  1556. a.full = dfixed_const(10);
  1557. disp_clk_request_efficiency.full = dfixed_const(8);
  1558. disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
  1559. min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
  1560. a.full = dfixed_const(min_bandwidth);
  1561. bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
  1562. return dfixed_trunc(bandwidth);
  1563. }
  1564. static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
  1565. {
  1566. /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
  1567. u32 dram_bandwidth = dce6_dram_bandwidth(wm);
  1568. u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
  1569. u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
  1570. return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
  1571. }
  1572. static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
  1573. {
  1574. /* Calculate the display mode Average Bandwidth
  1575. * DisplayMode should contain the source and destination dimensions,
  1576. * timing, etc.
  1577. */
  1578. fixed20_12 bpp;
  1579. fixed20_12 line_time;
  1580. fixed20_12 src_width;
  1581. fixed20_12 bandwidth;
  1582. fixed20_12 a;
  1583. a.full = dfixed_const(1000);
  1584. line_time.full = dfixed_const(wm->active_time + wm->blank_time);
  1585. line_time.full = dfixed_div(line_time, a);
  1586. bpp.full = dfixed_const(wm->bytes_per_pixel);
  1587. src_width.full = dfixed_const(wm->src_width);
  1588. bandwidth.full = dfixed_mul(src_width, bpp);
  1589. bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
  1590. bandwidth.full = dfixed_div(bandwidth, line_time);
  1591. return dfixed_trunc(bandwidth);
  1592. }
  1593. static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
  1594. {
  1595. /* First calcualte the latency in ns */
  1596. u32 mc_latency = 2000; /* 2000 ns. */
  1597. u32 available_bandwidth = dce6_available_bandwidth(wm);
  1598. u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
  1599. u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
  1600. u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
  1601. u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
  1602. (wm->num_heads * cursor_line_pair_return_time);
  1603. u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
  1604. u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
  1605. u32 tmp, dmif_size = 12288;
  1606. fixed20_12 a, b, c;
  1607. if (wm->num_heads == 0)
  1608. return 0;
  1609. a.full = dfixed_const(2);
  1610. b.full = dfixed_const(1);
  1611. if ((wm->vsc.full > a.full) ||
  1612. ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
  1613. (wm->vtaps >= 5) ||
  1614. ((wm->vsc.full >= a.full) && wm->interlaced))
  1615. max_src_lines_per_dst_line = 4;
  1616. else
  1617. max_src_lines_per_dst_line = 2;
  1618. a.full = dfixed_const(available_bandwidth);
  1619. b.full = dfixed_const(wm->num_heads);
  1620. a.full = dfixed_div(a, b);
  1621. b.full = dfixed_const(mc_latency + 512);
  1622. c.full = dfixed_const(wm->disp_clk);
  1623. b.full = dfixed_div(b, c);
  1624. c.full = dfixed_const(dmif_size);
  1625. b.full = dfixed_div(c, b);
  1626. tmp = min(dfixed_trunc(a), dfixed_trunc(b));
  1627. b.full = dfixed_const(1000);
  1628. c.full = dfixed_const(wm->disp_clk);
  1629. b.full = dfixed_div(c, b);
  1630. c.full = dfixed_const(wm->bytes_per_pixel);
  1631. b.full = dfixed_mul(b, c);
  1632. lb_fill_bw = min(tmp, dfixed_trunc(b));
  1633. a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
  1634. b.full = dfixed_const(1000);
  1635. c.full = dfixed_const(lb_fill_bw);
  1636. b.full = dfixed_div(c, b);
  1637. a.full = dfixed_div(a, b);
  1638. line_fill_time = dfixed_trunc(a);
  1639. if (line_fill_time < wm->active_time)
  1640. return latency;
  1641. else
  1642. return latency + (line_fill_time - wm->active_time);
  1643. }
  1644. static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
  1645. {
  1646. if (dce6_average_bandwidth(wm) <=
  1647. (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
  1648. return true;
  1649. else
  1650. return false;
  1651. };
  1652. static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
  1653. {
  1654. if (dce6_average_bandwidth(wm) <=
  1655. (dce6_available_bandwidth(wm) / wm->num_heads))
  1656. return true;
  1657. else
  1658. return false;
  1659. };
  1660. static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
  1661. {
  1662. u32 lb_partitions = wm->lb_size / wm->src_width;
  1663. u32 line_time = wm->active_time + wm->blank_time;
  1664. u32 latency_tolerant_lines;
  1665. u32 latency_hiding;
  1666. fixed20_12 a;
  1667. a.full = dfixed_const(1);
  1668. if (wm->vsc.full > a.full)
  1669. latency_tolerant_lines = 1;
  1670. else {
  1671. if (lb_partitions <= (wm->vtaps + 1))
  1672. latency_tolerant_lines = 1;
  1673. else
  1674. latency_tolerant_lines = 2;
  1675. }
  1676. latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
  1677. if (dce6_latency_watermark(wm) <= latency_hiding)
  1678. return true;
  1679. else
  1680. return false;
  1681. }
  1682. static void dce6_program_watermarks(struct radeon_device *rdev,
  1683. struct radeon_crtc *radeon_crtc,
  1684. u32 lb_size, u32 num_heads)
  1685. {
  1686. struct drm_display_mode *mode = &radeon_crtc->base.mode;
  1687. struct dce6_wm_params wm;
  1688. u32 pixel_period;
  1689. u32 line_time = 0;
  1690. u32 latency_watermark_a = 0, latency_watermark_b = 0;
  1691. u32 priority_a_mark = 0, priority_b_mark = 0;
  1692. u32 priority_a_cnt = PRIORITY_OFF;
  1693. u32 priority_b_cnt = PRIORITY_OFF;
  1694. u32 tmp, arb_control3;
  1695. fixed20_12 a, b, c;
  1696. if (radeon_crtc->base.enabled && num_heads && mode) {
  1697. pixel_period = 1000000 / (u32)mode->clock;
  1698. line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
  1699. priority_a_cnt = 0;
  1700. priority_b_cnt = 0;
  1701. wm.yclk = rdev->pm.current_mclk * 10;
  1702. wm.sclk = rdev->pm.current_sclk * 10;
  1703. wm.disp_clk = mode->clock;
  1704. wm.src_width = mode->crtc_hdisplay;
  1705. wm.active_time = mode->crtc_hdisplay * pixel_period;
  1706. wm.blank_time = line_time - wm.active_time;
  1707. wm.interlaced = false;
  1708. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1709. wm.interlaced = true;
  1710. wm.vsc = radeon_crtc->vsc;
  1711. wm.vtaps = 1;
  1712. if (radeon_crtc->rmx_type != RMX_OFF)
  1713. wm.vtaps = 2;
  1714. wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
  1715. wm.lb_size = lb_size;
  1716. if (rdev->family == CHIP_ARUBA)
  1717. wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
  1718. else
  1719. wm.dram_channels = si_get_number_of_dram_channels(rdev);
  1720. wm.num_heads = num_heads;
  1721. /* set for high clocks */
  1722. latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
  1723. /* set for low clocks */
  1724. /* wm.yclk = low clk; wm.sclk = low clk */
  1725. latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
  1726. /* possibly force display priority to high */
  1727. /* should really do this at mode validation time... */
  1728. if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
  1729. !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
  1730. !dce6_check_latency_hiding(&wm) ||
  1731. (rdev->disp_priority == 2)) {
  1732. DRM_DEBUG_KMS("force priority to high\n");
  1733. priority_a_cnt |= PRIORITY_ALWAYS_ON;
  1734. priority_b_cnt |= PRIORITY_ALWAYS_ON;
  1735. }
  1736. a.full = dfixed_const(1000);
  1737. b.full = dfixed_const(mode->clock);
  1738. b.full = dfixed_div(b, a);
  1739. c.full = dfixed_const(latency_watermark_a);
  1740. c.full = dfixed_mul(c, b);
  1741. c.full = dfixed_mul(c, radeon_crtc->hsc);
  1742. c.full = dfixed_div(c, a);
  1743. a.full = dfixed_const(16);
  1744. c.full = dfixed_div(c, a);
  1745. priority_a_mark = dfixed_trunc(c);
  1746. priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
  1747. a.full = dfixed_const(1000);
  1748. b.full = dfixed_const(mode->clock);
  1749. b.full = dfixed_div(b, a);
  1750. c.full = dfixed_const(latency_watermark_b);
  1751. c.full = dfixed_mul(c, b);
  1752. c.full = dfixed_mul(c, radeon_crtc->hsc);
  1753. c.full = dfixed_div(c, a);
  1754. a.full = dfixed_const(16);
  1755. c.full = dfixed_div(c, a);
  1756. priority_b_mark = dfixed_trunc(c);
  1757. priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
  1758. }
  1759. /* select wm A */
  1760. arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
  1761. tmp = arb_control3;
  1762. tmp &= ~LATENCY_WATERMARK_MASK(3);
  1763. tmp |= LATENCY_WATERMARK_MASK(1);
  1764. WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
  1765. WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
  1766. (LATENCY_LOW_WATERMARK(latency_watermark_a) |
  1767. LATENCY_HIGH_WATERMARK(line_time)));
  1768. /* select wm B */
  1769. tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
  1770. tmp &= ~LATENCY_WATERMARK_MASK(3);
  1771. tmp |= LATENCY_WATERMARK_MASK(2);
  1772. WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
  1773. WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
  1774. (LATENCY_LOW_WATERMARK(latency_watermark_b) |
  1775. LATENCY_HIGH_WATERMARK(line_time)));
  1776. /* restore original selection */
  1777. WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
  1778. /* write the priority marks */
  1779. WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
  1780. WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
  1781. }
  1782. void dce6_bandwidth_update(struct radeon_device *rdev)
  1783. {
  1784. struct drm_display_mode *mode0 = NULL;
  1785. struct drm_display_mode *mode1 = NULL;
  1786. u32 num_heads = 0, lb_size;
  1787. int i;
  1788. radeon_update_display_priority(rdev);
  1789. for (i = 0; i < rdev->num_crtc; i++) {
  1790. if (rdev->mode_info.crtcs[i]->base.enabled)
  1791. num_heads++;
  1792. }
  1793. for (i = 0; i < rdev->num_crtc; i += 2) {
  1794. mode0 = &rdev->mode_info.crtcs[i]->base.mode;
  1795. mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
  1796. lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
  1797. dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
  1798. lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
  1799. dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
  1800. }
  1801. }
  1802. /*
  1803. * Core functions
  1804. */
  1805. static void si_tiling_mode_table_init(struct radeon_device *rdev)
  1806. {
  1807. const u32 num_tile_mode_states = 32;
  1808. u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
  1809. switch (rdev->config.si.mem_row_size_in_kb) {
  1810. case 1:
  1811. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
  1812. break;
  1813. case 2:
  1814. default:
  1815. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
  1816. break;
  1817. case 4:
  1818. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
  1819. break;
  1820. }
  1821. if ((rdev->family == CHIP_TAHITI) ||
  1822. (rdev->family == CHIP_PITCAIRN)) {
  1823. for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  1824. switch (reg_offset) {
  1825. case 0: /* non-AA compressed depth or any compressed stencil */
  1826. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1827. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1828. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1829. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  1830. NUM_BANKS(ADDR_SURF_16_BANK) |
  1831. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1832. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1833. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1834. break;
  1835. case 1: /* 2xAA/4xAA compressed depth only */
  1836. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1837. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1838. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1839. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  1840. NUM_BANKS(ADDR_SURF_16_BANK) |
  1841. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1842. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1843. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1844. break;
  1845. case 2: /* 8xAA compressed depth only */
  1846. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1847. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1848. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1849. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  1850. NUM_BANKS(ADDR_SURF_16_BANK) |
  1851. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1852. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1853. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1854. break;
  1855. case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
  1856. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1857. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1858. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1859. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  1860. NUM_BANKS(ADDR_SURF_16_BANK) |
  1861. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1862. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1863. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1864. break;
  1865. case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
  1866. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1867. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1868. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1869. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  1870. NUM_BANKS(ADDR_SURF_16_BANK) |
  1871. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1872. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1873. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1874. break;
  1875. case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
  1876. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1877. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1878. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1879. TILE_SPLIT(split_equal_to_row_size) |
  1880. NUM_BANKS(ADDR_SURF_16_BANK) |
  1881. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1882. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1883. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1884. break;
  1885. case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
  1886. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1887. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1888. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1889. TILE_SPLIT(split_equal_to_row_size) |
  1890. NUM_BANKS(ADDR_SURF_16_BANK) |
  1891. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1892. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1893. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  1894. break;
  1895. case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
  1896. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1897. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  1898. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1899. TILE_SPLIT(split_equal_to_row_size) |
  1900. NUM_BANKS(ADDR_SURF_16_BANK) |
  1901. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1902. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1903. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1904. break;
  1905. case 8: /* 1D and 1D Array Surfaces */
  1906. gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
  1907. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1908. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1909. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  1910. NUM_BANKS(ADDR_SURF_16_BANK) |
  1911. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1912. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1913. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1914. break;
  1915. case 9: /* Displayable maps. */
  1916. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1917. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1918. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1919. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  1920. NUM_BANKS(ADDR_SURF_16_BANK) |
  1921. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1922. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1923. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1924. break;
  1925. case 10: /* Display 8bpp. */
  1926. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1927. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1928. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1929. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  1930. NUM_BANKS(ADDR_SURF_16_BANK) |
  1931. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1932. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1933. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1934. break;
  1935. case 11: /* Display 16bpp. */
  1936. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1937. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1938. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1939. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  1940. NUM_BANKS(ADDR_SURF_16_BANK) |
  1941. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1942. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1943. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1944. break;
  1945. case 12: /* Display 32bpp. */
  1946. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1947. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1948. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1949. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  1950. NUM_BANKS(ADDR_SURF_16_BANK) |
  1951. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1952. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1953. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  1954. break;
  1955. case 13: /* Thin. */
  1956. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1957. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  1958. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1959. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  1960. NUM_BANKS(ADDR_SURF_16_BANK) |
  1961. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1962. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1963. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  1964. break;
  1965. case 14: /* Thin 8 bpp. */
  1966. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1967. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  1968. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1969. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  1970. NUM_BANKS(ADDR_SURF_16_BANK) |
  1971. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1972. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1973. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  1974. break;
  1975. case 15: /* Thin 16 bpp. */
  1976. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1977. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  1978. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1979. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  1980. NUM_BANKS(ADDR_SURF_16_BANK) |
  1981. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1982. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1983. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  1984. break;
  1985. case 16: /* Thin 32 bpp. */
  1986. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1987. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  1988. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1989. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  1990. NUM_BANKS(ADDR_SURF_16_BANK) |
  1991. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1992. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1993. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  1994. break;
  1995. case 17: /* Thin 64 bpp. */
  1996. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1997. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  1998. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  1999. TILE_SPLIT(split_equal_to_row_size) |
  2000. NUM_BANKS(ADDR_SURF_16_BANK) |
  2001. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2002. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2003. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2004. break;
  2005. case 21: /* 8 bpp PRT. */
  2006. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2007. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2008. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2009. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2010. NUM_BANKS(ADDR_SURF_16_BANK) |
  2011. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  2012. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2013. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2014. break;
  2015. case 22: /* 16 bpp PRT */
  2016. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2017. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2018. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2019. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2020. NUM_BANKS(ADDR_SURF_16_BANK) |
  2021. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2022. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2023. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2024. break;
  2025. case 23: /* 32 bpp PRT */
  2026. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2027. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2028. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2029. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2030. NUM_BANKS(ADDR_SURF_16_BANK) |
  2031. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2032. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2033. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2034. break;
  2035. case 24: /* 64 bpp PRT */
  2036. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2037. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2038. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2039. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2040. NUM_BANKS(ADDR_SURF_16_BANK) |
  2041. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2042. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2043. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2044. break;
  2045. case 25: /* 128 bpp PRT */
  2046. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2047. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2048. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2049. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
  2050. NUM_BANKS(ADDR_SURF_8_BANK) |
  2051. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2052. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2053. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2054. break;
  2055. default:
  2056. gb_tile_moden = 0;
  2057. break;
  2058. }
  2059. rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
  2060. WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
  2061. }
  2062. } else if ((rdev->family == CHIP_VERDE) ||
  2063. (rdev->family == CHIP_OLAND) ||
  2064. (rdev->family == CHIP_HAINAN)) {
  2065. for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  2066. switch (reg_offset) {
  2067. case 0: /* non-AA compressed depth or any compressed stencil */
  2068. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2069. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2070. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2071. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2072. NUM_BANKS(ADDR_SURF_16_BANK) |
  2073. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2074. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2075. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2076. break;
  2077. case 1: /* 2xAA/4xAA compressed depth only */
  2078. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2079. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2080. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2081. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  2082. NUM_BANKS(ADDR_SURF_16_BANK) |
  2083. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2084. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2085. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2086. break;
  2087. case 2: /* 8xAA compressed depth only */
  2088. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2089. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2090. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2091. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2092. NUM_BANKS(ADDR_SURF_16_BANK) |
  2093. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2094. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2095. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2096. break;
  2097. case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
  2098. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2099. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2100. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2101. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  2102. NUM_BANKS(ADDR_SURF_16_BANK) |
  2103. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2104. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2105. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2106. break;
  2107. case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
  2108. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2109. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2110. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2111. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2112. NUM_BANKS(ADDR_SURF_16_BANK) |
  2113. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2114. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2115. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2116. break;
  2117. case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
  2118. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2119. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2120. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2121. TILE_SPLIT(split_equal_to_row_size) |
  2122. NUM_BANKS(ADDR_SURF_16_BANK) |
  2123. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2124. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2125. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2126. break;
  2127. case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
  2128. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2129. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2130. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2131. TILE_SPLIT(split_equal_to_row_size) |
  2132. NUM_BANKS(ADDR_SURF_16_BANK) |
  2133. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2134. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2135. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2136. break;
  2137. case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
  2138. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2139. MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
  2140. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2141. TILE_SPLIT(split_equal_to_row_size) |
  2142. NUM_BANKS(ADDR_SURF_16_BANK) |
  2143. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2144. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2145. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2146. break;
  2147. case 8: /* 1D and 1D Array Surfaces */
  2148. gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
  2149. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2150. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2151. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2152. NUM_BANKS(ADDR_SURF_16_BANK) |
  2153. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2154. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2155. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2156. break;
  2157. case 9: /* Displayable maps. */
  2158. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2159. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2160. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2161. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2162. NUM_BANKS(ADDR_SURF_16_BANK) |
  2163. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2164. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2165. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2166. break;
  2167. case 10: /* Display 8bpp. */
  2168. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2169. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2170. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2171. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2172. NUM_BANKS(ADDR_SURF_16_BANK) |
  2173. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2174. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2175. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2176. break;
  2177. case 11: /* Display 16bpp. */
  2178. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2179. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2180. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2181. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2182. NUM_BANKS(ADDR_SURF_16_BANK) |
  2183. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2184. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2185. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2186. break;
  2187. case 12: /* Display 32bpp. */
  2188. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2189. MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
  2190. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2191. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2192. NUM_BANKS(ADDR_SURF_16_BANK) |
  2193. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2194. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2195. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2196. break;
  2197. case 13: /* Thin. */
  2198. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  2199. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2200. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2201. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  2202. NUM_BANKS(ADDR_SURF_16_BANK) |
  2203. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2204. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2205. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2206. break;
  2207. case 14: /* Thin 8 bpp. */
  2208. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2209. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2210. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2211. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2212. NUM_BANKS(ADDR_SURF_16_BANK) |
  2213. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2214. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2215. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2216. break;
  2217. case 15: /* Thin 16 bpp. */
  2218. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2219. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2220. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2221. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2222. NUM_BANKS(ADDR_SURF_16_BANK) |
  2223. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2224. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2225. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2226. break;
  2227. case 16: /* Thin 32 bpp. */
  2228. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2229. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2230. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2231. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2232. NUM_BANKS(ADDR_SURF_16_BANK) |
  2233. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2234. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2235. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2236. break;
  2237. case 17: /* Thin 64 bpp. */
  2238. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2239. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2240. PIPE_CONFIG(ADDR_SURF_P4_8x16) |
  2241. TILE_SPLIT(split_equal_to_row_size) |
  2242. NUM_BANKS(ADDR_SURF_16_BANK) |
  2243. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2244. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2245. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2246. break;
  2247. case 21: /* 8 bpp PRT. */
  2248. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2249. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2250. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2251. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2252. NUM_BANKS(ADDR_SURF_16_BANK) |
  2253. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  2254. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2255. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2256. break;
  2257. case 22: /* 16 bpp PRT */
  2258. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2259. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2260. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2261. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2262. NUM_BANKS(ADDR_SURF_16_BANK) |
  2263. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2264. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  2265. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
  2266. break;
  2267. case 23: /* 32 bpp PRT */
  2268. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2269. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2270. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2271. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  2272. NUM_BANKS(ADDR_SURF_16_BANK) |
  2273. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2274. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  2275. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2276. break;
  2277. case 24: /* 64 bpp PRT */
  2278. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2279. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2280. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2281. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  2282. NUM_BANKS(ADDR_SURF_16_BANK) |
  2283. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2284. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2285. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
  2286. break;
  2287. case 25: /* 128 bpp PRT */
  2288. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  2289. MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
  2290. PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
  2291. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
  2292. NUM_BANKS(ADDR_SURF_8_BANK) |
  2293. BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  2294. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  2295. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
  2296. break;
  2297. default:
  2298. gb_tile_moden = 0;
  2299. break;
  2300. }
  2301. rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
  2302. WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
  2303. }
  2304. } else
  2305. DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
  2306. }
  2307. static void si_select_se_sh(struct radeon_device *rdev,
  2308. u32 se_num, u32 sh_num)
  2309. {
  2310. u32 data = INSTANCE_BROADCAST_WRITES;
  2311. if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
  2312. data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
  2313. else if (se_num == 0xffffffff)
  2314. data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
  2315. else if (sh_num == 0xffffffff)
  2316. data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
  2317. else
  2318. data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
  2319. WREG32(GRBM_GFX_INDEX, data);
  2320. }
  2321. static u32 si_create_bitmask(u32 bit_width)
  2322. {
  2323. u32 i, mask = 0;
  2324. for (i = 0; i < bit_width; i++) {
  2325. mask <<= 1;
  2326. mask |= 1;
  2327. }
  2328. return mask;
  2329. }
  2330. static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
  2331. {
  2332. u32 data, mask;
  2333. data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
  2334. if (data & 1)
  2335. data &= INACTIVE_CUS_MASK;
  2336. else
  2337. data = 0;
  2338. data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
  2339. data >>= INACTIVE_CUS_SHIFT;
  2340. mask = si_create_bitmask(cu_per_sh);
  2341. return ~data & mask;
  2342. }
  2343. static void si_setup_spi(struct radeon_device *rdev,
  2344. u32 se_num, u32 sh_per_se,
  2345. u32 cu_per_sh)
  2346. {
  2347. int i, j, k;
  2348. u32 data, mask, active_cu;
  2349. for (i = 0; i < se_num; i++) {
  2350. for (j = 0; j < sh_per_se; j++) {
  2351. si_select_se_sh(rdev, i, j);
  2352. data = RREG32(SPI_STATIC_THREAD_MGMT_3);
  2353. active_cu = si_get_cu_enabled(rdev, cu_per_sh);
  2354. mask = 1;
  2355. for (k = 0; k < 16; k++) {
  2356. mask <<= k;
  2357. if (active_cu & mask) {
  2358. data &= ~mask;
  2359. WREG32(SPI_STATIC_THREAD_MGMT_3, data);
  2360. break;
  2361. }
  2362. }
  2363. }
  2364. }
  2365. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  2366. }
  2367. static u32 si_get_rb_disabled(struct radeon_device *rdev,
  2368. u32 max_rb_num, u32 se_num,
  2369. u32 sh_per_se)
  2370. {
  2371. u32 data, mask;
  2372. data = RREG32(CC_RB_BACKEND_DISABLE);
  2373. if (data & 1)
  2374. data &= BACKEND_DISABLE_MASK;
  2375. else
  2376. data = 0;
  2377. data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
  2378. data >>= BACKEND_DISABLE_SHIFT;
  2379. mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
  2380. return data & mask;
  2381. }
  2382. static void si_setup_rb(struct radeon_device *rdev,
  2383. u32 se_num, u32 sh_per_se,
  2384. u32 max_rb_num)
  2385. {
  2386. int i, j;
  2387. u32 data, mask;
  2388. u32 disabled_rbs = 0;
  2389. u32 enabled_rbs = 0;
  2390. for (i = 0; i < se_num; i++) {
  2391. for (j = 0; j < sh_per_se; j++) {
  2392. si_select_se_sh(rdev, i, j);
  2393. data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
  2394. disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
  2395. }
  2396. }
  2397. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  2398. mask = 1;
  2399. for (i = 0; i < max_rb_num; i++) {
  2400. if (!(disabled_rbs & mask))
  2401. enabled_rbs |= mask;
  2402. mask <<= 1;
  2403. }
  2404. for (i = 0; i < se_num; i++) {
  2405. si_select_se_sh(rdev, i, 0xffffffff);
  2406. data = 0;
  2407. for (j = 0; j < sh_per_se; j++) {
  2408. switch (enabled_rbs & 3) {
  2409. case 1:
  2410. data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
  2411. break;
  2412. case 2:
  2413. data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
  2414. break;
  2415. case 3:
  2416. default:
  2417. data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
  2418. break;
  2419. }
  2420. enabled_rbs >>= 2;
  2421. }
  2422. WREG32(PA_SC_RASTER_CONFIG, data);
  2423. }
  2424. si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
  2425. }
  2426. static void si_gpu_init(struct radeon_device *rdev)
  2427. {
  2428. u32 gb_addr_config = 0;
  2429. u32 mc_shared_chmap, mc_arb_ramcfg;
  2430. u32 sx_debug_1;
  2431. u32 hdp_host_path_cntl;
  2432. u32 tmp;
  2433. int i, j;
  2434. switch (rdev->family) {
  2435. case CHIP_TAHITI:
  2436. rdev->config.si.max_shader_engines = 2;
  2437. rdev->config.si.max_tile_pipes = 12;
  2438. rdev->config.si.max_cu_per_sh = 8;
  2439. rdev->config.si.max_sh_per_se = 2;
  2440. rdev->config.si.max_backends_per_se = 4;
  2441. rdev->config.si.max_texture_channel_caches = 12;
  2442. rdev->config.si.max_gprs = 256;
  2443. rdev->config.si.max_gs_threads = 32;
  2444. rdev->config.si.max_hw_contexts = 8;
  2445. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2446. rdev->config.si.sc_prim_fifo_size_backend = 0x100;
  2447. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2448. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2449. gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
  2450. break;
  2451. case CHIP_PITCAIRN:
  2452. rdev->config.si.max_shader_engines = 2;
  2453. rdev->config.si.max_tile_pipes = 8;
  2454. rdev->config.si.max_cu_per_sh = 5;
  2455. rdev->config.si.max_sh_per_se = 2;
  2456. rdev->config.si.max_backends_per_se = 4;
  2457. rdev->config.si.max_texture_channel_caches = 8;
  2458. rdev->config.si.max_gprs = 256;
  2459. rdev->config.si.max_gs_threads = 32;
  2460. rdev->config.si.max_hw_contexts = 8;
  2461. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2462. rdev->config.si.sc_prim_fifo_size_backend = 0x100;
  2463. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2464. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2465. gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
  2466. break;
  2467. case CHIP_VERDE:
  2468. default:
  2469. rdev->config.si.max_shader_engines = 1;
  2470. rdev->config.si.max_tile_pipes = 4;
  2471. rdev->config.si.max_cu_per_sh = 2;
  2472. rdev->config.si.max_sh_per_se = 2;
  2473. rdev->config.si.max_backends_per_se = 4;
  2474. rdev->config.si.max_texture_channel_caches = 4;
  2475. rdev->config.si.max_gprs = 256;
  2476. rdev->config.si.max_gs_threads = 32;
  2477. rdev->config.si.max_hw_contexts = 8;
  2478. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2479. rdev->config.si.sc_prim_fifo_size_backend = 0x40;
  2480. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2481. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2482. gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
  2483. break;
  2484. case CHIP_OLAND:
  2485. rdev->config.si.max_shader_engines = 1;
  2486. rdev->config.si.max_tile_pipes = 4;
  2487. rdev->config.si.max_cu_per_sh = 6;
  2488. rdev->config.si.max_sh_per_se = 1;
  2489. rdev->config.si.max_backends_per_se = 2;
  2490. rdev->config.si.max_texture_channel_caches = 4;
  2491. rdev->config.si.max_gprs = 256;
  2492. rdev->config.si.max_gs_threads = 16;
  2493. rdev->config.si.max_hw_contexts = 8;
  2494. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2495. rdev->config.si.sc_prim_fifo_size_backend = 0x40;
  2496. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2497. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2498. gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
  2499. break;
  2500. case CHIP_HAINAN:
  2501. rdev->config.si.max_shader_engines = 1;
  2502. rdev->config.si.max_tile_pipes = 4;
  2503. rdev->config.si.max_cu_per_sh = 5;
  2504. rdev->config.si.max_sh_per_se = 1;
  2505. rdev->config.si.max_backends_per_se = 1;
  2506. rdev->config.si.max_texture_channel_caches = 2;
  2507. rdev->config.si.max_gprs = 256;
  2508. rdev->config.si.max_gs_threads = 16;
  2509. rdev->config.si.max_hw_contexts = 8;
  2510. rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
  2511. rdev->config.si.sc_prim_fifo_size_backend = 0x40;
  2512. rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
  2513. rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
  2514. gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
  2515. break;
  2516. }
  2517. /* Initialize HDP */
  2518. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  2519. WREG32((0x2c14 + j), 0x00000000);
  2520. WREG32((0x2c18 + j), 0x00000000);
  2521. WREG32((0x2c1c + j), 0x00000000);
  2522. WREG32((0x2c20 + j), 0x00000000);
  2523. WREG32((0x2c24 + j), 0x00000000);
  2524. }
  2525. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  2526. evergreen_fix_pci_max_read_req_size(rdev);
  2527. WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
  2528. mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
  2529. mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
  2530. rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
  2531. rdev->config.si.mem_max_burst_length_bytes = 256;
  2532. tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
  2533. rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
  2534. if (rdev->config.si.mem_row_size_in_kb > 4)
  2535. rdev->config.si.mem_row_size_in_kb = 4;
  2536. /* XXX use MC settings? */
  2537. rdev->config.si.shader_engine_tile_size = 32;
  2538. rdev->config.si.num_gpus = 1;
  2539. rdev->config.si.multi_gpu_tile_size = 64;
  2540. /* fix up row size */
  2541. gb_addr_config &= ~ROW_SIZE_MASK;
  2542. switch (rdev->config.si.mem_row_size_in_kb) {
  2543. case 1:
  2544. default:
  2545. gb_addr_config |= ROW_SIZE(0);
  2546. break;
  2547. case 2:
  2548. gb_addr_config |= ROW_SIZE(1);
  2549. break;
  2550. case 4:
  2551. gb_addr_config |= ROW_SIZE(2);
  2552. break;
  2553. }
  2554. /* setup tiling info dword. gb_addr_config is not adequate since it does
  2555. * not have bank info, so create a custom tiling dword.
  2556. * bits 3:0 num_pipes
  2557. * bits 7:4 num_banks
  2558. * bits 11:8 group_size
  2559. * bits 15:12 row_size
  2560. */
  2561. rdev->config.si.tile_config = 0;
  2562. switch (rdev->config.si.num_tile_pipes) {
  2563. case 1:
  2564. rdev->config.si.tile_config |= (0 << 0);
  2565. break;
  2566. case 2:
  2567. rdev->config.si.tile_config |= (1 << 0);
  2568. break;
  2569. case 4:
  2570. rdev->config.si.tile_config |= (2 << 0);
  2571. break;
  2572. case 8:
  2573. default:
  2574. /* XXX what about 12? */
  2575. rdev->config.si.tile_config |= (3 << 0);
  2576. break;
  2577. }
  2578. switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
  2579. case 0: /* four banks */
  2580. rdev->config.si.tile_config |= 0 << 4;
  2581. break;
  2582. case 1: /* eight banks */
  2583. rdev->config.si.tile_config |= 1 << 4;
  2584. break;
  2585. case 2: /* sixteen banks */
  2586. default:
  2587. rdev->config.si.tile_config |= 2 << 4;
  2588. break;
  2589. }
  2590. rdev->config.si.tile_config |=
  2591. ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
  2592. rdev->config.si.tile_config |=
  2593. ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
  2594. WREG32(GB_ADDR_CONFIG, gb_addr_config);
  2595. WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
  2596. WREG32(DMIF_ADDR_CALC, gb_addr_config);
  2597. WREG32(HDP_ADDR_CONFIG, gb_addr_config);
  2598. WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
  2599. WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
  2600. if (rdev->has_uvd) {
  2601. WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
  2602. WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
  2603. WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
  2604. }
  2605. si_tiling_mode_table_init(rdev);
  2606. si_setup_rb(rdev, rdev->config.si.max_shader_engines,
  2607. rdev->config.si.max_sh_per_se,
  2608. rdev->config.si.max_backends_per_se);
  2609. si_setup_spi(rdev, rdev->config.si.max_shader_engines,
  2610. rdev->config.si.max_sh_per_se,
  2611. rdev->config.si.max_cu_per_sh);
  2612. /* set HW defaults for 3D engine */
  2613. WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
  2614. ROQ_IB2_START(0x2b)));
  2615. WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
  2616. sx_debug_1 = RREG32(SX_DEBUG_1);
  2617. WREG32(SX_DEBUG_1, sx_debug_1);
  2618. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
  2619. WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
  2620. SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
  2621. SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
  2622. SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
  2623. WREG32(VGT_NUM_INSTANCES, 1);
  2624. WREG32(CP_PERFMON_CNTL, 0);
  2625. WREG32(SQ_CONFIG, 0);
  2626. WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
  2627. FORCE_EOV_MAX_REZ_CNT(255)));
  2628. WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
  2629. AUTO_INVLD_EN(ES_AND_GS_AUTO));
  2630. WREG32(VGT_GS_VERTEX_REUSE, 16);
  2631. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  2632. WREG32(CB_PERFCOUNTER0_SELECT0, 0);
  2633. WREG32(CB_PERFCOUNTER0_SELECT1, 0);
  2634. WREG32(CB_PERFCOUNTER1_SELECT0, 0);
  2635. WREG32(CB_PERFCOUNTER1_SELECT1, 0);
  2636. WREG32(CB_PERFCOUNTER2_SELECT0, 0);
  2637. WREG32(CB_PERFCOUNTER2_SELECT1, 0);
  2638. WREG32(CB_PERFCOUNTER3_SELECT0, 0);
  2639. WREG32(CB_PERFCOUNTER3_SELECT1, 0);
  2640. tmp = RREG32(HDP_MISC_CNTL);
  2641. tmp |= HDP_FLUSH_INVALIDATE_CACHE;
  2642. WREG32(HDP_MISC_CNTL, tmp);
  2643. hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
  2644. WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
  2645. WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
  2646. udelay(50);
  2647. }
  2648. /*
  2649. * GPU scratch registers helpers function.
  2650. */
  2651. static void si_scratch_init(struct radeon_device *rdev)
  2652. {
  2653. int i;
  2654. rdev->scratch.num_reg = 7;
  2655. rdev->scratch.reg_base = SCRATCH_REG0;
  2656. for (i = 0; i < rdev->scratch.num_reg; i++) {
  2657. rdev->scratch.free[i] = true;
  2658. rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
  2659. }
  2660. }
  2661. void si_fence_ring_emit(struct radeon_device *rdev,
  2662. struct radeon_fence *fence)
  2663. {
  2664. struct radeon_ring *ring = &rdev->ring[fence->ring];
  2665. u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
  2666. /* flush read cache over gart */
  2667. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  2668. radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
  2669. radeon_ring_write(ring, 0);
  2670. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  2671. radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
  2672. PACKET3_TC_ACTION_ENA |
  2673. PACKET3_SH_KCACHE_ACTION_ENA |
  2674. PACKET3_SH_ICACHE_ACTION_ENA);
  2675. radeon_ring_write(ring, 0xFFFFFFFF);
  2676. radeon_ring_write(ring, 0);
  2677. radeon_ring_write(ring, 10); /* poll interval */
  2678. /* EVENT_WRITE_EOP - flush caches, send int */
  2679. radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
  2680. radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
  2681. radeon_ring_write(ring, addr & 0xffffffff);
  2682. radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
  2683. radeon_ring_write(ring, fence->seq);
  2684. radeon_ring_write(ring, 0);
  2685. }
  2686. /*
  2687. * IB stuff
  2688. */
  2689. void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  2690. {
  2691. struct radeon_ring *ring = &rdev->ring[ib->ring];
  2692. u32 header;
  2693. if (ib->is_const_ib) {
  2694. /* set switch buffer packet before const IB */
  2695. radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
  2696. radeon_ring_write(ring, 0);
  2697. header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
  2698. } else {
  2699. u32 next_rptr;
  2700. if (ring->rptr_save_reg) {
  2701. next_rptr = ring->wptr + 3 + 4 + 8;
  2702. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  2703. radeon_ring_write(ring, ((ring->rptr_save_reg -
  2704. PACKET3_SET_CONFIG_REG_START) >> 2));
  2705. radeon_ring_write(ring, next_rptr);
  2706. } else if (rdev->wb.enabled) {
  2707. next_rptr = ring->wptr + 5 + 4 + 8;
  2708. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  2709. radeon_ring_write(ring, (1 << 8));
  2710. radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
  2711. radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
  2712. radeon_ring_write(ring, next_rptr);
  2713. }
  2714. header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
  2715. }
  2716. radeon_ring_write(ring, header);
  2717. radeon_ring_write(ring,
  2718. #ifdef __BIG_ENDIAN
  2719. (2 << 0) |
  2720. #endif
  2721. (ib->gpu_addr & 0xFFFFFFFC));
  2722. radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
  2723. radeon_ring_write(ring, ib->length_dw |
  2724. (ib->vm ? (ib->vm->id << 24) : 0));
  2725. if (!ib->is_const_ib) {
  2726. /* flush read cache over gart for this vmid */
  2727. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  2728. radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
  2729. radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
  2730. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  2731. radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
  2732. PACKET3_TC_ACTION_ENA |
  2733. PACKET3_SH_KCACHE_ACTION_ENA |
  2734. PACKET3_SH_ICACHE_ACTION_ENA);
  2735. radeon_ring_write(ring, 0xFFFFFFFF);
  2736. radeon_ring_write(ring, 0);
  2737. radeon_ring_write(ring, 10); /* poll interval */
  2738. }
  2739. }
  2740. /*
  2741. * CP.
  2742. */
  2743. static void si_cp_enable(struct radeon_device *rdev, bool enable)
  2744. {
  2745. if (enable)
  2746. WREG32(CP_ME_CNTL, 0);
  2747. else {
  2748. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  2749. WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
  2750. WREG32(SCRATCH_UMSK, 0);
  2751. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  2752. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  2753. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  2754. }
  2755. udelay(50);
  2756. }
  2757. static int si_cp_load_microcode(struct radeon_device *rdev)
  2758. {
  2759. const __be32 *fw_data;
  2760. int i;
  2761. if (!rdev->me_fw || !rdev->pfp_fw)
  2762. return -EINVAL;
  2763. si_cp_enable(rdev, false);
  2764. /* PFP */
  2765. fw_data = (const __be32 *)rdev->pfp_fw->data;
  2766. WREG32(CP_PFP_UCODE_ADDR, 0);
  2767. for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
  2768. WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
  2769. WREG32(CP_PFP_UCODE_ADDR, 0);
  2770. /* CE */
  2771. fw_data = (const __be32 *)rdev->ce_fw->data;
  2772. WREG32(CP_CE_UCODE_ADDR, 0);
  2773. for (i = 0; i < SI_CE_UCODE_SIZE; i++)
  2774. WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
  2775. WREG32(CP_CE_UCODE_ADDR, 0);
  2776. /* ME */
  2777. fw_data = (const __be32 *)rdev->me_fw->data;
  2778. WREG32(CP_ME_RAM_WADDR, 0);
  2779. for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
  2780. WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
  2781. WREG32(CP_ME_RAM_WADDR, 0);
  2782. WREG32(CP_PFP_UCODE_ADDR, 0);
  2783. WREG32(CP_CE_UCODE_ADDR, 0);
  2784. WREG32(CP_ME_RAM_WADDR, 0);
  2785. WREG32(CP_ME_RAM_RADDR, 0);
  2786. return 0;
  2787. }
  2788. static int si_cp_start(struct radeon_device *rdev)
  2789. {
  2790. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2791. int r, i;
  2792. r = radeon_ring_lock(rdev, ring, 7 + 4);
  2793. if (r) {
  2794. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  2795. return r;
  2796. }
  2797. /* init the CP */
  2798. radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
  2799. radeon_ring_write(ring, 0x1);
  2800. radeon_ring_write(ring, 0x0);
  2801. radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
  2802. radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
  2803. radeon_ring_write(ring, 0);
  2804. radeon_ring_write(ring, 0);
  2805. /* init the CE partitions */
  2806. radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
  2807. radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
  2808. radeon_ring_write(ring, 0xc000);
  2809. radeon_ring_write(ring, 0xe000);
  2810. radeon_ring_unlock_commit(rdev, ring);
  2811. si_cp_enable(rdev, true);
  2812. r = radeon_ring_lock(rdev, ring, si_default_size + 10);
  2813. if (r) {
  2814. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  2815. return r;
  2816. }
  2817. /* setup clear context state */
  2818. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  2819. radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
  2820. for (i = 0; i < si_default_size; i++)
  2821. radeon_ring_write(ring, si_default_state[i]);
  2822. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  2823. radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
  2824. /* set clear context state */
  2825. radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
  2826. radeon_ring_write(ring, 0);
  2827. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
  2828. radeon_ring_write(ring, 0x00000316);
  2829. radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
  2830. radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
  2831. radeon_ring_unlock_commit(rdev, ring);
  2832. for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
  2833. ring = &rdev->ring[i];
  2834. r = radeon_ring_lock(rdev, ring, 2);
  2835. /* clear the compute context state */
  2836. radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
  2837. radeon_ring_write(ring, 0);
  2838. radeon_ring_unlock_commit(rdev, ring);
  2839. }
  2840. return 0;
  2841. }
  2842. static void si_cp_fini(struct radeon_device *rdev)
  2843. {
  2844. struct radeon_ring *ring;
  2845. si_cp_enable(rdev, false);
  2846. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2847. radeon_ring_fini(rdev, ring);
  2848. radeon_scratch_free(rdev, ring->rptr_save_reg);
  2849. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  2850. radeon_ring_fini(rdev, ring);
  2851. radeon_scratch_free(rdev, ring->rptr_save_reg);
  2852. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  2853. radeon_ring_fini(rdev, ring);
  2854. radeon_scratch_free(rdev, ring->rptr_save_reg);
  2855. }
  2856. static int si_cp_resume(struct radeon_device *rdev)
  2857. {
  2858. struct radeon_ring *ring;
  2859. u32 tmp;
  2860. u32 rb_bufsz;
  2861. int r;
  2862. /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
  2863. WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
  2864. SOFT_RESET_PA |
  2865. SOFT_RESET_VGT |
  2866. SOFT_RESET_SPI |
  2867. SOFT_RESET_SX));
  2868. RREG32(GRBM_SOFT_RESET);
  2869. mdelay(15);
  2870. WREG32(GRBM_SOFT_RESET, 0);
  2871. RREG32(GRBM_SOFT_RESET);
  2872. WREG32(CP_SEM_WAIT_TIMER, 0x0);
  2873. WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
  2874. /* Set the write pointer delay */
  2875. WREG32(CP_RB_WPTR_DELAY, 0);
  2876. WREG32(CP_DEBUG, 0);
  2877. WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
  2878. /* ring 0 - compute and gfx */
  2879. /* Set ring buffer size */
  2880. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2881. rb_bufsz = drm_order(ring->ring_size / 8);
  2882. tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  2883. #ifdef __BIG_ENDIAN
  2884. tmp |= BUF_SWAP_32BIT;
  2885. #endif
  2886. WREG32(CP_RB0_CNTL, tmp);
  2887. /* Initialize the ring buffer's read and write pointers */
  2888. WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
  2889. ring->wptr = 0;
  2890. WREG32(CP_RB0_WPTR, ring->wptr);
  2891. /* set the wb address whether it's enabled or not */
  2892. WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
  2893. WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
  2894. if (rdev->wb.enabled)
  2895. WREG32(SCRATCH_UMSK, 0xff);
  2896. else {
  2897. tmp |= RB_NO_UPDATE;
  2898. WREG32(SCRATCH_UMSK, 0);
  2899. }
  2900. mdelay(1);
  2901. WREG32(CP_RB0_CNTL, tmp);
  2902. WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
  2903. ring->rptr = RREG32(CP_RB0_RPTR);
  2904. /* ring1 - compute only */
  2905. /* Set ring buffer size */
  2906. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  2907. rb_bufsz = drm_order(ring->ring_size / 8);
  2908. tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  2909. #ifdef __BIG_ENDIAN
  2910. tmp |= BUF_SWAP_32BIT;
  2911. #endif
  2912. WREG32(CP_RB1_CNTL, tmp);
  2913. /* Initialize the ring buffer's read and write pointers */
  2914. WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
  2915. ring->wptr = 0;
  2916. WREG32(CP_RB1_WPTR, ring->wptr);
  2917. /* set the wb address whether it's enabled or not */
  2918. WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
  2919. WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
  2920. mdelay(1);
  2921. WREG32(CP_RB1_CNTL, tmp);
  2922. WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
  2923. ring->rptr = RREG32(CP_RB1_RPTR);
  2924. /* ring2 - compute only */
  2925. /* Set ring buffer size */
  2926. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  2927. rb_bufsz = drm_order(ring->ring_size / 8);
  2928. tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  2929. #ifdef __BIG_ENDIAN
  2930. tmp |= BUF_SWAP_32BIT;
  2931. #endif
  2932. WREG32(CP_RB2_CNTL, tmp);
  2933. /* Initialize the ring buffer's read and write pointers */
  2934. WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
  2935. ring->wptr = 0;
  2936. WREG32(CP_RB2_WPTR, ring->wptr);
  2937. /* set the wb address whether it's enabled or not */
  2938. WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
  2939. WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
  2940. mdelay(1);
  2941. WREG32(CP_RB2_CNTL, tmp);
  2942. WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
  2943. ring->rptr = RREG32(CP_RB2_RPTR);
  2944. /* start the rings */
  2945. si_cp_start(rdev);
  2946. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
  2947. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
  2948. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
  2949. r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
  2950. if (r) {
  2951. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  2952. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  2953. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  2954. return r;
  2955. }
  2956. r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
  2957. if (r) {
  2958. rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
  2959. }
  2960. r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
  2961. if (r) {
  2962. rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
  2963. }
  2964. return 0;
  2965. }
  2966. static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
  2967. {
  2968. u32 reset_mask = 0;
  2969. u32 tmp;
  2970. /* GRBM_STATUS */
  2971. tmp = RREG32(GRBM_STATUS);
  2972. if (tmp & (PA_BUSY | SC_BUSY |
  2973. BCI_BUSY | SX_BUSY |
  2974. TA_BUSY | VGT_BUSY |
  2975. DB_BUSY | CB_BUSY |
  2976. GDS_BUSY | SPI_BUSY |
  2977. IA_BUSY | IA_BUSY_NO_DMA))
  2978. reset_mask |= RADEON_RESET_GFX;
  2979. if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
  2980. CP_BUSY | CP_COHERENCY_BUSY))
  2981. reset_mask |= RADEON_RESET_CP;
  2982. if (tmp & GRBM_EE_BUSY)
  2983. reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
  2984. /* GRBM_STATUS2 */
  2985. tmp = RREG32(GRBM_STATUS2);
  2986. if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
  2987. reset_mask |= RADEON_RESET_RLC;
  2988. /* DMA_STATUS_REG 0 */
  2989. tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
  2990. if (!(tmp & DMA_IDLE))
  2991. reset_mask |= RADEON_RESET_DMA;
  2992. /* DMA_STATUS_REG 1 */
  2993. tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
  2994. if (!(tmp & DMA_IDLE))
  2995. reset_mask |= RADEON_RESET_DMA1;
  2996. /* SRBM_STATUS2 */
  2997. tmp = RREG32(SRBM_STATUS2);
  2998. if (tmp & DMA_BUSY)
  2999. reset_mask |= RADEON_RESET_DMA;
  3000. if (tmp & DMA1_BUSY)
  3001. reset_mask |= RADEON_RESET_DMA1;
  3002. /* SRBM_STATUS */
  3003. tmp = RREG32(SRBM_STATUS);
  3004. if (tmp & IH_BUSY)
  3005. reset_mask |= RADEON_RESET_IH;
  3006. if (tmp & SEM_BUSY)
  3007. reset_mask |= RADEON_RESET_SEM;
  3008. if (tmp & GRBM_RQ_PENDING)
  3009. reset_mask |= RADEON_RESET_GRBM;
  3010. if (tmp & VMC_BUSY)
  3011. reset_mask |= RADEON_RESET_VMC;
  3012. if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
  3013. MCC_BUSY | MCD_BUSY))
  3014. reset_mask |= RADEON_RESET_MC;
  3015. if (evergreen_is_display_hung(rdev))
  3016. reset_mask |= RADEON_RESET_DISPLAY;
  3017. /* VM_L2_STATUS */
  3018. tmp = RREG32(VM_L2_STATUS);
  3019. if (tmp & L2_BUSY)
  3020. reset_mask |= RADEON_RESET_VMC;
  3021. /* Skip MC reset as it's mostly likely not hung, just busy */
  3022. if (reset_mask & RADEON_RESET_MC) {
  3023. DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
  3024. reset_mask &= ~RADEON_RESET_MC;
  3025. }
  3026. return reset_mask;
  3027. }
  3028. static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
  3029. {
  3030. struct evergreen_mc_save save;
  3031. u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
  3032. u32 tmp;
  3033. if (reset_mask == 0)
  3034. return;
  3035. dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
  3036. evergreen_print_gpu_status_regs(rdev);
  3037. dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
  3038. RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
  3039. dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
  3040. RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
  3041. /* Disable CP parsing/prefetching */
  3042. WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
  3043. if (reset_mask & RADEON_RESET_DMA) {
  3044. /* dma0 */
  3045. tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
  3046. tmp &= ~DMA_RB_ENABLE;
  3047. WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
  3048. }
  3049. if (reset_mask & RADEON_RESET_DMA1) {
  3050. /* dma1 */
  3051. tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
  3052. tmp &= ~DMA_RB_ENABLE;
  3053. WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
  3054. }
  3055. udelay(50);
  3056. evergreen_mc_stop(rdev, &save);
  3057. if (evergreen_mc_wait_for_idle(rdev)) {
  3058. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  3059. }
  3060. if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
  3061. grbm_soft_reset = SOFT_RESET_CB |
  3062. SOFT_RESET_DB |
  3063. SOFT_RESET_GDS |
  3064. SOFT_RESET_PA |
  3065. SOFT_RESET_SC |
  3066. SOFT_RESET_BCI |
  3067. SOFT_RESET_SPI |
  3068. SOFT_RESET_SX |
  3069. SOFT_RESET_TC |
  3070. SOFT_RESET_TA |
  3071. SOFT_RESET_VGT |
  3072. SOFT_RESET_IA;
  3073. }
  3074. if (reset_mask & RADEON_RESET_CP) {
  3075. grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
  3076. srbm_soft_reset |= SOFT_RESET_GRBM;
  3077. }
  3078. if (reset_mask & RADEON_RESET_DMA)
  3079. srbm_soft_reset |= SOFT_RESET_DMA;
  3080. if (reset_mask & RADEON_RESET_DMA1)
  3081. srbm_soft_reset |= SOFT_RESET_DMA1;
  3082. if (reset_mask & RADEON_RESET_DISPLAY)
  3083. srbm_soft_reset |= SOFT_RESET_DC;
  3084. if (reset_mask & RADEON_RESET_RLC)
  3085. grbm_soft_reset |= SOFT_RESET_RLC;
  3086. if (reset_mask & RADEON_RESET_SEM)
  3087. srbm_soft_reset |= SOFT_RESET_SEM;
  3088. if (reset_mask & RADEON_RESET_IH)
  3089. srbm_soft_reset |= SOFT_RESET_IH;
  3090. if (reset_mask & RADEON_RESET_GRBM)
  3091. srbm_soft_reset |= SOFT_RESET_GRBM;
  3092. if (reset_mask & RADEON_RESET_VMC)
  3093. srbm_soft_reset |= SOFT_RESET_VMC;
  3094. if (reset_mask & RADEON_RESET_MC)
  3095. srbm_soft_reset |= SOFT_RESET_MC;
  3096. if (grbm_soft_reset) {
  3097. tmp = RREG32(GRBM_SOFT_RESET);
  3098. tmp |= grbm_soft_reset;
  3099. dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
  3100. WREG32(GRBM_SOFT_RESET, tmp);
  3101. tmp = RREG32(GRBM_SOFT_RESET);
  3102. udelay(50);
  3103. tmp &= ~grbm_soft_reset;
  3104. WREG32(GRBM_SOFT_RESET, tmp);
  3105. tmp = RREG32(GRBM_SOFT_RESET);
  3106. }
  3107. if (srbm_soft_reset) {
  3108. tmp = RREG32(SRBM_SOFT_RESET);
  3109. tmp |= srbm_soft_reset;
  3110. dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  3111. WREG32(SRBM_SOFT_RESET, tmp);
  3112. tmp = RREG32(SRBM_SOFT_RESET);
  3113. udelay(50);
  3114. tmp &= ~srbm_soft_reset;
  3115. WREG32(SRBM_SOFT_RESET, tmp);
  3116. tmp = RREG32(SRBM_SOFT_RESET);
  3117. }
  3118. /* Wait a little for things to settle down */
  3119. udelay(50);
  3120. evergreen_mc_resume(rdev, &save);
  3121. udelay(50);
  3122. evergreen_print_gpu_status_regs(rdev);
  3123. }
  3124. int si_asic_reset(struct radeon_device *rdev)
  3125. {
  3126. u32 reset_mask;
  3127. reset_mask = si_gpu_check_soft_reset(rdev);
  3128. if (reset_mask)
  3129. r600_set_bios_scratch_engine_hung(rdev, true);
  3130. si_gpu_soft_reset(rdev, reset_mask);
  3131. reset_mask = si_gpu_check_soft_reset(rdev);
  3132. if (!reset_mask)
  3133. r600_set_bios_scratch_engine_hung(rdev, false);
  3134. return 0;
  3135. }
  3136. /**
  3137. * si_gfx_is_lockup - Check if the GFX engine is locked up
  3138. *
  3139. * @rdev: radeon_device pointer
  3140. * @ring: radeon_ring structure holding ring information
  3141. *
  3142. * Check if the GFX engine is locked up.
  3143. * Returns true if the engine appears to be locked up, false if not.
  3144. */
  3145. bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  3146. {
  3147. u32 reset_mask = si_gpu_check_soft_reset(rdev);
  3148. if (!(reset_mask & (RADEON_RESET_GFX |
  3149. RADEON_RESET_COMPUTE |
  3150. RADEON_RESET_CP))) {
  3151. radeon_ring_lockup_update(ring);
  3152. return false;
  3153. }
  3154. /* force CP activities */
  3155. radeon_ring_force_activity(rdev, ring);
  3156. return radeon_ring_test_lockup(rdev, ring);
  3157. }
  3158. /**
  3159. * si_dma_is_lockup - Check if the DMA engine is locked up
  3160. *
  3161. * @rdev: radeon_device pointer
  3162. * @ring: radeon_ring structure holding ring information
  3163. *
  3164. * Check if the async DMA engine is locked up.
  3165. * Returns true if the engine appears to be locked up, false if not.
  3166. */
  3167. bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  3168. {
  3169. u32 reset_mask = si_gpu_check_soft_reset(rdev);
  3170. u32 mask;
  3171. if (ring->idx == R600_RING_TYPE_DMA_INDEX)
  3172. mask = RADEON_RESET_DMA;
  3173. else
  3174. mask = RADEON_RESET_DMA1;
  3175. if (!(reset_mask & mask)) {
  3176. radeon_ring_lockup_update(ring);
  3177. return false;
  3178. }
  3179. /* force ring activities */
  3180. radeon_ring_force_activity(rdev, ring);
  3181. return radeon_ring_test_lockup(rdev, ring);
  3182. }
  3183. /* MC */
  3184. static void si_mc_program(struct radeon_device *rdev)
  3185. {
  3186. struct evergreen_mc_save save;
  3187. u32 tmp;
  3188. int i, j;
  3189. /* Initialize HDP */
  3190. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  3191. WREG32((0x2c14 + j), 0x00000000);
  3192. WREG32((0x2c18 + j), 0x00000000);
  3193. WREG32((0x2c1c + j), 0x00000000);
  3194. WREG32((0x2c20 + j), 0x00000000);
  3195. WREG32((0x2c24 + j), 0x00000000);
  3196. }
  3197. WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
  3198. evergreen_mc_stop(rdev, &save);
  3199. if (radeon_mc_wait_for_idle(rdev)) {
  3200. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  3201. }
  3202. if (!ASIC_IS_NODCE(rdev))
  3203. /* Lockout access through VGA aperture*/
  3204. WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
  3205. /* Update configuration */
  3206. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  3207. rdev->mc.vram_start >> 12);
  3208. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  3209. rdev->mc.vram_end >> 12);
  3210. WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
  3211. rdev->vram_scratch.gpu_addr >> 12);
  3212. tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
  3213. tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
  3214. WREG32(MC_VM_FB_LOCATION, tmp);
  3215. /* XXX double check these! */
  3216. WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
  3217. WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
  3218. WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
  3219. WREG32(MC_VM_AGP_BASE, 0);
  3220. WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
  3221. WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
  3222. if (radeon_mc_wait_for_idle(rdev)) {
  3223. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  3224. }
  3225. evergreen_mc_resume(rdev, &save);
  3226. if (!ASIC_IS_NODCE(rdev)) {
  3227. /* we need to own VRAM, so turn off the VGA renderer here
  3228. * to stop it overwriting our objects */
  3229. rv515_vga_render_disable(rdev);
  3230. }
  3231. }
  3232. static void si_vram_gtt_location(struct radeon_device *rdev,
  3233. struct radeon_mc *mc)
  3234. {
  3235. if (mc->mc_vram_size > 0xFFC0000000ULL) {
  3236. /* leave room for at least 1024M GTT */
  3237. dev_warn(rdev->dev, "limiting VRAM\n");
  3238. mc->real_vram_size = 0xFFC0000000ULL;
  3239. mc->mc_vram_size = 0xFFC0000000ULL;
  3240. }
  3241. radeon_vram_location(rdev, &rdev->mc, 0);
  3242. rdev->mc.gtt_base_align = 0;
  3243. radeon_gtt_location(rdev, mc);
  3244. }
  3245. static int si_mc_init(struct radeon_device *rdev)
  3246. {
  3247. u32 tmp;
  3248. int chansize, numchan;
  3249. /* Get VRAM informations */
  3250. rdev->mc.vram_is_ddr = true;
  3251. tmp = RREG32(MC_ARB_RAMCFG);
  3252. if (tmp & CHANSIZE_OVERRIDE) {
  3253. chansize = 16;
  3254. } else if (tmp & CHANSIZE_MASK) {
  3255. chansize = 64;
  3256. } else {
  3257. chansize = 32;
  3258. }
  3259. tmp = RREG32(MC_SHARED_CHMAP);
  3260. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  3261. case 0:
  3262. default:
  3263. numchan = 1;
  3264. break;
  3265. case 1:
  3266. numchan = 2;
  3267. break;
  3268. case 2:
  3269. numchan = 4;
  3270. break;
  3271. case 3:
  3272. numchan = 8;
  3273. break;
  3274. case 4:
  3275. numchan = 3;
  3276. break;
  3277. case 5:
  3278. numchan = 6;
  3279. break;
  3280. case 6:
  3281. numchan = 10;
  3282. break;
  3283. case 7:
  3284. numchan = 12;
  3285. break;
  3286. case 8:
  3287. numchan = 16;
  3288. break;
  3289. }
  3290. rdev->mc.vram_width = numchan * chansize;
  3291. /* Could aper size report 0 ? */
  3292. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  3293. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  3294. /* size in MB on si */
  3295. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
  3296. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
  3297. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  3298. si_vram_gtt_location(rdev, &rdev->mc);
  3299. radeon_update_bandwidth_info(rdev);
  3300. return 0;
  3301. }
  3302. /*
  3303. * GART
  3304. */
  3305. void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
  3306. {
  3307. /* flush hdp cache */
  3308. WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
  3309. /* bits 0-15 are the VM contexts0-15 */
  3310. WREG32(VM_INVALIDATE_REQUEST, 1);
  3311. }
  3312. static int si_pcie_gart_enable(struct radeon_device *rdev)
  3313. {
  3314. int r, i;
  3315. if (rdev->gart.robj == NULL) {
  3316. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  3317. return -EINVAL;
  3318. }
  3319. r = radeon_gart_table_vram_pin(rdev);
  3320. if (r)
  3321. return r;
  3322. radeon_gart_restore(rdev);
  3323. /* Setup TLB control */
  3324. WREG32(MC_VM_MX_L1_TLB_CNTL,
  3325. (0xA << 7) |
  3326. ENABLE_L1_TLB |
  3327. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  3328. ENABLE_ADVANCED_DRIVER_MODEL |
  3329. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
  3330. /* Setup L2 cache */
  3331. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
  3332. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  3333. ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
  3334. EFFECTIVE_L2_QUEUE_SIZE(7) |
  3335. CONTEXT1_IDENTITY_ACCESS_MODE(1));
  3336. WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
  3337. WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
  3338. L2_CACHE_BIGK_FRAGMENT_SIZE(0));
  3339. /* setup context0 */
  3340. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  3341. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  3342. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  3343. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  3344. (u32)(rdev->dummy_page.addr >> 12));
  3345. WREG32(VM_CONTEXT0_CNTL2, 0);
  3346. WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  3347. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
  3348. WREG32(0x15D4, 0);
  3349. WREG32(0x15D8, 0);
  3350. WREG32(0x15DC, 0);
  3351. /* empty context1-15 */
  3352. /* set vm size, must be a multiple of 4 */
  3353. WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
  3354. WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
  3355. /* Assign the pt base to something valid for now; the pts used for
  3356. * the VMs are determined by the application and setup and assigned
  3357. * on the fly in the vm part of radeon_gart.c
  3358. */
  3359. for (i = 1; i < 16; i++) {
  3360. if (i < 8)
  3361. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
  3362. rdev->gart.table_addr >> 12);
  3363. else
  3364. WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
  3365. rdev->gart.table_addr >> 12);
  3366. }
  3367. /* enable context1-15 */
  3368. WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
  3369. (u32)(rdev->dummy_page.addr >> 12));
  3370. WREG32(VM_CONTEXT1_CNTL2, 4);
  3371. WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
  3372. RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3373. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
  3374. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3375. DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
  3376. PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3377. PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
  3378. VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3379. VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
  3380. READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3381. READ_PROTECTION_FAULT_ENABLE_DEFAULT |
  3382. WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
  3383. WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
  3384. si_pcie_gart_tlb_flush(rdev);
  3385. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  3386. (unsigned)(rdev->mc.gtt_size >> 20),
  3387. (unsigned long long)rdev->gart.table_addr);
  3388. rdev->gart.ready = true;
  3389. return 0;
  3390. }
  3391. static void si_pcie_gart_disable(struct radeon_device *rdev)
  3392. {
  3393. /* Disable all tables */
  3394. WREG32(VM_CONTEXT0_CNTL, 0);
  3395. WREG32(VM_CONTEXT1_CNTL, 0);
  3396. /* Setup TLB control */
  3397. WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  3398. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
  3399. /* Setup L2 cache */
  3400. WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  3401. ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
  3402. EFFECTIVE_L2_QUEUE_SIZE(7) |
  3403. CONTEXT1_IDENTITY_ACCESS_MODE(1));
  3404. WREG32(VM_L2_CNTL2, 0);
  3405. WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
  3406. L2_CACHE_BIGK_FRAGMENT_SIZE(0));
  3407. radeon_gart_table_vram_unpin(rdev);
  3408. }
  3409. static void si_pcie_gart_fini(struct radeon_device *rdev)
  3410. {
  3411. si_pcie_gart_disable(rdev);
  3412. radeon_gart_table_vram_free(rdev);
  3413. radeon_gart_fini(rdev);
  3414. }
  3415. /* vm parser */
  3416. static bool si_vm_reg_valid(u32 reg)
  3417. {
  3418. /* context regs are fine */
  3419. if (reg >= 0x28000)
  3420. return true;
  3421. /* check config regs */
  3422. switch (reg) {
  3423. case GRBM_GFX_INDEX:
  3424. case CP_STRMOUT_CNTL:
  3425. case VGT_VTX_VECT_EJECT_REG:
  3426. case VGT_CACHE_INVALIDATION:
  3427. case VGT_ESGS_RING_SIZE:
  3428. case VGT_GSVS_RING_SIZE:
  3429. case VGT_GS_VERTEX_REUSE:
  3430. case VGT_PRIMITIVE_TYPE:
  3431. case VGT_INDEX_TYPE:
  3432. case VGT_NUM_INDICES:
  3433. case VGT_NUM_INSTANCES:
  3434. case VGT_TF_RING_SIZE:
  3435. case VGT_HS_OFFCHIP_PARAM:
  3436. case VGT_TF_MEMORY_BASE:
  3437. case PA_CL_ENHANCE:
  3438. case PA_SU_LINE_STIPPLE_VALUE:
  3439. case PA_SC_LINE_STIPPLE_STATE:
  3440. case PA_SC_ENHANCE:
  3441. case SQC_CACHES:
  3442. case SPI_STATIC_THREAD_MGMT_1:
  3443. case SPI_STATIC_THREAD_MGMT_2:
  3444. case SPI_STATIC_THREAD_MGMT_3:
  3445. case SPI_PS_MAX_WAVE_ID:
  3446. case SPI_CONFIG_CNTL:
  3447. case SPI_CONFIG_CNTL_1:
  3448. case TA_CNTL_AUX:
  3449. return true;
  3450. default:
  3451. DRM_ERROR("Invalid register 0x%x in CS\n", reg);
  3452. return false;
  3453. }
  3454. }
  3455. static int si_vm_packet3_ce_check(struct radeon_device *rdev,
  3456. u32 *ib, struct radeon_cs_packet *pkt)
  3457. {
  3458. switch (pkt->opcode) {
  3459. case PACKET3_NOP:
  3460. case PACKET3_SET_BASE:
  3461. case PACKET3_SET_CE_DE_COUNTERS:
  3462. case PACKET3_LOAD_CONST_RAM:
  3463. case PACKET3_WRITE_CONST_RAM:
  3464. case PACKET3_WRITE_CONST_RAM_OFFSET:
  3465. case PACKET3_DUMP_CONST_RAM:
  3466. case PACKET3_INCREMENT_CE_COUNTER:
  3467. case PACKET3_WAIT_ON_DE_COUNTER:
  3468. case PACKET3_CE_WRITE:
  3469. break;
  3470. default:
  3471. DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
  3472. return -EINVAL;
  3473. }
  3474. return 0;
  3475. }
  3476. static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
  3477. u32 *ib, struct radeon_cs_packet *pkt)
  3478. {
  3479. u32 idx = pkt->idx + 1;
  3480. u32 idx_value = ib[idx];
  3481. u32 start_reg, end_reg, reg, i;
  3482. u32 command, info;
  3483. switch (pkt->opcode) {
  3484. case PACKET3_NOP:
  3485. case PACKET3_SET_BASE:
  3486. case PACKET3_CLEAR_STATE:
  3487. case PACKET3_INDEX_BUFFER_SIZE:
  3488. case PACKET3_DISPATCH_DIRECT:
  3489. case PACKET3_DISPATCH_INDIRECT:
  3490. case PACKET3_ALLOC_GDS:
  3491. case PACKET3_WRITE_GDS_RAM:
  3492. case PACKET3_ATOMIC_GDS:
  3493. case PACKET3_ATOMIC:
  3494. case PACKET3_OCCLUSION_QUERY:
  3495. case PACKET3_SET_PREDICATION:
  3496. case PACKET3_COND_EXEC:
  3497. case PACKET3_PRED_EXEC:
  3498. case PACKET3_DRAW_INDIRECT:
  3499. case PACKET3_DRAW_INDEX_INDIRECT:
  3500. case PACKET3_INDEX_BASE:
  3501. case PACKET3_DRAW_INDEX_2:
  3502. case PACKET3_CONTEXT_CONTROL:
  3503. case PACKET3_INDEX_TYPE:
  3504. case PACKET3_DRAW_INDIRECT_MULTI:
  3505. case PACKET3_DRAW_INDEX_AUTO:
  3506. case PACKET3_DRAW_INDEX_IMMD:
  3507. case PACKET3_NUM_INSTANCES:
  3508. case PACKET3_DRAW_INDEX_MULTI_AUTO:
  3509. case PACKET3_STRMOUT_BUFFER_UPDATE:
  3510. case PACKET3_DRAW_INDEX_OFFSET_2:
  3511. case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
  3512. case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
  3513. case PACKET3_MPEG_INDEX:
  3514. case PACKET3_WAIT_REG_MEM:
  3515. case PACKET3_MEM_WRITE:
  3516. case PACKET3_PFP_SYNC_ME:
  3517. case PACKET3_SURFACE_SYNC:
  3518. case PACKET3_EVENT_WRITE:
  3519. case PACKET3_EVENT_WRITE_EOP:
  3520. case PACKET3_EVENT_WRITE_EOS:
  3521. case PACKET3_SET_CONTEXT_REG:
  3522. case PACKET3_SET_CONTEXT_REG_INDIRECT:
  3523. case PACKET3_SET_SH_REG:
  3524. case PACKET3_SET_SH_REG_OFFSET:
  3525. case PACKET3_INCREMENT_DE_COUNTER:
  3526. case PACKET3_WAIT_ON_CE_COUNTER:
  3527. case PACKET3_WAIT_ON_AVAIL_BUFFER:
  3528. case PACKET3_ME_WRITE:
  3529. break;
  3530. case PACKET3_COPY_DATA:
  3531. if ((idx_value & 0xf00) == 0) {
  3532. reg = ib[idx + 3] * 4;
  3533. if (!si_vm_reg_valid(reg))
  3534. return -EINVAL;
  3535. }
  3536. break;
  3537. case PACKET3_WRITE_DATA:
  3538. if ((idx_value & 0xf00) == 0) {
  3539. start_reg = ib[idx + 1] * 4;
  3540. if (idx_value & 0x10000) {
  3541. if (!si_vm_reg_valid(start_reg))
  3542. return -EINVAL;
  3543. } else {
  3544. for (i = 0; i < (pkt->count - 2); i++) {
  3545. reg = start_reg + (4 * i);
  3546. if (!si_vm_reg_valid(reg))
  3547. return -EINVAL;
  3548. }
  3549. }
  3550. }
  3551. break;
  3552. case PACKET3_COND_WRITE:
  3553. if (idx_value & 0x100) {
  3554. reg = ib[idx + 5] * 4;
  3555. if (!si_vm_reg_valid(reg))
  3556. return -EINVAL;
  3557. }
  3558. break;
  3559. case PACKET3_COPY_DW:
  3560. if (idx_value & 0x2) {
  3561. reg = ib[idx + 3] * 4;
  3562. if (!si_vm_reg_valid(reg))
  3563. return -EINVAL;
  3564. }
  3565. break;
  3566. case PACKET3_SET_CONFIG_REG:
  3567. start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
  3568. end_reg = 4 * pkt->count + start_reg - 4;
  3569. if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
  3570. (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
  3571. (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
  3572. DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
  3573. return -EINVAL;
  3574. }
  3575. for (i = 0; i < pkt->count; i++) {
  3576. reg = start_reg + (4 * i);
  3577. if (!si_vm_reg_valid(reg))
  3578. return -EINVAL;
  3579. }
  3580. break;
  3581. case PACKET3_CP_DMA:
  3582. command = ib[idx + 4];
  3583. info = ib[idx + 1];
  3584. if (command & PACKET3_CP_DMA_CMD_SAS) {
  3585. /* src address space is register */
  3586. if (((info & 0x60000000) >> 29) == 0) {
  3587. start_reg = idx_value << 2;
  3588. if (command & PACKET3_CP_DMA_CMD_SAIC) {
  3589. reg = start_reg;
  3590. if (!si_vm_reg_valid(reg)) {
  3591. DRM_ERROR("CP DMA Bad SRC register\n");
  3592. return -EINVAL;
  3593. }
  3594. } else {
  3595. for (i = 0; i < (command & 0x1fffff); i++) {
  3596. reg = start_reg + (4 * i);
  3597. if (!si_vm_reg_valid(reg)) {
  3598. DRM_ERROR("CP DMA Bad SRC register\n");
  3599. return -EINVAL;
  3600. }
  3601. }
  3602. }
  3603. }
  3604. }
  3605. if (command & PACKET3_CP_DMA_CMD_DAS) {
  3606. /* dst address space is register */
  3607. if (((info & 0x00300000) >> 20) == 0) {
  3608. start_reg = ib[idx + 2];
  3609. if (command & PACKET3_CP_DMA_CMD_DAIC) {
  3610. reg = start_reg;
  3611. if (!si_vm_reg_valid(reg)) {
  3612. DRM_ERROR("CP DMA Bad DST register\n");
  3613. return -EINVAL;
  3614. }
  3615. } else {
  3616. for (i = 0; i < (command & 0x1fffff); i++) {
  3617. reg = start_reg + (4 * i);
  3618. if (!si_vm_reg_valid(reg)) {
  3619. DRM_ERROR("CP DMA Bad DST register\n");
  3620. return -EINVAL;
  3621. }
  3622. }
  3623. }
  3624. }
  3625. }
  3626. break;
  3627. default:
  3628. DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
  3629. return -EINVAL;
  3630. }
  3631. return 0;
  3632. }
  3633. static int si_vm_packet3_compute_check(struct radeon_device *rdev,
  3634. u32 *ib, struct radeon_cs_packet *pkt)
  3635. {
  3636. u32 idx = pkt->idx + 1;
  3637. u32 idx_value = ib[idx];
  3638. u32 start_reg, reg, i;
  3639. switch (pkt->opcode) {
  3640. case PACKET3_NOP:
  3641. case PACKET3_SET_BASE:
  3642. case PACKET3_CLEAR_STATE:
  3643. case PACKET3_DISPATCH_DIRECT:
  3644. case PACKET3_DISPATCH_INDIRECT:
  3645. case PACKET3_ALLOC_GDS:
  3646. case PACKET3_WRITE_GDS_RAM:
  3647. case PACKET3_ATOMIC_GDS:
  3648. case PACKET3_ATOMIC:
  3649. case PACKET3_OCCLUSION_QUERY:
  3650. case PACKET3_SET_PREDICATION:
  3651. case PACKET3_COND_EXEC:
  3652. case PACKET3_PRED_EXEC:
  3653. case PACKET3_CONTEXT_CONTROL:
  3654. case PACKET3_STRMOUT_BUFFER_UPDATE:
  3655. case PACKET3_WAIT_REG_MEM:
  3656. case PACKET3_MEM_WRITE:
  3657. case PACKET3_PFP_SYNC_ME:
  3658. case PACKET3_SURFACE_SYNC:
  3659. case PACKET3_EVENT_WRITE:
  3660. case PACKET3_EVENT_WRITE_EOP:
  3661. case PACKET3_EVENT_WRITE_EOS:
  3662. case PACKET3_SET_CONTEXT_REG:
  3663. case PACKET3_SET_CONTEXT_REG_INDIRECT:
  3664. case PACKET3_SET_SH_REG:
  3665. case PACKET3_SET_SH_REG_OFFSET:
  3666. case PACKET3_INCREMENT_DE_COUNTER:
  3667. case PACKET3_WAIT_ON_CE_COUNTER:
  3668. case PACKET3_WAIT_ON_AVAIL_BUFFER:
  3669. case PACKET3_ME_WRITE:
  3670. break;
  3671. case PACKET3_COPY_DATA:
  3672. if ((idx_value & 0xf00) == 0) {
  3673. reg = ib[idx + 3] * 4;
  3674. if (!si_vm_reg_valid(reg))
  3675. return -EINVAL;
  3676. }
  3677. break;
  3678. case PACKET3_WRITE_DATA:
  3679. if ((idx_value & 0xf00) == 0) {
  3680. start_reg = ib[idx + 1] * 4;
  3681. if (idx_value & 0x10000) {
  3682. if (!si_vm_reg_valid(start_reg))
  3683. return -EINVAL;
  3684. } else {
  3685. for (i = 0; i < (pkt->count - 2); i++) {
  3686. reg = start_reg + (4 * i);
  3687. if (!si_vm_reg_valid(reg))
  3688. return -EINVAL;
  3689. }
  3690. }
  3691. }
  3692. break;
  3693. case PACKET3_COND_WRITE:
  3694. if (idx_value & 0x100) {
  3695. reg = ib[idx + 5] * 4;
  3696. if (!si_vm_reg_valid(reg))
  3697. return -EINVAL;
  3698. }
  3699. break;
  3700. case PACKET3_COPY_DW:
  3701. if (idx_value & 0x2) {
  3702. reg = ib[idx + 3] * 4;
  3703. if (!si_vm_reg_valid(reg))
  3704. return -EINVAL;
  3705. }
  3706. break;
  3707. default:
  3708. DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
  3709. return -EINVAL;
  3710. }
  3711. return 0;
  3712. }
  3713. int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
  3714. {
  3715. int ret = 0;
  3716. u32 idx = 0;
  3717. struct radeon_cs_packet pkt;
  3718. do {
  3719. pkt.idx = idx;
  3720. pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
  3721. pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
  3722. pkt.one_reg_wr = 0;
  3723. switch (pkt.type) {
  3724. case RADEON_PACKET_TYPE0:
  3725. dev_err(rdev->dev, "Packet0 not allowed!\n");
  3726. ret = -EINVAL;
  3727. break;
  3728. case RADEON_PACKET_TYPE2:
  3729. idx += 1;
  3730. break;
  3731. case RADEON_PACKET_TYPE3:
  3732. pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
  3733. if (ib->is_const_ib)
  3734. ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
  3735. else {
  3736. switch (ib->ring) {
  3737. case RADEON_RING_TYPE_GFX_INDEX:
  3738. ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
  3739. break;
  3740. case CAYMAN_RING_TYPE_CP1_INDEX:
  3741. case CAYMAN_RING_TYPE_CP2_INDEX:
  3742. ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
  3743. break;
  3744. default:
  3745. dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
  3746. ret = -EINVAL;
  3747. break;
  3748. }
  3749. }
  3750. idx += pkt.count + 2;
  3751. break;
  3752. default:
  3753. dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
  3754. ret = -EINVAL;
  3755. break;
  3756. }
  3757. if (ret)
  3758. break;
  3759. } while (idx < ib->length_dw);
  3760. return ret;
  3761. }
  3762. /*
  3763. * vm
  3764. */
  3765. int si_vm_init(struct radeon_device *rdev)
  3766. {
  3767. /* number of VMs */
  3768. rdev->vm_manager.nvm = 16;
  3769. /* base offset of vram pages */
  3770. rdev->vm_manager.vram_base_offset = 0;
  3771. return 0;
  3772. }
  3773. void si_vm_fini(struct radeon_device *rdev)
  3774. {
  3775. }
  3776. /**
  3777. * si_vm_set_page - update the page tables using the CP
  3778. *
  3779. * @rdev: radeon_device pointer
  3780. * @ib: indirect buffer to fill with commands
  3781. * @pe: addr of the page entry
  3782. * @addr: dst addr to write into pe
  3783. * @count: number of page entries to update
  3784. * @incr: increase next addr by incr bytes
  3785. * @flags: access flags
  3786. *
  3787. * Update the page tables using the CP (SI).
  3788. */
  3789. void si_vm_set_page(struct radeon_device *rdev,
  3790. struct radeon_ib *ib,
  3791. uint64_t pe,
  3792. uint64_t addr, unsigned count,
  3793. uint32_t incr, uint32_t flags)
  3794. {
  3795. uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
  3796. uint64_t value;
  3797. unsigned ndw;
  3798. if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
  3799. while (count) {
  3800. ndw = 2 + count * 2;
  3801. if (ndw > 0x3FFE)
  3802. ndw = 0x3FFE;
  3803. ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
  3804. ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
  3805. WRITE_DATA_DST_SEL(1));
  3806. ib->ptr[ib->length_dw++] = pe;
  3807. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  3808. for (; ndw > 2; ndw -= 2, --count, pe += 8) {
  3809. if (flags & RADEON_VM_PAGE_SYSTEM) {
  3810. value = radeon_vm_map_gart(rdev, addr);
  3811. value &= 0xFFFFFFFFFFFFF000ULL;
  3812. } else if (flags & RADEON_VM_PAGE_VALID) {
  3813. value = addr;
  3814. } else {
  3815. value = 0;
  3816. }
  3817. addr += incr;
  3818. value |= r600_flags;
  3819. ib->ptr[ib->length_dw++] = value;
  3820. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  3821. }
  3822. }
  3823. } else {
  3824. /* DMA */
  3825. if (flags & RADEON_VM_PAGE_SYSTEM) {
  3826. while (count) {
  3827. ndw = count * 2;
  3828. if (ndw > 0xFFFFE)
  3829. ndw = 0xFFFFE;
  3830. /* for non-physically contiguous pages (system) */
  3831. ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);
  3832. ib->ptr[ib->length_dw++] = pe;
  3833. ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
  3834. for (; ndw > 0; ndw -= 2, --count, pe += 8) {
  3835. if (flags & RADEON_VM_PAGE_SYSTEM) {
  3836. value = radeon_vm_map_gart(rdev, addr);
  3837. value &= 0xFFFFFFFFFFFFF000ULL;
  3838. } else if (flags & RADEON_VM_PAGE_VALID) {
  3839. value = addr;
  3840. } else {
  3841. value = 0;
  3842. }
  3843. addr += incr;
  3844. value |= r600_flags;
  3845. ib->ptr[ib->length_dw++] = value;
  3846. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  3847. }
  3848. }
  3849. } else {
  3850. while (count) {
  3851. ndw = count * 2;
  3852. if (ndw > 0xFFFFE)
  3853. ndw = 0xFFFFE;
  3854. if (flags & RADEON_VM_PAGE_VALID)
  3855. value = addr;
  3856. else
  3857. value = 0;
  3858. /* for physically contiguous pages (vram) */
  3859. ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
  3860. ib->ptr[ib->length_dw++] = pe; /* dst addr */
  3861. ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
  3862. ib->ptr[ib->length_dw++] = r600_flags; /* mask */
  3863. ib->ptr[ib->length_dw++] = 0;
  3864. ib->ptr[ib->length_dw++] = value; /* value */
  3865. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  3866. ib->ptr[ib->length_dw++] = incr; /* increment size */
  3867. ib->ptr[ib->length_dw++] = 0;
  3868. pe += ndw * 4;
  3869. addr += (ndw / 2) * incr;
  3870. count -= ndw / 2;
  3871. }
  3872. }
  3873. while (ib->length_dw & 0x7)
  3874. ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0);
  3875. }
  3876. }
  3877. void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
  3878. {
  3879. struct radeon_ring *ring = &rdev->ring[ridx];
  3880. if (vm == NULL)
  3881. return;
  3882. /* write new base address */
  3883. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3884. radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3885. WRITE_DATA_DST_SEL(0)));
  3886. if (vm->id < 8) {
  3887. radeon_ring_write(ring,
  3888. (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
  3889. } else {
  3890. radeon_ring_write(ring,
  3891. (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
  3892. }
  3893. radeon_ring_write(ring, 0);
  3894. radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
  3895. /* flush hdp cache */
  3896. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3897. radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3898. WRITE_DATA_DST_SEL(0)));
  3899. radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
  3900. radeon_ring_write(ring, 0);
  3901. radeon_ring_write(ring, 0x1);
  3902. /* bits 0-15 are the VM contexts0-15 */
  3903. radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3904. radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3905. WRITE_DATA_DST_SEL(0)));
  3906. radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
  3907. radeon_ring_write(ring, 0);
  3908. radeon_ring_write(ring, 1 << vm->id);
  3909. /* sync PFP to ME, otherwise we might get invalid PFP reads */
  3910. radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
  3911. radeon_ring_write(ring, 0x0);
  3912. }
  3913. void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
  3914. {
  3915. struct radeon_ring *ring = &rdev->ring[ridx];
  3916. if (vm == NULL)
  3917. return;
  3918. radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
  3919. if (vm->id < 8) {
  3920. radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
  3921. } else {
  3922. radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
  3923. }
  3924. radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
  3925. /* flush hdp cache */
  3926. radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
  3927. radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
  3928. radeon_ring_write(ring, 1);
  3929. /* bits 0-7 are the VM contexts0-7 */
  3930. radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
  3931. radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
  3932. radeon_ring_write(ring, 1 << vm->id);
  3933. }
  3934. /*
  3935. * RLC
  3936. */
  3937. void si_rlc_fini(struct radeon_device *rdev)
  3938. {
  3939. int r;
  3940. /* save restore block */
  3941. if (rdev->rlc.save_restore_obj) {
  3942. r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
  3943. if (unlikely(r != 0))
  3944. dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
  3945. radeon_bo_unpin(rdev->rlc.save_restore_obj);
  3946. radeon_bo_unreserve(rdev->rlc.save_restore_obj);
  3947. radeon_bo_unref(&rdev->rlc.save_restore_obj);
  3948. rdev->rlc.save_restore_obj = NULL;
  3949. }
  3950. /* clear state block */
  3951. if (rdev->rlc.clear_state_obj) {
  3952. r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
  3953. if (unlikely(r != 0))
  3954. dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
  3955. radeon_bo_unpin(rdev->rlc.clear_state_obj);
  3956. radeon_bo_unreserve(rdev->rlc.clear_state_obj);
  3957. radeon_bo_unref(&rdev->rlc.clear_state_obj);
  3958. rdev->rlc.clear_state_obj = NULL;
  3959. }
  3960. }
  3961. int si_rlc_init(struct radeon_device *rdev)
  3962. {
  3963. int r;
  3964. /* save restore block */
  3965. if (rdev->rlc.save_restore_obj == NULL) {
  3966. r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
  3967. RADEON_GEM_DOMAIN_VRAM, NULL,
  3968. &rdev->rlc.save_restore_obj);
  3969. if (r) {
  3970. dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
  3971. return r;
  3972. }
  3973. }
  3974. r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
  3975. if (unlikely(r != 0)) {
  3976. si_rlc_fini(rdev);
  3977. return r;
  3978. }
  3979. r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
  3980. &rdev->rlc.save_restore_gpu_addr);
  3981. radeon_bo_unreserve(rdev->rlc.save_restore_obj);
  3982. if (r) {
  3983. dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
  3984. si_rlc_fini(rdev);
  3985. return r;
  3986. }
  3987. /* clear state block */
  3988. if (rdev->rlc.clear_state_obj == NULL) {
  3989. r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
  3990. RADEON_GEM_DOMAIN_VRAM, NULL,
  3991. &rdev->rlc.clear_state_obj);
  3992. if (r) {
  3993. dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
  3994. si_rlc_fini(rdev);
  3995. return r;
  3996. }
  3997. }
  3998. r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
  3999. if (unlikely(r != 0)) {
  4000. si_rlc_fini(rdev);
  4001. return r;
  4002. }
  4003. r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
  4004. &rdev->rlc.clear_state_gpu_addr);
  4005. radeon_bo_unreserve(rdev->rlc.clear_state_obj);
  4006. if (r) {
  4007. dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
  4008. si_rlc_fini(rdev);
  4009. return r;
  4010. }
  4011. return 0;
  4012. }
  4013. static void si_rlc_stop(struct radeon_device *rdev)
  4014. {
  4015. WREG32(RLC_CNTL, 0);
  4016. }
  4017. static void si_rlc_start(struct radeon_device *rdev)
  4018. {
  4019. WREG32(RLC_CNTL, RLC_ENABLE);
  4020. }
  4021. static int si_rlc_resume(struct radeon_device *rdev)
  4022. {
  4023. u32 i;
  4024. const __be32 *fw_data;
  4025. if (!rdev->rlc_fw)
  4026. return -EINVAL;
  4027. si_rlc_stop(rdev);
  4028. WREG32(RLC_RL_BASE, 0);
  4029. WREG32(RLC_RL_SIZE, 0);
  4030. WREG32(RLC_LB_CNTL, 0);
  4031. WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
  4032. WREG32(RLC_LB_CNTR_INIT, 0);
  4033. WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
  4034. WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
  4035. WREG32(RLC_MC_CNTL, 0);
  4036. WREG32(RLC_UCODE_CNTL, 0);
  4037. fw_data = (const __be32 *)rdev->rlc_fw->data;
  4038. for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
  4039. WREG32(RLC_UCODE_ADDR, i);
  4040. WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
  4041. }
  4042. WREG32(RLC_UCODE_ADDR, 0);
  4043. si_rlc_start(rdev);
  4044. return 0;
  4045. }
  4046. static void si_enable_interrupts(struct radeon_device *rdev)
  4047. {
  4048. u32 ih_cntl = RREG32(IH_CNTL);
  4049. u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  4050. ih_cntl |= ENABLE_INTR;
  4051. ih_rb_cntl |= IH_RB_ENABLE;
  4052. WREG32(IH_CNTL, ih_cntl);
  4053. WREG32(IH_RB_CNTL, ih_rb_cntl);
  4054. rdev->ih.enabled = true;
  4055. }
  4056. static void si_disable_interrupts(struct radeon_device *rdev)
  4057. {
  4058. u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  4059. u32 ih_cntl = RREG32(IH_CNTL);
  4060. ih_rb_cntl &= ~IH_RB_ENABLE;
  4061. ih_cntl &= ~ENABLE_INTR;
  4062. WREG32(IH_RB_CNTL, ih_rb_cntl);
  4063. WREG32(IH_CNTL, ih_cntl);
  4064. /* set rptr, wptr to 0 */
  4065. WREG32(IH_RB_RPTR, 0);
  4066. WREG32(IH_RB_WPTR, 0);
  4067. rdev->ih.enabled = false;
  4068. rdev->ih.rptr = 0;
  4069. }
  4070. static void si_disable_interrupt_state(struct radeon_device *rdev)
  4071. {
  4072. u32 tmp;
  4073. WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  4074. WREG32(CP_INT_CNTL_RING1, 0);
  4075. WREG32(CP_INT_CNTL_RING2, 0);
  4076. tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
  4077. WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
  4078. tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
  4079. WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
  4080. WREG32(GRBM_INT_CNTL, 0);
  4081. if (rdev->num_crtc >= 2) {
  4082. WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  4083. WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  4084. }
  4085. if (rdev->num_crtc >= 4) {
  4086. WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  4087. WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  4088. }
  4089. if (rdev->num_crtc >= 6) {
  4090. WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  4091. WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  4092. }
  4093. if (rdev->num_crtc >= 2) {
  4094. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  4095. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  4096. }
  4097. if (rdev->num_crtc >= 4) {
  4098. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  4099. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  4100. }
  4101. if (rdev->num_crtc >= 6) {
  4102. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  4103. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  4104. }
  4105. if (!ASIC_IS_NODCE(rdev)) {
  4106. WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
  4107. tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  4108. WREG32(DC_HPD1_INT_CONTROL, tmp);
  4109. tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  4110. WREG32(DC_HPD2_INT_CONTROL, tmp);
  4111. tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  4112. WREG32(DC_HPD3_INT_CONTROL, tmp);
  4113. tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  4114. WREG32(DC_HPD4_INT_CONTROL, tmp);
  4115. tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  4116. WREG32(DC_HPD5_INT_CONTROL, tmp);
  4117. tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  4118. WREG32(DC_HPD6_INT_CONTROL, tmp);
  4119. }
  4120. }
  4121. static int si_irq_init(struct radeon_device *rdev)
  4122. {
  4123. int ret = 0;
  4124. int rb_bufsz;
  4125. u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
  4126. /* allocate ring */
  4127. ret = r600_ih_ring_alloc(rdev);
  4128. if (ret)
  4129. return ret;
  4130. /* disable irqs */
  4131. si_disable_interrupts(rdev);
  4132. /* init rlc */
  4133. ret = si_rlc_resume(rdev);
  4134. if (ret) {
  4135. r600_ih_ring_fini(rdev);
  4136. return ret;
  4137. }
  4138. /* setup interrupt control */
  4139. /* set dummy read address to ring address */
  4140. WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
  4141. interrupt_cntl = RREG32(INTERRUPT_CNTL);
  4142. /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
  4143. * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
  4144. */
  4145. interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
  4146. /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
  4147. interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
  4148. WREG32(INTERRUPT_CNTL, interrupt_cntl);
  4149. WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
  4150. rb_bufsz = drm_order(rdev->ih.ring_size / 4);
  4151. ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
  4152. IH_WPTR_OVERFLOW_CLEAR |
  4153. (rb_bufsz << 1));
  4154. if (rdev->wb.enabled)
  4155. ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
  4156. /* set the writeback address whether it's enabled or not */
  4157. WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
  4158. WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
  4159. WREG32(IH_RB_CNTL, ih_rb_cntl);
  4160. /* set rptr, wptr to 0 */
  4161. WREG32(IH_RB_RPTR, 0);
  4162. WREG32(IH_RB_WPTR, 0);
  4163. /* Default settings for IH_CNTL (disabled at first) */
  4164. ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
  4165. /* RPTR_REARM only works if msi's are enabled */
  4166. if (rdev->msi_enabled)
  4167. ih_cntl |= RPTR_REARM;
  4168. WREG32(IH_CNTL, ih_cntl);
  4169. /* force the active interrupt state to all disabled */
  4170. si_disable_interrupt_state(rdev);
  4171. pci_set_master(rdev->pdev);
  4172. /* enable irqs */
  4173. si_enable_interrupts(rdev);
  4174. return ret;
  4175. }
  4176. int si_irq_set(struct radeon_device *rdev)
  4177. {
  4178. u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
  4179. u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
  4180. u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
  4181. u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
  4182. u32 grbm_int_cntl = 0;
  4183. u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
  4184. u32 dma_cntl, dma_cntl1;
  4185. if (!rdev->irq.installed) {
  4186. WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  4187. return -EINVAL;
  4188. }
  4189. /* don't enable anything if the ih is disabled */
  4190. if (!rdev->ih.enabled) {
  4191. si_disable_interrupts(rdev);
  4192. /* force the active interrupt state to all disabled */
  4193. si_disable_interrupt_state(rdev);
  4194. return 0;
  4195. }
  4196. if (!ASIC_IS_NODCE(rdev)) {
  4197. hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
  4198. hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
  4199. hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
  4200. hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
  4201. hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
  4202. hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
  4203. }
  4204. dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
  4205. dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
  4206. /* enable CP interrupts on all rings */
  4207. if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
  4208. DRM_DEBUG("si_irq_set: sw int gfx\n");
  4209. cp_int_cntl |= TIME_STAMP_INT_ENABLE;
  4210. }
  4211. if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
  4212. DRM_DEBUG("si_irq_set: sw int cp1\n");
  4213. cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
  4214. }
  4215. if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
  4216. DRM_DEBUG("si_irq_set: sw int cp2\n");
  4217. cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
  4218. }
  4219. if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
  4220. DRM_DEBUG("si_irq_set: sw int dma\n");
  4221. dma_cntl |= TRAP_ENABLE;
  4222. }
  4223. if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
  4224. DRM_DEBUG("si_irq_set: sw int dma1\n");
  4225. dma_cntl1 |= TRAP_ENABLE;
  4226. }
  4227. if (rdev->irq.crtc_vblank_int[0] ||
  4228. atomic_read(&rdev->irq.pflip[0])) {
  4229. DRM_DEBUG("si_irq_set: vblank 0\n");
  4230. crtc1 |= VBLANK_INT_MASK;
  4231. }
  4232. if (rdev->irq.crtc_vblank_int[1] ||
  4233. atomic_read(&rdev->irq.pflip[1])) {
  4234. DRM_DEBUG("si_irq_set: vblank 1\n");
  4235. crtc2 |= VBLANK_INT_MASK;
  4236. }
  4237. if (rdev->irq.crtc_vblank_int[2] ||
  4238. atomic_read(&rdev->irq.pflip[2])) {
  4239. DRM_DEBUG("si_irq_set: vblank 2\n");
  4240. crtc3 |= VBLANK_INT_MASK;
  4241. }
  4242. if (rdev->irq.crtc_vblank_int[3] ||
  4243. atomic_read(&rdev->irq.pflip[3])) {
  4244. DRM_DEBUG("si_irq_set: vblank 3\n");
  4245. crtc4 |= VBLANK_INT_MASK;
  4246. }
  4247. if (rdev->irq.crtc_vblank_int[4] ||
  4248. atomic_read(&rdev->irq.pflip[4])) {
  4249. DRM_DEBUG("si_irq_set: vblank 4\n");
  4250. crtc5 |= VBLANK_INT_MASK;
  4251. }
  4252. if (rdev->irq.crtc_vblank_int[5] ||
  4253. atomic_read(&rdev->irq.pflip[5])) {
  4254. DRM_DEBUG("si_irq_set: vblank 5\n");
  4255. crtc6 |= VBLANK_INT_MASK;
  4256. }
  4257. if (rdev->irq.hpd[0]) {
  4258. DRM_DEBUG("si_irq_set: hpd 1\n");
  4259. hpd1 |= DC_HPDx_INT_EN;
  4260. }
  4261. if (rdev->irq.hpd[1]) {
  4262. DRM_DEBUG("si_irq_set: hpd 2\n");
  4263. hpd2 |= DC_HPDx_INT_EN;
  4264. }
  4265. if (rdev->irq.hpd[2]) {
  4266. DRM_DEBUG("si_irq_set: hpd 3\n");
  4267. hpd3 |= DC_HPDx_INT_EN;
  4268. }
  4269. if (rdev->irq.hpd[3]) {
  4270. DRM_DEBUG("si_irq_set: hpd 4\n");
  4271. hpd4 |= DC_HPDx_INT_EN;
  4272. }
  4273. if (rdev->irq.hpd[4]) {
  4274. DRM_DEBUG("si_irq_set: hpd 5\n");
  4275. hpd5 |= DC_HPDx_INT_EN;
  4276. }
  4277. if (rdev->irq.hpd[5]) {
  4278. DRM_DEBUG("si_irq_set: hpd 6\n");
  4279. hpd6 |= DC_HPDx_INT_EN;
  4280. }
  4281. WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
  4282. WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
  4283. WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
  4284. WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
  4285. WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
  4286. WREG32(GRBM_INT_CNTL, grbm_int_cntl);
  4287. if (rdev->num_crtc >= 2) {
  4288. WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
  4289. WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
  4290. }
  4291. if (rdev->num_crtc >= 4) {
  4292. WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
  4293. WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
  4294. }
  4295. if (rdev->num_crtc >= 6) {
  4296. WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
  4297. WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
  4298. }
  4299. if (rdev->num_crtc >= 2) {
  4300. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
  4301. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
  4302. }
  4303. if (rdev->num_crtc >= 4) {
  4304. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
  4305. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
  4306. }
  4307. if (rdev->num_crtc >= 6) {
  4308. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
  4309. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
  4310. }
  4311. if (!ASIC_IS_NODCE(rdev)) {
  4312. WREG32(DC_HPD1_INT_CONTROL, hpd1);
  4313. WREG32(DC_HPD2_INT_CONTROL, hpd2);
  4314. WREG32(DC_HPD3_INT_CONTROL, hpd3);
  4315. WREG32(DC_HPD4_INT_CONTROL, hpd4);
  4316. WREG32(DC_HPD5_INT_CONTROL, hpd5);
  4317. WREG32(DC_HPD6_INT_CONTROL, hpd6);
  4318. }
  4319. return 0;
  4320. }
  4321. static inline void si_irq_ack(struct radeon_device *rdev)
  4322. {
  4323. u32 tmp;
  4324. if (ASIC_IS_NODCE(rdev))
  4325. return;
  4326. rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
  4327. rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
  4328. rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
  4329. rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
  4330. rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
  4331. rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
  4332. rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
  4333. rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
  4334. if (rdev->num_crtc >= 4) {
  4335. rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
  4336. rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
  4337. }
  4338. if (rdev->num_crtc >= 6) {
  4339. rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
  4340. rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
  4341. }
  4342. if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
  4343. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  4344. if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
  4345. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  4346. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
  4347. WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
  4348. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
  4349. WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
  4350. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
  4351. WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
  4352. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
  4353. WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
  4354. if (rdev->num_crtc >= 4) {
  4355. if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
  4356. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  4357. if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
  4358. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  4359. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
  4360. WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
  4361. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
  4362. WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
  4363. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
  4364. WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
  4365. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
  4366. WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
  4367. }
  4368. if (rdev->num_crtc >= 6) {
  4369. if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
  4370. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  4371. if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
  4372. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  4373. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
  4374. WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
  4375. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
  4376. WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
  4377. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
  4378. WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
  4379. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
  4380. WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
  4381. }
  4382. if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
  4383. tmp = RREG32(DC_HPD1_INT_CONTROL);
  4384. tmp |= DC_HPDx_INT_ACK;
  4385. WREG32(DC_HPD1_INT_CONTROL, tmp);
  4386. }
  4387. if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
  4388. tmp = RREG32(DC_HPD2_INT_CONTROL);
  4389. tmp |= DC_HPDx_INT_ACK;
  4390. WREG32(DC_HPD2_INT_CONTROL, tmp);
  4391. }
  4392. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
  4393. tmp = RREG32(DC_HPD3_INT_CONTROL);
  4394. tmp |= DC_HPDx_INT_ACK;
  4395. WREG32(DC_HPD3_INT_CONTROL, tmp);
  4396. }
  4397. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
  4398. tmp = RREG32(DC_HPD4_INT_CONTROL);
  4399. tmp |= DC_HPDx_INT_ACK;
  4400. WREG32(DC_HPD4_INT_CONTROL, tmp);
  4401. }
  4402. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
  4403. tmp = RREG32(DC_HPD5_INT_CONTROL);
  4404. tmp |= DC_HPDx_INT_ACK;
  4405. WREG32(DC_HPD5_INT_CONTROL, tmp);
  4406. }
  4407. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
  4408. tmp = RREG32(DC_HPD5_INT_CONTROL);
  4409. tmp |= DC_HPDx_INT_ACK;
  4410. WREG32(DC_HPD6_INT_CONTROL, tmp);
  4411. }
  4412. }
  4413. static void si_irq_disable(struct radeon_device *rdev)
  4414. {
  4415. si_disable_interrupts(rdev);
  4416. /* Wait and acknowledge irq */
  4417. mdelay(1);
  4418. si_irq_ack(rdev);
  4419. si_disable_interrupt_state(rdev);
  4420. }
  4421. static void si_irq_suspend(struct radeon_device *rdev)
  4422. {
  4423. si_irq_disable(rdev);
  4424. si_rlc_stop(rdev);
  4425. }
  4426. static void si_irq_fini(struct radeon_device *rdev)
  4427. {
  4428. si_irq_suspend(rdev);
  4429. r600_ih_ring_fini(rdev);
  4430. }
  4431. static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
  4432. {
  4433. u32 wptr, tmp;
  4434. if (rdev->wb.enabled)
  4435. wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
  4436. else
  4437. wptr = RREG32(IH_RB_WPTR);
  4438. if (wptr & RB_OVERFLOW) {
  4439. /* When a ring buffer overflow happen start parsing interrupt
  4440. * from the last not overwritten vector (wptr + 16). Hopefully
  4441. * this should allow us to catchup.
  4442. */
  4443. dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
  4444. wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
  4445. rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
  4446. tmp = RREG32(IH_RB_CNTL);
  4447. tmp |= IH_WPTR_OVERFLOW_CLEAR;
  4448. WREG32(IH_RB_CNTL, tmp);
  4449. }
  4450. return (wptr & rdev->ih.ptr_mask);
  4451. }
  4452. /* SI IV Ring
  4453. * Each IV ring entry is 128 bits:
  4454. * [7:0] - interrupt source id
  4455. * [31:8] - reserved
  4456. * [59:32] - interrupt source data
  4457. * [63:60] - reserved
  4458. * [71:64] - RINGID
  4459. * [79:72] - VMID
  4460. * [127:80] - reserved
  4461. */
  4462. int si_irq_process(struct radeon_device *rdev)
  4463. {
  4464. u32 wptr;
  4465. u32 rptr;
  4466. u32 src_id, src_data, ring_id;
  4467. u32 ring_index;
  4468. bool queue_hotplug = false;
  4469. if (!rdev->ih.enabled || rdev->shutdown)
  4470. return IRQ_NONE;
  4471. wptr = si_get_ih_wptr(rdev);
  4472. restart_ih:
  4473. /* is somebody else already processing irqs? */
  4474. if (atomic_xchg(&rdev->ih.lock, 1))
  4475. return IRQ_NONE;
  4476. rptr = rdev->ih.rptr;
  4477. DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
  4478. /* Order reading of wptr vs. reading of IH ring data */
  4479. rmb();
  4480. /* display interrupts */
  4481. si_irq_ack(rdev);
  4482. while (rptr != wptr) {
  4483. /* wptr/rptr are in bytes! */
  4484. ring_index = rptr / 4;
  4485. src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
  4486. src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
  4487. ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
  4488. switch (src_id) {
  4489. case 1: /* D1 vblank/vline */
  4490. switch (src_data) {
  4491. case 0: /* D1 vblank */
  4492. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
  4493. if (rdev->irq.crtc_vblank_int[0]) {
  4494. drm_handle_vblank(rdev->ddev, 0);
  4495. rdev->pm.vblank_sync = true;
  4496. wake_up(&rdev->irq.vblank_queue);
  4497. }
  4498. if (atomic_read(&rdev->irq.pflip[0]))
  4499. radeon_crtc_handle_flip(rdev, 0);
  4500. rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
  4501. DRM_DEBUG("IH: D1 vblank\n");
  4502. }
  4503. break;
  4504. case 1: /* D1 vline */
  4505. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
  4506. rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
  4507. DRM_DEBUG("IH: D1 vline\n");
  4508. }
  4509. break;
  4510. default:
  4511. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4512. break;
  4513. }
  4514. break;
  4515. case 2: /* D2 vblank/vline */
  4516. switch (src_data) {
  4517. case 0: /* D2 vblank */
  4518. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
  4519. if (rdev->irq.crtc_vblank_int[1]) {
  4520. drm_handle_vblank(rdev->ddev, 1);
  4521. rdev->pm.vblank_sync = true;
  4522. wake_up(&rdev->irq.vblank_queue);
  4523. }
  4524. if (atomic_read(&rdev->irq.pflip[1]))
  4525. radeon_crtc_handle_flip(rdev, 1);
  4526. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
  4527. DRM_DEBUG("IH: D2 vblank\n");
  4528. }
  4529. break;
  4530. case 1: /* D2 vline */
  4531. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
  4532. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
  4533. DRM_DEBUG("IH: D2 vline\n");
  4534. }
  4535. break;
  4536. default:
  4537. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4538. break;
  4539. }
  4540. break;
  4541. case 3: /* D3 vblank/vline */
  4542. switch (src_data) {
  4543. case 0: /* D3 vblank */
  4544. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
  4545. if (rdev->irq.crtc_vblank_int[2]) {
  4546. drm_handle_vblank(rdev->ddev, 2);
  4547. rdev->pm.vblank_sync = true;
  4548. wake_up(&rdev->irq.vblank_queue);
  4549. }
  4550. if (atomic_read(&rdev->irq.pflip[2]))
  4551. radeon_crtc_handle_flip(rdev, 2);
  4552. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
  4553. DRM_DEBUG("IH: D3 vblank\n");
  4554. }
  4555. break;
  4556. case 1: /* D3 vline */
  4557. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
  4558. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
  4559. DRM_DEBUG("IH: D3 vline\n");
  4560. }
  4561. break;
  4562. default:
  4563. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4564. break;
  4565. }
  4566. break;
  4567. case 4: /* D4 vblank/vline */
  4568. switch (src_data) {
  4569. case 0: /* D4 vblank */
  4570. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
  4571. if (rdev->irq.crtc_vblank_int[3]) {
  4572. drm_handle_vblank(rdev->ddev, 3);
  4573. rdev->pm.vblank_sync = true;
  4574. wake_up(&rdev->irq.vblank_queue);
  4575. }
  4576. if (atomic_read(&rdev->irq.pflip[3]))
  4577. radeon_crtc_handle_flip(rdev, 3);
  4578. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
  4579. DRM_DEBUG("IH: D4 vblank\n");
  4580. }
  4581. break;
  4582. case 1: /* D4 vline */
  4583. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
  4584. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
  4585. DRM_DEBUG("IH: D4 vline\n");
  4586. }
  4587. break;
  4588. default:
  4589. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4590. break;
  4591. }
  4592. break;
  4593. case 5: /* D5 vblank/vline */
  4594. switch (src_data) {
  4595. case 0: /* D5 vblank */
  4596. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
  4597. if (rdev->irq.crtc_vblank_int[4]) {
  4598. drm_handle_vblank(rdev->ddev, 4);
  4599. rdev->pm.vblank_sync = true;
  4600. wake_up(&rdev->irq.vblank_queue);
  4601. }
  4602. if (atomic_read(&rdev->irq.pflip[4]))
  4603. radeon_crtc_handle_flip(rdev, 4);
  4604. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
  4605. DRM_DEBUG("IH: D5 vblank\n");
  4606. }
  4607. break;
  4608. case 1: /* D5 vline */
  4609. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
  4610. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
  4611. DRM_DEBUG("IH: D5 vline\n");
  4612. }
  4613. break;
  4614. default:
  4615. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4616. break;
  4617. }
  4618. break;
  4619. case 6: /* D6 vblank/vline */
  4620. switch (src_data) {
  4621. case 0: /* D6 vblank */
  4622. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
  4623. if (rdev->irq.crtc_vblank_int[5]) {
  4624. drm_handle_vblank(rdev->ddev, 5);
  4625. rdev->pm.vblank_sync = true;
  4626. wake_up(&rdev->irq.vblank_queue);
  4627. }
  4628. if (atomic_read(&rdev->irq.pflip[5]))
  4629. radeon_crtc_handle_flip(rdev, 5);
  4630. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
  4631. DRM_DEBUG("IH: D6 vblank\n");
  4632. }
  4633. break;
  4634. case 1: /* D6 vline */
  4635. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
  4636. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
  4637. DRM_DEBUG("IH: D6 vline\n");
  4638. }
  4639. break;
  4640. default:
  4641. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4642. break;
  4643. }
  4644. break;
  4645. case 42: /* HPD hotplug */
  4646. switch (src_data) {
  4647. case 0:
  4648. if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
  4649. rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
  4650. queue_hotplug = true;
  4651. DRM_DEBUG("IH: HPD1\n");
  4652. }
  4653. break;
  4654. case 1:
  4655. if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
  4656. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
  4657. queue_hotplug = true;
  4658. DRM_DEBUG("IH: HPD2\n");
  4659. }
  4660. break;
  4661. case 2:
  4662. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
  4663. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
  4664. queue_hotplug = true;
  4665. DRM_DEBUG("IH: HPD3\n");
  4666. }
  4667. break;
  4668. case 3:
  4669. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
  4670. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
  4671. queue_hotplug = true;
  4672. DRM_DEBUG("IH: HPD4\n");
  4673. }
  4674. break;
  4675. case 4:
  4676. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
  4677. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
  4678. queue_hotplug = true;
  4679. DRM_DEBUG("IH: HPD5\n");
  4680. }
  4681. break;
  4682. case 5:
  4683. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
  4684. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
  4685. queue_hotplug = true;
  4686. DRM_DEBUG("IH: HPD6\n");
  4687. }
  4688. break;
  4689. default:
  4690. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4691. break;
  4692. }
  4693. break;
  4694. case 146:
  4695. case 147:
  4696. dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
  4697. dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
  4698. RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
  4699. dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
  4700. RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
  4701. /* reset addr and status */
  4702. WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
  4703. break;
  4704. case 176: /* RINGID0 CP_INT */
  4705. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  4706. break;
  4707. case 177: /* RINGID1 CP_INT */
  4708. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  4709. break;
  4710. case 178: /* RINGID2 CP_INT */
  4711. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  4712. break;
  4713. case 181: /* CP EOP event */
  4714. DRM_DEBUG("IH: CP EOP\n");
  4715. switch (ring_id) {
  4716. case 0:
  4717. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  4718. break;
  4719. case 1:
  4720. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  4721. break;
  4722. case 2:
  4723. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  4724. break;
  4725. }
  4726. break;
  4727. case 224: /* DMA trap event */
  4728. DRM_DEBUG("IH: DMA trap\n");
  4729. radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
  4730. break;
  4731. case 233: /* GUI IDLE */
  4732. DRM_DEBUG("IH: GUI idle\n");
  4733. break;
  4734. case 244: /* DMA trap event */
  4735. DRM_DEBUG("IH: DMA1 trap\n");
  4736. radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
  4737. break;
  4738. default:
  4739. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  4740. break;
  4741. }
  4742. /* wptr/rptr are in bytes! */
  4743. rptr += 16;
  4744. rptr &= rdev->ih.ptr_mask;
  4745. }
  4746. if (queue_hotplug)
  4747. schedule_work(&rdev->hotplug_work);
  4748. rdev->ih.rptr = rptr;
  4749. WREG32(IH_RB_RPTR, rdev->ih.rptr);
  4750. atomic_set(&rdev->ih.lock, 0);
  4751. /* make sure wptr hasn't changed while processing */
  4752. wptr = si_get_ih_wptr(rdev);
  4753. if (wptr != rptr)
  4754. goto restart_ih;
  4755. return IRQ_HANDLED;
  4756. }
  4757. /**
  4758. * si_copy_dma - copy pages using the DMA engine
  4759. *
  4760. * @rdev: radeon_device pointer
  4761. * @src_offset: src GPU address
  4762. * @dst_offset: dst GPU address
  4763. * @num_gpu_pages: number of GPU pages to xfer
  4764. * @fence: radeon fence object
  4765. *
  4766. * Copy GPU paging using the DMA engine (SI).
  4767. * Used by the radeon ttm implementation to move pages if
  4768. * registered as the asic copy callback.
  4769. */
  4770. int si_copy_dma(struct radeon_device *rdev,
  4771. uint64_t src_offset, uint64_t dst_offset,
  4772. unsigned num_gpu_pages,
  4773. struct radeon_fence **fence)
  4774. {
  4775. struct radeon_semaphore *sem = NULL;
  4776. int ring_index = rdev->asic->copy.dma_ring_index;
  4777. struct radeon_ring *ring = &rdev->ring[ring_index];
  4778. u32 size_in_bytes, cur_size_in_bytes;
  4779. int i, num_loops;
  4780. int r = 0;
  4781. r = radeon_semaphore_create(rdev, &sem);
  4782. if (r) {
  4783. DRM_ERROR("radeon: moving bo (%d).\n", r);
  4784. return r;
  4785. }
  4786. size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
  4787. num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
  4788. r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
  4789. if (r) {
  4790. DRM_ERROR("radeon: moving bo (%d).\n", r);
  4791. radeon_semaphore_free(rdev, &sem, NULL);
  4792. return r;
  4793. }
  4794. if (radeon_fence_need_sync(*fence, ring->idx)) {
  4795. radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
  4796. ring->idx);
  4797. radeon_fence_note_sync(*fence, ring->idx);
  4798. } else {
  4799. radeon_semaphore_free(rdev, &sem, NULL);
  4800. }
  4801. for (i = 0; i < num_loops; i++) {
  4802. cur_size_in_bytes = size_in_bytes;
  4803. if (cur_size_in_bytes > 0xFFFFF)
  4804. cur_size_in_bytes = 0xFFFFF;
  4805. size_in_bytes -= cur_size_in_bytes;
  4806. radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
  4807. radeon_ring_write(ring, dst_offset & 0xffffffff);
  4808. radeon_ring_write(ring, src_offset & 0xffffffff);
  4809. radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
  4810. radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
  4811. src_offset += cur_size_in_bytes;
  4812. dst_offset += cur_size_in_bytes;
  4813. }
  4814. r = radeon_fence_emit(rdev, fence, ring->idx);
  4815. if (r) {
  4816. radeon_ring_unlock_undo(rdev, ring);
  4817. return r;
  4818. }
  4819. radeon_ring_unlock_commit(rdev, ring);
  4820. radeon_semaphore_free(rdev, &sem, *fence);
  4821. return r;
  4822. }
  4823. /*
  4824. * startup/shutdown callbacks
  4825. */
  4826. static int si_startup(struct radeon_device *rdev)
  4827. {
  4828. struct radeon_ring *ring;
  4829. int r;
  4830. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
  4831. !rdev->rlc_fw || !rdev->mc_fw) {
  4832. r = si_init_microcode(rdev);
  4833. if (r) {
  4834. DRM_ERROR("Failed to load firmware!\n");
  4835. return r;
  4836. }
  4837. }
  4838. r = si_mc_load_microcode(rdev);
  4839. if (r) {
  4840. DRM_ERROR("Failed to load MC firmware!\n");
  4841. return r;
  4842. }
  4843. r = r600_vram_scratch_init(rdev);
  4844. if (r)
  4845. return r;
  4846. si_mc_program(rdev);
  4847. r = si_pcie_gart_enable(rdev);
  4848. if (r)
  4849. return r;
  4850. si_gpu_init(rdev);
  4851. /* allocate rlc buffers */
  4852. r = si_rlc_init(rdev);
  4853. if (r) {
  4854. DRM_ERROR("Failed to init rlc BOs!\n");
  4855. return r;
  4856. }
  4857. /* allocate wb buffer */
  4858. r = radeon_wb_init(rdev);
  4859. if (r)
  4860. return r;
  4861. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  4862. if (r) {
  4863. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  4864. return r;
  4865. }
  4866. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  4867. if (r) {
  4868. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  4869. return r;
  4870. }
  4871. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  4872. if (r) {
  4873. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  4874. return r;
  4875. }
  4876. r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
  4877. if (r) {
  4878. dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
  4879. return r;
  4880. }
  4881. r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
  4882. if (r) {
  4883. dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
  4884. return r;
  4885. }
  4886. if (rdev->has_uvd) {
  4887. r = rv770_uvd_resume(rdev);
  4888. if (!r) {
  4889. r = radeon_fence_driver_start_ring(rdev,
  4890. R600_RING_TYPE_UVD_INDEX);
  4891. if (r)
  4892. dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
  4893. }
  4894. if (r)
  4895. rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
  4896. }
  4897. /* Enable IRQ */
  4898. r = si_irq_init(rdev);
  4899. if (r) {
  4900. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  4901. radeon_irq_kms_fini(rdev);
  4902. return r;
  4903. }
  4904. si_irq_set(rdev);
  4905. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  4906. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
  4907. CP_RB0_RPTR, CP_RB0_WPTR,
  4908. 0, 0xfffff, RADEON_CP_PACKET2);
  4909. if (r)
  4910. return r;
  4911. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  4912. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
  4913. CP_RB1_RPTR, CP_RB1_WPTR,
  4914. 0, 0xfffff, RADEON_CP_PACKET2);
  4915. if (r)
  4916. return r;
  4917. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  4918. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
  4919. CP_RB2_RPTR, CP_RB2_WPTR,
  4920. 0, 0xfffff, RADEON_CP_PACKET2);
  4921. if (r)
  4922. return r;
  4923. ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
  4924. r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
  4925. DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
  4926. DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
  4927. 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
  4928. if (r)
  4929. return r;
  4930. ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
  4931. r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
  4932. DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
  4933. DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
  4934. 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
  4935. if (r)
  4936. return r;
  4937. r = si_cp_load_microcode(rdev);
  4938. if (r)
  4939. return r;
  4940. r = si_cp_resume(rdev);
  4941. if (r)
  4942. return r;
  4943. r = cayman_dma_resume(rdev);
  4944. if (r)
  4945. return r;
  4946. if (rdev->has_uvd) {
  4947. ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  4948. if (ring->ring_size) {
  4949. r = radeon_ring_init(rdev, ring, ring->ring_size,
  4950. R600_WB_UVD_RPTR_OFFSET,
  4951. UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
  4952. 0, 0xfffff, RADEON_CP_PACKET2);
  4953. if (!r)
  4954. r = r600_uvd_init(rdev);
  4955. if (r)
  4956. DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
  4957. }
  4958. }
  4959. r = radeon_ib_pool_init(rdev);
  4960. if (r) {
  4961. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  4962. return r;
  4963. }
  4964. r = radeon_vm_manager_init(rdev);
  4965. if (r) {
  4966. dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
  4967. return r;
  4968. }
  4969. return 0;
  4970. }
  4971. int si_resume(struct radeon_device *rdev)
  4972. {
  4973. int r;
  4974. /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
  4975. * posting will perform necessary task to bring back GPU into good
  4976. * shape.
  4977. */
  4978. /* post card */
  4979. atom_asic_init(rdev->mode_info.atom_context);
  4980. /* init golden registers */
  4981. si_init_golden_registers(rdev);
  4982. rdev->accel_working = true;
  4983. r = si_startup(rdev);
  4984. if (r) {
  4985. DRM_ERROR("si startup failed on resume\n");
  4986. rdev->accel_working = false;
  4987. return r;
  4988. }
  4989. return r;
  4990. }
  4991. int si_suspend(struct radeon_device *rdev)
  4992. {
  4993. radeon_vm_manager_fini(rdev);
  4994. si_cp_enable(rdev, false);
  4995. cayman_dma_stop(rdev);
  4996. if (rdev->has_uvd) {
  4997. r600_uvd_rbc_stop(rdev);
  4998. radeon_uvd_suspend(rdev);
  4999. }
  5000. si_irq_suspend(rdev);
  5001. radeon_wb_disable(rdev);
  5002. si_pcie_gart_disable(rdev);
  5003. return 0;
  5004. }
  5005. /* Plan is to move initialization in that function and use
  5006. * helper function so that radeon_device_init pretty much
  5007. * do nothing more than calling asic specific function. This
  5008. * should also allow to remove a bunch of callback function
  5009. * like vram_info.
  5010. */
  5011. int si_init(struct radeon_device *rdev)
  5012. {
  5013. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  5014. int r;
  5015. /* Read BIOS */
  5016. if (!radeon_get_bios(rdev)) {
  5017. if (ASIC_IS_AVIVO(rdev))
  5018. return -EINVAL;
  5019. }
  5020. /* Must be an ATOMBIOS */
  5021. if (!rdev->is_atom_bios) {
  5022. dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
  5023. return -EINVAL;
  5024. }
  5025. r = radeon_atombios_init(rdev);
  5026. if (r)
  5027. return r;
  5028. /* Post card if necessary */
  5029. if (!radeon_card_posted(rdev)) {
  5030. if (!rdev->bios) {
  5031. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  5032. return -EINVAL;
  5033. }
  5034. DRM_INFO("GPU not posted. posting now...\n");
  5035. atom_asic_init(rdev->mode_info.atom_context);
  5036. }
  5037. /* init golden registers */
  5038. si_init_golden_registers(rdev);
  5039. /* Initialize scratch registers */
  5040. si_scratch_init(rdev);
  5041. /* Initialize surface registers */
  5042. radeon_surface_init(rdev);
  5043. /* Initialize clocks */
  5044. radeon_get_clock_info(rdev->ddev);
  5045. /* Fence driver */
  5046. r = radeon_fence_driver_init(rdev);
  5047. if (r)
  5048. return r;
  5049. /* initialize memory controller */
  5050. r = si_mc_init(rdev);
  5051. if (r)
  5052. return r;
  5053. /* Memory manager */
  5054. r = radeon_bo_init(rdev);
  5055. if (r)
  5056. return r;
  5057. r = radeon_irq_kms_init(rdev);
  5058. if (r)
  5059. return r;
  5060. ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  5061. ring->ring_obj = NULL;
  5062. r600_ring_init(rdev, ring, 1024 * 1024);
  5063. ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
  5064. ring->ring_obj = NULL;
  5065. r600_ring_init(rdev, ring, 1024 * 1024);
  5066. ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
  5067. ring->ring_obj = NULL;
  5068. r600_ring_init(rdev, ring, 1024 * 1024);
  5069. ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
  5070. ring->ring_obj = NULL;
  5071. r600_ring_init(rdev, ring, 64 * 1024);
  5072. ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
  5073. ring->ring_obj = NULL;
  5074. r600_ring_init(rdev, ring, 64 * 1024);
  5075. if (rdev->has_uvd) {
  5076. r = radeon_uvd_init(rdev);
  5077. if (!r) {
  5078. ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  5079. ring->ring_obj = NULL;
  5080. r600_ring_init(rdev, ring, 4096);
  5081. }
  5082. }
  5083. rdev->ih.ring_obj = NULL;
  5084. r600_ih_ring_init(rdev, 64 * 1024);
  5085. r = r600_pcie_gart_init(rdev);
  5086. if (r)
  5087. return r;
  5088. rdev->accel_working = true;
  5089. r = si_startup(rdev);
  5090. if (r) {
  5091. dev_err(rdev->dev, "disabling GPU acceleration\n");
  5092. si_cp_fini(rdev);
  5093. cayman_dma_fini(rdev);
  5094. si_irq_fini(rdev);
  5095. si_rlc_fini(rdev);
  5096. radeon_wb_fini(rdev);
  5097. radeon_ib_pool_fini(rdev);
  5098. radeon_vm_manager_fini(rdev);
  5099. radeon_irq_kms_fini(rdev);
  5100. si_pcie_gart_fini(rdev);
  5101. rdev->accel_working = false;
  5102. }
  5103. /* Don't start up if the MC ucode is missing.
  5104. * The default clocks and voltages before the MC ucode
  5105. * is loaded are not suffient for advanced operations.
  5106. */
  5107. if (!rdev->mc_fw) {
  5108. DRM_ERROR("radeon: MC ucode required for NI+.\n");
  5109. return -EINVAL;
  5110. }
  5111. return 0;
  5112. }
  5113. void si_fini(struct radeon_device *rdev)
  5114. {
  5115. si_cp_fini(rdev);
  5116. cayman_dma_fini(rdev);
  5117. si_irq_fini(rdev);
  5118. si_rlc_fini(rdev);
  5119. radeon_wb_fini(rdev);
  5120. radeon_vm_manager_fini(rdev);
  5121. radeon_ib_pool_fini(rdev);
  5122. radeon_irq_kms_fini(rdev);
  5123. if (rdev->has_uvd)
  5124. radeon_uvd_fini(rdev);
  5125. si_pcie_gart_fini(rdev);
  5126. r600_vram_scratch_fini(rdev);
  5127. radeon_gem_fini(rdev);
  5128. radeon_fence_driver_fini(rdev);
  5129. radeon_bo_fini(rdev);
  5130. radeon_atombios_fini(rdev);
  5131. kfree(rdev->bios);
  5132. rdev->bios = NULL;
  5133. }
  5134. /**
  5135. * si_get_gpu_clock_counter - return GPU clock counter snapshot
  5136. *
  5137. * @rdev: radeon_device pointer
  5138. *
  5139. * Fetches a GPU clock counter snapshot (SI).
  5140. * Returns the 64 bit clock counter snapshot.
  5141. */
  5142. uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
  5143. {
  5144. uint64_t clock;
  5145. mutex_lock(&rdev->gpu_clock_mutex);
  5146. WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
  5147. clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
  5148. ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
  5149. mutex_unlock(&rdev->gpu_clock_mutex);
  5150. return clock;
  5151. }
  5152. int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
  5153. {
  5154. unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
  5155. int r;
  5156. /* bypass vclk and dclk with bclk */
  5157. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  5158. VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
  5159. ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  5160. /* put PLL in bypass mode */
  5161. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
  5162. if (!vclk || !dclk) {
  5163. /* keep the Bypass mode, put PLL to sleep */
  5164. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  5165. return 0;
  5166. }
  5167. r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
  5168. 16384, 0x03FFFFFF, 0, 128, 5,
  5169. &fb_div, &vclk_div, &dclk_div);
  5170. if (r)
  5171. return r;
  5172. /* set RESET_ANTI_MUX to 0 */
  5173. WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
  5174. /* set VCO_MODE to 1 */
  5175. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
  5176. /* toggle UPLL_SLEEP to 1 then back to 0 */
  5177. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  5178. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
  5179. /* deassert UPLL_RESET */
  5180. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
  5181. mdelay(1);
  5182. r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  5183. if (r)
  5184. return r;
  5185. /* assert UPLL_RESET again */
  5186. WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
  5187. /* disable spread spectrum. */
  5188. WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
  5189. /* set feedback divider */
  5190. WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
  5191. /* set ref divider to 0 */
  5192. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
  5193. if (fb_div < 307200)
  5194. WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
  5195. else
  5196. WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
  5197. /* set PDIV_A and PDIV_B */
  5198. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  5199. UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
  5200. ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
  5201. /* give the PLL some time to settle */
  5202. mdelay(15);
  5203. /* deassert PLL_RESET */
  5204. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
  5205. mdelay(15);
  5206. /* switch from bypass mode to normal mode */
  5207. WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
  5208. r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  5209. if (r)
  5210. return r;
  5211. /* switch VCLK and DCLK selection */
  5212. WREG32_P(CG_UPLL_FUNC_CNTL_2,
  5213. VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
  5214. ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  5215. mdelay(100);
  5216. return 0;
  5217. }